MSC7119_08_技术文档

Freescale Semiconductor

Data Sheet

Document Number: MSC7119

Rev. 8, 4/2008

MSC7119

Low-Cost 16-bit DSP with

DDR Controller and 10/100

Mbps Ethernet MAC

MAP-BGA–400

17 mm × 17 mm

•

StarCore^®SC1400 DSP extended core with one SC1400 DSP

core, 256 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte

instruction cache (ICache), four-entry write buffer, programmable

interrupt controller (PIC), and low-power Wait and Stop

processing modes.

192 Kbyte M2 memory for critical data and temporary data

buffering.

8 Kbyte boot ROM.

•

Multi-channel DMA controller with 32 time-multiplexed

unidirectional channels, priority-based time-multiplexing

between channels using 32 internal priority levels, fixed- or

round-robin-priority operation, major-minor loop structure, and

DONE or DRACK protocol from requesting units.

Two independent TDM modules with independent receive and

transmit, programmable sharing of frame sync and clock,

programmable word size (8 or 16-bit), hardware-base

A-law/μ-law conversion, up to 50 Mbps data rate per TDM, up to

128 channels, with glueless interface to E1/T1 frames and MVIP,

SCAS, and H.110 buses.

Ethernet controller with support for 10/100 Mbps MII/RMII

designed to comply with IEEE Std. 802.3™, 802.3u™, 802.3x™,

and 802.3ac™; with internal receive and transmit FIFOs and a

FIFO controller; direct access to internal memories via its own

DMA controller; full and half duplex operation; programmable

maximum frame length; virtual local area network (VLAN) tag

and priority support; retransmission of transmit FIFO following

collision; CRC generation and verification for inbound and

outbound packets; and address recognition including

promiscuous, broadcast, individual address. hash/exact match,

and multicast hash match.

•

AHB-Lite crossbar switch that allows parallel data transfers

between four master ports and six slave ports, where each port

connects to an AHB-Lite bus; fixed or round robin priority

programmable at each slave port; programmable bus parking at

each slave port; low power mode.

Internal PLL generates up to 300 MHz clock for the SC1400 core

and up to 150 MHz for the crossbar switch, DMA channels, M2

memory, and other peripherals.

Clock synthesis module provides predivision of PLL input clock;

independent clocking of the internal timers and DDR module;

programmable operation in the SC1400 low power Stop mode;

independent shutdown of different regions of the device.

Enhanced 16-bit wide host interface (HDI16) provides a glueless

connection to industry-standard microcomputers,

microprocessors, and DSPs and can also operate with an 8-bit host

data bus, making if fully compatible with the DSP56300 HI08

from the external host side.

DDR memory controller that supports byte enables for up to a

32-bit data bus; glueless interface to 150 MHz 14-bit page mode

DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;

and 16-bit or 32-bit external data bus.

•

UART with full-duplex operation up to 5.0 Mbps.

Up to 41 general-purpose input/output (GPIO) ports.

I²C interface that allows booting from EEPROM devices up to 1

Mbyte.

Two quad timer modules, each with sixteen configurable 16-bit

timers.

fieldBIST™ unit detects and provides visibility into unlikely field

failures for systems with high availability to ensure structural

integrity, that the device operates at the rated speed, is free from

reliability defects, and reports diagnostics for partial or complete

device inoperability.

Standard JTAG interface allows easy integration to system

firmware and internal on-chip emulation (OCE10) module.

Optional booting external host via 8-bit or 16-bit access through

the HDI16, I²C, or SPI using in the boot ROM to access serial SPI

Flash/EEPROM devices; different clocking options during boot

with the PLL on or off using a variety of input frequency ranges.

•

Programmable memory interface with independent read buffers,

programmable predictive read feature for each buffer, and a write

buffer.

System control unit performs software watchdog timer function;

includes programmable bus time-out monitors on AHB-Lite slave

buses; includes bus error detection and programmable time-out

monitors on AHB-Lite master buses; and has address

out-of-range detection on each crossbar switch buses.

Event port collects and counts important signal events including

DMA and interrupt requests and trigger events such as interrupts,

breakpoints, DMA transfers, or wake-up events; units operate

independently, in sequence, or triggered externally; can be used

standalone or with the OCE10.

•

Table of Contents

1

2

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Figure 8. TDM Receive Signals. . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 9. TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 10. Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . . 29

Figure 11. Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . . 30

Figure 12. Asynchronous Input Signal Timing. . . . . . . . . . . . . . . 30

Figure 13. Serial Management Channel Timing . . . . . . . . . . . . . 31

Figure 14. Read Timing Diagram, Single Data Strobe . . . . . . . . 33

Figure 15. Read Timing Diagram, Double Data Strobe. . . . . . . . 33

Figure 16. Write Timing Diagram, Single Data Strobe. . . . . . . . . 34

Figure 17. Write Timing Diagram, Double Data Strobe . . . . . . . . 34

Figure 18. Host DMA Read Timing Diagram, HPCR[OAD] = 0. . 35

Figure 19. Host DMA Write Timing Diagram, HPCR[OAD] = 0 . . 35

Figure 20. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 21. UART Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 22. UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 23. EE Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 24. EVNT Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 25. GPI/GPO Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 26. Test Clock Input Timing Diagram . . . . . . . . . . . . . . . . 39

Figure 27. Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . 40

Figure 28. Test Access Port Timing Diagram . . . . . . . . . . . . . . . 40

Figure 29. TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 30. Voltage Sequencing Case 1. . . . . . . . . . . . . . . . . . . . 43

Figure 31. Voltage Sequencing Case 2. . . . . . . . . . . . . . . . . . . . 44

Figure 32. Voltage Sequencing Case 3. . . . . . . . . . . . . . . . . . . . 45

Figure 33. Voltage Sequencing Case 4. . . . . . . . . . . . . . . . . . . . 46

Figure 34. Voltage Sequencing Case 5. . . . . . . . . . . . . . . . . . . . 47

Figure 35. PLL Power Supply Filter Circuits . . . . . . . . . . . . . . . . 48

Figure 36. SSTL Termination Techniques . . . . . . . . . . . . . . . . . . 54

Figure 37. SSTL Power Value . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

1.1 MAP-BGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . .4

1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.2 Recommended Operating Conditions. . . . . . . . . . . . . .18

2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .19

2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .19

2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . .41

3.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . .41

3.2 Power Supply Design Considerations. . . . . . . . . . . . . .42

3.3 Estimated Power Usage Calculations. . . . . . . . . . . . . .49

3.4 Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

3.5 DDR Memory System Guidelines . . . . . . . . . . . . . . . . .54

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

3

4

5

6

7

List of Figures

Figure 1. MSC7119 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. MSC7119 Molded Array Process-Ball Grid Array

(MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. MSC7119 Molded Array Process-Ball Grid Array

(MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4. Timing Diagram for a Reset Configuration Write . . . . 25

Figure 5. DDR DRAM Input Timing Diagram . . . . . . . . . . . . . . 26

Figure 6. DDR DRAM Output Timing Diagram . . . . . . . . . . . . . 27

Figure 7. DDR DRAM AC Test Load. . . . . . . . . . . . . . . . . . . . . 28

MSC7119 Data Sheet, Rev. 8

2

Freescale Semiconductor

DMA

(32 Channel)

AMDMA

M2

SRAM

(192 KB)

JTAG Port

128

64

JTAG

ASM2

128

64

to IPBus

64

Boot ROM

(8 KB)

DSP

Extended

Core

128

SC1400

Core

ASEMI

External Bus

32

External

Memory

Interface

Trace

Buffer

(8 KB)

from

IPBus

64

Interrupts

Interrupt Control

Fetch

Unit

Host

HDI16

Port

Interface

(HDI16)

Instruction

Cache

(16 KB)

ASTH

AMIC

TDM

32

64

128

64

2 TDMs

AMEC

PLL/Clock

Extended

Core

Interface

ASAPB

PLL/Clock

2

I C

32

2

APB

I C

RS-232

GPIO

UART

M1

SRAM

ASM1

GPIO

(256 KB)

128

64

ASIB

64

System Ctrl

64

P XA XB

Events

32

AMENT

Watchdog

Event Port

BTMs

to EMI

to/from OCE10

Timers

Ethernet

MAC

to DMA

Note: The arrows show the

direction of the transfer.

MII/RMII

IPBus

Figure 1. MSC7119 Block Diagram

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

3

Pin Assignments

1

Pin Assignments

This section includes diagrams of the MSC7119 package ball grid array layouts and pinout allocation tables.

1.1

MAP-BGA Ball Layout Diagrams

Top and bottom views of the MAP-BGA package are shown in Figure 2 and Figure 3 with their ball location index numbers.

Top View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

A

B

C

D

E

F

GND

DQM1 DQS2

CK

HD15

HD12

HD10

HD7

HD6

HD4

HD1

HD0

GND

BM3

NC

V_DDM

NC

D30

D28

D26

D15

D13

D12

V_DDM

CS0

D25

D27

D31

D29

GND

D11

D9

DQM2 DQS3 DQS0

CKE

WE

HD14

CAS

HD11

HD13

V_DDM

HD8

HD9

HD5

HD3

HD2

NC

BM2

NC

HA2

NC

HA1

D24

CS1

DQM3 DQM0 DQS1

RAS

V_DDM

V_DDC

NC

V_DDM

V_DDC

V_DDM

V_DDC

A10

V_DDM

V_DDC

V_DDM

V_DDIOV_DDIOV_DDIOV_DDIOV_DDIOV_DDIO

V_DDC

GND

V_DDM

V_DDC

V_DDM

V_DDC

V_DDM

V_DDC

V_DDIOV_DDIOV_DDIOV_DDIOV_DDIO

V_DDC

GND

V_DDM

V_DDIO

V_DDC

GND

V_DDM

V_DDC

GND

V_DDM

V_DDC

GND

V_DDC

GND

V_DDIO

GND

V_DDIOV_DDIO

G

H

J

GND

D14

D10

D0

GND

V_DDM

GND

V_DDM

V_DDC

GND

V_DDM

V_DDC

V_DDIOV_DDIO

V_DDIO

GND

HA3

HA0

HACK HREQ

V_DDIOV_DDIO

K

L

GND

V_DDM

D8

GND

V_DDM

V_DDC

HDDS

HDS

V_DDIOV_DDIOV_DDIO

D1

D3

HCS2 HCS1

HRW

V_DDC

M

N

P

R

T

D2

D5

GND

SDA

UTXD URXD

V_REF

V_DDIO

V_DDC

V_SSPLL

V_DDPLL

TEST0

D4

D6

D17

D19

D20

D21

NC

CLKIN

SCL

V_DDIOV_DDIO

D7

D16

D18

D22

D23

A13

A12

A9

PORESET TPSEL

V_DDIOV_DDIO

GND

V_DDM

TDO

MDIO

COL

EE0

V_DDIOV_DDIOV_DDIOV_DDIO

V_DDC

TMS HRESET

V_DDC

U

V

W

Y

GND

TCK

TRST

TDI

V_DDM

A11

A8

A5

A6

A4

A2

A3

BA0

NC

EVNT0 EVNT4 T0TCK T1RFS T1TD TX_ER RXD2 RXD0 TX_EN CRS

V_DDM

GND

A7

EVNT1 EVNT2 T0RFS T0TFS T1RD T1TFS TXD2 RXD3 TXD1 TXCLK RX_ER MDC

V_DDM

GND

A1

A0

BA1

NMI

EVNT3 T0RCK T0RD TOTD T1RCK T1TCK TXD3 RXCLK TXD0 RXD1

GND RX_DV

Figure 2. MSC7119 Molded Array Process-Ball Grid Array (MAP-BGA), Top View

MSC7119 Data Sheet, Rev. 8

4

Freescale Semiconductor

Pin Assignments

Bottom View

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

NC

BM3

GND

HD0

HD1

HD4

HD6

HD7

HD10

HD12

HD15

CK

DQS2 DQM1

GND

V_DDM

NC

HA1

NC

HA2

NC

HA3

HA0

NC

BM2

NC

HD2

NC

HD5

HD3

HD8

HD9

HD11

HD13

V_DDM

HD14

CAS

V_DDM

V_DD

WE

RAS

V_DDM

V_DD

CKE

DQS0 DQS3 DQM2

CS0

D25

D27

D31

D29

GND

D11

D9

NC

D30

D28

D26

D15

D13

D12

V_DDM

DQS1 DQM0 DQM3

CS1

GND

V_DDM

V_DD

D24

V_DD

V_DDIOV_DDIOV_DDIOV_DDIOV_DDIOV_DDIO

V_DDM

V_DD

V_DDM

V_DD

V_DDIOV_DDIOV_DDIOV_DDIOV_DDIO

V_DD

GND

V_DD

V_DDIO

V_DDM

V_DD

V_DDM

GND

V_DDIO

GND

V_DD

GND

V_DDM

V_DD

GND

V_DDM

V_DD

V_DDIOV_DDIO

V_DDM

V_DD

V_DDM

V_DD

G

H

J

GND

V_DDM

V_DD

GND

V_DDM

V_DD

GND

V_DDM

GND

D14

D10

D0

V_DDIOV_DDIO

V_DDIO

HREQ HACK

GND

V_DDIOV_DDIO

K

L

HDS

HDDS

GND

V_DDM

V_DD

D8

GND

V_DDM

V_DDIOV_DDIOV_DDIO

V_DD

HRW

HCS1 HCS2

D3

D1

V_DD

V_DDM

M

N

P

R

T

URXD UTXD

SDA

CLKIN

PORESET

TDO

GND

D5

D2

V_SSPLL

V_DDPLL

TEST0

V_DD

V_DDIO

V_REF

SCL

TPSEL

EE0

D6

D17

D19

D20

D21

NC

D4

V_DDIOV_DDIO

D16

D18

D22

D23

A13

A12

A9

D7

V_DDIOV_DDIO

GND

V_DDM

V_DD

V_DDIOV_DDIOV_DDIOV_DDIO

HRESET TMS

MDIO

COL

V_DD

U

V

W

Y

TRST

TDI

TCK

GND

V_DDM

CRS TX_EN RXD0 RXD2 TX_ER T1TD T1RFS T0TCK EVNT4 EVNT0

NC

BA0

NC

A2

A3

A5

A6

A4

A10

A11

A8

V_DDM

MDC RX_ER TXCLK TXD1 RXD3 TXD2 T1TFS T1RD T0TFS T0RFS EVNT2 EVNT1

A7

GND

V_DDM

RX_DV GND

RXD1 TXD0 RXCLK TXD3 T1TCK T1RCK TOTD T0RD T0RCK EVNT3

NMI

BA1

A0

A1

GND

Figure 3. MSC7119 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

5

Pin Assignments

1.2

Signal List By Ball Location

Table 1 lists the signals sorted by ball number and configuration.

Table 1. MSC7119 Signals by Ball Designator

Signal Names

Software Controlled

Hardware Controlled

Primary Alternate

Number

End of Reset

GPI Enabled

(Default)

Interrupt

Enabled

GPO Enabled

A1

A2

GND

DQM1

DQS2

CK

A3

A4

A5

A6

CK

A7

GPIC7

GPIC4

GPIC2

GPOC7

GPOC4

GPOC2

HD15

HD12

HD10

HD7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

B1

reserved

HD6

HD4

HD1

HD0

GND

BM3

GPID8

GPOD8

reserved

NC

V

DDM

B2

NC

CS0

B3

B4

DQM2

DQS3

DQS0

CKE

B5

B6

B7

B8

WE

B9

GPIC6

GPIC3

GPIC0

GPOC6

GPOC3

GPOC0

HD14

HD11

HD8

B10

B11

B12

B13

reserved

HD5

HD2

MSC7119 Data Sheet, Rev. 8

6

Freescale Semiconductor

Pin Assignments

Table 1. MSC7119 Signals by Ball Designator (continued)

Signal Names

Software Controlled

Hardware Controlled

Primary Alternate

Number

End of Reset

GPI Enabled

(Default)

Interrupt

Enabled

GPO Enabled

B14

B15

B16

B17

B18

B19

B20

C1

NC

BM2

GPID7

GPOD7

reserved

NC

D24

D30

D25

CS1

C2

C3

C4

C5

DQM3

DQM0

DQS1

RAS

C6

C7

C8

C9

CAS

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

D1

GPIC5

GPIC1

GPOC5

GPOC1

HD13

HD9

HD3

reserved

NC

V

DDM

D2

D28

D27

D3

D4

GND

D5

V

DDM

D6

D7

D8

D9

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

7

Pin Assignments

Table 1. MSC7119 Signals by Ball Designator (continued)

Signal Names

Software Controlled

Hardware Controlled

Primary Alternate

Number

End of Reset

GPI Enabled

(Default)

Interrupt

Enabled

GPO Enabled

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

E1

V

DDM

V

DDIO

V

DDC

NC

GND

D26

D31

E2

E3

E4

V

DDM

E5

E6

V

DDC

DDM

DDIO

E7

E8

E9

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

F1

V

DDC

NC

V

DDM

F2

D15

F3

D29

F4

V

DDC

F5

V

MSC7119 Data Sheet, Rev. 8

8

Freescale Semiconductor

Pin Assignments

Table 1. MSC7119 Signals by Ball Designator (continued)

Signal Names

Software Controlled

Hardware Controlled

Primary Alternate

Number

End of Reset

GPI Enabled

(Default)

Interrupt

Enabled

GPO Enabled

F6

F7

V

DDC

GND

F8

F9

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

G1

V

DDM

GND

V

DDIO

V

DDC

V

DDC

NC

GND

D13

GND

G2

G3

G4

V

DDM

G5

G6

GND

G7

G8

G9

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

H1

V

DDIO

V

DDC

NC

D14

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

9

Pin Assignments

Table 1. MSC7119 Signals by Ball Designator (continued)

Signal Names

Software Controlled

Hardware Controlled

Primary Alternate

Number

End of Reset

GPI Enabled

(Default)

Interrupt

Enabled

GPO Enabled

H2

H3

D12

D11

H4

V

DDM

H5

V

H6

GND

H7

H8

H9

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

J1

V

DDIO

V

DDC

NC

reserved

HA2

HA1

D10

J2

V

DDM

J3

D9

J4

V

DDM

J5

V

J6

J7

GND

J8

J9

J10

J11

J12

J13

J14

J15

J16

J17

V

DDIO

V

DDC

MSC7119 Data Sheet, Rev. 8

10

Freescale Semiconductor

Pin Assignments

Table 1. MSC7119 Signals by Ball Designator (continued)

Signal Names

Software Controlled

Hardware Controlled

Primary Alternate

Number

End of Reset

GPI Enabled

(Default)

Interrupt

Enabled

GPO Enabled

J18

J19

J20

K1

GPIC11

GPOC11

HA3

reserved

HACK/HACK or HRRQ/HRRQ

HREQ/HREQ or HTRQ/HTRQ

HDSP

reserved

D0

K2

GND

D8

K3

K4

V

DDC

DDM

K5

V

K6

GND

K7

K8

K9

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

L1

V

DDIO

V

DDC

reserved

HA0

HDDS

HDS/HDS or HWR/HWR

D1

GND

D3

L2

L3

L4

V

DDC

DDM

L5

V

L6

GND

L7

L8

L9

L10

L11

L12

L13

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

11

Pin Assignments

Table 1. MSC7119 Signals by Ball Designator (continued)

Signal Names

Software Controlled

Hardware Controlled

Primary Alternate

Number

End of Reset

GPI Enabled

(Default)

Interrupt

Enabled

GPO Enabled

L14

L15

L16

L17

L18

L19

L20

M1

V

DDIO

V

DDC

GPIB11

GPOB11

HCS2/HCS2

HCS1/HCS1

reserved

HRW or HRD/HRD

D2

M2

V

DDM

M3

D5

M4

V

DDM

M5

V

M6

GND

M7

M8

M9

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

N1

V

DDC

GPIA14

IRQ15

IRQ3

IRQ2

GPOA14

GPOA12

GPOA13

SDA

UTXD

URXD

GPIA12

GPIA13

D4

D6

N2

N3

V

REF

DDM

N4

V

N5

N6

N7

GND

N8

N9

MSC7119 Data Sheet, Rev. 8

12

Freescale Semiconductor

Pin Assignments

Table 1. MSC7119 Signals by Ball Designator (continued)

Signal Names

Software Controlled

Hardware Controlled

Primary Alternate

Number

End of Reset

GPI Enabled

(Default)

Interrupt

Enabled

GPO Enabled

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

P1

GND

V

DDIO

V

DDC

V

CLKIN

GPIA15

IRQ14

GPOA15

SCL

V

SSPLL

D7

P2

D17

D16

P3

P4

V

DDM

P5

V

P6

V

P7

GND

P8

P9

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

R1

V

DDIO

V

DDC

PORESET

TPSEL

V

DDPLL

GND

D19

D18

R2

R3

R4

V

DDM

R5

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

13

Pin Assignments

Table 1. MSC7119 Signals by Ball Designator (continued)

Signal Names

Software Controlled

Hardware Controlled

Primary Alternate

Number

End of Reset

GPI Enabled

(Default)

Interrupt

Enabled

GPO Enabled

R6

R7

V

DDM

GND

R8

V

DDM

R9

GND

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

T1

V

DDM

GND

V

DDIO

GND

V

DDIO

V

DDC

TDO

reserved

EE0/DBREQ

TEST0

V

DDM

T2

D20

D22

T3

T4

V

DDM

T5

V

T6

V

DDC

DDM

T7

V

T8

T9

V

DDC

DDM

DDIO

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

U1

V

DDC

V

reserved

MDIO

TMS

HRESET

GND

MSC7119 Data Sheet, Rev. 8

14

Freescale Semiconductor

Pin Assignments

Table 1. MSC7119 Signals by Ball Designator (continued)

Signal Names

Software Controlled

Hardware Controlled

Number

End of Reset

GPI Enabled

(Default)

Interrupt

Enabled

GPO Enabled

Primary

Alternate

U2

U3

D21

D23

U4

V

DDM

U5

V

DDC

U6

V

U7

U8

U9

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

V1

reserved

COL

TCK

TRST

V

DDM

V2

NC

A13

A11

A10

A5

V3

V4

V5

V6

V7

A2

V8

BA0

NC

V9

V10

V11

V12

V13

V14

V15

V16

V17

reserved

EVNT0

EVNT4

T0TCK

T1RFS

T1TD

SWTE

GPIA16

IRQ12

IRQ6

GPOA16

GPOA8

GPOA4

GPOA0

GPOA28

GPOD6

GPOA22

GPIA8

GPIA4

GPIA0

GPIA28

IRQ1

IRQ11

IRQ17

TX_ER

RXD2

reserved

GPID6

GPIA22

IRQ22

RXD0

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

15

Pin Assignments

Table 1. MSC7119 Signals by Ball Designator (continued)

Signal Names

Software Controlled

Hardware Controlled

Primary Alternate

Number

End of Reset

GPI Enabled

(Default)

Interrupt

Enabled

GPO Enabled

V18

V19

V20

W1

GPIA24

IRQ24

GPOA24

TX_EN

CRS

reserved

TDI

GND

W2

V

DDM

W3

A12

A8

W4

W5

A7

W6

A6

W7

A3

W8

NC

W9

GPIA17

IRQ13

GPOA17

GPOC14

GPOA10

GPOA7

EVNT1

CLKO

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

Y1

BM0

GPIC14

EVNT2

T0RFS

T0TFS

T1RD

GPIA10

GPIA7

GPIA3

GPIA1

IRQ5

IRQ7

IRQ8

IRQ10

GPOA3

GPOA1

T1TFS

GPID4

GPOD4

GPOA27

GPOA19

GPOA23

GPOA26

TXD2

RXD3

reserved

GPIA27

GPIA19

GPIA23

GPIA26

IRQ18

IRQ19

TXD1

IRQ23

TXCLK or REFCLK

RX_ER

IRQ26

H8BIT

reserved

MDC

V

DDM

Y2

GND

Y3

A9

A1

Y4

Y5

A0

Y6

A4

Y7

BA1

Y8

reserved

GPIA11

NMI

reserved

Y9

BM1

GPIC15

GPOC15

GPOA11

GPOA9

GPOA6

GPOA5

EVNT3

T0RCK

T0RD

Y10

Y11

Y12

Y13

IRQ4

GPIA9

GPIA6

T0TD

GPIA5

IRQ0

T1RCK

MSC7119 Data Sheet, Rev. 8

16

Freescale Semiconductor

Electrical Characteristics

Hardware Controlled

Table 1. MSC7119 Signals by Ball Designator (continued)

Signal Names

Software Controlled

Number

End of Reset

GPI Enabled

(Default)

Interrupt

Enabled

GPO Enabled

Primary

Alternate

Y14

Y15

Y16

Y17

Y18

Y19

Y20

GPIA2

IRQ9

GPOA2

GPOA29

GPOD5

GPOA20

GPOA21

T1TCK

GPIA29

IRQ16

TXD3

reserved

GPID5

RXCLK

GPIA20

GPIA21

IRQ20

IRQ21

TXD0

RXD1

GND

GPIA25

IRQ25

GPOA25

RX_DV or CRS_DV

2

Electrical Characteristics

This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing

specifications. For additional information, see the MSC711x Reference Manual.

2.1

Maximum Ratings

CAUTION

This device contains circuitry protecting against damage

due to high static voltage or electrical fields; however,

normal precautions should be taken to avoid exceeding

maximum voltage ratings. Reliability is enhanced if unused

inputs are tied to an appropriate logic voltage level (for

example, either GND or V ).

DD

In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification

does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values

in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction.

Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another

specification; adding a maximum to a minimum represents a condition that can never exist.

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

17

Electrical Characteristics

Table 2 describes the maximum electrical ratings for the MSC7119.

Table 2. Absolute Maximum Ratings

Symbol

Rating

Value

Unit

Core supply voltage

Memory supply voltage

PLL supply voltage

I/O supply voltage

Input voltage

V

1.5

V

DDC

DDM

4.0

1.5

V

DDPLL

V

–0.2 to 4.0

(GND – 0.2) to 4.0

4.0

V

DDIO

V

IN

Reference voltage

V

REF

Maximum operating temperature

T

105

°C

J

Minimum operating temperature

T

–40

A

Storage temperature range

T

–55 to +150

STG

Notes: 1. Functional operating conditions are given in Table 3.

2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond

the listed limits may affect device reliability or cause permanent damage.

3. Section 3.1, Thermal Design Considerations includes a formula for computing the chip junction temperature (T ).

J

2.2

Recommended Operating Conditions

Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed.

Table 3. Recommended Operating Conditions

Rating

Symbol

Value

Unit

Core supply voltage

Memory supply voltage

PLL supply voltage

V

1.14 to 1.26

2.38 to 2.63

1.14 to 1.26

3.14 to 3.47

1.19 to 1.31

V

DDC

DDM

V

DDPLL

I/O supply voltage

V

DDIO

Reference voltage

V

REF

Operating temperature range

T

maximum: 105

minimum: –40

°C

J

T

A

MSC7119 Data Sheet, Rev. 8

18

Freescale Semiconductor

Electrical Characteristics

2.3

Thermal Characteristics

Table 4 describes thermal characteristics of the MSC7119 for the MAP-BGA package.

Table 4. Thermal Characteristics for MAP-BGA Package

^{MAP-BGA 17}× 17 mm⁵

Characteristic

Symbol

Unit

Natural

200 ft/min

Convection

(1 m/s) airflow

1, 2

Junction-to-ambient

R

39

23

12

7

31

20

°C/W

θJA

θJB

θJC

1, 3

Junction-to-ambient, four-layer board

4

Junction-to-board

5

Junction-to-case

6

Junction-to-package-top

Ψ

2

JT

Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature

per JEDEC JESD51-2.

Section 3.1, Thermal Design Considerations explains these characteristics in detail.

2.4

DC Electrical Characteristics

This section describes the DC electrical characteristics for the MSC7119.

Note: The leakage current is measured for nominal voltage values must vary in the same direction (for example, both V_DDIO

and V_DDCvary by +2 percent or both vary by –2 percent).

Table 5. DC Electrical Characteristics

Characteristic

Symbol

Min

Typical

Max

Unit

Core and PLL voltage

V

1.14

1.2

1.26

V

DDC

V

DDPLL

1

DRAM interface I/O voltage

I/O voltage

V

2.375

3.135

2.5

3.3

2.625

3.465

V

DDM

V

DDIO

2

DRAM interface I/O reference voltage

V

0.49 × V

1.25

0.51 × V

DDM

V

REF

DDM

3

DRAM interface I/O termination voltage

Input high CLKIN voltage

VTT

V

– 0.04

V

V + 0.04

REF

V

REF

V

2.4

3.0

3.465

V + 0.3

DDM

V

IHCLK

DRAM interface input high I/O voltage

DRAM interface input low I/O voltage

V

+ 0.28

V

IHM

DDM

V

–0.3

GND

V

– 0.18

REF

V

ILM

Input leakage current, V = V

I

–1.0

—

0.09

—

1

µA

IN

DDIO

IN

V

input leakage current

I

5

REF

VREF

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

19

Electrical Characteristics

Table 5. DC Electrical Characteristics (continued)

Characteristic

Symbol

Min

Typical

Max

Unit

Tri-state (high impedance off state) leakage current,

= V

I

–1.0

0.09

1

µA

OZ

V

IN

DDIO

Signal low input current, V = 0.4 V

I

–1.0

2.0

—

0.09

3.0

1

µA

V

IL

L

Signal high input current, V = 2.0 V

I

IH

H

Output high voltage, I = –2 mA, except open drain pins

V

—

0.4

—

OH

Output low voltage, I = 5 mA

V

0

V

OL

5

Typical power at 300 MHz

P

—

324.0

mW

Notes: 1. The value of V

at the MSC7119 device must remain within 50 mV of V

at the DRAM device at all times.

DDM

2.

V

must be equal to 50% of V

and track V

variations as measured at the receiver. Peak-to-peak noise must not

REF

DDM

exceed ±2% of the DC value.

is not applied directly to the MSC7119 device. It is the level measured at the far end signal termination. It should be equal

3.

V

TT

to V

. This rail should track variations in the DC level of V

.

REF

4. Output leakage for the memory interface is measured with all outputs disabled, 0 V ≤ V

≤ V

.

DDM

OUT

5. The core power values were measured.using a standard EFR pattern at typical conditions (25°C, 300 MHz, 1.2 V core).

Table 6 lists the DDR DRAM capacitance.

Table 6. DDR DRAM Capacitance

Parameter/Condition

Symbol

Max

Unit

Input/output capacitance: DQ, DQS

Delta input/output capacitance: DQ, DQS

Note: These values were measured under the following conditions:

C

30

pF

IO

C

DIO

• V = 2.5 V ± 0.125 V

DDM

• f = 1 MHz

• T = 25°C

A

• V

= V

/2

OUT

DDM

(peak to peak) = 0.2 V

MSC7119 Data Sheet, Rev. 8

20

Freescale Semiconductor

Electrical Characteristics

2.5

AC Timings

This section presents timing diagrams and specifications for individual signals and parallel I/O outputs and inputs. All AC

timings are based on a 30 pF load, except where noted otherwise, and a 50 Ω transmission line. For any additional pF, use the

following equations to compute the delay:

— Standard interface: 2.45 + (0.054 × C_load) ns

— DDR interface: 1.6 + (0.002 × C_load) ns

2.5.1

Clock and Timing Signals

The following tables describe clock signal characteristics. Table 6 shows the maximum frequency values for internal (core,

reference, and peripherals) and external (CLKO) clocks. You must ensure that maximum frequency values are not exceeded (see

Section 2.5.2 for the allowable ranges when using the PLL).

Table 6. Maximum Frequencies

Characteristic

Maximum in MHz

Core clock frequency (CLOCK)

300

75

External output clock frequency (CLKO)

Memory clock frequency (CK, CK)

150

50

TDM clock frequency (TxRCK, TxTCK)

Table 7. Clock Frequencies in MHz

Characteristic Symbol

Min

Max

CLKIN frequency

F

10

—

100

300

150

50

CLKIN

CORE

CLOCK frequency

CK, CK frequency

F

CK

TDMxRCK, TDMxTCK frequency

CLKO frequency

F

TDMCK

F

75

CKO

BCK

AHB/IPBus/APB clock frequency

F

150

Note:

The rise and fall time of external clocks should be 5 ns maximum

Table 8. System Clock Parameters

Min

Characteristic

Max

Unit

CLKIN frequency

CLKIN slope

10

—

100

5

MHz

ns

CLKIN frequency jitter (peak-to-peak)

CLKO frequency jitter (peak-to-peak)

1000

150

ps

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

21

Electrical Characteristics

2.5.2

Configuring Clock Frequencies

This section describes important requirements for configuring clock frequencies in the MSC7119 device when using the PLL

block. To configure the device clocking, you must program four fields in the Clock Control Register (CLKCTL):

•

PLLDVF field. Specifies the PLL division factor (PLLDVF + 1) to divide the input clock frequency F_CLKIN. The output

of the divider block is the input to the multiplier block.

PLLMLTF field. Specifies the PLL multiplication factor (PLLMLTF + 1). The output from the multiplier block is the

loop frequency F_LOOP

.

RNG field. Selects the available PLL frequency range for F_VCO, either F_LOOPwhen the RNG bit is set (1) or F_LOOP/2

when the RNG bit is cleared (0).

CKSEL field. Selects F_CLKIN, F_VCO, or F_VCO/2 as the source for the core clock.

There are restrictions on the frequency range permitted at the beginning of the multiplication portion of the PLL that affect the

allowable values for the PLLDVF and PLLMLTF fields. The following sections define these restrictions and provide guidelines

to configure the device clocking when using the PLL. Refer to the Clock and Power Management chapter in the MSC711x

Reference Manual for details on the clock programming model.

2.5.2.1

PLL Multiplier Restrictions

There are two restrictions for correct usage of the PLL block:

•

The input frequency to the PLL multiplier block (that is, the output of the divider) must be in the range 10–25 MHz.

The output frequency of the PLL multiplier must be in the range 266–532 MHz.

When programming the PLL for a desired output frequency using the PLLDVF, PLLMLTF, and RNG fields, you must meet

these constraints.

2.5.2.2

Input Division Factors and Corresponding CLKIN Frequency Range

The value of the PLLDVF field determines the allowable CLKIN frequency range, as shown in Table 9.

Table 9. CLKIN Frequency Ranges by Divide Factor Value

PLLDVF

Field Value

Input Divide

Factor

CLKIN Frequency Range

Comments

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

1

2

10 to 25 MHz

20 to 50 MHz

30 to 75 MHz

40 to 100 MHz

50 to 100 MHz

60 to 100 MHz

70 to 100 MHz

80 to 100 MHz

90 to 100 MHz

100 MHz

Input Division by 1

Input Division by 2

Input Division by 3

Input Division by 4

Input Division by 5

Input Division by 6

Input Division by 7

Input Division by 8

Input Division by 9

Input Division by 10

3

4

5

6

7

8

9

10

Note:

The maximum CLKIN frequency is 100 MHz. Therefore, the PLLDVF value must be in the range from 1–10.

MSC7119 Data Sheet, Rev. 8

22

Freescale Semiconductor

Electrical Characteristics

2.5.2.3

Multiplication Factor Range

The multiplier block output frequency ranges depend on the divided input clock frequency as shown in Table 10.

Table 10. PLLMLTF Ranges

Multiplier Block (Loop) Output Range

Minimum PLLMLTF Value Maximum PLLMLTF Value

266 ≤ [Divided Input Clock × (PLLMLTF + 1)] ≤ 532 MHz

266/Divided Input Clock

532/Divided Input Clock

Note:

This table results from the allowed range for F . The minimum and maximum multiplication factors are dependent on the

Loop

frequency of the Divided Input Clock.

2.5.2.4

Allowed Core Clock Frequency Range

The frequency delivered to the core, extended core, and peripherals depends on the value of the CLKCTRL[RNG] bit as shown

in Table 11.

Table 11. F_vcoFrequency Ranges

CLKCTRL[RNG] Value

Allowed Range of F_vco

1

0

266 ≤ F

133 ≤ F

≤ 532 MHz

≤ 266 MHz

vco

Note:

This table results from the allowed range for F , which is F

modified by CLKCTRL[RNG].

Loop

vco

This bit along with the CKSEL determines the frequency range of the core clock.

Table 12. Resulting Ranges Permitted for the Core Clock

Resulting

Division

Factor

Allowed Range

of Core Clock

CLKCTRL[CKSEL]

CLKCTRL[RNG]

Comments

11

1

266 ≤ core clock ≤ 300 MHz

Limited by maximum core

frequency

11

01

0

1

0

2

4

133 ≤ core clock ≤ 266 MHz

66.5 ≤ core clock ≤ 133 MHz

Limited by range of PLL

Note:

This table results from the allowed range for F

, which depends on clock selected via CLKCTRL[CKSEL].

OUT

2.5.2.5

Core Clock Frequency Range When Using DDR Memory

The core clock can also be limited by the frequency range of the DDR devices in the system. Table 13 summarizes this

restriction.

Table 13. Core Clock Ranges When Using DDR

Allowed Frequency

Range for DDR CK

Corresponding Range

for the Core Clock

DDR Type

Comments

DDR 200 (PC-1600)

DDR 266 (PC-2100)

DDR 333 (PC-2600)

83–100 MHz

83–133 MHz

83–150 MHz

166 ≤ core clock ≤ 200 MHz

166 ≤ core clock ≤ 266 MHz

166 ≤ core clock ≤ 300 MHz

Core limited to 2 × maximum DDR frequency

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

23

Electrical Characteristics

2.5.3

Reset Timing

The MSC7119 device has several inputs to the reset logic. All MSC7119 reset sources are fed into the reset controller, which

takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause

a reset. Table 14 describes the reset sources.

Table 14. Reset Sources

Name

Direction

Description

Power-on reset

(PORESET)

Input

Initiates the power-on reset flow that resets the MSC7119 and configures various attributes of the

MSC7119. On PORESET, the entire MSC7119 device is reset. SPLL and DLL states are reset,

HRESET is driven, the SC1400 extended core is reset, and system configuration is sampled. The

system is configured only when PORESET is asserted.

External Hard

reset (HRESET)

Input/ Output

Initiates the hard reset flow that configures various attributes of the MSC7119. While HRESET is

asserted, HRESET is an open-drain output. Upon hard reset, HRESET is driven and the SC1400

extended core is reset.

Software

watchdog reset

Internal

When the MSC7119 watchdog count reaches zero, a software watchdog reset is signalled. The

enabled software watchdog event then generates an internal hard reset sequence.

Bus monitor

reset

When the MSC7119 bus monitor count reaches zero, a bus monitor hard reset is asserted. The

enabled bus monitor event then generates an internal hard reset sequence.

JTAG EXTEST,

CLAMP, or

When a Test Access Port (TAP) executes an EXTEST, CLAMP, or HIGHZ command, the TAP logic

asserts an internal reset signal that generates an internal soft reset sequence.

HIGHZ command

Table 15 summarizes the reset actions that occur as a result of the different reset sources.

Table 15. Reset Actions for Each Reset Source

Power-On Reset

(PORESET)

Hard Reset

(HRESET)

Soft Reset

(SRESET)

Reset Action/Reset Source

External or

Internal (Software

Watchdog or Bus

Monitor)

JTAG Command:

EXTEST, CLAMP,

or HIGHZ

External only

Configuration pins sampled (refer to Section 2.5.3.1 for

details).

Yes

No

PLL and clock synthesis states Reset

HRESET Driven

Yes

No

Yes

Software watchdog and bus time-out monitor registers

Yes

Clock synthesis modules (STOPCTRL, HLTREQ, and

HLTACK) reset

Extended core reset

Yes

Peripheral modules reset

2.5.3.1

Power-On Reset (PORESET) Pin

Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after

external power to the MSC7119 reaches at least 2/3 V_DD

.

MSC7119 Data Sheet, Rev. 8

24

Freescale Semiconductor

Electrical Characteristics

2.5.3.2

Reset Configuration

The MSC7119 has two mechanisms for writing the reset configuration:

•

From a host through the host interface (HDI16)

From memory through the I²C interface

Five signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the boot and

operating conditions:

•

BM[0–1]

SWTE

H8BIT

HDSP

2.5.3.3

Reset Timing Tables

Table 16 and Figure 4 describe the reset timing for a reset configuration write.

Table 16. Timing for a Reset Configuration Write

No.

Characteristics

Expression

Unit

1

2

Required external PORESET duration minimum

16/F

clocks

CLKIN

Delay from PORESET deassertion to HRESET deassertion

Timings are not tested, but are guaranteed by design.

521/F

CLKIN

Note:

1

PORESET

Input

Configuration Pins

are sampled

PORESET

Internal

HRESET

Output(I/O)

2

Figure 4. Timing Diagram for a Reset Configuration Write

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

25

Electrical Characteristics

2.5.4

DDR DRAM Controller Timing

This section provides the AC electrical characteristics for the DDR DRAM interface.

2.5.4.1

DDR DRAM Input AC Timing Specifications

Table 17 provides the input AC timing specifications for the DDR DRAM interface.

Table 17. DDR DRAM Input AC Timing

No.

Parameter

Symbol

Min

Max

Unit

—

AC input low voltage

AC input high voltage

V

—

V

– 0.31

V

IL

REF

V

+ 0.31

V

+ 0.3

IH

REF

DDM

201

202

Maximum Dn input setup skew relative to DQSn input

Maximum Dn input hold skew relative to DQSn input

—

900

ps

—

Notes: 1. Maximum possible skew between a data strobe (DQSn) and any corresponding bit of data (D[8n + {0...7}] if 0 ≤ n ≤ 7).

2. See Table 18 for t value.

CK

3. Dn should be driven at the same time as DQSn. This is necessary because the DQSn centering on the DQn data tenure is

done internally.

DQSn

202

D1

D0

Dn

201

Note: DQS centering is done internally.

Figure 5. DDR DRAM Input Timing Diagram

2.5.4.2

DDR DRAM Output AC Timing Specifications

Table 18 and Table 19 list the output AC timing specifications and measurement conditions for the DDR DRAM

interface.

Table 18. DDR DRAM Output AC Timing

No.

Parameter

Symbol

Min

Max

Unit

1

200

CK cycle time, (CK/CK crossing)

t

CK

•

100 MHz (DDR200)

150 MHz (DDR300)

10

6.67

—

ns

204

205

206

207

208

An/RAS/CAS/WE/CKE output setup with respect to CK

An/RAS/CAS/WE/CKE output hold with respect to CK

CSn output setup with respect to CK

t

0.5 × t – 1000

—

ps

DDKHAS

CK

0.5 × t – 1000

DDKHAX

CK

0.5 × t – 1000

—

DDKHCS

DDKHCX

DDKHMH

CK

CSn output hold with respect to CK

t

0.5 × t – 1000

—

CK

2

CK to DQSn

t

–600

600

MSC7119 Data Sheet, Rev. 8

26

Freescale Semiconductor

Electrical Characteristics

Table 18. DDR DRAM Output AC Timing (continued)

No.

Parameter

Symbol

Min

Max

Unit

3

209

Dn/DQMn output setup with respect to DQSn

t

0.25 × t – 750

—

ps

DDKHDS,

CK

t

DDKLDS

3

210

Dn/DQMn output hold with respect to DQSn

t

0.25 × t – 750

—

ps

DDKHDX,

CK

t

DDKLDX

DDKHMP

DDKHME

4

211

212

DQSn preamble start

t

–0.25 × t

—

ps

CK

5

DQSn epilogue end

–600

600

Notes: 1. All CK/CK referenced measurements are made from the crossing of the two signals ±0.1 V.

2. can be modified through the TCFG2[WRDD] DQSS override bits. The DRAM requires that the first write data strobe

t

DDKHMH

arrives 75–125% of a DRAM cycle after the write command is issued. Any skew between DQSn and CK must be considered

when trying to achieve this 75%–125% goal. The TCFG2[WRDD] bits can be used to shift DQSn by 1/4 DRAM cycle

increments. The skew in this case refers to an internal skew existing at the signal connections. By default, the CK/CK crossing

occurs in the middle of the control signal (An/RAS/CAS/WE/CKE) tenure. Setting TCFG2[ACSM] bit shifts the control signal

assertion 1/2 DRAM cycle earlier than the default timing. This means that the signal is asserted no earlier than 600 ps before

the CK/CK crossing and no later than 600 ps after the crossing time; the device uses 1200 ps of the skew budget (the interval

from –600 to +600 ps). Timing is verified by referencing the falling edge of CK. See Chapter 10 of the MSC711x Reference

Manual for details.

3. Determined by maximum possible skew between a data strobe (DQS) and any corresponding bit of data. The data strobe

should be centered inside of the data eye.

4. Please note that this spec is in reference to the DQSn first rising edge. It could also be referenced from CK(r), but due to

programmable delay of the write strobes (TCFG2[WRDD]), there pre-amble may be extended for a full DRAM cycle. For this

reason, we reference from DQSn.

5. All outputs are referenced to the rising edge of CK. Note that this is essentially the CK/DQSn skew in spec 208. In addition

there is no real “maximum” time for the epilogue end. JEDEC does not require this is as a device limitation, but simply for the

chip to guarantee fast enough write-to-read turn-around times. This is already guaranteed by the memory controller operation.

Figure 6 shows the DDR DRAM output timing diagram.

CK

200

204

205

206

An

RAS

207

CAS

WE

CKE

Write A0

NOOP

211

DQMn

208

DQSn

Dn

212

209

D0

D1

210

Figure 6. DDR DRAM Output Timing Diagram

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

27

Electrical Characteristics

Figure 7 provides the AC test load for the DDR DRAM bus.

Output

V_OUT

Z₀= 50 Ω

R_L= 50 Ω

Figure 7. DDR DRAM AC Test Load

Table 19. DDR DRAM Measurement Conditions

Symbol

DDR DRAM

Unit

1

V

± 0.31 V

REF

V

TH

2

0.5 × V

OUT

DDM

Notes: 1. Data input threshold measurement point.

2. Data output measurement point.

2.5.5

TDM Timing

Table 20. TDM Timing

Expression

No.

Characteristic

Min

Max

Units

300

301

302

303

304

305

306

307

308

309

310

311

TDMxRCK/TDMxTCK

TC

20.0

8.0

3.0

3.5

2.0

4.0

—

ns

TDMxRCK/TDMxTCK High Pulse Width

TDMxRCK/TDMxTCK Low Pulse Width

TDM all input Setup time

0.4 × TC

—

TDMxRD Hold time

—

TDMxTFS/TDMxRFS input Hold time

TDMxTCK High to TDMxTD output active

TDMxTCK High to TDMxTD output valid

TDMxTD hold time

—

14.0

—

2.0

—

TDMxTCK High to TDMxTD output high impedance

TDMxTFS/TDMxRFS output valid

TDMxTFS/TDMxRFS output hold time

10.0

13.5

—

2.5

Notes: 1. Output values are based on 30 pF capacitive load.

2. Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming edge

they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. Refer to the MSC711x

Reference Manual for details. TDMxTCK and TDMxRCK are shown using the rising edge.

300

302

301

304

TDMxRCK

TDMxRD

303

305

303

TDMxRFS

310

311

TDMxRFS (output)

Figure 8. TDM Receive Signals

MSC7119 Data Sheet, Rev. 8

28

Freescale Semiconductor

Electrical Characteristics

300

302

301

TDMxTCK

309

308

307

306

TDMxTD

TDMxRCK

310

311

TDMxTFS (output)

TDMxTFS (input)

305

303

Figure 9. TDM Transmit Signals

2.5.6

Ethernet Timing

Receive Signal Timing

2.5.6.1

Table 21. Receive Signal Timing

Characteristics

No.

Min

Max

Unit

800

Receive clock period:

• MII: RXCLK (max frequency = 25 MHz)

• RMII: REFCLK (max frequency = 50 MHz)

40

20

—

ns

801

802

Receive clock pulse width high—as a percent of clock period

• MII: RXCLK

• RMII: REFCLK

35

14

7

65

—

%

ns

Receive clock pulse width low—as a percent of clock period:

• MII: RXCLK

• RMII: REFCLK

35

14

7

65

—

%

ns

803

804

RXDn, RX_DV, CRS_DV, RX_ER to receive clock rising edge setup time

Receive clock rising edge to RXDn, RX_DV, CRS_DV, RX_ER hold time

4

2

—

ns

800

802

801

Receive

clock

803

804

RXDn

RX_DV

CRS_DV

RX_ER

Valid

Figure 10. Ethernet Receive Signal Timing

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

29

Electrical Characteristics

2.5.6.2

Transmit Signal Timing

Table 22. Transmit Signal Timing

Characteristics

No.

Min

Max

Unit

800

Transmit clock period:

• MII: TXCLK

40

20

—

ns

• RMII: REFCLK

801

802

Transmit clock pulse width high—as a percent of clock period

• MII: RXCLK

• RMII: REFCLK

35

14

7

65

—

%

ns

Transmit clock pulse width low—as a percent of clock period:

• MII: RXCLK

• RMII: REFCLK

35

14

7

65

—

%

ns

805

806

Transmit clock to TXDn, TX_EN, TX_ER invalid

Transmit clock to TXDn, TX_EN, TX_ER valid

4

—

ns

—

14

800

802

801

Transmit

clock

806

805

TXDn

TX_EN

TX_ER

Valid

Figure 11. Ethernet Receive Signal Timing

2.5.6.3

Asynchronous Input Signal Timing

Table 23. Asynchronous Input Signal Timing

Characteristics

No.

Min

Max

Unit

807

• MII: CRS and COL minimum pulse width (1.5 × TXCLK period)

• RMII: CRS_DV minimum pulse width (1.5 x REFCLK period)

60

30

—

ns

CRS

COL

807

CRS_DV

Figure 12. Asynchronous Input Signal Timing

MSC7119 Data Sheet, Rev. 8

30

Freescale Semiconductor

Electrical Characteristics

2.5.6.4

Management Interface Timing

Table 24. Ethernet Controller Management Interface Timing

Characteristics

No.

Min

Max

Unit

808

809

810

811

812

813

814

MDC period

400

160

0

—

15

—

ns

MDC pulse width high

MDC pulse width low

MDS falling edge to MDIO output invalid (minimum propagation delay)

MDS falling edge to MDIO output valid (maximum propagation delay)

MDIO input to MDC rising edge setup time

—

10

MDC rising edge to MDIO input hold time

10

808

809

810

MDC (output)

MDIO (output)

811

812

813

814

MDIO (input)

Figure 13. Serial Management Channel Timing

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

31

Electrical Characteristics

2.5.7

HDI16 Signals

Table 25. Host Interface (HDI16) Timing^{1, 2}

No.

Characteristics³

Expression

Value

Unit

40

Host Interface Clock period

T

Note 1

ns

CORE

4

44a

Read data strobe minimum assertion width

HACK read minimum assertion width

2.0 × T

+ 9.0

Note 11

CORE

4

44b

44c

Read data strobe minimum deassertion width

HACK read minimum deassertion width

1.5 × T

Note 11

ns

CORE

Read data strobe minimum deassertion width after “Last Data Register”

2.5 × T

1.5 × T

CORE

5,6

7

reads , or between two consecutive CVR, ICR, or ISR reads

HACK minimum deassertion width after “Last Data Register” reads

5,6

8

45

46

Write data strobe minimum assertion width

Note 11

ns

HACK write minimum assertion width

8

Write data strobe minimum deassertion width

HACK write minimum deassertion width after ICR, CVR and Data Register

5

writes

2.5 × T

—

Note 11

2.5

ns

CORE

8

47

48

49

Host data input minimum setup time before write data strobe deassertion

Host data input minimum setup time before HACK write deassertion

8

Host data input minimum hold time after write data strobe deassertion

Host data input minimum hold time after HACK write deassertion

—

2.5

Read data strobe minimum assertion to output data active from high

impedance

4

HACK read minimum assertion to output data active from high impedance

—

1.0

Note 11

9.0

ns

4

50

51

52

Read data strobe maximum assertion to output data valid

HACK read maximum assertion to output data valid

(2.0 × T

) + 8.0

CORE

4

Read data strobe maximum deassertion to output data high impedance

HACK read maximum deassertion to output data high impedance

—

4

Output data minimum hold time after read data strobe deassertion

Output data minimum hold time after HACK read deassertion

—

1.0

0.5

ns

4

53

54

55

56

57

58

61

HCS[1–2] minimum assertion to read data strobe assertion

8

HCS[1–2] minimum assertion to write data strobe assertion

0.0

HCS[1–2] maximum assertion to output data valid

(2.0 × T

(3.0 × T

) + 6.0

Note 11

0.5

CORE

9

HCS[1–2] minimum hold time after data strobe deassertion

—

9

HA[0–2], HRW minimum setup time before data strobe assertion

—

5.0

9

HA[0–2], HRW minimum hold time after data strobe deassertion

5.0

Maximum delay from read data strobe deassertion to host request

Note 11

CORE

4, 5, 10

deassertion for “Last Data Register” read

62

63

64

Maximum delay from write data strobe deassertion to host request

deassertion for “Last Data Register” write

5,8,10

(3.0 × T

(2.0 × T

(5.0 × T

) + 6.0

) + 1.0

) + 6.0

Note 11

ns

CORE

Minimum delay from DMA HACK (OAD=0) or Read/Write data

strobe(OAD=1) deassertion to HREQ assertion.

Maximum delay from DMA HACK (OAD=0) or Read/Write data

strobe(OAD=1) assertion to HREQ deassertion

Notes: 1.

2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.

3. = 3.3 V ± 0.15 V; T = –40°C to +105 °C, C = 30 pF for maximum delay timings and C = 0 pF for minimum delay timings.

T

= core clock period. At 300 MHz, T

= 3.333 ns.

CORE

V

DD

J

L

4. The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode.

5. For 64-bit transfers, the “last data register” is the register at address 0x7, which is the last location to be read or written in data

transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1).

6. This timing is applicable only if a read from the “last data register” is followed by a read from the RX[0–3] registers without first

polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal.

7. This timing is applicable only if two consecutive reads from one of these registers are executed.

8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.

9. The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe

(HDS/HDS) in the single data strobe mode.

10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host

request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full

11. Compute the value using the expression.

12. The read and write data strobe minimum deassertion width for non-”last data register” accesses in single and dual data strobe

modes is based on timings 57 and 58.

MSC7119 Data Sheet, Rev. 8

32

Freescale Semiconductor

Figure 14 and Figure 15 show HDI16 read signal timing. Figure 16 and Figure 17 show HDI16 write signal timing.

HA[0–2]

57

58

56

53

HCS[1–2]

57

58

HRW

HDS

44a

44b

51

55

50

44c

52

49

HD[0–15]

61

HREQ (single host request)

HRRQ (double host request)

Figure 14. Read Timing Diagram, Single Data Strobe

HA[0–2]

57

58

56

53

HCS[1–2]

HRD

44a

44b

51

55

44a

50

52

49

HD[0–15]

61

HREQ (single host request)

HRRQ (double host request)

Figure 15. Read Timing Diagram, Double Data Strobe

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

33

HA[0–2]

57

58

56

54

HCS[1–2]

HRW

57

58

45

HDS

46

47

48

HD[0–15]

62

HREQ (single host request)

HTRQ (double host request)

Figure 16. Write Timing Diagram, Single Data Strobe

HA[0–2]

57

58

56

54

HCS[1–2]

HWR

45

46

48

47

HD[0–15]

62

HREQ (single host request)

HTRQ (double host request)

Figure 17. Write Timing Diagram, Double Data Strobe

MSC7119 Data Sheet, Rev. 8

34

Freescale Semiconductor

HREQ

(Output)

63

64

44a

44b

RX[0–3]

Read

HACK

51

50

49

52

Data

Valid

HD[0–15]

(Output)

Figure 18. Host DMA Read Timing Diagram, HPCR[OAD] = 0

HREQ

(Output)

63

64

46

45

TX[0–3]

Write

HACK

47

48

Data

Valid

HD[0–15]

(Input)

Figure 19. Host DMA Write Timing Diagram, HPCR[OAD] = 0

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

35

2

2.5.8

I C Timing

Table 26. I²C Timing

Fast

No.

Characteristic

Unit

Min

Max

450

451

452

453

454

455

456

457

458

459

460

Note:

SCL clock frequency

0

400

—

kHz

μs

ns

μs

Hold time START condition

SCL low period

(SCL clock period/2) – 0.3

(SCL clock period/2) – 0.1

—

SCL high period

—

Repeated START set-up time (not shown in figure)

Data hold time

2 × 1/F

—

BCK

0

—

Data set-up time

250

—

SDA and SCL rise time

SDA and SCL fall time

Set-up time for STOP

—

700

300

—

(SCL clock period/2) – 0.7

(SCL clock period/2) – 0.3

Bus free time between STOP and START

—

SDA set-up time is referenced to the rising edge of SCL. SDA hold time is referenced to the falling edge of SCL. Load capacitance

on SDA and SCL is 400 pF.

453

458

3

457

Start Condition

Stop Condition

Start Condition

1

4

5

6

SCL

SDA

2

7

8

9

A

C

K

452

451

Data Byte

457

460

458

459

Start Condition

SCL

SDA

Data Byte

Figure 20. I²C Timing Diagram

MSC7119 Data Sheet, Rev. 8

36

Freescale Semiconductor

2.5.9

UART Timing

Table 27. UART Timing

Expression

No.

Characteristics

Min

Max

Unit

—

Internal bus clock (APBCLK)

F

/2

—

6.67

106.67

—

150

—

5

MHz

ns

CORE

Internal bus clock period (1/APBCLK)

URXD and UTXD inputs high/low duration

URXD and UTXD inputs rise/fall time

UTXD output rise/fall time

T

APBCLK

400

401

402

16 × T

ns

APBCLK

ns

—

5

ns

401

UTXD, URXD

inputs

400

Figure 21. UART Input Timing

402

UTXD Output

Figure 22. UART Output Timing

2.5.10 EE Timing

Table 28. EE0 Timing

Type

Number

Characteristics

Min

65

66

EE0 input to the core

Asynchronous

4 core clock periods

1 core clock period

EE0 output from the core

Synchronous to core clock

Notes: 1. The core clock is the SC1400 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.

2. Configure the direction of the EE pin in the EE_CTRL register (see the SC140/SC1400 Core Reference Manual for details.

3. Refer to Table 1-11 on page 1-16 for details on EE pin functionality.

Figure 24 shows the signal behavior of the EE pin.

65

EE0 In

66

EE0 Out

Figure 23. EE Pin Timing

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

37

2.5.11 Event Timing

Table 29. EVNT Signal Timing

Type

Number

Characteristics

Min

67

68

EVNT as input

EVNT as output

Asynchronous

1.5 × APBCLK periods

1 APBCLK period

Synchronous to core clock

Notes: 1. Refer to Table 27 for a definition of the APBCLK period.

2. Direction of the EVNT signal is configured through the GPIO and Event port registers.

3. Refer to the signal chapter in the MSC711x Reference Manual for details on EVNT pin functionality.

Figure 24 shows the signal behavior of the EVNT pins.

67

EVNT in

68

EVNT out

Figure 24. EVNT Pin Timing

2.5.12 GPIO Timing

Table 30. GPIO Signal Timing^1,2,3

Number

Characteristics

Type

Min

4.5

5

601

602

603

604

GPI

Asynchronous

Synchronous to core clock

Asynchronous

1.5 × APBCLK periods

1 APBCLK period

GPO

Port A edge-sensitive interrupt

Port A level-sensitive interrupt

1.5 × APBCLK periods

6

Asynchronous

3 × APBCLK periods

Notes: 1. Refer to Table 27 for a definition of the APBCLK period.

2. Direction of the GPIO signal is configured through the GPIO port registers.

3. Refer to Section 1.5 for details on GPIO pin functionality.

4. GPI data is synchronized to the APBCLK internally and the minimum listed is the capability of the hardware to capture data

into a register when the GPADR is read. The specification is not tested due to the asynchronous nature of the input and

dependence on the state of the DSP core. It is guaranteed by design.

5. The output signals cannot toggle faster than 75 MHz.

6. Level-sensitive interrupts should be held low until the system determines (via the service routine) that the interrupt is

acknowledged.

Figure 25 shows the signal behavior of the GPI/GPO pins.

601

GPI

602

GPO

Figure 25. GPI/GPO Pin Timing

MSC7119 Data Sheet, Rev. 8

38

Freescale Semiconductor

2.5.13 JTAG Signals

Table 31. JTAG Timing

All frequencies

No.

Characteristics

Unit

Min

Max

700

TCK frequency of operation (1/(T × 3)

0.0

40.0

MHz

C

Note:

T

= 1/CLOCK which is the period of the core clock. The TCK

C

frequency must less than 1/3 of the core frequency with an absolute

maximum limit of 40 MHz.

701

702

703

704

705

706

707

708

709

710

711

712

Note:

TCK cycle time

25.0

11.0

0.0

—

ns

TCK clock pulse width measured at V

TCK rise and fall times

1.6 V

M =

3.0

—

Boundary scan input data set-up time

Boundary scan input data hold time

TCK low to output data valid

TCK low to output high impedance

TMS, TDI data set-up time

TMS, TDI data hold time

5.0

14.0

0.0

—

20.0

—

0.0

5.0

14.0

0.0

—

TCK low to TDO data valid

TCK low to TDO high impedance

TRST assert time

24.0

10.0

—

0.0

100.0

All timings apply to OCE module data transfers as the OCE module uses the JTAG port as an interface.

701

702

V

M

V

M

V

TCK

(Input)

IH

V

IL

703

Figure 26. Test Clock Input Timing Diagram

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

39

V

TCK

(Input)

IH

V

IL

704

705

Data

Inputs

Input Data Valid

706

707

Data

Outputs

Output Data Valid

Data

Outputs

Figure 27. Boundary Scan (JTAG) Timing Diagram

V

IH

TCK

(Input)

V

IL

709

708

Input Data Valid

TDI

TMS

(Input)

710

TDO

(Output)

Output Data Valid

711

TDO

(Output)

Figure 28. Test Access Port Timing Diagram

TRST

(Input)

712

Figure 29. TRST Timing Diagram

MSC7119 Data Sheet, Rev. 8

40

Freescale Semiconductor

Hardware Design Considerations

3

Hardware Design Considerations

This section described various areas to consider when incorporating the MSC7119 device into a system design.

3.1

Thermal Design Considerations

An estimation of the chip-junction temperature, T_J, in °C can be obtained from the following:

T_J= T_A+ (R _JA× P_D)

Eqn. 1

θ

where

T_A= ambient temperature near the package (°C)

R

_JA= junction-to-ambient thermal resistance (°C/W)

θ

P_D= P_INT+ P_I/O= power dissipation in the package (W)

P_INT= I_DD× V_DD= internal power dissipation (W)

P_I/O= power dissipated from device on output pins (W)

The power dissipation values for the MSC7119 are listed in Table 4. The ambient temperature for the device is the air

temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC

standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the

value determined on a single layer board and the value obtained on a board with two planes. The value that more closely

approximates a specific application depends on the power dissipated by other components on the printed circuit board (PCB).

The value obtained using a single layer board is appropriate for tightly packed PCB configurations. The value obtained using a

board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 W/cm²with natural

convection) and well separated components. Based on an estimation of junction temperature using this technique, determine

whether a more detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the

device thermal junction temperature below its maximum. If T_Jappears to be too high, either lower the ambient temperature or

the power dissipation of the chip.

You can verify the junction temperature by measuring the case temperature using a small diameter thermocouple (40 gauge is

recommended) or an infrared temperature sensor on a spot on the device case. Use the following equation to determine T_J:

^T_J^{= T}_T^{+ (}Ψ_JT× P_D)

Eqn. 2

where

T_T= thermocouple (or infrared) temperature on top of the package (°C)

_JT= thermal characterization parameter (°C/W)

P_D= power dissipation in the package (W)

Ψ

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

41

Hardware Design Considerations

3.2

Power Supply Design Considerations

This section outlines the MSC7119 power considerations: power supply, power sequencing, power planes, decoupling, power

supply filtering, and power consumption. It also presents a recommended power supply design and options for low-power

consumption. For information on AC/DC electrical specifications and thermal characteristics, refer to Section 2.

3.2.1

Power Supply

The MSC7119 requires four input voltages, as shown in Table 32.

Table 32. MSC7119 Voltages

Symbol

Voltage

Value

Core

V

1.2 V

2.5 V

1.25 V

3.3 V

DDC

DDM

Memory

Reference

I/O

V

REF

V

DDIO

You should supply the MSC7119 core voltage via a variable switching supply or regulator to allow for compatibility with

possible core voltage changes on future silicon revisions. The core voltage is supplied with 1.2 V (+5% and –10%) across V_DDC

and GND and the I/O section is supplied with 3.3 V (± 10%) across V_DDIOand GND. The memory and reference voltages supply

the DDR memory controller block. The memory voltage is supplied with 2.5 V across V_DDMand GND. The reference voltage

is supplied across V_REFand GND and must be between 0.49 × V_DDMand 0.51 × V_DDM. Refer to the JEDEC standard JESD8

(Stub Series Terminated Logic for 2.5 Volts (STTL_2)) for memory voltage supply requirements.

3.2.2

Power Sequencing

One consequence of multiple power supplies is that the voltage rails ramp up at different rates when power is initially applied.

The rates depend on the power supply, the type of load on each power supply, and the way different voltages are derived. It is

extremely important to observe the power up and power down sequences at the board level to avoid latch-up, forward biasing

of ESD devices, and excessive currents, which all lead to severe device damage.

Note: There are five possible power-up/power-down sequence cases. The first four cases listed in the following sections are

recommended for new designs. The fifth case is not recommended for new designs and must be carefully evaluated

for current spike risks based on actual information for the specific application.

MSC7119 Data Sheet, Rev. 8

42

Freescale Semiconductor

Hardware Design Considerations

3.2.2.1

Case 1

The power-up sequence is as follows:

1. Turn on the V_DDIO(3.3 V) supply first.

2. Turn on the V_DDC(1.2 V) supply second.

3. Turn on the V_DDM(2.5 V) supply third.

4. Turn on the V_REF(1.25 V) supply fourth (last).

The power-down sequence is as follows:

1. Turn off the V_REF(1.25 V) supply first.

2. Turn off the V_DDM(2.5 V) supply second.

3. Turn off the V_DDC(1.2 V) supply third.

4. Turn of the V_DDIO(3.3 V) supply fourth (last).

Use the following guidelines:

•

Make sure that the time interval between the ramp-down of V_DDIOand V_DDCis less than 10 ms.

Make sure that the time interval between the ramp-up or ramp-down for V_DDCand V_DDMis less than 10 ms for

power-up and power-down.

•

Refer to Figure 30 for relative timing for power sequencing case 1.

Ramp-down

Ramp-up

V_DDIO= 3.3 V

V_DDM= 2.5 V

V_REF= 1.25 V

V_DDC= 1.2 V

<10 ms

Time

Figure 30. Voltage Sequencing Case 1

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

43

Hardware Design Considerations

3.2.2.2

Case 2

The power-up sequence is as follows:

1. Turn on the V_DDIO(3.3 V) supply first.

2. Turn on the V_DDC(1.2 V) and V_DDM(2.5 V) supplies simultaneously (second).

3. Turn on the V_REF(1.25 V) supply last (third).

Note: Make sure that the time interval between the ramp-up of V_DDIOand V_DDC/V_DDMis less than 10 ms.

The power-down sequence is as follows:

1. Turn off the V_REF(1.25 V) supply first.

2. Turn off the V_DDM(2.5 V) supply second.

3. Turn off the V_DDC(1.2 V) supply third.

4. Turn of the V_DDIO(3.3 V) supply fourth (last).

Use the following guidelines:

•

Make sure that the time interval between the ramp-down for V_DDIOand V_DDCis less than 10 ms.

Make sure that the time interval between the ramp-up or ramp-down for V_DDCand V_DDMis less than 10 ms for

power-up and power-down.

•

Refer to Figure 31 for relative timing for Case 2.

Ramp-down

Ramp-up

V_DDIO= 3.3 V

V_DDM= 2.5 V

V_REF= 1.25 V

V_DDC= 1.2 V

<10 ms

Time

Figure 31. Voltage Sequencing Case 2

MSC7119 Data Sheet, Rev. 8

44

Freescale Semiconductor

Hardware Design Considerations

3.2.2.3

Case 3

The power-up sequence is as follows:

1. Turn on the V_DDIO(3.3 V) supply first.

2. Turn on the V_DDC(1.2 V) supply second.

3. Turn on the V_DDM(2.5 V) and V_REF(1.25 V) supplies simultaneously (third).

Note: Make sure that the time interval between the ramp-up of V_DDIOand V_DDCis less than 10 ms.

The power-down sequence is as follows:

1. Turn off the V_DDM(2.5 V) and V_REF(1.25 V) supplies simultaneously (first).

2. Turn off the V_DDC(1.2 V) supply second.

3. Turn of the V_DDIO(3.3 V) supply third (last).

Use the following guidelines:

•

Make sure that the time interval between the ramp-down for V_DDIOand V_DDCis less than 10 ms.

Make sure that the time interval between the ramp-up or ramp-down time for V_DDCand V_DDMis less than 10 ms for

power-up and power-down.

•

Refer to Figure 32 for relative timing for Case 3.

Ramp-down

Ramp-up

V_DDIO= 3.3 V

V_DDM= 2.5 V

V_REF= 1.25 V

V_DDC= 1.2 V

<10 ms

Time

Figure 32. Voltage Sequencing Case 3

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

45

Hardware Design Considerations

3.2.2.4

Case 4

The power-up sequence is as follows:

1. Turn on the V_DDIO(3.3 V) supply first.

2. Turn on the V_DDC(1.2 V), V_DDM(2.5 V), and V_REF(1.25 V) supplies simultaneously (second).

Note: Make sure that the time interval between the ramp-up of V_DDIOand V_DDCis less than 10 ms.

The power-down sequence is as follows:

1. Turn off the V_DDC(1.2 V), V_REF(1.25 V), and V_DDM(2.5 V) supplies simultaneously (first).

2. Turn of the V_DDIO(3.3 V) supply last.

Use the following guidelines:

•

Make sure that the time interval between the ramp-up or ramp-down time for V_DDCand V_DDMis less than 10 ms for

power-up and power-down.

•

Refer to Figure 33 for relative timing for Case 4.

Ramp-down

Ramp-up

V_DDIO= 3.3 V

V_DDM= 2.5 V

V_REF= 1.25 V

V_DDC= 1.2 V

<10 ms

Time

Figure 33. Voltage Sequencing Case 4

MSC7119 Data Sheet, Rev. 8

46

Freescale Semiconductor

Hardware Design Considerations

3.2.2.5

Case 5 (not recommended for new designs)

The power-up sequence is as follows:

1. Turn on the V_DDIO(3.3 V) supply first.

2. Turn on the V_DDM(2.5 V) supply second.

3. Turn on the V_DDC(1.2 V) supply third.

4. Turn on the V_REF(1.25 V) supply fourth (last).

Note: Make sure that the time interval between the ramp-up of V_DDIOand V_DDMis less than 10 ms.

The power-down sequence is as follows:

1. Turn off the V_REF(1.25 V) supply first.

2. Turn off the V_DDC(1.2 V) supply second.

3. Turn off the V_DDM(2.5 V) supply third.

4. Turn of the V_DDIO(3.3 V) supply fourth (last).

Use the following guidelines:

•

Make sure that the time interval between the ramp-down of V_DDIOand V_DDMis less than 10 ms.

Make sure that the time interval between the ramp-up or ramp-down for V_DDCand V_DDMis less than 2 ms for

power-up and power-down.

•

Refer to Figure 34 for relative timing for power sequencing case 5.

Ramp-down

Ramp-up

V_DDIO= 3.3 V

V_DDM= 2.5 V

V_REF= 1.25 V

V_DDC= 1.2 V

<2 ms

<10 ms

Time

Figure 34. Voltage Sequencing Case 5

Note: Cases 1, 2, 3, and 4 are recommended for system design. Designs that use Case 5 may have large current spikes on

the V_DDMsupply at startup and is not recommended for most designs. If a design uses case 5, it must accommodate

the potential current spikes. Verify risks related to current spikes using actual information for the specific application.

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

47

Hardware Design Considerations

3.2.3

Power Planes

Each power supply pin (V_DDC, V_DDM,and V_DDIO) should have a low-impedance path to the board power supply. Each GND pin

should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the device.

The MSC7119 V_DDCpower supply pins should be bypassed to ground using decoupling capacitors. The capacitor leads and

associated printed circuit traces connecting to device power pins and GND should be kept to less than half an inch per capacitor

lead. A minimum four-layer board that employs two inner layers as power and GND planes is recommended. See Section 3.5

for DDR Controller power guidelines.

3.2.4

Decoupling

Both the I/O voltage and core voltage should be decoupled for switching noise. For I/O decoupling, use standard capacitor

values of 0.01 μF for every two to three voltage pins. For core voltage decoupling, use two levels of decoupling. The first level

should consist of a 0.01 µF high frequency capacitor with low effective series resistance (ESR) and effective series inductance

(ESL) for every two to three voltage pins. The second decoupling level should consist of two bulk/tantalum decoupling

capacitors, one 10 μF and one 47 μF, (with low ESR and ESL) mounted as closely as possible to the MSC7119 voltage pins.

Additionally, the maximum drop between the power supply and the DSP device should be 15 mV at 1 A.

3.2.5

PLL Power Supply Filtering

The MSC7119 V_DDPLLpower signal provides power to the clock generation PLL. To ensure stability of the internal clock, the

power supplied to this pin should be filtered with capacitors that have low and high frequency filtering characteristics. V_DDPLL

can be connected to V_DDCthrough a 2 Ω resistor. V_SSPLLcan be tied directly to the GND plane. A circuit similar to the one

shown in Figure 35 is recommended. The PLL loop filter should be placed as closely as possible to the V_DDPLLpin (which are

located on the outside edge of the silicon package) to minimize noise coupled from nearby circuits.The 0.01 µF capacitor should

be closest to V_DDPLL, followed by the 0.1 µF capacitor, the 10 µF capacitor, and finally the 2-Ω resistor to V_DDC. These traces

should be kept short.

2 Ω

V_DDC

V_DDPLL

0.1 µF 0.01 µF

10 µF

Figure 35. PLL Power Supply Filter Circuits

3.2.6

Power Consumption

You can reduce power consumption in your design by controlling the power consumption of the following regions of the device:

•

Extended core. Use the SC1400 Stop and Wait modes by issuing a stop or wait instruction.

Clock synthesis module. Disable the PLL, timer, watchdog, or DDR clocks or disable the CLKO pin.

AHB subsystem. Freeze or shut down the AHB subsystem using the GPSCTL[XBR_HRQ] bit.

Peripheral subsystem. Halt the individual on-device peripherals such as the DDR memory controller, Ethernet MAC,

HDI16, TDM, UART, I²C, and timer modules.

For details, see the “Clocks and Power Management” chapter of the MSC711x Reference Manual.

MSC7119 Data Sheet, Rev. 8

48

Freescale Semiconductor

Hardware Design Considerations

3.2.7

Power Supply Design

One of the most common ways to derive power is to use either a simple fixed or adjustable linear regulator. For the system I/O

voltage supply, a simple fixed 3.3 V supply can be used. However, a separate adjustable linear regulator supply for the core

voltage V_DDCshould be implemented. For the memory power supply, regulators are available that take care of all DDR power

requirements.

Table 33. Recommended Power Supply Ratings

Supply

Symbol

Nominal Voltage

Current Rating

Core

V

1.2 V

2.5 V

1.25 V

3.3 V

1.5 A per device

0.5 A per device

10 µA per device

1.0 A per device

DDC

DDM

Memory

Reference

I/O

V

REF

V

DDIO

3.3

Estimated Power Usage Calculations

The following equations permit estimated power usage to be calculated for individual design conditions. Overall power is

derived by totaling the power used by each of the major subsystems:

P_TOTAL= P_CORE+ P_PERIPHERALS+ P_DDRIO+ P_IO+ P_LEAKAGE

This equation combines dynamic and static power. Dynamic power is determined using the generic equation:

C × V²× F × 10^–3mW

Eqn. 3

Eqn. 4

where,

C = load capacitance in pF

V = peak-to-peak voltage swing in V

F = frequency in MHz

3.3.1

Core Power

Estimation of core power is straightforward. It uses the generic dynamic power equation and assumes that the core load

capacitance is 750 pF, core voltage swing is 1.2 V, and the core frequency is 300 MHz. This yields:

P_CORE= 750 pF × (1.2 V)²× 300 MHz × 10^–3= 324.0 mW

Eqn. 5

This equation allows for adjustments to voltage and frequency if necessary.

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

49

Hardware Design Considerations

3.3.2

Peripheral Power

Peripherals include the DDR memory controller, Ethernet controller, DMA controller, HDI16, TDM, UART, timers, GPIOs,

and the I²C module. Basic power consumption by each module is assumed to be the same and is computed by using the

following equation which assumes an effective load of 20 pF, core voltage swing of 1.2 V, and a switching frequency of 100

MHz. This yields:

P_PERIPHERAL= 20 pF × (1.2 V)²× 150 MHz × 10^–3= 4.32 mW per peripheral

Eqn. 6

Multiply this value by the number of peripherals used in the application to compute the total peripheral power consumption.

3.3.3

External Memory Power

Estimation of power consumption by the DDR memory system is complex. It varies based on overall system signal line usage,

termination and load levels, and switching rates. Because the DDR memory includes terminations external to the MSC7119

device, the 2.5 V power source provides the power for the termination, which is a static value of 16 mA per signal driven high.

The dynamic power is computed, however, using a differential voltage swing of ±0.200 V, yielding a peak-to-peak swing of 0.4

V. The equations for computing the DDR power are:

P_DDRIO= P_STATIC+ P_DYNAMIC

Eqn. 7

Eqn. 8

P_STATIC= (unused pins × % driven high) × 16 mA × 2.5 V

P

_DYNAMIC= (pin activity value) × 20 pF × (0.4 V)²× 300 MHz × 10^–3mW

Eqn. 9

pin activity value = (active data lines × % activity × % data switching) + (active address lines × % activity)

Eqn. 10

As an example, assume the following:

unused pins = 16 (DDR uses 16-pin mode)

% driven high = 50%

active data lines = 16

% activity = 60%

% data switching = 50%

active address lines = 3

In this example, the DDR memory power consumption is:

P_DDRIO= ((16 × 0.5) × 16 × 2.5) + (((16 × 0.6 × 0.5) + (3 × 0.6)) × 20 × (0.4)²× 300 × 10^–3) = 326.3 mW

Eqn. 11

3.3.4

External I/O Power

The estimation of the I/O power is similar to the computation of the peripheral power estimates. The power consumption per

signal line is computed assuming a maximum load of 20 pF, a voltage swing of 3.3 V, and a switching frequency of 25 MHz,

which yields:

P_IO= 20 pF × (3.3 V)²× 25 MHz × 10^–3= 5.44 mW per I/O line

Eqn. 12

Multiply this number by the number of I/O signal lines used in the application design to compute the total I/O power.

Note: The signal loading depends on the board routing. For systems using a single DDR device, the load could be as low as

7 pF.

3.3.5

Leakage Power

The leakage power is for all power supplies combined at a specific temperature. The value is temperature dependent. The

observed leakage value at room temperature is 64 mW.

MSC7119 Data Sheet, Rev. 8

50

Freescale Semiconductor

Hardware Design Considerations

3.3.6

Example Total Power Consumption

Using the examples in this section and assuming four peripherals and 10 I/O lines active, a total power consumption value is

estimated as the following:

P_TOTAL= 324.0 + (4 × 4.32) + 326.3 + (10 × 5.44) + 64 = 784.98 mW

Eqn. 13

3.4

Reset and Boot

This section describes the recommendations for configuring the MSC7119 at reset and boot.

3.4.1

Reset Circuit

HRESET is a bidirectional signal and, if driven as an input, should be driven with an open collector or open-drain device. For

an open-drain output such as HRESET, take care when driving many buffers that implement input bus-hold circuitry. The

bus-hold currents can cause enough voltage drop across the pull-up resistor to change the logic level to low. Either a smaller

value of pull-up or less current loading from the bus-hold drivers overcomes this issue. To avoid exceeding the MSC7119 output

current, the pull-up value should not be too small (a 1 KΩ pull-up resistor is used in the MSC711xADS reference design).

3.4.2

Reset Configuration Pins

Table 34 shows the MSC7119 reset configuration signals. These signals are sampled at the deassertion (rising edge) of

PORESET. For details, refer to the Reset chapter of the MSC711x Reference Manual.

Table 34. Reset Configuration Signals

Signal

Description

Settings

BM[3–0]

SWTE

Determines boot mode.

See Table 35 for details.

Determines watchdog functionality.

0

1

0

1

0

1

Watchdog timer disabled.

Watchdog timer enabled.

HDSP

H8BIT

Configures HDI16 strobe polarity.

Configures HDI16 operation mode.

Host Data strobes active low.

Host Data strobes active high.

HDI16 port configured for 16-bit operation.

HDI16 port configured for 8-bit operation.

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

51

Hardware Design Considerations

Table 35. Boot Mode Source Selection

Boot

Port

Input Clock

Frequency

Clock

Divide

RNG

Bit

Core Clock

Frequency

BM[3–0]

PLL

CKSEL

Comments

HDI Boot Modes

0000

HDI16

< F

N/A

00

0

< F

Not clocked by the PLL.

max

Can boot as 8- or 16-bit HDI.

0101

0010

0111

0100

HDI16

22.2-25 MHz

25-33.3 MHz

33-66 MHz

1

2

3

2

12

32

12

11

01

11

1

266–300 MHz

200–266 MHz

132–264 MHz

266–300 MHz

Can boot as 8- or 16-bit HDI.

44.3-50 MHz

SPI Boot Modes - Using HA3, HCS2, BM3, BM2 Pins

1000

1001

1010

1011

SPI (SW)

< F

15.6-25 MHz

33-50 MHz

N/A

1

N/A

17

00

11

0

< F

The boot program automatically

determines whether EEPROM

or Flash memory.

max

133–212.5 MHz

132–200 MHz

133–225 MHz

2

16

44.3-75 MHz

3

18

SPI Boot Modes - Using URXD, UTXD, SCL, SDA Pins

1100

SPI (SW)

< F

N/A

00

0

< F

Boots through different set of

pins.

max

2

I C Boot Modes

0001

2

I C

< 100 MHz

N/A

< 100 MHz

Not clocked by the PLL.

2

I C is limited to a maximum bit

rate of 400 Kbps. With a clock

divider of 128, this limits the

maximum input clock frequency

to 100 MHz.

Reserved

0011

0110

1101

1110

1111

Reserved

—

Notes: 1. The clock divider determines the value used in the clock module CLKCTRL[PLLDVF] field.

2. The clock multiplier determines the value used in the clock module CLKCTRL[PLLMLTF] field.

3.

F

is determined by the maximum frequency of the peripheral and of the SC1400 core as specified in the data sheet.

max

3.4.3

Boot

After a power-on reset, the PLL is bypassed and the device is directly clocked from the CLKIN pin. Thus, the device operates

slowly during the boot process. After the boot program is loaded, it can enable the PLL and start the device operating at a higher

speed. The MSC7119 can boot from an external host through the HDI16 or download a user program through the I²C port. The

boot operating mode is set by configuring the BM[0–3] signals sampled at the rising edge of PORESET, as shown in Table 35.

See the MSC711x Reference Manual for details of boot program operation.

3.4.3.1

HDI16 Boot

If the MSC7119 device boots from an external host through the HDI16, the port is configured as follows:

•

Operate in Non-DMA mode.

Operate in polled mode on the device side.

Operate in polled mode on the external host side.

External host must write four 16-bit values at a time with the first word as the most significant and the fourth word as

the least significant.

MSC7119 Data Sheet, Rev. 8

52

Freescale Semiconductor

Hardware Design Considerations

When booting from a power-on reset, the HDI16 is additionally configurable as follows:

•

8- or 16-bit mode as specified by the H8BIT pin.

Data strobe as specified by the HDSP and HDDS pins.

These pins are sampled only on the deassertion of power-on reset. During a boot from a hard reset, the configuration of these

pins is unaffected.

Note: When the HDI16 is used for booting or other purposes, bit 0 is the least significant bit and not the most significant bit

as for other DSP products.

3.4.3.2

I²C Boot

When the MSC7119 device is configured to boot from the I²C port, the boot program configures the GPIO pins for I²C

operation. Then the MSC7118 device initiates accesses to the I²C module, downloading data to the MSC7118 device. The I²C

interface is configured as follows:

•

PLL is disabled and bypassed so that the I²C module is clocked with the IPBus clock.

I²C interface operates in master mode and polling is used.

EPROM operates in slave mode.

Clock divider is set to 128.

Address of slave during boot is 0xA0.

The IPBus clock is internally divided to generate the bit clock, as follows:

•

CLKIN must be a maximum of 100 MHz

PLL is bypassed.

IPBus clock = CLKIN/2 is a maximum of 50 MHz.

I²C bit clock must be less than or equal to:

— IPBus clock/I²C clock divider

— 50 MHz (max)/128

— 390.6 KHz

This satisfies the maximum clock rate requirement of 400 kbps for the I²C interface. For details on the boot procedure, see the

“Boot Program” chapter of the MSC711x Reference Manual.

3.4.3.3

SPI Boot

When the MSC7119 device is configured to boot from the SPI port, the boot program configures the GPIO pins for SPI

operation. Then the MSC7118 device initiates accesses to the SPI module, downloading data to the MSC7118 device. When

the SPI routines run in the boot ROM, the MSC7118 is always configured as the SPI master. Booting through the SPI is

supported for serial EEPROM devices and serial Flash devices. When a READ_ID instruction is issued to the serial memory

device and the device returns a value of 0x00 or 0xFF, the routines for accessing a serial EEPROM are used, at a maximum

frequency of 4 Mbps. Otherwise, the routines for accessing a serial Flash are used, and they can run at faster speeds. Booting is

performed through one of two sets of pins:

•

Main set: BM[2–3], HA3, and HCS2, which allow use of the PLL.

Alternate set: UTXD, URXD, SDA, and SCL, which cannot be used with the PLL.

In either configuration, an error during SPI boot is flagged on the EVNT3 pin. For details on the boot procedure, see the “Boot

Program” chapter of the MSC711x Reference Manual.

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

53

Hardware Design Considerations

3.5

DDR Memory System Guidelines

MSC7119 devices contain a memory controller that provides a glueless interface to external double data rate (DDR) SDRAM

memory modules with Class 2 Series Stub Termination Logic 2.5 V (SSTL_2). There are two termination techniques, as shown

in Figure 36. Technique B is the most popular termination technique.

V_TT

Generator

V_TT

Controller

RS

DDR

Bank

DDR

Bank

RT

SSTL_2

Address

Command

Chip Selects

Technique A

RS

RT

Data

Strobes

Mask

SSTL_2

VREF

V_TT

Generator

Controller

RS

DDR

Bank

DDR

Bank

RT

SSTL_2

Address

Command

Technique B

Chip Selects

RS

RT

Data

Strobes

Mask

SSTL_2

Figure 36. SSTL Termination Techniques

Figure 37 illustrates the power wattage for the resistors. Typical values for the resistors are as follows:

•

RS = 22 Ω

RT = 24 Ω

MSC7119 Data Sheet, Rev. 8

54

Freescale Semiconductor

Hardware Design Considerations

V_TT

Driver

V_DDQ

RT

Receiver

RS

V_REF

V_SS

Figure 37. SSTL Power Value

3.5.1

V

and V Design Constraints

REF TT

V_TTand V_REFare isolated power supplies at the same voltage, with V_TTas a high current power source. This section outlines

the voltage supply design needs and goals:

•

Minimize the noise on both rails.

V_TTmust track variation in the V_REFDC offsets. Although they are isolated supplies, one possible solution is to use a

single IC to generate both signals.

•

Both references should have minimal drift over temperature and source supply.

It is important to minimize the noise from coupling onto V_REFas follows:

— Isolate V_REFand shield it with a ground trace.

— Use 15–20 mm track.

— Use 20–30 mm clearance between other traces for isolating.

— Use the outer layer route when possible.

— Use distributed decoupling to localize transient currents and return path and decouple with an inductance less than

3 nH.

•

Max source/sink transient currents of up to 1.8 A for a 32-bit data bus.

Use a wide island trace on the outer layer:

— Place the island at the end of the bus.

— Decouple both ends of the bus.

— Use distributed decoupling across the island.

— Place SSTL termination resistors inside the V_TTisland and ensure a good, solid connection.

Place the V_TTregulator as closely as possible to the termination island.

— Reduce inductance and return path.

•

— Tie current sense pin at the midpoint of the island.

3.5.2

Decoupling

The DDR decoupling considerations are as follows:

•

DDR memory requires significantly more burst current than previous SDRAMs.

In the worst case, up to 64 drivers may be switching states.

Pay special attention and decouple discrete ICs per manufacturer guidelines.

Leverage V_TTisland topology to minimize the number of capacitors required to supply the burst current needs of the

termination rail.

•

See the Micron DesignLine publication entitled Decoupling Capacitor Calculation for a DDR Memory Channel

(http://download.micron.com/pdf/pubs/designline/3Q00dl1-4.pdf).

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

55

Hardware Design Considerations

3.5.3

General Routing

The general routing considerations for the DDR are as follows:

•

All DDR signals must be routed next to a solid reference:

— For data, next to solid ground planes.

— For address/command, power planes if necessary.

•

All DDR signals must be impedance controlled. This is system dependent, but typical values are 50–60 ohm.

Minimize other cross-talk opportunities. As possible, maintain at least a four times the trace width spacing between all

DDR signals to non-DDR signals.

•

Keep the number of vias to a minimum to eliminate additional stubs and capacitance.

Signal group routing priorities are as follows:

— DDR clocks.

— Route MVTT/MVREF.

— Data group.

— Command/address.

•

Minimize data bit jitter by trace matching.

3.5.4

Routing Clock Distribution

The DDR clock distribution considerations are as follows:

•

DDR controller supports six clock pairs:

— 2 DIMM modules.

— Up to 36 discrete chips.

•

For route traces as for any other differential signals:

— Maintain proper difference pair spacing.

— Match pair traces within 25 mm.

Match all clock traces to within 100 mm.

Keep all clocks equally loaded in the system.

Route clocks on inner critical layers.

•

3.5.5

Data Routing

The DDR data routing considerations are as follows:

•

Route each data group (8-bits data + DQS + DM) on the same layer. Avoid switching layers within a byte group.

Take care to match trace lengths, which is extremely important.

To make trace matching easier, let adjacent groups be routed on alternate critical layers.

Pin swap bits within a byte group to facilitate routing (discrete case).

Tight trace matching is recommended within the DDR data group. Keep each 8-bit datum and its DM signal within ±

25 mm of its respective strobe.

•

Minimize lengths across the entire DDR channel:

— Between all groups maintain a delta of no more than 500 mm.

— Allows greater flexibility in the design for readjustments as needed.

DDR data group separation:

•

— If stack-up allows, keep DDR data groups away from the address and control nets.

— Route address and control on separate critical layers.

— If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages.

MSC7119 Data Sheet, Rev. 8

56

Freescale Semiconductor

Ordering Information

3.6

Connectivity Guidelines

This section summarizes the connections and special conditions, such as pull-up or pull-down resistors, for the MSC7119

device. Following are guidelines for signal groups and configuration settings:

•

Clock and reset signals.

— SWTE is used to configure the MSC7119 device and is sampled on the deassertion of PORESET, so it should be

tied to V_DDCor GND either directly or through pull-up or pull-down resistors until PORESET is deasserted. After

PORESET, this signal can be left floating.

— BM[0–1] configure the MSC7119 device and are sampled until PORESET is deasserted, so they should be tied to

V_DDIOor GND either directly or through pull-up or pull-down resistors.

— HRESET should be pulled up.

Interrupt signals. When used, IRQ pins must be pulled up.

HDI16 signals.

•

— When they are configured for open-drain, the HREQ/HREQ or HTRQ/HTRQ signals require a pull-up resistor.

However, these pins are also sampled at power-on reset to determine the HDI16 boot mode and may need to be

pulled down. When these pins must be pulled down on reset and pulled up otherwise, a buffer can be used with

the HRESET signal as the enable.

— When the device boots through the HDI16, the HDDS, HDSP and H8BIT pins should be pulled up or down,

depending on the required boot mode settings.

•

Ethernet MAC/TDM2 signals. The MDIO signal requires an external pull-up resistor.

I²C signals. The SCL and SDA signals, when programmed for I²C, requires an external pull-up resistor.

General-purpose I/O (GPIO) signals. An unused GPIO pin can be disconnected. After boot, program it as an output

pin.

•

Other signals.

— The TEST0 pin must be connected to ground.

— The TPSEL pin should be pulled up to enable debug access via the EOnCE port and pulled down for boundary

scan.

— Pins labelled NO CONNECT (NC) must not be connected.

— When a 16-pin double data rate (DDR) interface is used, the 16 unused data pins should be no connects (floating)

if the used lines are terminated.

— Do not connect DBREQ to DONE (as you would for the MSC8101 device). Connect DONE to one of the EVNT

pins, and DBREQ to HRRQ.

4

Ordering Information

Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.

Core

Count

Part

Supply Voltage

Package Type

Frequency

(MHz)

Solder Spheres

Order Number

MSC7119

1.2 V core

2.5 V memory

3.3 V I/O

Molded Array Process-Ball Grid

Array (MAP-BGA)

400

300

Lead-free

MSC7119VM1200

MSC7119VF1200

Lead-bearing

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

57

Package Information

5

Package Information

Notes:

1. All dimensions in millimeters.

2. Dimensioning and tolerancing

per ASME Y14.5M–1994.

3. Maximum solder ball diameter

measured parallel to Datum A.

4. Datum A, the seating plane, is

determined by the spherical

crowns of the solder balls.

5. Parallelism measurement shall

exclude any effect of mark on

top surface of package.

CASE 1568-01

Figure 38. MSC7119 Mechanical Information, 400-pin MAP-BGA Package

6

Product Documentation

•

MSC711x Reference Manual (MSC711xRM). Includes functional descriptions of the extended cores and all the

internal subsystems including configuration and programming information.

•

Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC7119 device.

SC140/SC1400 DSP Core Reference Manual. Covers the SC140 and SC1400 core architecture, control registers, clock

registers, program control, and instruction set.

MSC7119 Data Sheet, Rev. 8

58

Freescale Semiconductor

Revision History

7

Revision History

Table 36 provides a revision history for this data sheet.

Table 36. Document Revision History

Description

Revision

Date

0

1

2

Sep. 2005

Oct 2005

Oct. 2005

•

Initial public release.

Added explanatory note to HDI16 timing table.

Added information about signals GPIOB11, GPIOC11, GPIOD7, and GPIOD8 to the signal descriptions

and pinout location lists.

3

Dec. 2005

•

Added information about signals GPIOA16, GPIOA17, GPIOA27, GPIOA28, and GPIOA29 to signal

description and pinout location lists.

4

5

Feb. 2006

Nov. 2006

•

Updated orderable part numbers.

•

Updated Reference Manual reference to MSC711x Reference Manual.

Updated arrows in Host DMA Writing Timing figure.

6

7

8

Jun. 2007

Aug 2007

Apr 2008

•

Updated to new data sheet format. Reorganized and renumbered sections, figures, and tables.

Added a note to clarify the definition of TCK timing 700 in new Table 31.

Removed references to V_CCSYNand V_CCSYN1in the new power supply design recommendation Section

3.2.

•

The power-up and power-down sequences described in Section 3.2 starting on page 42 have been expanded

to five possible design scenarios/cases. These cases replace the previously recommended

power-up/power-down sequence recommendations. Section 3.2 has been clarified by adding subsection

headings.

•

Change the PLL filter resistor from 20 Ω to 2 Ω in Section 3.2.5.

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

59

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Document Number: MSC7119

Rev. 8

4/2008


型号：	MSC7119_08
厂家：	Freescale
描述：	Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC 低成本的16位DSP与DDR控制器和10/100 Mbps以太网MAC 双倍数据速率控制器以太网局域网（LAN）标准
文件：	总60页 (文件大小：1142K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MSC7119_08 [FREESCALE]

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