概述
规格参数
数据手册
替代型号N74F174D 概述
Hex D flip-flops 十六进制D触发器 触发器 触发器/锁存器
N74F174D 规格参数
| 是否Rohs认证： | 符合 | 生命周期： | Obsolete |
| 零件包装代码： | SOIC | 包装说明： | SOP, SOP16,.25 |
| 针数： | 16 | Reach Compliance Code： | unknown |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.32 |
| Is Samacsys： | N | 系列： | F/FAST |
| JESD-30 代码： | R-PDSO-G16 | JESD-609代码： | e4 |
| 负载电容（CL）： | 50 pF | 逻辑集成电路类型： | D FLIP-FLOP |
| 最大频率@ Nom-Sup： | 80000000 Hz | 最大I（ol）： | 0.02 A |
| 湿度敏感等级： | 1 | 位数： | 6 |
| 功能数量： | 1 | 端子数量： | 16 |
| 最高工作温度： | 70 °C | 最低工作温度： | |
| 输出极性： | TRUE | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SOP | 封装等效代码： | SOP16,.25 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE |
| 峰值回流温度（摄氏度）： | 260 | 电源： | 5 V |
| 最大电源电流（ICC）： | 45 mA | 传播延迟（tpd）： | 11 ns |
| 认证状态： | Not Qualified | 子类别： | FF/Latches |
| 最大供电电压 (Vsup)： | 5.5 V | 最小供电电压 (Vsup)： | 4.5 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | YES |
| 技术： | TTL | 温度等级： | COMMERCIAL |
| 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) | 端子形式： | GULL WING |
| 端子节距： | 1.27 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | 40 | 触发器类型： | POSITIVE EDGE |
| 最小 fmax： | 80 MHz | Base Number Matches： | 1 |
N74F174D 数据手册
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74F174
Hex D flip-flops
Product specification
IC15 Data Handbook
1988 Oct 07
Philips
Semiconductors
Philips Semiconductors
Product specification
Hex D flip-flop
74F174
FEATURES
PIN CONFIGURATION
• Six edge-triggered D-type flip-flops
MR
Q0
D0
D1
Q1
1
2
3
4
5
16
V
CC
• Buffered common Clock
15 Q5
14 D5
13 D4
12 Q4
11 D3
10 Q3
• Buffered, asynchronous Master Reset
DESCRIPTION
The 74F174 has six edge-triggered D-type flip-flops with individual D
inputs and Q outputs. The common buffered Clock (CP) and Master
Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
D2
Q2
6
7
8
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
GND
9
CP
SF00188
All Q outputs will be forced Low independent of Clock or Data inputs
by a Low voltage level on the MR input. The device is useful for
applications where true outputs only are required, and the Clock and
Master Reset are common to all storage elements.
ORDERING INFORMATION
COMMERCIAL RANGE
= 5V ±10%,
TYPICAL
SUPPLY CURRENT
(TOTAL)
V
DESCRIPTION
PKG DWG #
CC
TYPE
TYPICAL f
MAX
T
amb
= 0°C to +70°C
16-pin plastic DIP
16-pin plastic SO
N74F174N
SOT38-4
74F174
100MHz
35mA
N74F174D
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
D0–D5
CP
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
20µA/0.6mA
Data inputs
1.0/1.0
1.0/1.0
1.0/1.0
50/33
Clock Pulse input (active rising edge)
Master Reset input (active-Low)
Outputs
20µA/0.6mA
MR
20µA/0.6mA
Q0–Q5
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
9
1
3
4
6
11
13
14
C1
R
3
2
5
D0 D1 D2 D3
D4 D5
1D
9
1
CP
MR
4
6
7
Q0 Q1 Q2
Q3
Q4 Q5
11
13
14
10
12
15
2
5
7
10 12
15
V
= Pin 16
CC
GND = Pin 8
SF00190
SF00189
2
October 7, 1988
853–0060 94766
Philips Semiconductors
Product specification
Hex D flip-flop
74F174
LOGIC DIAGRAM
D0
D1
D2
D3
11
D4
D5
3
4
6
13
14
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
R
CP
R
CP
R
CP
R
CP
R
CP
R
D
D
D
D
D
D
9
CP
1
MR
2
5
7
10
12
15
V
= Pin 16
Q0
Q1
Q2
Q3
Q4
Q5
CC
GND = Pin 8
SF00192
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODE
MR
L
CP
X
D
Qn
L
X
h
l
Reset (clear)
Load “1”
H
↑
H
H
↑
L
Load “0”
H = High voltage level
L = Low voltage level
X = Don’t care
↑ = Low-to-High Clock transition
h = High voltage level one set-up time prior to the Low-to-High Clock transition.
l = Low voltage level one set-up time prior to the Low-to-High Clock transition.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
OUT
OUT
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
–0.5 to V
40
CC
I
mA
°C
°C
T
amb
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
NOM
5.0
SYMBOL
PARAMETER
UNIT
MIN
4.5
MAX
V
Supply voltage
5.5
V
V
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–1
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
OH
OL
20
T
amb
Operating free-air temperature range
0
+70
3
October 7, 1988
Philips Semiconductors
Product specification
Hex D flip-flop
74F174
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
= MIN, V = MAX
UNIT
MAX
2
MIN
2.5
TYP
V
V
V
V
V
V
V
V
V
V
±10%V
CC
IL
CC
V
OH
High-level output voltage
V
= MIN, I = MAX
±5%V
2.7
3.4
0.30
0.30
–0.73
IH
OH
CC
= MIN, V = MAX
±10%V
0.50
V
0.50
CC
IL
CC
CC
V
V
Low-level output voltage
OL
= MIN, I = MAX
±5%V
IH
OL
Input clamp voltage
= MIN, I = I
IK
–1.2
100
20
V
IK
CC
CC
CC
CC
CC
CC
I
I
I
I
I
I
Input current at maximum input voltage
High-level input current
= MAX, V = 7.0V
µA
µA
mA
mA
mA
I
I
= MAX, V = 2.7V
IH
I
Low-level input current
= MAX, V = 0.5V
–0.6
–150
45
IL
I
3
Short-circuit output current
= MAX
–60
OS
Supply current (total)
= MAX, Dn = MR = 4.5V, CP = ↑
35
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
AC ELECTRICAL CHARACTERISTICS
LIMITS
V
= +5.0V
= +25°C
V
= +5.0V ± 10%
= 0°C to +70°C
CC
CC
TEST
CONDITION
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
Waveform 2
80
100
80
MHz
ns
MAX
t
t
Propagation delay
CP to Qn
3.5
4.5
5.5
6.0
8.0
10.0
3.5
4.5
9.0
11.0
PLH
PHL
t
Propagation delay MR to Qn
5.0
8.5
14.0
5.0
15.0
ns
PHL
AC SETUP REQUIREMENTS
LIMITS
V
= +5.0V
= +25°C
V
= +5.0V ± 10%
= 0°C to +70°C
CC
CC
TEST
CONDITION
T
amb
T
amb
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t (H)
t (L)
S
Setup time, High or Low
Dn to CP
4.0
4.0
4.0
4.0
S
Waveform 3
Waveform 3
Waveform 1
ns
ns
ns
t (H)
Hold time, High or Low
Dn to CP
0.0
0.0
0.0
0.0
h
t (L)
h
t (H)
CP Pulse width,
High or Low
4.0
6.0
4.0
6.0
w
t (L)
w
t (L)
MR Pulse width, Low
Waveform 2
Waveform 2
5.0
5.0
5.0
5.0
ns
ns
w
t
Recovery time, MR to CP
REC
4
October 7, 1988
Philips Semiconductors
Product specification
Hex D flip-flop
74F174
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
Dn
V
V
t
V
V
t
(L)
M
M
M
M
w
CP
Qn
V
V
M
t
M
t
t (H)
(H)
t (L)
t (L)
h
s
h
s
(H)
w
PLH
t
PHL
CP
V
V
M
M
V
V
M
M
SF00191
SF00166
Waveform 3. Data Setup and Hold Times
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
MR
CP
V
V
M
M
t
w
(L)
t
REC
V
M
t
PHL
Qn
V
M
SF00158
Waveform 2. Master Reset Pulse Width, Master Reset to
Output Delay and Master Reset to Clock recovery Time
TEST CIRCUIT AND WAVEFORMS
t
AMP (V)
V
w
CC
90%
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
family
74F
V
rep. rate
t
w
t
t
THL
amplitude
M
TLH
Termination resistance should be equal to Z
pulse generators.
of
OUT
2.5ns 2.5ns
3.0V
1.5V
1MHz
500ns
SF00006
5
October 7, 1988
Philips Semiconductors
Product specification
Hex D flip-flops
74F174
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
6
1988 Oct 07
Philips Semiconductors
Product specification
Hex D flip-flops
74F174
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
7
1988 Oct 07
Philips Semiconductors
Product specification
Hex D flip-flops
74F174
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05089
Document order number:
Philips
Semiconductors
N74F174D 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| N74F174N,602 | NXP | N74F174N | 类似代替 |
|
| 74F174SC | FAIRCHILD | Hex D-Type Flip-Flop with Master Reset | 功能相似 |
|
| SN74F174ADR | TI | 暂无描述 | 功能相似 |
|
N74F174D 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| N74F174D,602 | NXP | N74F174D | 获取价格 |
|
| N74F174D,623 | NXP | N74F174D | 获取价格 |
|
| N74F174D-T | ETC | Hex D-Type Flip-Flop | 获取价格 |
|
| N74F174DB | PHILIPS | D Flip-Flop, 6-Func, Positive Edge Triggered, TTL, PDSO16 | 获取价格 |
|
| N74F174N | NXP | Hex D flip-flops | 获取价格 |
|
| N74F174N,602 | NXP | N74F174N | 获取价格 |
|
| N74F175AD | NXP | IC F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SOT-109, SO-16, FF/Latch | 获取价格 |
|
| N74F175AD,602 | NXP | IC F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SOT-109, SO-16, FF/Latch | 获取价格 |
|
| N74F175AD,623 | NXP | IC F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SOT-109, SO-16, FF/Latch | 获取价格 |
|
| N74F175AD-T | NXP | IC F/FAST SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SOT-109, SO-16, FF/Latch | 获取价格 |
|
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