N74F195AD [NXP]
4-bit parallel-access shift register; 4位并行存取移位寄存器
| 型号： | N74F195AD |
| 厂家： | 
NXP |
| 描述： | 4-bit parallel-access shift register |
| 文件： | 总10页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F195A
4-bit parallel-access shift register
Product specification
IC15 Data Handbook
1996 Mar 12
Philips
Semiconductors
Philips Semiconductors
Product specification
4-bit parallel-access shift register
74F195A
J, K, Dn, and PE inputs for logic operation, other than the set-up and
hold time requirements.
FEATURES
• Shift right and parallel load capability
A Low on the asynchronous Master Reset (MR) input sets all Q
outputs Low, independent of any other input condition.
• J – K (D) inputs to first stage
• Complement output from last stage
• Asynchronous Master Reset
• Diode inputs
PIN CONFIGURATION
MR
J
1
2
3
4
5
16
V
CC
15 Q0
14 Q1
13 Q2
12 Q3
DESCRIPTION
K
The 74F195A is a 4-Bit Parallel Access Shift Register and its
functional characteristics are indicated in the Logic Diagram and
Function Table. This device is useful in a variety of shifting, counting
and storage applications. It performs serial, parallel, serial to
parallel, or parallel to serial data transfers at very high speeds.
D0
D1
D2
6
7
8
11
Q3
D3
10
The 74F195A operates in two primary modes: shift right (Q0→Q1)
and parallel load, which are controlled by the state of the Parallel
Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J
and K inputs when the PE input is High, and is shifted one bit in the
direction Q0→Q1→Q2→Q3 following each Low-to-High clock
transition.
CP
GND
9
PE
SF00757
TYPICAL
SUPPLY CURRENT
(TOTAL)
The J and K inputs provide the flexibility of the J-K type input for
special applications, and by tying the two together the simple D-type
input is made for general applications.
TYPE
TYPICAL f
MAX
74F195A
180MHz
40mA
The device appears as four common clocked D flip-flops when the
PE input is Low. After the Low-to-High clock transition, data on the
parallel inputs (D0–D3) is transferred to the respective Q0–Q3
outputs. Shift left operation (Q3–Q2) can be achieved by tying the
Qn outputs to the Dn-1 inputs and holding the PE input Low.
ORDERING INFORMATION
COMMERCIAL RANGE
= 5V ±10%,
V
CC
DESCRIPTION
PKG. DWG. #
T
amb
= 0°C to +70°C
All parallel and serial data transfers are synchronous, occurring after
each Low-to-High clock transition. The 74F195A utilizes
edge-triggering, therefore there is no restriction on the activity of the
16-pin plastic DIP
16-pin plastic SO
N74F195AN
N74F195AD
SOT 38-4
SOT 109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F (U.L.)
HIGH/LOW
LOAD VALUE HIGH/LOW
PINS
DESCRIPTION
74F195
74F195A
74F195
1.0/0.033
1.0/1.0
20µA/20µA
20µA/0.6mA
20µA/20µA
20µA/0.6mA
20µA/20µA
20µA/0.6mA
40µA/40µA
20µA/0.6mA
D0–D3
Data inputs
1.0/0.033
1.0/1.0
J, K
CP
J-K or D type serial inputs
74F195A
74F195
1.0/0.033
1.0/1.0
Clock Pulse input (active rising edge)
74F195A
74F195
2.0/0.066
1.0/1.0
MR
Master Reset input (active Low)
Data outputs
74F195A
Q0–Q3,
Q3
50/33
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
2
1996 Mar 12
853-0024 16555
Philips Semiconductors
Product specification
4-bit parallel-access shift register
74F195A
LOGIC SYMBOL
IEC/IEEE SYMBOL
4
5
6
7
SRG4
9
1
M1
R
D0
D1
D2
D3
10
C2/1
9
2
PE
J
2
3
4
5
6
7
Q3
11
1, 2J
1, 2K
1, 2D
1, 2D
10
CP
15
3
1
K
14
13
MR
Q2 Q3
13 12
Q0 Q1
12
11
V
= Pin 16
GND = Pin 8
CC
15
14
SF00758
SF00759
LOGIC DIAGRAM
10
9
CP
PE
2
3
J
K
15
R
S
Q0
CP
Q
Q
1
4
MR
D0
R
D
5
6
7
D1
D2
D3
14
R
R
R
S
S
S
Q1
CP
Q
R
D
13
Q2
CP
Q
R
D
12
11
Q3
Q3
CP
Q
Q
R
D
V
= Pin 16
CC
GND = Pin 8
SF00760
3
1996 Mar 12
Philips Semiconductors
Product specification
4-bit parallel-access shift register
74F195A
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODES
MR
L
CP
X
↑
PE
X
h
J
X
h
l
K
X
h
l
Dn
X
Q0
L
Q1
L
Q2
L
Q3
L
Q3
H
Reset (clear)
H
X
H
q0
q0
q0
q0
q1
q1
q1
q1
q2
q2
q2
q2
q2
q2
q2
q2
Shift, set First stage
Shift, reset First stage
Shift, toggle First stage
Shift, retain First stage
H
↑
h
X
L
H
↑
h
h
l
l
X
q0
q0
H
↑
h
h
X
H = High voltage level
h = High voltage level one setup time prior to Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
dn(qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature
–0.5 to +V
40
OUT
OUT
CC
I
mA
°C
°C
T
amb
0 to +70
T
stg
–65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
NOM
MAX
V
Supply voltage
5.0
5.5
V
V
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–1
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
OH
OL
20
T
amb
Operating free-air temperature range
0
70
4
1996 Mar 12
Philips Semiconductors
Product specification
4-bit parallel-access shift register
74F195A
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
NO TAG
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MAX
TYP
MIN
NO TAG
±10%V
2.5
2.7
V
V
CC
V
V
= MIN, V = MAX
IL
CC
V
High-level output voltage
Low-level output voltage
OH
= MIN, I = MAX
IH
OH
±5%V
3.4
0.35
0.35
–0.73
CC
±10%V
0.50
V
CC
CC
V
V
= MIN, V = MAX
IL
CC
IH
V
V
OL
= MIN, I = MAX
OL
±5%V
0.50
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MIN, I = I
IK
–1.2
100
20
V
IK
I
I
I
I
I
I
Input current at maximum input voltage
High-level input current
= MAX, V = 7.0V 74F195A
µA
µA
mA
mA
mA
I
I
= MAX, V = 2.7V all others
IH
I
Low-level input current
= MAX, V = 0.5V 74F195A
–600
–150
58
IL
I
3
Short-circuit output current
= MAX
–60
OS
Supply current (total)
= MAX
74F195A
40
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
AC ELECTRICAL CHARACTERISTICS
LIMITS
V
amb
= +5V
= +25°C
V
amb
= +5V ± 10%
= 0°C to +70°C
CC
CC
TEST
CONDITION
T
T
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
Load mode
Shift mode
165
180
180
190
150
170
Maximum clock
frequency
Waveform
NO TAG
f
MHz
MAX
t
t
Propagation delay
CP to Qn
Waveform
NO TAG
3.0
2.5
5.0
4.0
9.5
7.0
2.5
2.0
10.0
7.5
PLH
PHL
ns
ns
ns
ns
t
t
Propagation delay
CP to Q3
Waveform
NO TAG
2.0
2.0
5.5
4.0
9.5
6.5
2.5
2.0
9.5
7.0
PLH
PHL
Propagation delay
MR to Qn
t
Waveform 2
Waveform 2
2.0
2.5
4.0
4.5
7.0
8.0
2.0
2.0
7.0
PHL
PLH
Propagation delay
MR to Q3
t
10.0
5
1996 Mar 12
Philips Semiconductors
Product specification
4-bit parallel-access shift register
74F195A
AC SETUP REQUIREMENTS
LIMITS
V
amb
= +5V
= +25°C
V
amb
= +5V ± 10%
= 0°C to +70°C
CC
CC
TEST
CONDITION
T
T
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t (H)
t (L)
S
Setup time, High or Low
J, K and Dn to CP
2.5
2.5
2.5
2.5
S
Waveform 3
Waveform 3
Waveform 4
Waveform 4
ns
ns
ns
ns
ns
ns
ns
t (H)
Hold time, High or Low
J, K and Dn to CP
0.0
1.0
0.0
1.0
h
t (L)
h
t (H)
Setup time, High or Low
PE to CP
2.0
2.5
2.0
2.5
S
t (L)
S
t (H)
Hold time, High or Low
PE to CP
0.0
0.0
0.0
0.0
h
t (L)
h
CP Pulse width
High
Waveform
NO TAG
t (H)
W
4.5
4.5
2.5
4.5
4.5
3.0
MR Pulse width
Low
t (L)
W
Waveform 2
Waveform 2
Recovery time
MR to CP
t
REC
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
max
V
V
MR
CP
M
M
V
V
V
t
CP
M
M
M
t
rec
t
w
(L)
t
w
(H)
t
PHL
PLH
V
V
M
V
M
M
M
M
Q3
Qn
t
PHL
t
t
PLH
PHL
Qn
Q3
V
V
M
M
V
V
t
PLH
SF00761
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
SF00762
Waveform 3. Master Reset Pulse Width, Master Reset to
Output Delay, and Master Reset to Clock Recovery Time
SERIAL-SHIFT RIGHT
PARALLEL LOAD
J, K,
Dn
V
V
V
V
M
M
M
M
t (H)
t
(H)
t (L)
t
(L)
V
V
V
V
V
M
s
h
s
h
M
M
M
M
PE
CP
t (H)
t
t (L)
t
h
s
h
s
CP
V
V
M
M
V
M
SF00763
Qn
RESPONSE
Qn=Qn–1
Qn=Dn
Waveform 2. Data Setup and Hold Times
SF00764
Waveform 4. Setup and Hold Times, Parallel Enable to Clock
6
1996 Mar 12
Philips Semiconductors
Product specification
4-bit parallel-access shift register
74F195A
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
90%
V
CC
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
0V
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
Termination resistance should be equal to Z
pulse generators.
family
74F
V
rep. rate
t
t
t
amplitude
M
w
TLH
THL
of
OUT
2.5ns 2.5ns
3.0V
1.5V
1MHz
500ns
SF00006
7
1996 Mar 12
Philips Semiconductors
Product specification
74F195A
4-bit parallel-access shift register
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
8
1996 Mar 12
Philips Semiconductors
Product specification
74F195A
4-bit parallel-access shift register
NOTES
9
1996 Mar 12
Philips Semiconductors
Product specification
74F195A
4-bit parallel-access shift register
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05096
Document order number:
Philips
Semiconductors
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