N74F225N [NXP]
16X5 asynchronous FIFO 3-State; 16X5异步FIFO三态
| 型号： | N74F225N |
| 厂家： | 
NXP |
| 描述： | 16X5 asynchronous FIFO 3-State |
| 文件： | 总14页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F225
16X5 asynchronous FIFO (3-State)
Product specification
IC15 Data Handbook
1992 Jun 15
Philips
Semiconductors
Philips Semiconductors
Product specification
16 × 5 asynchronous FIFO (3-State)
74F225
Ready (IR), Unload Clock Output (UNCPOUT) and Output Ready
(OR). The data outputs are non–inverting with respect to the data
inputs and are disabled when the OE input is High. When OE is
Low, the data outputs are enabled to function as totem–pole outputs.
FEATURES
• Independent synchronous inputs and outputs
• Organized as 16 words of 5 bits
• DC to 25MHz data rate
TYPICAL SUPPLY
TYPE
TYPICAL f
CURRENT
( TOTAL)
• 3–State outputs
MAX
• Cascadable in word–width and depth direction
74F225
25MHz
65mA
DESCRIPTION
ORDERING INFORMATION
This 80–bit active element First–In–First–Out (FIFO) is a monolithic
Schottky–clamped transistor–transistor logic (STTL) array organized
as 16–words of 5–bits each. A memory system using the ’F225 can
be easily expanded in multiples of 16–words of 5–bits as shown in
Figure 1. The 3–State outputs controlled by a single enable input
(OE) make bus connection and multiplexing simple. The ’F225
processes data in a parallel format at any desired clock rate from
DC to 25MHz. Status of the ’F225 is provided by three outputs, Input
ORDER CODE
COMMERCIAL RANGE
= 5V ±10%,
DESCRIPTION
PKG DWG #
V
CC
T
amb
= 0°C to +70°C
20–pin plastic DIP
20–pin plastic SOL
N74F225N
SOT146-1
SOT163-1
N74F225D
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
CPA, CPB
D0 – D4
OE
Load clock A and load clock B inputs
Data inputs
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
1.0/0.033
50/33
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
1.0mA/20mA
3.0mA/24mA
1.0mA/20mA
Output enable input (active–Low)
Unload clock input
UNCPIN
MR
Master reset input (active–Low)
Input ready output
IR
UNCPOUT
Q0 – Q4
OR
Unload clock output (active–Low)
Data outputs
50/33
150/40
Output ready output
50/33
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
RESET MODE
READ MODE
A High–to–Low transition on the Master Reset (MR) input invalidates
all data stored in the FIFO by clearing the control logic and setting
OR Low. This High–to–Low transition on the MR input does not
effect the data outputs but since OR is driven Low, it signifies invalid
data on the outputs.
The Output Ready (OR) output is High when valid data is present on
the data outputs. Data in the array is shifted on the Low–to–High
transition of the Unload Clock Input (UNCPIN). In order for Output
Ready (OR) to go High, Unload Clock Input (UNCPIN) must also be
High.
WRITE MODE
Data may be written into the array on the Low–to–High transition of
either load clock (CPA or CPB) input. When writing data into the
FIFO, one of the load clock inputs must be held High while the other
strobes data into the FIFO. This arrangement allows either load
clock to function as an inhibit for the other. Input Ready (IR)
monitors the status of the last word location and signifies when the
FIFO is full. This output is High whenever the FIFO is available to
accept new data. The unload clock output (UNCPOUT) also
monitors the last word location. This output generates a
Low–logic–level pulse (synchronized to the internal clock pulse)
when the last word location is vacant
2
June 15, 1992
853-1652 06992
Philips Semiconductors
Product specification
16 × 5 asynchronous FIFO (3-State)
74F225
PIN CONFIGURATION
IEC/IEEE SYMBOL
FIFO 16 X
CPA
IR
1
2
3
4
5
6
7
8
9
20
19
V
CC
9
5
3
EN5
CTR
3
CPB
18
CT=0
&
+
UNCPOUT
18 MR
CT<16
1
19
1
G1
OR
17
D0
D1
D2
D3
D4
OE
G2/Z3
2
UNCPIN
16
&
2CT<16
CT>0
1D
–
17
15 Q0
16
4
Z4
14
13
12
11
Q1
4
5
15
14
13
5
Q2
Q3
6
7
8
12
11
GND 10
Q4
SF00334
SF00336
LOGIC SYMBOL
4
5
6
7
8
D0 D1 D2 D3 D4
CPA
CPB
1
19
16
9
UNCPOUT
3
UNCPIN
OE
MR
18
Q0 Q1 Q2 Q3 Q4 IR OR
15 14 13 12 11 2 17
V
= Pin 20
CC
GND = Pin 10
SF00335
3
June 15, 1992
Philips Semiconductors
Product specification
16 × 5 asynchronous FIFO (3-State)
74F225
LOGIC DIAGRAM
Word 1
(first word)
Word 3–14
same as 2 or 16
Word 16
(last word)
Word 2
Word 15
Detail A
4
15
D0
QO
5
14
Q1
D1
D2
D3
D4
Detail A
6
7
8
13
Q2
Detail A
12
Q3
Detail A
Detail A
11
Q4
9
OE
1
Q
CPA
CPB
17
CP
19
OR
D
CLR
3
16
UNC-
UNCPIN
2
POUT
IR
V
= pin 20
CC
GND = pin 10
18
MR
SF00337
4
June 15, 1992
Philips Semiconductors
Product specification
16 × 5 asynchronous FIFO (3-State)
74F225
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
Supply voltage
V
I
CC
V
IN
Input voltage
Input current
V
mA
V
IN
V
Voltage applied to output in High output state
Current applied to output in Low output state
Current applied to output in Low output state
Operating free air temperature range
–0.5 to V
OUT
OUT
CC
I
IR, OR, UNCPOUT
Data outputs
40
48
mA
mA
T
amb
0 to +70
°C
°C
T
stg
Storage temperature range
–65 to +150
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
4.5
NOM
MAX
V
CC
Supply voltage
5.0
5.5
V
V
High–level input voltage
Low–level input voltage
Input clamp current
2.0
V
IN
V
0.8
–18
–1
V
IL
I
Ik
mA
mA
mA
mA
mA
I
High–level output current
IR, OR, UNCPOUT
OH
Data outputs
–3
I
OL
Low–level output current
IR, OR, UNCPOUT
Data outputs
20
24
T
amb
Operating free air temperature range
0
+70
°C
5
June 15, 1992
Philips Semiconductors
Product specification
16 × 5 asynchronous FIFO (3-State)
74F225
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
1
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
2
MIN
2.5
2.7
2.4
2.7
TYP
MAX
IR, OR,
UNCPOUT
Data
V
V
V
V
V
V
V
V
V
V
= MIN, V = MAX
V
V
±10%V
CC
IL
CC
V
High-level output voltage
= MIN, I = MAX
±5%V
OH
IH
OH
CC
= MIN, V = MAX
V
±10%V
±5%V
CC
IL
CC
outputs
= MIN, I = MAX
V
IH
OH
CC
V
Low-level output voltage
Input clamp voltage
= MIN, V = MAX
0.35
0.35
-0.73
0.50
0.50
-1.2
100
20
V
±10%V
OL
CC
IL
CC
CC
= MIN, I = MAX
V
±5%V
IH
OL
V
I
= MIN, I = I
IK
V
IK
CC
CC
I
I
I
Input current at maximum input voltage
High–level input current
= MAX, V = 7.0V
µA
I
= MAX, V = 2.7V
µA
µA
IH
CC
CC
I
I
Low–level input current
= MAX, V = 0.5V
–20
IL
I
Offset–output current,
High–level voltage applied
I
V
V
= MAX, V = 2.7V
50
µA
µA
OZH
CC
I
Offset–output current,
Low–level voltage applied
I
= MAX, V = 0.5V
–50
OZL
CC
I
3
I
Short-circuit output current
V
V
= MAX
= MAX
-60
-150
95
mA
mA
OS
CC
I
Supply current (total)
65
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T
= 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of High-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
6
June 15, 1992
Philips Semiconductors
Product specification
16 × 5 asynchronous FIFO (3-State)
74F225
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
amb
= +25°C
T
amb
= 0°C to +70°C
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
UNIT
V
CC
= +5.0V ± 10%
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
Maximum clock frequency,
Cascade mode
f
Waveform 2 and 3
Waveform 2
Waveform 2
Waveform 4
Waveform 2
Waveform 4
Waveform 4
Waveform 4
Waveform 3
Waveform 3
Waveform 3
25
25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX
t
t
Propagation delay
UNCPIN to Qn
10.0
9.5
13.0
12.0
19.5
16.0
9.0
8.5
22.0
19.0
PLH
PHL
t
t
Propagation delay
UNCPIN to OR
16.0
6.0
20.0
8.5
25.0
11.0
14.0
5.0
29.0
12.0
PLH
PHL
Output skew
Qn to OR ↑
t
SK
2.0
50
55
12.0
70
0.0
50
50
15.0
85
Propagation delay
UNCPIN to IR
t
60
65
PLH
PLH
Propagation delay
CPA or CPB to OR
t
75
90
t
t
Propagation delay
CPA or CPB to UNCPOUT
20.0
8.5
23.0
11.5
27.0
15.0
17.0
7.5
29.0
16.0
PLH
PHL
Pulse width, Low
UNCPOUT
t (L)
w
12.0
13.5
8.5
Propagation delay
CPA or CPB to IR
t
t
t
11.0
5.5
17.0
11.5
7.0
9.0
5.0
1.5
19.0
13.0
7.5
PHL
Propagation delay
MR to OR
PHL
Propagation delay
MR to IR
2.0
4.0
PHL
t
t
Output enable time to
High or Low level
Waveform 5
Waveform 6
1.5
2.5
3.5
4.5
6.5
7.5
1.0
2.0
7.0
9.0
PZH
PZL
t
t
Output disable time from
High or Low level
Waveform 5
Waveform 6
1.5
2.0
3.5
4.0
7.0
7.0
1.0
1.5
7.5
7.5
PHZ
PLZ
AC SETUP REQUIREMENTS
LIMITS
T
= +25°C
= +5.0V
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
SYMBOL
PARAMETER
TEST
V
UNIT
V
CC
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t (H)
t (L)
s
Setup time, High or Low
Dn to CPA or CPB
0.0
0.0
0.0
0.0
s
Waveform 1
Waveform 1
Waveform 1
Waveform 1
ns
ns
ns
ns
t (H)
Hold time, High or Low
Dn to CPA or CPB
14.0
12.5
16.5
14.0
h
t (L)
h
Recovery time
MR to CPA or CPB
t
0.0
0.0
rec
t (H)
CPA or CPB pulse width,
High or Low
6.5
3.0
8.5
3.5
w
t (L)
w
UNCPIN pulse width,
High or Low
24.0
3.5
28.0
4.0
t (L)
Waveform 2
Waveform 1
ns
ns
w
t (L)
w
MR pulse width, Low
3.5
4.5
7
June 15, 1992
Philips Semiconductors
Product specification
16 × 5 asynchronous FIFO (3-State)
74F225
TYPICAL TIMING DIAGRAM
MR
CPA
CPB
Word 3
is Low
Word
16
Dn
UNCPIN
IR
Word 1
Word 2
UNCPOUT
OR
Qn
Word 3
Word 16
Word 1
Word 2
Word 1
Clear
Load
words
3–15
Unload
words
4–15
Load
word 1
Load
word 2
Load
word 16
Unload
word 2
Unload
word 3
Unload
word 16
SF00338
NOTE: Shaded areas Indicates irrelevant input conditions.
8
June 15, 1992
Philips Semiconductors
Product specification
16 × 5 asynchronous FIFO (3-State)
74F225
AC WAVEFORMS
1/f
t
(L)
MAX
w
V
CP
V
V
V
CPA
or
CPB
M
M
M
t
M
V
t
V
M
(H)
M
t
w
t
h
t
(L)
PHL
w
PLH
t
su
V
V
V
M
M
UNCPOUT
M
Dn
V
V
V
M
M
M
t
PLH
t
su
t
(L)
w
V
M
OR
V
V
M
MR
M
t
SK
SF00339
Waveform 1. MR and Clock Pulse Widths, Data Setup and
Hold Times and MR to Clock Setup Time
Qn
V
M
SF00342
1/fMAX
t
(L)
w
Waveform 4. CPA or CPB to UNCPOUT and OR Delay,
UNCPOUT Pulse Width and Qn to OR Skew
V
V
V
V
M
UNCPIN
Qn
M
M
M
t
(H)
V
w
t
PHL
t
t
PLH
V
M
M
V
V
M
M
OE
Qn
t
PHL
PLH
V
-0.3V
0V
OH
t
t
PHZ
PZH
V
V
M
OR
IR
M
V
M
t
PLH
SF00343
V
M
Waveform 5. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
SF00340
Waveform 2. UNCPIN to Output Delays
V
t
V
M
M
OE
Qn
1/f
MAX
CPA
or
CPB
t
PZL
PLZ
V
V
M
M
V
M
V
+0.3V
OL
SF00344
V
M
t
MR
IR
t
PHL
PLH
Waveform 6. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
V
V
M
M
t
PHL
OR
V
M
SF00341
Waveform 3. CPA or CPB to IR Delay and MR to IR
and OR Delay
NOTES:
1. For all waveforms, V = 1.5V.
M
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
9
June 15, 1992
Philips Semiconductors
Product specification
16 × 5 asynchronous FIFO (3-State)
74F225
APPLICATION
Load clock
CPA
CPB
OR
CPA
CPB
OR
CPA
CPB
OR
Output ready
Unload clock
NC
UNCPOUT UNCPIN
IR
UNCPOUT UNCPIN
IR
UNCPOUT UNCPIN
IR
NC
NC
D0
D1
D2
D3
D4
Q0
Q1
Q2
Q3
Q4
D0
D1
D2
D3
D4
Q0
Q1
Q2
Q3
Q4
D0
D1
D2
D3
D4
Q0
Q1
Q2
Q3
Q4
5–bit data input
5–bit data output
Output enable
MR
MR
OE
OE
MR
MR
OE
OE
MR
MR
OE
OE
Master reset
Input ready
CPA
CPB
OR
CPA
CPB
OR
CPA
CPB
OR
UNCPOUT
UNCPIN
UNCPOUT UNCPIN
IR
NC
UNCPOUT UNCPIN
IR
IR
NC
NC
D0
D1
D2
D3
D4
Q0
Q1
Q2
Q3
Q4
D0
D1
D2
D3
D4
Q0
Q1
Q2
Q3
Q4
D0
D1
D2
D3
D4
Q0
Q1
Q2
Q3
Q4
5–bit data input
5–bit data output
SF00345
Figure 1. Expanding the 74F225 FIFO (48 words of 10 bits)
TEST CIRCUIT AND WAVEFORM
V
CC
t
w
AMP (V)
90%
7.0V
90%
NEGATIVE
PULSE
V
V
M
R
M
L
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
0V
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for Open Collector Outputs
10%
10%
0V
t
w
SWITCH POSITION
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
INPUT PULSE REQUIREMENTS
family
V
M
rep. rate
t
w
t
t
amplitude
TLH
THL
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00128
10
June 15, 1992
Philips Semiconductors
Product specification
16X5 asynchronous FIFO (3-State)
74F225
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
11
1992 Jun 15
Philips Semiconductors
Product specification
16X5 asynchronous FIFO (3-State)
74F225
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
12
1992 Jun 15
Philips Semiconductors
Product specification
16X5 asynchronous FIFO (3-State)
74F225
NOTES
13
1992 Jun 15
Philips Semiconductors
Product specification
16X5 asynchronous FIFO (3-State)
74F225
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05099
Document order number:
Philips
Semiconductors
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