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N74F259D,623 [NXP]

74F259 - Latch SOP 16-Pin;
N74F259D,623
型号： N74F259D,623
厂家： NXP    NXP
描述：

74F259 - Latch SOP 16-Pin

光电二极管 逻辑集成电路 触发器
文件： 总12页 (文件大小：106K)
中文：  中文翻译
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INTEGRATED CIRCUITS  
74F259  
Latch  
Product specification  
IC15 Data Handbook  
1989 Apr 11  
Philips  
Semiconductors  
Philips Semiconductors  
Product specification  
Latch  
74F259  
FEATURES  
PIN CONFIGURATION  
• Combines demultiplexer and 8-bit latch  
1
2
3
4
5
16  
15  
14  
13  
12  
A0  
A1  
V
CC  
• Serial-to-parallel capability  
• Output from each storage bit available  
• Random (addressable) data entry  
• Easily expandable  
MR  
E
A2  
Q0  
D
Q1  
Q7  
Q6  
Q5  
Q4  
• Common reset input  
6
7
8
11  
10  
9
Q2  
Q3  
• Useful as 1-of-8 active-High decoder  
GND  
SF00823  
DESCRIPTION  
The 74F259 addressable latch has four distinct modes of operation  
which are selectable by controlling the Master Reset (MR) and  
Enable (E) inputs (see Function Table). In the addressable latch  
mode, data at the Data inputs is written into the addressed latches.  
The addressed latches will follow the Data input with all  
unaddressed latches remaining in their previous states. In the store  
mode, all latches remain in their previous states and are unaffected  
by the Data or Address inputs. To eliminate the possibility of entering  
erroneous data in the latches, the enable should be held High  
(inactive) while the address lines are changing. In the 1-of-8  
decoding or demultiplexing mode (MR=E=Low), addressed outputs  
will follow the level of the Data input, with all other outputs Low. In  
the Master Reset mode, all outputs are Low and unaffected by the  
Address and Data inputs.  
TYPE  
TYPICAL  
PROPAGATION  
DELAY  
TYPICAL SUPPLY  
CURRENT (TOTAL)  
74F259  
7.5ns  
31mA  
ORDERING INFORMATION  
ORDER CODE  
DESCRIPTION  
COMMERCIAL RANGE  
PKG DWG #  
V
amb  
= 5V ±10%,  
= 0°C to +70°C  
CC  
T
16-pin plastic DIP  
16-pin plastic SO  
N74F259N  
SOT38-4  
N74F259D  
SOT109-1  
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE  
PINS  
DESCRIPTION  
74F (U.L.)  
HIGH/LOW  
LOAD VALUE  
HIGH/LOW  
D
A0, A1, A2  
E
Data input  
1.0/1.0  
1.0/1.0  
1.0/1.0  
1.0/1.0  
50/33  
20µA/0.6mA  
20µA/0.6mA  
20µA/0.6mA  
20µA/0.6mA  
1.0mA/20mA  
Address inputs  
Enable input (active Low)  
MR  
Master Reset inputs (active Low)  
Q0 – Q7  
Data outputs  
NOTE:  
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.  
2
1989 Apr 11  
853–0362 06316  
Philips Semiconductors  
Product specification  
Latch  
74F259  
LOGIC SYMBOL  
IEC/IEEE SYMBOL  
1
2
0
2
0
7
8M  
3
14  
13  
15  
G8  
Z9  
13  
D
1
2
3
Z10  
A0  
A1  
A3  
9, 10D  
10m 0R  
4
14  
15  
E
9, 10D  
10m 1R  
5
6
7
9
MR  
9, 10D  
10m 2R  
Q0  
4
Q1  
5
Q2  
Q3 Q4  
Q5  
10  
Q6  
Q7  
12  
9, 10D  
10m 3R  
9, 10D  
10m 4R  
9, 10D  
10m 5R  
6
7
9
11  
10  
11  
9, 10D  
10m 6R  
12  
9, 10D  
10m 7R  
V
= Pin 16  
CC  
GND = Pin 8  
SF00824  
SF00825  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
OPERATING MODE  
MR  
L
L
L
L
•
E
H
L
L
L
•
D
X
d
d
d
•
A0  
A1  
X
L
L
H
•
A2  
Q0  
Q1  
L
Q2  
L
Q3  
L
Q4  
L
Q5  
L
Q6  
L
Q7  
L
X
L
H
L
•
L
L
L
L
•
L
Master Reset  
Q=d  
L
L
L
L
L
L
L
L
L
Q=d  
L
L
L
L
L
L
L
Q=d  
•
L
L
L
L
L
Demultiplex  
(active-High decoder  
when D=H)  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
L
H
H
H
H
•
L
H
L
L
L
•
d
X
d
d
d
•
H
X
L
H
L
•
H
X
L
L
H
•
H
X
L
L
L
•
L
L
L
L
L
L
L
Q=d  
q7  
q7  
q7  
q7  
•
q0  
Q=d  
q0  
q0  
•
q1  
q1  
Q=d  
q1  
•
q2  
q2  
q2  
Q=d  
•
q3  
q3  
q3  
q3  
•
q4  
q4  
q4  
q4  
•
q5  
q5  
q5  
q5  
•
q6  
q6  
q6  
q6  
•
Store (do nothing)  
Addressable Latch  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
H
L
d
H
H
H
q0  
q1  
q2  
q3  
q4  
q5  
q6  
Q=d  
H = High voltage level  
L
X
d
q
=
=
=
=
Low voltage level  
Don’t care  
High or Low data one setup time prior to the Low-to-High Enable transition  
Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared.  
3
1989 Apr 11  
Philips Semiconductors  
Product specification  
Latch  
74F259  
LOGIC DIAGRAM  
12  
Q7  
11  
Q6  
10  
Q5  
9
7
6
5
Q4  
Q3  
Q2  
13  
D
14  
E
15  
MR  
Q1  
3
2
A2  
A1  
A0  
1
4
Q0  
V
= Pin 16  
CC  
GND = Pin 8  
SF00826  
4
1989 Apr 11  
Philips Semiconductors  
Product specification  
Latch  
74F259  
ABSOLUTE MAXIMUM RATINGS  
(Operation beyond the limit set forth in this table may impair the useful life of the device.  
Unless otherwise noted these limits are over the operating free air temperature range.)  
SYMBOL  
PARAMETER  
RATING  
UNIT  
V
Supply voltage  
V
CC  
–0.5 to +7.0  
–0.5 to +7.0  
–30 to +5  
V
IN  
Input voltage  
Input current  
V
I
IN  
mA  
V
Voltage applied to output in High output state  
Current applied to output in Low output state  
Operating free-air temperature range  
Storage temperature range  
V
OUT  
–0.5 to V  
40  
CC  
I
mA  
OUT  
T
amb  
0 to +70  
°C  
°C  
T
stg  
–65 to +150  
RECOMMENDED OPERATING CONDITIONS  
PARAMETER  
SYMBOL  
LIMITS  
UNIT  
MIN  
4.5  
NOM  
MAX  
Supply voltage  
V
5.0  
5.5  
V
V
CC  
V
High-level input voltage  
Low-level input voltage  
Input clamp current  
2.0  
IH  
V
0.8  
–18  
–1  
V
IL  
IK  
I
mA  
mA  
mA  
I
High-level output current  
Low-level output current  
OH  
I
OL  
20  
T
amb  
Operating free-air temperature range  
0
70  
°C  
DC ELECTRICAL CHARACTERISTICS  
(Over recommended operating free-air temperature range unless otherwise noted.)  
SYMBOL  
PARAMETER  
TEST  
LIMITS  
UNIT  
1
2
CONDITIONS  
MIN TYP  
MAX  
V
High-level output voltage  
V
V
V
V
V
V
V
V
= MIN, V = MAX,  
±10%V  
2.5  
V
V
OH  
CC  
IL  
CC  
= MIN, I = MAX  
±5%V  
2.7  
3.4  
IH  
OL  
CC  
V
Low-level output voltage  
= MIN, V = MAX,  
±10%V  
0.35  
0.35  
0.50  
0.50  
V
OL  
CC  
IL  
CC  
CC  
= MIN, I = MAX  
±5%V  
V
IH  
OL  
V
Input clamp voltage  
= MIN, I = I  
IK  
–0.73 –1.2  
V
IK  
CC  
CC  
CC  
CC  
I
I
I
Input current at maximum input voltage  
High-level input current  
= MAX, V = 7.0V  
100  
20  
µA  
µA  
mA  
I
I
= MAX, V = 2.7V  
I
IH  
I
Low-level input current  
= MAX, V = 0.5V  
–0.6  
IL  
I
3
Short-circuit output current  
I
V
CC  
V
CC  
= MAX  
= MAX  
–60  
–150  
mA  
OS  
CC  
I
Supply current (total)  
I
24  
37  
46  
75  
mA  
mA  
CCH  
I
CCL  
NOTES:  
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.  
2. All typical values are at V = 5V, T = 25°C.  
CC  
amb  
3. To reduce the effect of external noise during test.  
4. Not more than one output should be shorted at a time. For testing I , the use of High-speed test apparatus and/or sample-and-hold  
OS  
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting  
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any  
sequence of parameter tests, I tests should be performed last.  
OS  
5
1989 Apr 11  
Philips Semiconductors  
Product specification  
Latch  
74F259  
AC ELECTRICAL CHARACTERISTICS  
LIMITS  
T
T
amb  
= +25°C  
= 0°C to +70°C  
amb  
SYMBOL  
PARAMETER  
TEST  
V
CC  
= +5V  
V
CC  
= +5V ± 10%  
UNIT  
CONDITION  
C = 50pF, R = 500Ω  
C = 50pF, R = 500Ω  
L L  
L
L
MIN  
TYP  
MAX  
MIN  
MAX  
t
t
Propagation delay  
D to Qn  
4.0  
3.0  
7.0  
5.0  
9.0  
7.0  
4.0  
2.5  
10.0  
7.5  
PLH  
PHL  
Waveform  
NO TAG  
ns  
ns  
ns  
ns  
t
t
Propagation delay  
E to Qn  
4.5  
3.0  
8.0  
5.0  
10.5  
7.0  
4.5  
3.0  
12.0  
8.0  
PLH  
PHL  
Waveform  
NO TAG  
t
t
Propagation delay  
An to Qn  
5.0  
4.0  
10.0  
8.5  
14.0  
9.5  
5.0  
4.0  
14.5  
10.0  
PLH  
PHL  
Waveform  
NO TAG  
Propagation delay  
MR to Qn  
t
Waveform  
NO TAG  
5.0  
7.0  
9.0  
4.5  
10.0  
PHL  
AC SETUP REQUIREMENTS  
LIMITS  
T
T
V
= +25°C  
= +5.0V  
= 0°C to +70°C  
= +5.0V ± 10%  
amb  
amb  
SYMBOL  
PARAMETER  
TEST  
UNIT  
V
CC  
CC  
CONDITION  
C = 50pF, R = 500Ω  
C = 50pF, R = 500Ω  
L L  
L
L
MIN  
TYP  
MAX  
MIN  
MAX  
t (H)  
t (L)  
s
Setup time, High or Low  
D to E  
Waveform  
NO TAG  
3.0  
6.5  
3.0  
7.0  
ns  
ns  
ns  
ns  
ns  
ns  
s
t (H)  
Hold time, High or Low  
D to E  
Waveform  
NO TAG  
0
0
0
0
h
t (L)  
h
t (H)  
Setup time, High or Low  
Waveform  
NO TAG  
2.0  
2.0  
2.0  
2.0  
s
1
t (L)  
s
An to E  
t (H)  
Hold time, High or Low  
Waveform  
NO TAG  
0
0
0
0
h
2
t (L)  
h
An to E  
t (L)  
w
E Pulse width, Low  
Waveform  
NO TAG  
7.5  
8.0  
t (L)  
w
MR Pulse width, Low  
Waveform  
NO TAG  
3.0  
3.0  
NOTES:  
1. The Address to Enable setup time is the time before the High-to-Low Enable transition that the Address must be stable so that the correct  
latch is addressed and the other latches are not affected.  
2. The Address to Enable hold time is the time before the Low-to-High Enable transition that the Address must be stable so that the correct  
latch is addressed and the other latches are not affected.  
6
1989 Apr 11  
Philips Semiconductors  
Product specification  
Latch  
74F259  
AC WAVEFORMS  
For all waveforms, V = 1.5V.  
M
The shaded areas indicate when the input is permitted to change for predictable output performance.  
D
V
V
M
M
An  
Qn  
t (L)  
W
t
t
PLH  
PHL  
E
V
V
V
M
M
M
t
V
V
M
t
M
PHL  
PLH  
SF00811  
Q
n
V
V
M
M
Waveform 2. Propagation Delay Address to Output  
SF00827  
Waveform 1. Propagation Delay,  
Enable Input to Output, Enable Pulse Width  
D
t (L)  
W
V
V
M
MR  
V
V
V
V
V
M
M
M
M
M
t (H)  
t
(H)  
t (L)  
t (L)  
h
t
s
h
s
PHL  
Qn  
V
M
M
V
M
E
SF00812  
Q=D  
Q=D  
Waveform 3. Master Reset Pulse Width and  
Master Reset to Output Delay  
Qn  
SF00828  
Waveform 4. Data Setup and Hold Times  
V
V
M
Address Stable  
M
An  
t
s
t
h
E
V
V
M
M
SF00814  
Waveform 5. Address Setup and Hold Times  
7
1989 Apr 11  
Philips Semiconductors  
Product specification  
Latch  
74F259  
TEST CIRCUIT AND WAVEFORMS  
t
w
AMP (V)  
90%  
V
CC  
90%  
NEGATIVE  
PULSE  
V
V
M
M
10%  
10%  
V
V
OUT  
IN  
0V  
PULSE  
GENERATOR  
D.U.T.  
t
t )  
t
t )  
THL ( f  
TLH ( r  
R
C
R
L
t
t )  
T
L
t
t )  
TLH ( r  
THL ( f  
AMP (V)  
90%  
M
90%  
POSITIVE  
PULSE  
V
V
M
10%  
10%  
0V  
Test Circuit for Totem-Pole Outputs  
DEFINITIONS:  
t
w
Input Pulse Definition  
INPUT PULSE REQUIREMENTS  
R
L
C
L
R
T
=
=
=
Load resistor;  
see AC ELECTRICAL CHARACTERISTICS for value.  
Load capacitance includes jig and probe capacitance;  
see AC ELECTRICAL CHARACTERISTICS for value.  
Termination resistance should be equal to Z  
pulse generators.  
family  
74F  
V
rep. rate  
t
t
t
amplitude  
M
w
TLH  
THL  
of  
OUT  
2.5ns 2.5ns  
3.0V  
1.5V  
1MHz  
500ns  
SF00006  
8
1989 Apr 11  
Philips Semiconductors  
Product specification  
Latch  
74F259  
DIP16: plastic dual in-line package; 16 leads (300 mil)  
SOT38-4  
9
1989 Apr 11  
Philips Semiconductors  
Product specification  
Latch  
74F259  
SO16: plastic small outline package; 16 leads; body width 3.9 mm  
SOT109-1  
10  
1989 Apr 11  
Philips Semiconductors  
Product specification  
Latch  
74F259  
NOTES  
11  
1989 Apr 11  
Philips Semiconductors  
Product specification  
Latch  
74F259  
Data sheet status  
[1]  
Data sheet  
status  
Product  
status  
Definition  
Objective  
specification  
Development  
This data sheet contains the design target or goal specifications for product development.  
Specification may change in any manner without notice.  
Preliminary  
specification  
Qualification  
Production  
This data sheet contains preliminary data, and supplementary data will be published at a later date.  
Philips Semiconductors reserves the right to make chages at any time without notice in order to  
improve design and supply the best possible product.  
Product  
specification  
This data sheet contains final specifications. Philips Semiconductors reserves the right to make  
changes at any time without notice in order to improve design and supply the best possible product.  
[1] Please consult the most recently issued datasheet before initiating or completing a design.  
Definitions  
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or  
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended  
periods may affect device reliability.  
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips  
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or  
modification.  
Disclaimers  
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications  
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.  
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard  
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Philips Semiconductors  
811 East Arques Avenue  
P.O. Box 3409  
Copyright Philips Electronics North America Corporation 1998  
All rights reserved. Printed in U.S.A.  
Sunnyvale, California 94088–3409  
Telephone 800-234-7381  
print code  
Date of release: 10-98  
9397-750-05109  
Document order number:  
Philips  
Semiconductors  

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