N74F322D [NXP]
8-bit serial/parallel register with sign extend 3-State; 8位的串行/并行寄存器，符号延伸三态
| 型号： | N74F322D |
| 厂家： | 
NXP |
| 描述： | 8-bit serial/parallel register with sign extend 3-State |
| 文件： | 总9页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
FEATURES
PIN CONFIGURATION
• Multiplexed parallel I/O ports
RE
S/P
D0
1
2
3
4
5
20
19
• Separate serial input and output
• Sign extend function
V
CC
S
18 SE
17 D1
• 3-State outputs for bus applications
• Direct Overriding Clear
I/O0
I/O2
I/O4
I/O1
16
15
14
13
I/O3
I/O5
I/O7
6
7
8
9
DESCRIPTION
The 74F322 is an 8-bit shift register with provision for either serial or
parallel loading and with 3-State parallel outputs plus a bi-state
serial output. Parallel data inputs and outputs are multiplexed to
minimize pin count. State changes are initiated by the rising edge of
the clock. Four synchronous modes of operation are possible: hold
(store), shift right with serial entry, shift right with sign extend, and
parallel load. An asynchronous Master Reset (MR) input overrides
clocked operation and clears the registers.
I/O6
OE
MR
12 Q7
11 CP
GND 10
SF00874
TYPICAL
SUPPLY CURRENT
(TOTAL)
The 74F322 contains eight D-type edge triggered flip-flops and the
interstage gating required to perform right shift and the intrastage
gating necessary for hold and synchronous parallel load operations.
A Low signal on RE enables shifting or parallel loading, while a High
signal enables the hold mode. A High signal on S/P enables shift
right, while a Low signal disables the 3-State output buffers and
enables parallel loading. In the shift right mode a High signal on SE
enables serial entry from either D0 or D1, as determined by the S
input. A Low signal on SE enables shift right, but Q7 reloads its
contents, thus performing the sign extend function. A High signal on
OE disables the 3-State output buffers, regardless of the other
control inputs. In this condition the shifting and loading operations
can still be performed.
TYPE
TYPICAL f
MAX
74F322
125MHz
60mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
= 5V ±10%, T = 0°C to +70°C
V
CC
amb
20-pin plastic DIP
20-pin plastic SOL
N74F322N
N74F322D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F(U.L.)
LOAD VALUE
HIGH/LOW
PINS
DESCRIPTION
HIGH/LOW
1.0/1.0
1.0/2.0
1.0/3.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
D0, D1
S
Serial data inputs
20µA/0.6mA
20µA/1.2mA
20µA/1.8mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
70µA/0.6mA
3.0mA/24mA
Serial data select input
Sign Extend input
SE
CP
Clock Pulse input (Active rising edge)
Serial (High) or Parallel (Low) mode control input
Register Enable input (Active Low)
Asynchronous Master Reset input (Active Low)
Output Enable input (Active Low)
Bi-state serial output
S/P
RE
MR
OE
Q7
Multiplexed parallel data inputs or
3-State parallel outputs
3.5/1.0
150/40
I/On
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High State and 0.6mA in the Low state.
1
1988 Apr 22
853-0366 93020
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
3
17
SRG8
9
R
8
1
2
2EN15
G3
S
D0
D1
19
RE
1
3M1[SHIFT]
3M2[PAR LOAD]
2
S/P
SE
11
C6/1 →
18
18
19
11
8
G4
8, 4, 1, 6D
CP
OE
G5
9
MR
3
17
4
8, 5, 1, 6D
8, 4, 1, 6D
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Q7
2, 6D
7, 15
Z7
4
16
5
15
6
14
7
13
12
SF00875
V
= Pin 20
CC
GND = Pin 10
2, 96D
16
5
8, 15
Z8
15
6
14
7
13
2, 6D
12, 13
Z14
12
SF00876
FUNCTION TABLE
INPUTS
SE
INPUTS
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
OPERATING
MODE
MR
RE
S/P
S
OE*
CP
Q7
L
L
H
X
X
H
X
X
X
X
L
L
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Clear
H
L
L
X
X
X
↑
I0
I1
I2
I3
I4
I5
I6
I7
I7
Parallel load
Shift right
H
H
L
L
H
H
H
H
L
H
L
L
↑
↑
D0
D1
O0
O0
O1
O1
O2
O2
O3
O3
O4
O4
O5
O5
O6
O6
O6
O6
H
H
L
H
X
L
X
X
L
L
↑
O0
NC
O0
NC
O1
NC
O2
NC
O3
NC
O4
NC
O5
NC
O6
NC
O6
NC
Sign extend
Hold
H
X
X
X
X
L
X
L
X
X
X
X
X
X
H
X
↑
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
NC
NC
3-State
*
= When the input is High, all I/O terminals are at the high impedance state, sequential operation or clearing of the register is not
affected.
H
L
NC
X
= High voltage level
= Low voltage level
= No change
= Don’t care
Z
↑
= High impedance “off” state
= Low-to-High clock transition
I0–I7 = The level of the steady state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs (except Q7) are
isolated from the I/O terminal.
D0–D7 = The level of the steady state inputs to the serial multiplexer input.
O0–O7= The level of the respective Qn flip-flop prior to the last clock Low-to-High transition.
↑
= Not a Low-to-High clock transition
2
1988 Apr 22
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
LOGIC DIAGRAM
8
OE
1
RE
2
S/P
17
D1
19
S
3
D0
CP
D
Q
Q
4
I/O0
18
SE
R
CP
D
Q
Q
16
I/O1
R
CP
D
Q
Q
5
I/O2
R
CP
D
Q
Q
15
I/O3
R
CP
D
Q
Q
6
I/O4
I/O5
I/O6
R
R
R
R
CP
D
Q
Q
14
CP
D
Q
Q
7
12
13
Q7
CP
D
Q
Q
I/O7
9
MR
CP
V
= Pin 20
11
CC
GND = Pin 10
SF00877
3
1988 Apr 22
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.)
SYMBOL
PARAMETER
RATING
UNIT
V
V
Supply voltage
Input voltage
Input current
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to +5.5
40
V
V
CC
IN
I
IN
mA
V
V
OUT
Voltage applied to output in High output state
Q7
mA
mA
°C
°C
I
Current applied to output in Low output state
OUT
I/On
48
T
amb
Operating free-air temperature range
Storage temperature
0 to +70
–65 to +150
T
stg
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
NOM
5.0
UNIT
MIN
4.5
MAX
V
CC
V
IH
V
IL
Supply voltage
5.5
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
V
0.8
–18
–1
V
I
IK
mA
mA
mA
mA
mA
°C
Q7
I/On
Q7
I
High-level output current
OH
OL
–3
20
I
Low-level output current
I/On
24
T
amb
Operating free-air temperature range
0
70
4
1988 Apr 22
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN
2.5
2.7
2.4
2.7
TYP
MAX
±10%V
±5%V
V
V
V
V
CC
Q7
I
= –1mA
= –3mA
OH
OH
V
V
V
= MIN,
= MAX,
= MIN
CC
IL
IH
3.4
CC
V
OH
High-level output voltage
±10%V
CC
CC
I/On
I
±5%V
3.3
V
V
V
= MIN,
= MAX,
= MIN
±10%V
CC
IL
IH
0.38
0.55
V
CC
V
Low-level output voltage
Input clamp voltage
I
= MAX
OL
OL
±5%V
0.35
0.50
–1.2
100
1
V
CC
V
IK
V
= MIN, I = I
IK
–0.73
V
CC
I
I
I
I
others
I/On
V
CC
V
CC
V
CC
= MAX, V = 7.0V
µA
mA
µA
mA
mA
mA
I
I
Input current at
maximum input voltage
= MAX, V = 5.5V
I
High-level input current
Low-level input current
= MAX, V = 2.7V
20
IH
IL
I
SE
S
–1.8
–1.2
–0.6
V
CC
= MAX, V = 0.5V
I
others
Off-state output current
High-level voltage applied
I
I
V
V
= MAX, V = 2.7V
70
µA
IH + OZH
CC
I
Off-state output current
Low-level voltage applied
I
I
I
= MAX, V = 0.5V
–0.6
mA
IL + OZL
CC
I
3
Short-circuit output current
V
= MAX
= MAX
–60
–150
75
mA
mA
mA
mA
OS
CC
I
50
60
65
CCH
I
Supply current (total)
I
V
CC
90
CC
CCL
I
95
CCZ
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T = 25°C.
CC
amb
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
5
1988 Apr 22
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
V
= +25°C
= +5.0V
T
V
CC
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
CC
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
110
125
90
MHz
MAX
t
t
Propagation delay
CP to I/On
4.0
4.5
6.0
7.0
9.0
9.5
4.0
4.5
10.0
10.0
ns
ns
PLH
PHL
t
t
Propagation delay
CP to Q7
4.5
5.0
6.5
6.5
9.0
9.0
4.5
5.0
10.0
9.0
ns
ns
PLH
PHL
Waveform 1
Waveform 2
Waveform 2
Propagation delay
MR to I/On
t
t
5.0
5.0
6.5
6.5
9.5
9.5
4.5
4.5
10.0
10.0
ns
ns
PHL
Propagation delay
MR to Q7
PHL
t
t
Output Enable time
OE to I/On
Waveform 4
Waveform 5
3.0
5.5
5.0
7.5
8.0
10.5
3.0
5.0
9.0
11.0
ns
ns
PZH
PZL
t
t
Output Disable time
OE to I/On
Waveform 4
Waveform 5
2.0
1.0
4.0
2.5
6.5
5.5
2.0
1.0
7.5
6.0
ns
ns
PHZ
PLZ
t
t
Output Disable time
S/P to I/On
Waveform 4
Waveform 5
4.0
6.0
6.0
8.0
9.0
11.0
3.5
5.5
10.0
11.5
ns
ns
PZH
PZL
t
t
Output Disable time
S/P to I/On
Waveform 4
Waveform 5
4.0
2.0
6.0
4.0
9.0
7.0
3.5
2.0
10.5
7.5
ns
ns
PHZ
PLZ
t
t
Output Disable time
RE to I/On
Waveform 4
Waveform 5
8.0
9.0
9.5
11.0
12.5
14.0
7.0
8.0
14.0
16.0
ns
ns
PZH
PZL
t
t
Output Disable time
RE to I/On
Waveform 4
Waveform 5
6.5
4.5
8.5
6.5
11.5
9.5
5.5
4.0
13.0
10.5
ns
ns
PHZ
PLZ
6
1988 Apr 22
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
AC SETUP REQUIREMENTS
LIMITS
T
amb
= +25°C
T
amb
= 0°C to +70°C
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
V
CC
= +5.0V
V
CC
= +5.0V ± 10%
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t (H)
t (L)
s
Setup time, High or Low
RE to CP
8.0
12.5
9.5
14.0
ns
ns
s
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
Waveform 3
t (H)
Hold time, High or Low
RE to CP
0
0
0
0
ns
ns
h
t (L)
h
t (H)
Setup time, High or Low
D0, D1 or I/On to CP
4.0
4.5
6.0
5.0
ns
ns
s
t (L)
s
t (H)
Hold time, High or Low
D0, D1 or I/On to CP
0
0
0
0
ns
ns
h
t (L)
h
t (H)
Setup time, High or Low
SE to CP
5.5
5.0
7.0
5.5
ns
ns
s
t (L)
s
t (H)
Hold time, High or Low
SE to CP
0
0
0
0
ns
ns
h
t (L)
h
t (H)
Setup time, High or Low
S/P to CP
10.5
9.5
11.0
10.5
ns
ns
s
t (L)
s
t (H)
Setup time, High or Low
S to CP
4.0
8.5
4.5
9.5
ns
ns
s
t (L)
s
t (H)
Hold time, High or Low
S or S/P to CP
0
0
0
0
ns
ns
h
t (L)
h
t (H)
5.0
5.0
5.0
5.0
w
CP Pulse width, High or Low
ns
t (L)
w
t (L)
MR Pulse width, Low
Waveform 3
Waveform 2
5.0
4.0
5.0
4.5
ns
ns
w
t
Recovery time, MR to CP
REC
7
1988 Apr 22
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
AC WAVEFORMS
For all waveforms, V = 1.5V
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/f
MAX
MR
V
V
t
M
t
M
CP
V
t
V
M
M
(L)
W
REC
(H)
t
(L)
W
W
t
t
PLH
CP
V
PHL
M
Q7, I/On
V
V
M
M
t
PHL
Q7, I/On
V
M
SF00878
SF00879
Waveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock Frequency
Waveform 2. Master Reset Pulse Width, Master Reset to Output
Delay, and Master Reset to Clock Recovery Time
RE, S/P, OE
V
V
M
M
RE, D0,
D1, I/On,
SE, S/P, S
V
V
V
V
M
M
M
M
t
V
-0.3V
0V
OH
t
t
PHZ
PZH
t (H)
t
(H)
t (L)
(L)
V
s
h
s
h
I/On
V
M
CP
V
M
M
SF00880
SF00881
Waveform 3. Data Setup and Hold Times
Waveform 4. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
RE, S/P, OE
V
t
V
M
M
t
PZL
PLZ
I/On
V
M
V
+0.3V
OL
SF00882
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
8
1988 Apr 22
Philips Semiconductors
Product specification
8-bit serial/parallel register with sign extend (3-State)
74F322
TEST CIRCUIT AND WAVEFORM
V
CC
t
w
AMP (V)
90%
7.0V
90%
NEGATIVE
PULSE
V
V
M
R
M
L
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
0V
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
0V
t
w
SWITCH POSITION
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
INPUT PULSE REQUIREMENTS
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
family
V
M
rep. rate
t
t
t
amplitude
w
TLH
THL
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00777
9
1988 Apr 22
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