N74F373N [NXP]
Octal transparent latch 3-State; 八路透明锁存器三态
| 型号： | N74F373N |
| 厂家： | 
NXP |
| 描述： | Octal transparent latch 3-State |
| 文件： | 总12页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAST PRODUCTS
74F373
Octal transparent latch (3-State)
74F374
Octal D flip-flop (3-State)
Product specification
IC15 Data Handbook
1994 Dec 05
Philip s Se m ic ond uc tors
Philips Semiconductors
Product specification
Latch/flip-flop
74F373/74F374
74F373 Octal transparent latch (3-State)
74F374 Octal D-type flip-flop (3-State)
The 74F374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE) control gates.
FEATURES
• 8-bit transparent latch — 74F373
• 8-bit positive edge triggered register — 74F374
• 3-State outputs glitch free during power-up and power-down
• Common 3-State output register
The register is fully edge triggered. The state of the D input, one
setup time before the low-to-high clock transition is transferred to the
corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
• Independent register and 3-State buffer operation
• SSOP Type II Package
The active low output enable (OE) controls all eight 3-State buffers
independent of the register operation. When OE is low, the data in
the register appears at the outputs. When OE is high, the outputs
are in high impedance “off” state, which means they will neither drive
nor load the bus.
DESCRIPTION
The 74F373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY
CURRENT
TYPE
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is high. The latch remains transparent to the data
input while E is high, and stores the data that is present one setup
time before the high-to-low enable transition.
(TOTAL)
74F373
4.5ns
35mA
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
TYPICAL SUPPLY
CURRENT
TYPE
TYPICAL f
max
(TOTAL)
The active low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is low, latched or
transparent data appears at the output.
74F374
165MHz
55mA
When OE is high, the outputs are in high impedance “off” state,
which means they will neither drive nor load the bus.
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
= 5V ±10%, T = 0°C to +70°C
DESCRIPTION
PKG DWG #
V
CC
amb
20-pin plastic DIP
20-pin plastic SOL
N74F373N, N74F374N
N74F373D, N74F374D
N74F373DB, N74374DB
SOT146-1
SOT163-1
SOT399-1
20-pin plastic SSOP type II
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
LOAD VALUE
HIGH/LOW
74F (U.L.)
HIGH/LOW
PINS
DESCRIPTION
20µA/0.6mA
D0 - D7
E (74F373)
OE
Data inputs
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
3.0mA/24mA
Enable input (active high)
Output enable inputs (active low)
Clock pulse input (active rising edge)
3-State outputs
CP (74F374)
Q0 - Q7
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2
December 5, 1994
853-0369 14383
Philips Semiconductors
Product specification
Latch/flip-flop
74F373/74F374
PIN CONFIGURATION – 74F373
PIN CONFIGURATION – 74F374
OE
Q0
V
CC
1
2
20
19
18
17
16
15
14
13
12
11
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
D0
3
D1
4
Q1
5
Q2
6
D2
7
D3
8
Q3
9
GND
10
GND 10
11 E
SF00250
SF00253
LOGIC SYMBOL – 74F373
IEC/IEE SYMBOL – 74F374
3
4
7
8
13 14 17 18
3
4
7
8
13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
11
E
11
CP
OE
OE
1
1
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2
5
6
9 12 15 16 19
2
5
6
9 12 15 16 19
V
= Pin 20
CC
V
= Pin 20
CC
GND = Pin 10
GND = Pin 10
SF00251
SF00254
IEC/IEEE SYMBOL – 74F374
IEC/IEEE SYMBOL – 74F373
1
EN1
11
1
C2
EN1
11
EN2
2
3
2D
1
5
6
4
7
3
2
2D
1
5
6
9
4
9
8
7
12
15
16
19
13
8
14
13
12
15
16
19
17
18
14
17
18
SF00255
SF00252
3
December 5, 1994
Philips Semiconductors
Product specification
Latch/flip-flop
74F373/74F374
LOGIC DIAGRAM FOR 74F373
D0
D1
4
D2
D3
D4
13
D5
14
D6
17
D7
18
3
7
8
D
E
D
E
D
E
D
E
D
E
D
E
D
E
D
E
Q
Q
Q
Q
Q
Q
Q
Q
11
1
E
OE
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q7
SF00256
Q0
Q1
Q2
Q3
V
= Pin 20
CC
GND = Pin 10
LOGIC DIAGRAM FOR 74F374
D0
D1
4
D2
D3
D4
13
D5
14
D6
17
D7
18
3
7
8
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
D
CP
Q
Q
Q
Q
Q
Q
Q
Q
11
1
CP
OE
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q7
V
= Pin 20
CC
GND = Pin 10
Q0
Q1
Q2
Q3
SF00257
FUNCTION TABLE FOR 74F373
INPUTS
OUTPUTS
Q0 - Q7
INTERNAL
REGISTER
OPERATING MODE
OE
L
E
H
H
↓
Dn
L
L
H
L
H
Enable and read register
L
H
l
L
L
L
Latch and read register
Hold
L
↓
h
H
H
L
L
X
NC
NC
Dn
NC
Z
H
L
X
Disable outputs
H
H
Dn
Z
NOTES:
H
h
L
l
=
=
=
=
High-voltage level
High state must be present one setup time before the high-to-low enable transition
Low-voltage level
Low state must be present one setup time before the high-to-low enable transition
No change
NC=
X
Z
↓
=
=
=
Don’t care
High impedance “off” state
High-to-low enable transition
4
December 5, 1994
Philips Semiconductors
Product specification
Latch/flip-flop
74F373/74F374
FUNCTION TABLE FOR 74F374
INPUTS
INTERNAL
REGISTER
OUTPUTS
Q0 - Q7
OPERATING MODE
OE
L
CP
↑
Dn
l
L
L
H
Load and read register
L
↑
h
H
L
↑
X
NC
NC
Dn
NC
Z
Hold
H
↑
X
Disable outputs
H
↑
Dn
Z
NOTES:
H
h
L
l
=
=
=
=
High-voltage level
High state must be present one setup time before the low-to-high clock transition
Low-voltage level
Low state must be present one setup time before the low-to-high clock transition
NC=
No change
Don’t care
High impedance “off” state
Low-to-high clock transition
Not low-to-high clock transition
X
Z
↑
=
=
=
=
↑
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
-0.5 to +7.0
-0.5 to +7.0
-30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
IN
mA
V
I
Voltage applied to output in high output state
Current applied to output in low output state
-0.5 to V
V
OUT
CC
48
mA
OUT
T
Operating free air temperature range
Storage temperature range
0 to +70
°C
°C
amb
T
stg
-65 to +150
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
NOM
MAX
V
5.0
5.5
V
V
Supply voltage
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
-18
-3
V
I
I
I
mA
mA
mA
Ik
High-level output current
Low-level output current
OH
OL
24
T
amb
Operating free air temperature range
0
+70
°C
5
December 5, 1994
Philips Semiconductors
Product specification
Latch/flip-flop
74F373/74F374
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
TEST
CONDITIONS
SYMBOL
PARAMETER
UNIT
1
2
MIN TYP
MAX
±10%V
±5%V
V
V
= MIN, V = MAX,
2.4
V
V
CC
CC
IL
V
OH
High-level output voltage
= MIN, I = MAX
2.7
3.4
CC
IH
OH
V
V
= MIN, V = MAX,
±10%V
0.35
0.35
0.50
0.50
V
V
CC
IL
CC
V
V
Low-level output voltage
OL
= MIN, I = MAX
±5%V
IH
OL
CC
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
= MIN, I = I
IK
-0.73 -1.2
V
IK
I
I
I
I
Input current at maximum input voltage
High-level input current
= MAX, V = 7.0V
100
20
µA
µA
mA
I
I
= MAX, V = 2.7V
IH
IL
I
Low-level input current
= MAX, V = 0.5V
-0.6
I
µA
µA
I
I
I
Off-state output current, high-level voltage applied
Off-state output current, low-level voltage applied
V
V
V
= MAX, V = 2.7V
50
-50
OZH
OZL
OS
CC
CC
CC
O
= MAX, V = 0.5V
O
3
Short-circuit output current
= MAX
= MAX
-60
-150
mA
74F373
74F374
35
57
60
86
mA
mA
I
Supply current (total)
V
CC
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T
= 25°C.
amb
CC
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
T
= +25°C
= +5.0V
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
V
SYMBOL
PARAMETER
TEST
V
UNIT
CC
CC
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
Dn to Qn
3.0
2.0
5.3
3.7
7.0
5.0
3.0
2.0
8.0
6.0
PLH
PHL
Waveform 3
Waveform 2
ns
ns
ns
t
t
Propagation delay
E to Qn
5.0
3.0
9.0
4.0
11.5
7.0
5.0
3.0
12.0
8.0
PLH
PHL
74F373
t
t
Output enable time
to high or low level
Waveform 6
Waveform 7
2.0
2.0
5.0
5.6
11.0
7.5
2.0
2.0
11.5
8.5
PZH
PZL
t
t
Output disable time
from high or low level
Waveform 6
Waveform 7
2.0
2.0
4.5
3.8
6.5
5.0
2.0
2.0
7.0
6.0
PHZ
PLZ
ns
ns
ns
f
Maximum clock frequency
Waveform 1
Waveform 1
150
165
140
max
t
t
Propagation delay
CP to Qn
3.5
3.5
5.0
5.0
7.5
7.5
3.0
3.0
8.5
8.5
PLH
PHL
74F374
t
t
Output enable time
to high or low level
Waveform 6
Waveform 7
2.0
2.0
9.0
5.3
11.0
7.5
2.0
2.0
12.0
8.5
PZH
PZL
ns
ns
t
t
Output disable time
from high or low level
Waveform 6
Waveform 7
2.0
2.0
5.3
4.3
6.0
5.5
2.0
2.0
7.0
6.5
PHZ
PLZ
6
December 5, 1994
Philips Semiconductors
Product specification
Latch/flip-flop
74F373/74F374
AC SETUP REQUIREMENTS
LIMITS
T
T
amb
= +25°C
= 0°C to +70°C
amb
V
CC
= +5.0V ± 10%
SYMBOL
PARAMETER
TEST
V
CC
= +5.0V
UNIT
CONDITION
C = 50pF, R = 500Ω
C = 50pF, R = 500Ω
L L
L
L
MIN
TYP
MAX
MIN
MAX
t
su
t
su
(H)
(L)
Setup time, high or low level
Dn to E
0
1.0
0
1.0
Waveform 4
ns
t (H)
Hold time, high or low level
Dn to E
74F373
74F374
3.0
3.0
3.0
3.0
h
Waveform 4
Waveform 1
Waveform 5
ns
ns
ns
t
h
(L)
t
w
(H)
E Pulse width, high
3.5
4.0
t
su
t
su
(H)
(L)
Setup time, high or low level
Dn to CP
2.0
2.0
2.0
2.0
t (H)
Hold time, high or low level
Dn to CP
0
0
0
0
h
Waveform 5
Waveform 5
ns
ns
t
h
(L)
t
w
t
w
(H)
(L)
CP Pulse width,
high or low
3.5
4.0
3.5
4.0
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for
predictable output performance.
Dn
V
V
t
M
1/f
M
max
CP
V
V
M
V
M
t
M
PHL
PLH
t
(H)
w
t
t
(L)
t
PHL
PLH
w
Qn
V
V
M
M
V
V
Qn
M
M
SF00260
SF00258
Waveform 3. Propagation delay for data to output
Waveform 1. Propagation delay for clock input to output,
clock pulse widths, and maximum clock frequency
Dn
E
V
V
V
V
M
M
M
M
t
(L)
t (L)
h
t
(H)
t
(H)
t (H)
h
su
w
su
E
V
M
V
V
t
M
M
V
V
M
M
t
PHL
PLH
V
SF00261
Qn
V
M
M
Waveform 4. Data setup time and hold times
SF00259
Waveform 2. Propagation delay for enable to output
and enable pulse width
7
December 5, 1994
Philips Semiconductors
Product specification
Latch/flip-flop
74F373/74F374
AC WAVEFORMS (Continued)
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for
predictable output performance.
Dn
V
V
V
V
M
M
M
M
OEn
V
t
V
M
M
t
(L)
t (L)
h
t
(H)
t (H)
h
su
su
t
PZL
PLZ
CP
V
M
V
M
V
M
Qn, Qn
V
+0.3V
OL
SF00262
Waveform 5. Data setup time and hold times
SF00264
Waveform 7. 3-State output enable time to low level
and output disable time from low level
OEn
V
V
M
M
V
-0.3V
OH
t
t
PHZ
PZH
Qn, Qn
V
M
0V
SF00263
Waveform 6. 3-State output enable time to high level
and output disable time from high level
TEST CIRCUIT AND WAVEFORMS
SWITCH POSITION
t
w
AMP (V)
0V
TEST
SWITCH
closed
open
90%
90%
7.0V
V
CC
NEGATIVE
PULSE
t
, t
PLZ PZL
V
V
M
M
All other
10%
10%
R
L
V
V
OUT
IN
t
t )
t
t )
THL ( f
TLH ( r
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
TLH ( r
THL ( f
R
C
R
L
AMP (V)
0V
T
L
90%
M
90%
POSITIVE
PULSE
V
V
M
Test circuit for 3-state outputs
DEFINITIONS:
10%
10%
t
w
Input pulse definition
R
C
Load resistor; see AC electrical characteristics for value.
L =
L =
INPUT PULSE REQUIREMENTS
V
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
family
rep. rate
t
t
t
THL
amplitude
M
w
TLH
R
T =
Termination resistance should be equal to Z
generators.
of pulse
OUT
74F
3.0V
1.5V
1MHz
500ns 2.5ns
2.5ns
SF00265
8
December 5, 1994
Philips Semiconductors
Product specification
Latch/flip-flop
74F373, 74F374
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
9
1994 Dec 05
Philips Semiconductors
Product specification
Latch/flip-flop
74F373, 74F374
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
10
1994 Dec 05
Philips Semiconductors
Product specification
Latch/flip-flop
74F373, 74F374
NOTES
11
1994 Dec 05
Philips Semiconductors FAST Products
Product specification
Latch/flip-flop
74F373, 74F374
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
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indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1994
All rights reserved. Printed in U.S.A.
(print code)
Date of release: July 1994
9397-750-05119
Document order number:
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