NE56632-46D [NXP]
Active-LOW system reset with adjustable delay time; 带可调延时低有效的系统复位
| 型号： | NE56632-46D |
| 厂家： | 
NXP |
| 描述： | Active-LOW system reset with adjustable delay time |
| 文件： | 总16页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
NE56632-XX
Active-LOW system reset
with adjustable delay time
Product data
2002 Mar 25
Philips
Semiconductors
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
DESCRIPTION
The NE56632-XX is a family of Active-LOW, power-on reset that
offers precision threshold voltage detection within ±1.5% and super
low operating supply current of typically 3.0 µA. It includes a reset
delay that is user adjustable with an external capacitor.
Several detection threshold voltages are available at 1.9V , 2.0 V,
2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 4.2 V, 4.3 V, 4.4 V, 4.5 V, and 4.6 V.
Other thresholds are offered upon request at 100 mV steps from
1.9 V to 4.6 V.
With its ultra low supply current and high precision voltage threshold
detection capability, the NE56632-XX is well suited for various
battery powered applications such as reset circuits for logic and
microprocessors, voltage check, and level detecting. It is available in
the SOT23-5 package.
FEATURES
APPLICATIONS
• High precision threshold detection voltage: V ±1.5%
• Reset for microprocessor and logic circuits
• Voltage level detection circuit
S
• Super low operating supply current: 3 µA typ.
• Built-in hysteresis voltage: 50 mV typ.
• Battery voltage check circuit
• Detection threshold voltage: 1.9 V, 2.0 V, 2.7 V, 2.8 V, 2.9 V,
• Detection circuit for battery back-up
3.0 V, 3.1 V, 4.2 V, 4.3 V, 4.4 V, 4.5 V, and 4.6 V.
• Reset Output: Active-LOW, open collector
• Other detection threshold voltages available upon request at
100 mV steps from 1.9 V to 4.6 V.
• Large low reset output current: 30 mA typ.
• Power-on reset delay time adjustable with external capacitor:
200 µs to 200 ms
• Reset assertion with V down to 0.65 V
CC
SIMPLIFIED SYSTEM DIAGRAM
TO V
TO RESET
TERMINAL
OF CPU
CC
R
PU
5
1
4
3
NE56632-XX
2
C
D
SL01605
Figure 1. Simplified system diagram.
2
2002 Mar 25
853–2329 27919
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
ORDERING INFORMATION
PACKAGE
TEMPERATURE
RANGE
TYPE NUMBER
NAME
DESCRIPTION
NE56632-XXD
SOT23-5 / SOT25 (SO5)
plastic small outline package; 5 leads (see dimensional drawing)
Part number marking
–20 to +75 °C
NOTE:
The device has 12 voltage output options, indicated by the XX on
the ‘Type number’.
The package is marked with a four letter code. The first three letters
designate the product. The fourth letter, represented by ‘x’, is a date
tracking code.
XX
19
20
27
28
29
30
31
42
43
44
45
46
VOLTAGE (Typical)
1.9 V
Part Number
NE56632-19D
NE56632-20D
NE56632-27D
NE56632-28D
NE56632-29D
NE56632-30D
NE56632-31D
NE56632-42D
NE56632-43D
NE56632-44D
NE56632-45D
NE56632-46D
Marking
AKZx
ALAx
ALBx
ALCx
ALDx
ALEx
ALFx
ALGx
ALHx
ALJx
2.0 V
2.7 V
2.8 V
2.9 V
3.0 V
3.1 V
4.2 V
4.3 V
4.4 V
4.5 V
ALKx
ALLx
4.6 V
PIN CONFIGURATION
PIN DESCRIPTION
PIN
SYMBOL
DESCRIPTION
1
TC
Delay time control; set with external
capacitor.
TC
SUB
GND
1
2
3
5
4
V
V
CC
2
3
4
5
SUB
GND
Substrate. Connect to ground (GND).
Ground. Negative supply.
NE56632-XX
V
OUT
Reset output voltage. Active-LOW.
OUT
V
CC
Positive supply voltage; detection threshold
voltage input.
SL01604
Figure 2. Pin configuration.
MAXIMUM RATINGS
SYMBOL
PARAMETER
MIN.
–0.3
–20
–40
–
MAX.
+10
UNIT
V
V
CC
Supply voltage
T
amb
Ambient operating temperature
Storage temperature
+75
°C
T
stg
+125
150
°C
P
Power dissipation
mW
3
2002 Mar 25
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
ELECTRICAL CHARACTERISTICS
T
amb
= 25 °C, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
-XX
46
45
44
43
42
31
30
29
28
27
20
19
MIN.
4.531
4.432
4.334
4.235
4.137
3.053
2.955
2.856
2.758
2.659
1.970
1.871
25
TYP.
4.600
4.500
4.400
4.300
4.200
3.100
3.000
2.900
2.800
2.700
2.000
1.900
50
MAX.
4.669
4.568
4.466
4.365
4.263
3.147
3.045
2.944
2.842
2.741
2.030
1.929
100
UNIT
V
V
S
Detection threshold
V
= HIGH-to-LOW; R = 4.7 kΩ; S1=ON;
CC
L
V
OL
≤ 0.4 V;
V
Test Circuit 1 (Figure 27)
V
V
V
V
V
V
V
V
V
V
V
hys
Hysteresis voltage
R = 4.7 kΩ; V = LOW-to-HIGH-to-LOW; S1 = ON; Test
mV
L
CC
Circuit 1 (Figure 27)
V /∆T
Detection threshold voltage
temperature coefficient
R = 4.7 kΩ; T = –20 °C to +75 °C; S1 = ON;
–
–
±0.01
–
%/°C
S
L
amb
Test Circuit 1 (Figure 27)
V
OL
LOW-level output voltage
V
CC1
= V
– 0.05 V; R = 4.7 kΩ; S1 = ON;
0.2
0.4
V
S(min)
L
Test Circuit 1 (Figure 27)
I
I
I
t
t
Output leakage current
Supply current (ON time)
Supply current (OFF time)
LOW-to-HIGH delay time
HIGH-to-LOW delay time
V
= V
= 10 V; S2 = ON; Test Circuit 1 (Figure 27)
–
–
–
–
–
–
–
±0.1
9.0
5.0
–
µA
µA
µA
ms
µs
V
LO
CC1
CC2
V
CC1
= V
– 0.05 V; R = ∞; Test Circuit 1 (Figure 27)
5.0
CCL
CCH
PLH
PHL
S(min)
L
V
= V
/0.85; R = ∞; Test Circuit 1 (Figure 27)
3.0
CC1
S(typ)
L
C = 100 pF; R = 4.7 kΩ; C = 10 nF (Note 1)
L
(Note 3)
(Note 3)
0.65
L
D
C = 100 pF; R = 4.7 kΩ; C = 10 nF (Note 2)
L
–
L
D
V
Minimum operating
threshold voltage
R = 4.7 kΩ; V ≤ 0.4 V; S1 = ON;
0.80
OPL
L
OL
Test Circuit 1 (Figure 27)
I
Output current (ON Time 1)
V
CC2
= 0.4 V; R = 0; V
= 0.4 V; S2 = ON; Test Circuit 1 (Figure 27)
= V – 0.05 V;
S(min)
5
3
–
–
–
–
mA
mA
OL1
O
L
CC1
V
I
Output current (ON Time 2)
V
O
= 0.4 V; R = 0; V
= V
– 0.05 V;
S(min)
OL2
L
CC1
T
amb
= –20 °C to +75 °C; S2 = ON;
Test Circuit 1 (Figure 27)
NOTES:
1. t
2. t
:
:
V
V
= (V
= (V
– 0.4 V) to (V
+ 0.4 V) to (V
+ 0.4 V); t
– 0.4 V); t
is release delay time (Test Circuit 2, Figure 28).
is assertion delay time (Test Circuit 2, Figure 28).
PLH
CC
S(typ)
S(typ)
S(typ)
S(typ)
PLH
PHL
PHL
CC
3. See Table 1.
Table 1. NE56632-XX series typical delay time
–XX
46
45
44
43
42
31
30
29
28
27
20
19
t
t
PHL
PLH
195 ms
190 ms
185 ms
180 ms
175 ms
120 ms
115 ms
110 ms
105 ms
100 ms
65 ms
140 µs
140 µs
140 µs
140 µs
140 µs
120 µs
120 µs
120 µs
100 µs
100 µs
100 µs
100 µs
60 ms
4
2002 Mar 25
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
TYPICAL PERFORMANCE CURVES, NE56632-20
2.0050
2.0025
2.0000
1.9975
1.9950
1.9925
1.9900
1.9875
1.9850
100
90
80
70
60
50
40
30
Test Circuit 1
= HIGH-to-LOW
Test Circuit 1
V
CC
V = LOW-to-HIGH-to-LOW
R
= 4.7 kΩ
≤ 0.4 V
CC
L
R
= 4.7 kΩ
V
L
OL
S1 = ON
S1 = ON
–40
–20
–40 –20
0
20
40
60
80
100
0
20
40
60
80
100
100
100
AMBIENT TEMPERATURE, T
(°C)
AMBIENT TEMPERATURE, T
(°C)
amb
amb
SL01620
SL01621
Figure 3. Detection threshold versus temperature.
Figure 4. Hysteresis voltage versus temperature.
0.225
9
8
7
6
5
0.220
0.215
0.210
0.205
0.200
0.195
0.190
0.185
Test Circuit 1
= V
4
V
– 0.05 V
S(min)
Test Circuit 1
CC1
R
= 4.7 kΩ
V
R
= V
= ∞
– 0.05 V
0
L
CC1
L
S(min)
S1 = ON
3
–40
–20
–40
–20
0
20
40
60
80
100
20
40
60
80
AMBIENT TEMPERATURE, T
(°C)
AMBIENT TEMPERATURE, T
(°C)
amb
amb
SL01622
SL01623
Figure 5. LOW-level output voltage versus temperature.
Figure 6. Supply current (ON time) versus temperature.
0.9
0.8
0.7
0.6
0.5
4.5
4.0
3.5
3.0
2.5
Test Circuit 1
0.4
Test Circuit 1
R
V
= 4.7 kΩ
≤ 0.4 V
L
OL
R
V
= ∞
L
= V
/0.85
S(typ)
S1 = ON
CC1
2.0
0.3
–40
–40
–20
–20
0
20
40
60
80
100
0
20
40
60
80
AMBIENT TEMPERATURE, T
(°C)
AMBIENT TEMPERATURE, T (°C)
amb
amb
SL01624
SL01625
Figure 7. Supply current (OFF time) versus temperature.
Figure 8. Min. operating threshold voltage versus temperature.
5
2002 Mar 25
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
TYPICAL PERFORMANCE CURVES, NE56632-20 (continued)
100
90
80
70
60
50
40
37
35
33
31
29
27
25
Test Circuit 2
C
R
C
= 100 pF
= 4.7 kΩ
= 10 nF
L
L
D
Test Circuit 1
V
V
V
= V
= 0.4 V
= 0.4 V
= 0 Ω
– 0.05 V
CC1
CC2
O
S(min)
V
= (V
– 0.4 V) to (V
+ 0.4 V)
S(typ)
CC
S(typ)
R
L
S2 = ON
t
= Release Delay Time
PLH
–40 –20
–40
–20
0
20
40
60
(°C)
80
100
0
20
40
60
80
100
AMBIENT TEMPERATURE, T
AMBIENT TEMPERATURE, T
(°C)
amb
amb
SL01626
SL01627
Figure 9. Output current (ON time 1) versus temperature.
Figure 10. LOW-to-HIGH delay time versus temperature.
120
Test Circuit 2
C
R
C
= 100 pF
= 4.7 kΩ
= 10 nF
L
L
D
115
110
105
100
95
90
85
V
= (V
+ 0.4 V) to (V
– 0.4 V)
S(typ)
CC
S(typ)
t
= Assertion Delay Time
PHL
80
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE, T
(°C)
amb
SL01628
Figure 11. HIGH-to-LOW delay time versus temperature.
6
2002 Mar 25
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
TYPICAL PERFORMANCE CURVES, NE56632-31
3.11
3.10
3.09
3.08
90
80
70
60
50
40
30
Test Circuit 1
Test Circuit 1
= LOW-to-HIGH
V
R
= HIGH-to-LOW
= 4.7 kΩ
CC
L
V
CC
R
= 4.7 kΩ
V
≤ 0.4 V
L
OL
S1 = ON
S1 = ON
–40
–20
–40 –20
0
20
40
60
80
100
0
20
40
60
80
100
AMBIENT TEMPERATURE, T
(°C)
AMBIENT TEMPERATURE, T (°C)
amb
amb
SL01629
SL01630
Figure 12. Detection threshold versus temperature.
Figure 13. Hysteresis voltage versus temperature.
0.23
0.22
0.21
0.20
0.19
9
8
7
6
5
4
Test Circuit 1
= V
0.18
Test Circuit 1
3
V
– 0.05 V
S(min)
CC1
V
= V
– 0.05 V
0
R
= 4.7 kΩ
CC1
S(min)
L
R
= ∞
S1 = ON
L
0.17
–40
2
–20
–40
–20
0
20
40
60
80
100
20
40
60
80
100
AMBIENT TEMPERATURE, T
(°C)
AMBIENT TEMPERATURE, T
(°C)
amb
amb
SL01631
SL01632
Figure 14. LOW–level output voltage versus temperature.
Figure 15. Supply current (ON time) versus temperature.
0.9
0.8
0.7
0.6
0.5
4.5
4.0
3.5
3.0
Test Circuit 1
0.4
2.5
Test Circuit 1
R
V
= 4.7 kΩ
≤ 0.4 V
L
R
V
= ∞
L
OL
S1 = ON
= V
/0.85
CC1
S(typ)
2.0
–40
0.3
–40
–20
–20
0
20
40
60
80
100
0
20
40
60
80
100
AMBIENT TEMPERATURE, T
(°C)
AMBIENT TEMPERATURE, T (°C)
amb
amb
SL01633
SL01634
Figure 16. Supply current (OFF time) versus temperature.
Figure 17. Min. operating threshold voltage versus
temperature.
7
2002 Mar 25
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
TYPICAL PERFORMANCE CURVES, NE56632-31 (continued)
36
37
34
35
32
30
33
28
31
26
Test Circuit 1
V
V
V
= V
= 0.4 V
= 0.4 V
– 0.05 V
– 0.05 V
24
22
20
CC1
CC2
O
S(min)
29
R
= 0 Ω
R = 0 Ω
L
L
S2 = ON
S2 = ON
–20
27
–40
–20
–40
0
20
40
60
80
100
0
20
40
60
80
100
AMBIENT TEMPERATURE, T
(°C)
AMBIENT TEMPERATURE, T (°C)
amb
amb
SL01635
SL01636
Figure 18. Output current (ON time 1) versus temperature.
Figure 19. Output current (ON time 2) versus temperature.
180
160
Test Circuit 2
Test Circuit 2
C
R
C
= 100 pF
= 4.7 kΩ
= 10 nF
C
R
C
= 100 pF
= 4.7 kΩ
= 10 nF
L
L
D
L
L
D
150
140
130
120
110
100
90
160
140
120
100
80
60
V
t
= (V
+ 0.4 V) to (V
– 0.4 V)
S(typ)
V
t
= (V
– 0.4 V) to (V
+ 0.4 V)
S(typ)
CC
S(typ)
CC
S(typ)
= Assertion Delay Time
= Release Delay Time
PHL
20
PLH
20
40
80
–40
–20
–40
–20
0
40
60
80
100
0
40
60
80
100
AMBIENT TEMPERATURE, T
(°C)
AMBIENT TEMPERATURE, T
(°C)
amb
amb
SL01637
SL01638
Figure 20. LOW-to-HIGH delay time versus temperature.
Figure 21. HIGH-to-LOW delay time versus temperature.
8
2002 Mar 25
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
the threshold comparator which is less than V , causing the output
TECHNICAL DISCUSSION
REF
of the comparator to go to a HIGH state. This causes the common
emitter amplifier, Q1 to turn ON pulling down the non-inverting
terminal of Comparator 2 which causes its output to go to a HIGH
state. This HIGH output level turns on the output common emitter
transistor, Q2. The collector output of Q2 is pulled LOW through the
external pull-up resistor, thereby asserting the Active-LOW reset.
The NE56632-XX is a bipolar IC designed to provide power source
monitoring and a system reset function in the event the power sags
below an acceptable level for the system to operate reliably. The
reset threshold incorporates a typical hysteresis of 50 mV to prevent
erratic reasserts from being generated. An internal delay time circuit
provides a adjustable power-on reset delay of typically 200 µs to
200 ms using an external capacitor.
Threshold hysteresis is established by turning on the bipolar common
emitter transistor, Q1 when the input threshold Comparator 1 goes
The output of the NE56632-XX utilizes an open collector topology,
to a HIGH state. This occurs when V sags to or below the
CC
which requires an external pull-up resistor to V . Though this may
CC
threshold level. With the output of Q1 connected to the non-inverting
terminal of Comparator 2, the non-inverting terminal has a level near
ground at about 0.4 V when the reset is asserted (Active-LOW). For
the Comparator 2 to reverse its output, the Comparator 1 output and
Q1 must overcome the additional pull-down voltage present on the
inverting input of Comparator 2. The differential voltage required to
do this establishes the hysteresis voltage of the sensed threshold
voltage. Typically, it is 50 mV.
be regarded as a disadvantage, it is advantageous in many
sensitive applications. Because the open collector output cannot
source reset current when both are operated from a common supply,
the NE56632-XX offers a safe interconnect to a wide variety of
microprocessors.
The NE56632-XX operates at low supply currents, typically 3 µA,
while offering precision threshold detection (±1.5%).
Figure 22 is a functional block diagram of the NE56632-XX. The
When V sags, and it is below the detection Threshold (V ), the
CC
SL
internal reference source voltage, V
, is typically 0.65 V over the
REF
device will assert a Reset LOW output at or near ground potential.
As V rises from (V < V ) to V or higher, the Reset is
temperature range. The reference voltage is connected to the
non-inverting inputs of the threshold Comparator 1 and
Comparator 2, while the inverting input of Comparator 1 monitors
the supply voltage through a voltage divider (R1 and R2). The output
of the comparator drives the series base resistor, R3 of a common
emitter amplifier, Q1. The collector of Q1 is connected to the
inverting terminal of Comparator 2. The output of Comparator 2 is
connected to the series base resistor, R4 of the output common
emitter transistor, Q2. The open collector output of Q2 provides the
reset output.
CC
CC
SL
SH
released and the output follows V . Conversely, decreases in V
CC
CC
from (V > V ) to V will cause the output to be pulled to ground.
CC
SL
SL
Hysteresis voltage = Release voltage – Detection Threshold voltage
V
hys
= V – V
SH SL
where:
V
SH
V
SL
= V + V
SL
hys
hys
= V – V
SH
The Delay Time Control is outputted at the junction of the collector
of Q1 and the inverting input of Comparator 2. The reset release
When V drops below the minimum operating voltage, typically
0.65 V, the output is undefined and the output reset low assertion is
CC
time delay, t
is set with an external capacitor. Figures 25 and 26
PLH
no longer guaranteed. At this level of V the output will try to rise to
CC
show t
as a function of the external delay capacitor, C .
D
PLH
V
CC
. As V drops even further to zero, V
reset also goes to
OUT
CC
zero.
When the supply voltage sags to the threshold detection voltage, the
resistor divider network supplies a voltage to the inverting terminal of
5
V
CC
I
D
R1
R2
COMP1
COMP2
4
V
OUT
V
REF
R3
R4
Q1
Q2
GND
SUB
3
2
1
(SUBSTRATE)
SL01607
TC
Figure 22. Functional diagram.
9
2002 Mar 25
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
TIMING DIAGRAM
The timing diagram in Figure 23 depicts the operation of the device.
Letters A–N on the TIME axis indicates specific events.
G-H: At “G”, V is above the upper threshold and begins to fall,
CC
causing V
to follow it. As long as V remains above the V
,
OUT
CC
SH
no reset signal will be generated.
A: At “A”, V begins to increase. Also the V
voltage initially
CC
OUT
increases but abruptly decreases when V reaches the level
H: At event “H”, V falls until the V undervoltage detection
CC
CC
SL
(approximately 0.65 V) that activates the internal bias circuitry and
RESET is asserted.
threshold is reached. At this level, a RESET signal is generated and
goes LOW.
V
OUT
B: At “B”, V reaches the threshold level of V . At this point the
H-I: Between “H” and “I”, V continues to fall and then starts to
CC
CC
SH
delay time, t
is initiated while V rises above V to its normal
rise rising. V rises to the V level at “I”, where the delay time is
CC SH
PLH
CC
SH
operating level. The V
voltage remains in a low voltage state.
again initiated.
OUT
C: At “C”, V is above V and the delay time elapses. At this
I-J: Between “I” and “J”, V rises above V to V normal and
CC SH CC
CC
SL
instant, the IC releases the hold on the V
reset. The reset output
then falls back to V level at “J”. At “J”, the reset signal is
OUT
SL
then goes HIGH (assuming the reset pull-up resistor R is
reasserted before the delay time has elapsed. The time between “I”
PU
connected to V ). In a microprocessor based system these events
and “J” is less than t
(reset delay time). Thus, the reset is not
CC
PLH
release the reset from the microprocessor, allowing the
microprocessor to function normally.
released and the reset output remains LOW.
K–L: Between “K” and “L”, V rises again back to normal
CC
D-E: At “D”, V begins to fall, causing V
to follow. V
CC
operating level causing the reset delay to be initiated at “K” and the
reset to be released at “L”.
CC
OUT
continues to fall until the V undervoltage detection threshold is
SL
reached at “E”. This causes a reset signal to be generated (V
goes LOW).
OUT
M: At “M”, V falls to V where the reset is asserted (V
OUT
Reset goes LOW).
CC
SL
E-F: Between “E” and “F”, V continues to fall and then starts
rising.
CC
N: At “N”, the V voltage has decreased until normal internal
CC
circuit bias is unable to maintain a V
reset. As a result, V may
CC
OUT
F: At “F”, V rises to the V level. Once again, the device
rise to less than 0.65 V. As V decreases further, the V
reset
CC
SH
CC
OUT
initiates the delay timer.
also decreases to zero.
F-G:
(t
V
rises above V and returns to normal. At “G”, the delay
CC SH
) times out and once again, then it releases the hold on the
PLH
V
OUT
reset.
V
V
hys
V
V
SH
SL
V
CC
< t
PLH
V
V
OUT
(RESET)
t
t
t
PLH
PLH
PLH
A
B
C
D
E
F
G
H
I
J
K
L
M
N
SL01606
Figure 23. Timing diagram.
10
2002 Mar 25
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
APPLICATION INFORMATION
A typical application circuit for the NE56632-XX is shown in
1.0E+00
Figure 24. Note that a pull-up resistor, R is necessary since the
PU
output is an open collector. The value of RPU is calculated by the
following expression.
1.0E–01
1.0E–02
1.0E–03
1.0E–04
1.0E–05
R
≥ (V – V
) / I
RESET OL
PU
CC
where:
V
V
= V
– 0.05 V (for a 3 V reset this is 2.905 V)
S(min)
CC
= 0.4 V (this is V
)
RESET
OL(max)
I
OL
= 5 mA; minimum output current at T
= 25 °C
amb
Substituting these values into the expression and calculating, finds
should be greater than or equal to 510 Ω. To ensure that the
R
PU
Active-LOW level is sufficient, a value of 4.7 kΩ is chosen in the test
and application examples.
1.0E+00
1.0E+01
1.0E+02
(pF)
1.0E+03
1.0E+04
C
D
SL01611
TO V
TO RESET
TERMINAL
OF CPU
CC
Figure 25. NE56632-20 C versus t
characteristics.
D
PLH
R
PU
1.0E+00
1.0E–01
1.0E–02
1.0E–03
1.0E–04
1.0E–05
5
1
4
3
NE56632-XX
2
C
D
SL01605
Figure 24. Typical application.
1.0E+00
1.0E+01
1.0E+02
(pF)
1.0E+03
1.0E+04
Figure 25 (NE56632-20 C versus t
) and Figure 26
PLH
D
C
D
(NE56632-44 C versus t
delay or reset release delay time varies as a function of the external
) show how t
, the “H” transmission
PHL
D
PLH
SL01612
delay capacitance, C . From Figure 26, typical range of the delay
Figure 26. NE56632-44 C versus t
characteristics.
D
D
PLH
capacitance is 1 pF to 10 nF which yields typical delays from 200 µs
to 200 ms.
The following formula can be used to find the approximate delay
Table 2. Delay time coefficient
Device
time based on external delay capacitance, C and the delay time
D
d
coefficient, d shown in Table 2.
4
NE56632–46
1.95 × 10
t
(ms) ≈ C (µF) × d
D
PLH
4
NE56632–45
1.90 × 10
For example, a NE56632-44 using an external capacitor,
4
NE56632–44
1.85 × 10
C
= 1 nF = 1000 pF yields:
D
4
NE56632–43
1.80 × 10
–3
4
t
(ms) ≈ (1 × 10 ) (1.85 × 10 ) ≈ 18.5 ms
PLH
4
NE56632–42
1.75 × 10
Compare this to the value of t
extracted from Figure 26.
≈ 17 ms for C = 1000 pF that is
D
PLH
4
NE56632–31
1.20 × 10
4
NE56632–30
1.15 × 10
4
NE56632–29
1.10 × 10
4
NE56632–28
1.05 × 10
4
NE56632–27
1.00 × 10
4
NE56632–20
0.65 × 10
4
NE56632–19
0.60 × 10
11
2002 Mar 25
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
TEST CIRCUITS
S1
R
L
A1
S2
A2
5
1
4
3
10 µF
/10 V
V1
V2
V
V
CC2
NE56632-XX
CC1
2
C
D
S3
SL01608
Figure 27. Test circuit 1.
5
1
4
3
R
L
10 µF
/10 V
V
+ 0.4 V
V
– 0.4 V
S(typ)
S(typ)
5.0 V
INPUT
PULSE
0V
NE56632-XX
SL01610
2
Figure 29. Input pulse.
CRT
C
L
100 pF
C
D
NOTES:
A = DC amperemeter
V = DC voltmeter
CRT = oscilloscope
SL01609
Figure 28. Test circuit 2.
12
2002 Mar 25
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
PACKING METHOD
The NE56632-XX is packed in reels, as shown in Figure 30.
GUARD
BAND
TAPE
TAPE DETAIL
REEL
ASSEMBLY
COVER TAPE
CARRIER TAPE
BARCODE
LABEL
BOX
SL01305
Figure 30. Tape and reel packing method.
13
2002 Mar 25
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
SOT23-5: plastic small outline package; 5 leads; body width 1.5 mm
1.2
1.0
0.55
0.41
0.22
0.08
3.00
2.70
1.70
1.50
0.55
0.35
0.025
1.35
14
2002 Mar 25
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
NOTES
15
2002 Mar 25
Philips Semiconductors
Product data
Active-LOW system reset with adjustable delay time
NE56632-XX
Data sheet status
Product
status
Definitions
[1]
Data sheet status
[2]
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Koninklijke Philips Electronics N.V. 2002
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 08-02
9397 750 10239
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
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