NTS0304EPW [NXP]
4-bit dual supply translating transceiver; open drain; auto direction sensing;型号: | NTS0304EPW |
厂家: | NXP |
描述: | 4-bit dual supply translating transceiver; open drain; auto direction sensing |
文件: | 总26页 (文件大小:680K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NTS0304E
4-bit dual supply translating transceiver; open drain; auto
direction sensing
Rev. 1 — 01 February 2019
Product data sheet
1. General description
The NTS0304E is a 4-bit, dual supply translating transceiver family with auto direction
sensing, that enables bidirectional voltage level translation. It features eight 1-bit
input-output ports (A and B), one output enable input (OE) and two supply pins (VCC(A)
and VCC(B)). VCC(A) can be supplied at any voltage between 0.95 V and 3.6 V. VCC(B) can
be supplied at any voltage between 1.65 V and 5.5 V. This flexibility makes the device
suitable for translating between any of the voltage nodes (0.95 V, 1.2 V, 1.8 V, 2.5 V, 3.3 V
and 5.0 V). Pins A and OE are referenced to VCC(A) and pin B is referenced to VCC(B). A
LOW level at pin OE causes the outputs to assume a high-impedance OFF-state.
2. Features and benefits
Wide supply voltage range:
VCC(A): 0.95 V to 3.6 V and VCC(B): 1.65 V to 5.5 V
No power-sequencing required
Maximum data rate
Open-drain: 2 Mbps
Push-pull: 20 Mbps
Longer one-shot pulse for driving larger capacitive loads with much reduced ringing
and overshoot
A-side and OE inputs accept voltages up to 3.6 V and are 3.6 V tolerant
B-side inputs accept voltages up to 5.5 V and are 5.5 V tolerant
ESD protection:
IEC 61000-4-2 Class 4, 8 kV contact for B-side port
HBM JESD22-A114E Class 2 exceeds 2000 V for both ports
CDM JESD22-C101E exceeds 1000 V for both ports
Latch-up performance exceeds 100 mA per JESD 78B Class II
Package options: TSSOP14 and WLCSP12
Specified from 40 C to +125 C
3. Applications
I2C/SMBus, UART
GPIO
NTS0304E
NXP Semiconductors
4-bit dual supply translating transceiver; open drain; auto direction
sensing
4. Ordering information
Table 1.
Ordering information
Type number
Topside
marking
Package
Name
Description
Version
NTS0304EUK
NTS0304EPW
S4
WLCSP12 wafer level chip scale package; 12 balls with 0.4 mm pitch; SOT1390-10
1.42 x 1.97 x 0.525 mm
NTS0304
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
WLCSP12
TSSOP14
Packing method
Minimum
order quantity
Temperature
Tamb = 40 C to +125 C
NTS0304EUK
NTS0304EPW
NTS0304EUKZ
NTS0304EPWJ
reel 7" q1/t1 *special 4000
mark chips dp
reel 13" q1/t1
2500
Tamb = 40 C to +125 C
*standard mark smd
5. Functional diagram
GATE BIAS
OE
A1
B1
An
Bn
V
V
CC(B)
CC(A)
aaa-031817
Fig 1. Logic symbol
NTS0304E
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© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 1 — 01 February 2019
2 of 26
NTS0304E
NXP Semiconductors
4-bit dual supply translating transceiver; open drain; auto direction
sensing
6. Pinning information
6.1 Pinning
NTS0304E
ball A1
index area
1
2
3
A
B
C
D
1
2
3
4
5
6
7
14
13
12
11
10
9
V
V
CC(B)
CC(A)
A1
B1
B2
B3
B4
n.c.
OE
A2
A3
NTS0304EPW
A4
n.c.
GND
Transparent top view
8
aaa-031818
aaa-031040
Fig 2. NTS0304EPW Pin configuration
Fig 3. NTS0304EUK Pin configuration WLCSP12
6.2 Pin description
Table 3.
Symbol
NTS0304E Pin description
Pin
Ball
Description
SOT402-1
WLCSP12
VCC(A)
1
B2
supply voltage A
A1, A2, A3, A4 2, 3, 4, 5
A3, B3, C3, D3
data input or output (referenced to VCC(A)
)
n.c.
GND
OE
6, 9
7
-
not connected
D2
ground (0 V)
8
C2
output enable input (active HIGH; referenced to VCC(A))
B4, B3, B2, B1 10, 11, 12, 13
VCC(B) 14
D1, C1, B1, A1
A2
data input or output (referenced to VCC(B)
)
supply voltage B
7. Functional description
Table 4.
Function table[1]
Supply voltage
VCC(A)
Input
OE
L
Input/output
VCC(B)
A
B
0.95 V to VCC(B)
0.95 V to VCC(B)
GND[2]
1.65 V to 5.5 V
1.65 V to 5.5 V
GND[2]
Z
Z
H
input or output
Z
output or input
Z
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] When either VCC(A) or VCC(B) is at GND level, the device goes into power-down mode.
NTS0304E
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 1 — 01 February 2019
3 of 26
NTS0304E
NXP Semiconductors
4-bit dual supply translating transceiver; open drain; auto direction
sensing
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC(A)
VCC(B)
VI
Parameter
Conditions
Min
Max
+4.6
+6.5
+6.5
+6.5
Unit
V
supply voltage A
supply voltage B
input voltage
0.5
0.5
0.5
0.5
V
[1][2]
[1][2]
[1][2]
A port and OE input
B port
V
V
VO
output voltage
Active mode
A or B port
0.5
VCCO + 0.5
V
[1]
Power-down or 3-state mode
A port
0.5
0.5
50
50
-
+4.6
+6.5
-
V
B port
V
IIK
input clamping current
output clamping current
output current
VI < 0 V
mA
mA
mA
mA
mA
C
IOK
IO
VO < 0 V
-
[2]
VO = 0 V to VCCO
ICC(A) or ICC(B)
50
100
-
ICC
IGND
Tstg
supply current
-
ground current
100
65
storage temperature
+150
[1] The minimum input and minimum output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output.
9. Recommended operating conditions
Table 6.
Symbol
VCC(A)
VCC(B)
VI_EN
Recommended operating conditions[1][2]
Parameter
Conditions
Min
0.95
1.65
-0.3
40
40
Max
Unit
V
[2]
supply voltage A
3.6
supply voltage B
5.5
V
EN input voltage
VCC(A)+0.3
+125
+85
V
Tamb
ambient temperature
C
C
[3]
[2]
TJ
junction temperature
t/V
input transition rise and fall rate A or B port; push-pull driving
VCC(A) = 0.95 V to 3.6 V;
VCC(B) = 1.65 V to 5.5 V
-
-
10
10
ns/V
ns/V
OE input
VCC(A) = 0.95 V to 3.6 V;
VCC(B) = 1.65 V to 5.5 V
[1] The A and B sides of an unused I/O pair must be held in the same state, both at VCCI or both at GND.
[2] CC(A) must be less than or equal to VCC(B)
V
.
[3] The TJ limits shall be supported by proper thermal PCB design taking the power consumption and the thermal resistance as listed in
Table 7 into account.
NTS0304E
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 1 — 01 February 2019
4 of 26
NTS0304E
NXP Semiconductors
4-bit dual supply translating transceiver; open drain; auto direction
sensing
10. Thermal characteristics
Table 7.
Symbol
Thermal resistance information
Rating
NTS0304EPW
(TSSOP14)
NTS0304EUK
(WLCSP12)
RJA
Junction to ambient
114.9
1.6
57.8
0.2
JT
Junction to top characterization
11. Static characteristics
Table 8.
Typical static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
II
input leakage
current
OE input; VI = 0 V to 3.6 V; VCC(A) = 0.95 V to 3.6 V;
VCC(B) = 1.65 V to 5.5 V
-
-
1
A
[1]
IOZ
CI
OFF-stateoutput A or B port; VO = 0 V or VCCO; VCC(A) = 0.95 V to 3.6 V;
-
-
-
1
A
current
VCC(B) = 1.65 V to 5.5 V
input
OE input; VCC(A) = 3.3 V; VCC(B) = 3.3 V
1
-
pF
capacitance
CI/O
input/output
capacitance
A port
-
-
-
4
-
-
-
pF
pF
pF
B port
7.5
11
A or B port; VCC(A) = 3.3 V; VCC(B) = 3.3 V
[1] VCCO is the supply voltage associated with the output.
Table 9.
Typical supply current
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C.
VCC(B)
1.65 V
ICC(A)
2.5 V
ICC(A)
3.3 V
ICC(A)
5.0 V
ICC(A)
ICC(B)
ICC(B)
ICC(B)
ICC(B)
VCC(A)
0.95 V
1.2 V
1.8 V
2.5 V
3.3 V
Unit
0.1
0.1
0.1
0.1
0.1
0.2
-
0.5
0.5
0.5
0.5
0.1
0.1
0.1
0.1
0.1
0.5
0.5
0.5
0.5
0.1
0.1
0.1
0.1
0.1
0.1
3
3
3
3
2
A
A
A
A
A
0.1
0.1
-
-
-
-
-
-
-
NTS0304E
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 1 — 01 February 2019
5 of 26
NTS0304E
NXP Semiconductors
4-bit dual supply translating transceiver; open drain; auto direction
sensing
Table 10. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
VIH
HIGH-level
A port
input voltage
[1]
[1]
VCC(A) = 0.95 V to 1.65 V;
VCC(B) = 1.65 V to 5.5 V
VCCI 0.2
VCCI 0.4
-
-
VCCI 0.2
VCCI 0.4
-
-
V
V
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
B port
[1]
VCC(A) = 0.95 V to 3.6 V;
VCC(B) = 1.65 V to 5.5 V
VCCI 0.4
-
-
VCCI 0.4
-
-
V
V
OE input
VCC(A) = 0.95 V to 3.6 V;
0.65VCC(A)
0.65VCC(A)
VCC(B) = 1.65 V to 5.5 V
VIL
LOW-level
A or B port
input voltage
VCC(A) = 0.95 V to 1.65 V;
VCC(B) = 1.65 V to 5.5 V
-
-
0.13
0.15
-
-
0.13
0.15
V
V
VCC(A) = 1.65 V to 3.6 V;
VCC(B) = 2.3 V to 5.5 V
OE input
VCC(A) = 0.95 V to 3.6 V;
-
0.35VCC(A)
-
0.35VCC(A)
V
VCC(B) = 1.65 V to 5.5 V
VOHA
HIGH-level
IO = 20 A
output voltage
[2]
VCC(B) = 1.65 V to 5.5 V;
VCCI = VCC(B) - 0.4 V
[2]
[2]
VCC(A) = 1.65 V to 3.6 V
VCC(A) = 0.95 V to 1.65 V
IO = 20 A
0.8VCC(A)
-
-
0.75VCC(A)
0.62VCC(A)
-
-
V
V
0.65VCC(A)
VOHB
HIGH-level
output voltage
[2]
[2]
VCC(A) = 0.95 V to 3.6 V;
VCC(B) = 1.65 V to 5.5 V;
VCCI = VCC(A) - 0.2 V
0.8VCC(B)
-
0.75VCC(B)
-
V
VOL
LOW-level
A or B port; IO = 1 mA
output voltage
VI 0.15 V;
VCC(A) = 0.95 V to 3.6 V;
VCC(B) = 1.65 V to 5.5 V
-
-
-
0.30
2
-
-
-
0.30
12
12
V
II
input leakage OE input; VI = 0 V to 3.6 V;
current
A
A
VCC(A) = 0.95 V to 3.6 V;
VCC(B) = 1.65 V to 5.5 V
[2]
IOZ
OFF-state
A or B port; VO = 0 V or VCCO
;
2
output current VCC(A) = 0.95 V to 3.6 V;
VCC(B) = 1.65 V to 5.5 V
NTS0304E
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 1 — 01 February 2019
6 of 26
NTS0304E
NXP Semiconductors
4-bit dual supply translating transceiver; open drain; auto direction
sensing
Table 10. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
[1]
ICC
supply current VI = 0 V or VCCI; IO = 0 A
ICC(A)
VCC(A) = 0.95 V to 3.6 V;
VCC(B) = 1.65 V to 5.5 V
-
2.4
-
15
A
V
CC(A) = 3.6 V; VCC(B) = 0 V
VCC(A) = 0 V; VCC(B) = 5.5 V
ICC(B)
-
-
2.2
-
-
15
A
A
1
8
VCC(A) = 0.95 V to 3.6 V;
VCC(B) = 1.65 V to 5.5 V
-
18
-
51
A
VCC(A) = 3.6 V; VCC(B) = 0 V
VCC(A) = 0 V; VCC(B) = 5.5 V
ICC(A) + ICC(B)
-
-
1
-
-
5
A
A
18
46
VCC(A) = 0.95 V to 3.6 V;
VCC(B) = 1.65 V to 5.5 V
-
14.4
-
59
A
[1] VCCI is the supply voltage associated with the input.
[2] CCO is the supply voltage associated with the output.
V
NTS0304E
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© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 1 — 01 February 2019
7 of 26
NTS0304E
NXP Semiconductors
4-bit dual supply translating transceiver; open drain; auto direction
sensing
12. Dynamic characteristics
Table 11. Dynamic characteristics for temperature range 40 C to +125 C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 6; for wave forms, see Figure 4 and Figure 5.
Symbol Parameter
Conditions
VCC(B)
3.3 V
Unit
1.8 V
Max
5.0 V
Max
Min
Min
Max
Min
VCC(A) = 0.95V
tPHL
tPLH
tPHL
tPLH
HIGH to LOW
propagation delay
A to B
A to B
B to A
B to A
-
-
-
-
20
14.8
9.2
-
-
-
-
11.1
12.5
5.2
-
-
-
-
12.3 ns
12.2 ns
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
5.2
1.4
ns
ns
LOW to HIGH
8.8
2.9
propagation delay
ten
enable time
disable time
OE to A; B
-
200
100
100
250
220
15.3
17.0
-
200
100
100
250
220
15.1
14.0
-
200
100
100
250
220
ns
ns
ns
ns
ns
[2]
[2]
tdis
OE to A; no external load
OE to B; no external load
OE to A
-
-
-
-
-
-
-
-
-
OE to B
-
-
-
tTLH
LOW to HIGH
output transition
time
A port
6.0
6.0
2.2
4.0
1.8
4.0
11.1 ns
20.0 ns
B port
tTHL
HIGH to LOW
output transition
time
A port
B port
0.9
1.6
18.0
22.0
0.7
2.8
9.0
0.6
3.2
9.0
ns
10.7
14.2 ns
tW
pulse width
data rate
data inputs
49
-
-
49
-
-
49
-
-
ns
[3]
fdata
20
20
20
Mbps
[1] ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
[2] Delay between OE going LOW and when the outputs are disabled.
[3] Assuming a maximum one-shot accelerator pulse length of 50ns and equal time for 1 and 0 bit information
.
.
NTS0304E
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 1 — 01 February 2019
8 of 26
NTS0304E
NXP Semiconductors
4-bit dual supply translating transceiver; open drain; auto direction
sensing
Table 12. Dynamic characteristics for temperature range 40 C to +125 C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 6; for wave forms, see Figure 4 and Figure 5.
Symbol Parameter
Conditions
VCC(B)
3.3 V
Unit
2.5 V
Max
5.0 V
Max
Min
Min
Max
Min
VCC(A) = 1.8 V
tPHL
tPLH
tPHL
tPLH
HIGH to LOW
propagation delay
A to B
A to B
B to A
B to A
-
-
-
-
5.8
8.5
5.5
6.7
-
-
-
-
5.9
8.5
5.7
5.7
-
-
-
-
7.3
8.8
5.9
1.4
ns
ns
ns
ns
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
LOW to HIGH
propagation delay
ten
enable time
disable time
OE to A; B
-
200
100
100
250
220
11.9
13.5
-
200
100
100
250
220
11.7
14.5
-
200
100
100
250
220
9.5
ns
ns
ns
ns
ns
ns
[2]
[2]
tdis
OE to A; no external load
OE to B; no external load
OE to A
-
-
-
-
-
-
-
-
-
OE to B
-
-
-
tTLH
LOW to HIGH
output transition
time
A port
3.2
3.3
1.2
2.7
1.1
2.7
B port
13.5 ns
tTHL
HIGH to LOW
output transition
time
A port
B port
1.2
2.6
7.4
9.5
1.0
2.2
7.5
9.4
1.0
2.8
16.7 ns
12.5 ns
tW
pulse width
data rate
data inputs
49
-
-
49
-
-
49
-
-
ns
[3]
fdata
20
20
20
Mbps
VCC(A) = 2.5 V
tPHL
tPLH
tPHL
tPLH
HIGH to LOW
propagation delay
A to B
A to B
B to A
B to A
-
-
-
-
4.0
4.4
3.8
3.2
-
-
-
-
4.2
5.2
4.5
2.0
-
-
-
-
4.3
5.5
5.4
1.5
ns
ns
ns
ns
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
LOW to HIGH
propagation delay
ten
enable time
disable time
OE to A; B
-
200
100
100
220
220
10
-
200
100
100
220
220
8.3
-
200
100
100
220
220
7.8
ns
ns
ns
ns
ns
ns
[2]
[2]
tdis
OE to A; no external load
OE to B; no external load
OE to A
-
-
-
-
-
-
-
-
-
OE to B
-
-
-
tTLH
LOW to HIGH
output transition
time
A port
2.8
3.2
1.4
2.9
1.2
2.4
B port
10.4
15.5
16.9 ns
tTHL
HIGH to LOW
output transition
time
A port
B port
1.0
2.2
7.2
9.8
1.0
2.4
6.9
8.4
1.0
2.6
6.7
8.3
ns
ns
NTS0304E
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 1 — 01 February 2019
9 of 26
NTS0304E
NXP Semiconductors
4-bit dual supply translating transceiver; open drain; auto direction
sensing
Table 12. Dynamic characteristics for temperature range 40 C to +125 C[1] …continued
Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 6; for wave forms, see Figure 4 and Figure 5.
Symbol Parameter
Conditions
VCC(B)
3.3 V
Unit
2.5 V
Max
5.0 V
Max
Min
49
-
Min
Max
-
Min
49
-
tW
pulse width
data rate
data inputs
-
49
-
-
ns
[3]
fdata
20
20
20
Mbps
VCC(A) = 3.3 V
tPHL
tPLH
tPHL
tPLH
HIGH to LOW
propagation delay
A to B
A to B
B to A
B to A
-
-
-
-
-
-
-
-
-
-
-
-
3.0
5.3
3.2
3.2
-
-
-
-
3.9
5.5
4.2
3.3
ns
ns
ns
ns
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
LOW to HIGH
propagation delay
ten
enable time
disable time
OE to A; B
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
200
100
100
280
220
13.1
14.2
-
200
100
100
280
220
7.4
ns
ns
ns
ns
ns
ns
[2]
[2]
tdis
OE to A; no external load
OE to B; no external load
OE to A
-
-
-
-
-
-
OE to B
-
-
tTLH
LOW to HIGH
output transition
time
A port
1.2
2.5
1.1
2.1
B port
16.0 ns
tTHL
HIGH to LOW
output transition
time
A port
B port
-
-
-
-
1.0
2.3
6.8
9.3
1.0
2.4
6.3
9.5
ns
ns
tW
pulse width
data rate
data inputs
-
-
-
-
49
-
-
49
-
-
ns
[3]
fdata
20
20
Mbps
[1] ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
[2] Delay between OE going LOW and when the outputs are disabled.
[3] Assuming a maximum one-shot accelerator pulse length of 50ns and equal time for 1 and 0 bit information
.
.
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13. Waveforms
V
I
V
A, B input
GND
M
t
t
PLH
PHL
V
OH
90 %
B, A output
V
V
M
10 %
OL
t
t
THL
TLH
001aan321
Measurement points are given in Table 13.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 4. The data input (A, B) to data output (B, A) propagation delay times
V
I
OE input
V
M
GND
t
t
PLZ
PZL
V
CCO
output
V
LOW-to-OFF
OFF-to-LOW
M
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aal919
Measurement points are given in Table 13.
OL and VOH are typical output voltage levels that occur with the output load.
V
Fig 5. Enable and disable times
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Table 13. Measurement points[1][2]
Supply voltage
VCCO
Input
Output
VM
VM
VX
VY
0.95 V
0.5VCCI
0.5VCCI
0.5VCCI
0.5VCCI
0.5VCCI
0.5VCCO
0.5VCCO
0.5VCCO
0.5VCCO
0.5VCCO
VOL + 0.1 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOH 0.1 V
VOH 0.15 V
VOH 0.15 V
VOH 0.3 V
VOH 0.3 V
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5.0 V 0.5 V
[1] VCCI is the supply voltage associated with the input.
[2] VCCO is the supply voltage associated with the output.
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
V
CC
R
L
V
V
O
I
G
DUT
C
L
R
L
001aal963
Test data is given in Table 14.
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; ZO = 50 ; dV/dt 1.0 V/ns.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
VEXT = External voltage for measuring switching times.
Fig 6. Test circuit for measuring switching times
Table 14. Test data
Supply voltage
VCC(A)
Input
VI[1]
Load
CL
VEXT
[2]
[3]
VCC(B)
t/V
RL
tPLH, tPHL tPZH, tPHZ tPZL, tPLZ
0.95 V to 3.6 V 1.65 V to 5.5 V VCCI
1.0 ns/V
15 pF
50 k, 1 M open
open
2VCCO
[1] VCCI is the supply voltage associated with the input.
[2] For measuring data rate, pulse width, propagation delay and output rise and fall measurements, RL = 1 M. For measuring enable and
disable times, RL = 50 K.
[3] VCCO is the supply voltage associated with the output.
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14. Application information
14.1 Applications
Voltage level-translation applications. The NTS0304E can be used in point-to-point
applications to interface between devices or systems operating at different supply
voltages. The device is primarily targeted at I2C or 4-wire which use open-drain drivers. It
may also be used in applications where push-pull drivers are connected to the ports,
however the NTB010x or the newer lower voltage NTB030x series of devices are more
suitable.
1.8 V
3.3 V
1.8 V
V
V
CC(B)
3.3 V
CC(A)
0.1 μF
0.1 μF
1 μF
OE
SYSTEM
CONTROLLER
NTS0304x
SYSTEM
DATA
A
B
DATA
aaa-031126
Fig 7. Typical operating circuit
14.2 Architecture
The architecture of the NTS0304E is shown in Figure 8. The device does not require an
extra input signal to control the direction of data flow from A to B or B to A.
V
CC(A)
V
CC(B)
T1
T2
ONE-SHOT
AND SLEW
RATE
ONE-SHOT
AND SLEW
RATE
CONTROL
CONTROL
10 kΩ
10 kΩ
GATE BIAS CONTROL
T3
A
B
HBM JESD22-A114E
IEC61000-4-2
aaa-031819
Fig 8. Architecture of NTS0304E I/O cell
The NTS0304E is a “switch” type voltage translator, it employs two key circuits to enable
voltage translation:
1. A pass-gate transistor (N-channel) that ties the ports together.
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2. An output edge-rate accelerator that detects and accelerates rising edges on the I/O
pins.
The gate bias voltage of the pass gate transistor (T3) is set at approximately one
threshold voltage above the VCC level of the low-voltage side. During a LOW-to-HIGH
transition, the output one-shot accelerates the output transition by switching on the PMOS
transistors (T1, T2). It bypasses the 10 k pull-up resistors and increases the current
drive capability. The one-shot is activated once the input transition reaches approximately
V
CCI/2; it is deactivated approximately 50 ns after the output reaches VCCO/2. During the
acceleration time, the driver output resistance is between approximately 50 and 70 .
To avoid signal contention and minimize dynamic ICC, the user should wait for the
one-shot circuit to turn-off before applying a signal in the opposite direction. Pull-up
resistors are included in the device for DC current sourcing capability.
14.3 Input driver requirements
As the NTS0304E is a switch type translator, properties of the input driver directly effect
the output signal. The external open-drain or push-pull driver applied to an I/O determines
the static current sinking capability of the system. The max data rate, HIGH-to-LOW
output transition time (tTHL), and propagation delay (tPHL), are dependent upon the output
impedance and edge-rate of the external driver. The limits provided for these parameters
in the data sheet assume a driver with output impedance below 50 is used.
14.4 Output load considerations
The maximum lumped capacitive load that can be driven is dependent upon the one-shot
pulse duration. In cases with very heavy capacitive loading, there is a risk that the output
does not reach the positive rail within the one-shot pulse duration. The NTS0304E has a
longer one-shot pulse for driving larger capacitive loads.
To avoid excessive capacitive loading and to ensure correct triggering of the one-shot,
use short trace lengths and low capacitance connectors on NTS0304E PCB layouts. The
length of the PCB trace should be such that the round-trip delay of any reflection is within
the one-shot pulse duration (approximately 50 ns). It ensures low impedance termination
and avoids output signal oscillations and one-shot retriggering.
14.5 Output single shot slew rate control
Integrated slew-rate control and timed increase of the one-shot driver output current
reduce EMI. An additional comparator circuit on the VOUT side starts to reduce the
one-shot driver current when VOUT > 0.65VOUT with a slight delay, so it can safely drive
the output voltage to a safe high-level while at the same time reducing the driver strength
early enough to reduce overshoots and ringing.
14.6 Power-up
During operation, VCC(A) must never be higher than VCC(B). However, during power-up,
VCC(A) VCC(B) does not damage the device, so either power supply can be ramped up
first. There is no special power-up sequencing required. The NTS0304E includes circuitry
that disables all output ports when either VCC(A) or VCC(B) is switched off.
NTS0304E
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4-bit dual supply translating transceiver; open drain; auto direction
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14.7 Enable and disable
An output enable input (OE) is used to disable the device. Setting OE = LOW causes all
I/Os to assume the high-impedance OFF-state. The disable time (tdis with no external
load) indicates the delay between when OE goes LOW and when outputs actually
become disabled. The enable time (ten) indicates the amount of time the user must allow
for one one-shot circuitry to become operational after OE is taken HIGH. To ensure the
high-impedance OFF-state during power-up or power-down, pin OE should be tied to
GND through a pull-down resistor. The current-sourcing capability of the driver determines
the minimum value of the resistor.
14.8 Pull-up or pull-down resistors on I/Os lines
The A port I/O has an internal 10 k pull-up resistor to VCC(A). The B port I/O has an
internal 10 k pull-up resistor to VCC(B). If a smaller value of pull-up resistor is required,
add an external resistor in parallel to the internal 10 k. This pull-up resistor effects the
V
OL level. When OE goes LOW, the internal pull-ups of the NTS0304E are disabled.
14.9 ESD protection on I/Os lines
The NTS0304E contains rail to rail ESD protection structures connecting the A and B I/O
to their respective supply. As a consequence, if a supply pin is pulled low, the related I/Os
are pulled low too through the upper ESD protection diode and the 10 k pull-up resistor.
Additionally, besides the normal HBM and CDM ESD protection features on both A and B
Port I/O the B Port I/O features integrated ESD protection to IEC 61000-4-2 Class 4
system ESD level of 8kV contact for when users plug cameras, games, and other items
into their USB or video ports in real-world ESD stress applications.
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15. Package outline
Fig 9. Package outline SOT1390-10 (WLCSP12) 1 of 2
NTS0304E
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4-bit dual supply translating transceiver; open drain; auto direction
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Fig 10. Package outline SOT1390-10 (WLCSP12) 2 of 2
NTS0304E
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4-bit dual supply translating transceiver; open drain; auto direction
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TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c
y
H
v
M
A
E
Z
8
14
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
7
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.72
0.38
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT402-1
MO-153
Fig 11. NTS0304E Package outline SOT402-1 (TSSOP14)
NTS0304E
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16. Soldering
Fig 12. Soldering footprint for SOT1390-10 (WLCSP12) 1 of 3
NTS0304E
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Fig 13. Soldering footprint for SOT1390-10 (WLCSP12) 2 of 3
NTS0304E
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Fig 14. Soldering footprint for SOT1390-10 (WLCSP12) 3 of 3
NTS0304E
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Footprint information for reflow soldering of TSSOP14 package
SOT402-1
Hx
Gx
P2
(0.125)
(0.125)
By
Hy Gy
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650 0.750 7.200 4.500 1.350 0.400 0.600 4.950 5.300 5.800 7.450
sot402-1_fr
Fig 15. Soldering footprint for SOT402-1 (TSSOP14)
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17. Abbreviations
Table 15. Abbreviations
Acronym
CDM
DUT
Description
Charged Device Model
Device Under Test
ESD
ElectroStatic Discharge
GPIO
HBM
I2C
General Purpose Input Output
Human Body Model
Inter-Integrated Circuit
IEC
International Electrotechnical Commission
Machine Model
MM
PCB
Printed-Circuit Board
PMOS
SMBus
UART
Positive Metal Oxide Semiconductor
System Management Bus
Universal Asynchronous Receiver Transmitter
18. Revision history
Table 16. Revision history
Document ID
Release date Data sheet status
Change notice
Supersedes
NTS0304E v.1.0 20190201
Product data sheet
-
-
NTS0304E
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19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
19.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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21. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
2
3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
4
4.1
5
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Thermal characteristics . . . . . . . . . . . . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8
9
10
11
12
13
14
Application information. . . . . . . . . . . . . . . . . . 13
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input driver requirements . . . . . . . . . . . . . . . . 14
Output load considerations. . . . . . . . . . . . . . . 14
Output single shot slew rate control . . . . . . . . 14
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Enable and disable. . . . . . . . . . . . . . . . . . . . . 15
Pull-up or pull-down resistors on I/Os lines . . 15
ESD protection on I/Os lines . . . . . . . . . . . . . 15
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
15
16
17
18
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 23
19
Legal information. . . . . . . . . . . . . . . . . . . . . . . 24
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
19.1
19.2
19.3
19.4
20
21
Contact information. . . . . . . . . . . . . . . . . . . . . 25
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2019.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 01 February 2019
Document identifier: NTS0304E
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