NVT2002 [NXP]
Bidirectional voltage level translator for open-drain and push-pull applications; 为漏极开路和推挽应用双向电压电平转换器型号: | NVT2002 |
厂家: | NXP |
描述: | Bidirectional voltage level translator for open-drain and push-pull applications |
文件: | 总23页 (文件大小:198K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NVT2001; NVT2002
Bidirectional voltage level translator for open-drain and
push-pull applications
Rev. 2 — 26 October 2011
Product data sheet
1. General description
The NVT2001/02 are bidirectional voltage level translators operational from 1.0 V to 3.6 V
(Vref(A)) and 1.8 V to 5.5 V (Vref(B)), which allow bidirectional voltage translations between
1.0 V and 5 V without the need for a direction pin in open-drain or push-pull applications.
Bit widths ranging from 1-bit or 2-bit are offered for level translation application with
transmission speeds < 33 MHz for an open-drain system with a 50 pF capacitance and a
pull-up of 197 .
When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the An and Bn ports. The low ON-state resistance (Ron) of the
switch allows connections to be made with minimal propagation delay. Assuming the
higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is
limited to the voltage set by VREFA. When the An port is HIGH, the Bn port is pulled to the
drain pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control.
When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn I/O,
respectively, allowing bidirectional data flow between ports. When EN is LOW, the
translator switch is off, and a high-impedance state exists between ports. The EN input
circuit is designed to be supplied by Vref(B). To ensure the high-impedance state during
power-up or power-down, EN must be LOW.
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features and benefits
Provides bidirectional voltage translation with no direction pin
Less than 1.5 ns maximum propagation delay
Allows voltage level translation between:
1.0 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B)
1.2 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B)
1.8 V Vref(A) and 3.3 V or 5 V Vref(B)
2.5 V Vref(A) and 5 V Vref(B)
3.3 V Vref(A) and 5 V Vref(B)
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
Low 3.5 ON-state connection between input and output ports provides less signal
distortion
5 V tolerant I/O ports to support mixed-mode signal operation
High-impedance An and Bn pins for EN = LOW
Lock-up free operation
Flow through pinout for ease of printed-circuit board trace routing
ESD protection exceeds 4 kV HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Packages offered: TSSOP, XQFN, XSON
3. Ordering information
Table 1.
Ordering information
Tamb = 40 C to +85 C.
Type number
Topside
mark
Number Package
of bits
Name
Description
Version
NVT2001GM
N1X[1]
1
2
2
2
XSON6
TSSOP8
XSON8U
XSON8
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 1.45 0.5 mm
NVT2002DP[2] N2002
NVT2002GD[2] N02
NVT2002GF[2] N2
plastic thin shrink small outline package; 8 leads;
body width 3 mm
SOT505-1
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3 2 0.5 mm
extremely thin small outline package; no leads;
SOT1089
8 terminals; body 1.35 1 0.5 mm
[1] ‘X’ will change based on date code.
[2] GTL2002 = NVT2002.
4. Functional diagram
VREFA
VREFB
NVT20xx
EN
B1
A1
An
SW
SW
Bn
GND
002aae132
Fig 1. Logic diagram of NVT2001; NVT2002 (positive logic)
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
2 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
5. Pinning information
5.1 Pinning
5.1.1 1-bit in XSON6 package
NVT2001GM
GND
VREFA
A1
1
2
3
6
5
4
EN
VREFB
B1
002aae211
Transparent top view
Fig 2. Pin configuration for XSON6
5.1.2 2-bit in TSSOP8, XSON8U and XSON8 packages
GND
VREFA
A1
1
2
3
4
8
7
6
5
EN
VREFB
B1
NVT2002GD
1
2
3
4
8
7
6
5
GND
VREFA
A1
EN
VREFB
B1
NVT2002DP
A2
B2
A2
B2
002aae215
002aae214
Transparent top view
Fig 3. Pin configuration for TSSOP8
Fig 4. Pin configuration for XSON8U
GND
VREFA
A1
1
2
8
7
EN
VREFB
B1
NVT2002GF
3
4
6
5
A2
B2
002aaf317
Transparent top view
Fig 5. Pin configuration for XSON8
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
3 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
5.2 Pin description
Table 2.
Symbol
Pin description
Pin
Description
NVT2001[1] NVT2002[2]
GND
VREFA
A1
1
2
3
-
1
2
3
4
6
5
7
8
ground (0 V)
low-voltage side reference supply voltage for An
low-voltage side; connect to VREFA through a pull-up
resistor
A2
B1
4
-
high-voltage side; connect to VREFB through a pull-up
resistor
B2
VREFB
EN
5
6
high-voltage side reference supply voltage for Bn
switch enable input; connect to VREFB and pull-up
through a high resistor
[1] 1-bit NVT2001 available in XSON6 package.
[2] 2-bit NVT2002 available in TSSOP8, XSON8U, XSON8 packages.
6. Functional description
Refer to Figure 1 “Logic diagram of NVT2001; NVT2002 (positive logic)”.
6.1 Function table
Table 3.
Function selection (example)
H = HIGH level; L = LOW level.
Input EN[1]
Function
An = Bn
H
L
disconnect
[1] EN is controlled by the Vref(B) logic levels and should be at least 1 V higher than Vref(A) for best translator
operation.
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
4 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
7. Application design-in information
The NVT2001/02 can be used in level translation applications for interfacing devices or
systems operating at different interface voltages with one another. The NVT2001/02 is
ideal for use in applications where an open-drain driver is connected to the data I/Os. The
NVT2001/02 can also be used in applications where a push-pull driver is connected to the
data I/Os.
7.1 Enable and disable
The NVT20xx has an EN input that is used to disable the device by setting EN LOW,
which places all I/Os in the high-impedance state.
(1)
V
= 3.3 V
pu(D)
200 kΩ
NVT2002
(1)
V
= 1.8 V
8 EN
ref(A)
R
PU
R
PU
VREFA
VREFB
2
3
4
7
6
5
R
PU
R
PU
V
V
CC
CC
A1
A2
B1
B2
SCL
SW
SW
SCL
2
2
I C-BUS
MASTER
I C-BUS
DEVICE
SDA
SDA
GND
1
GND
GND
002aae134
(1) The applied voltages at Vref(A) and Vpu(D) should be such that Vref(B) is at least 1 V higher than
Vref(A) for best translator operation.
Fig 6. Typical application circuit (switch always enabled)
Table 4.
Application operating conditions
Refer to Figure 6.
Symbol
Vref(B)
VI(EN)
Vref(A)
Isw(pass)
Iref
Parameter
Conditions
Min
Typ[1]
Max
Unit
V
reference voltage (B)
input voltage on pin EN
reference voltage (A)
pass switch current
reference current
Vref(A) + 0.6 2.1
Vref(A) + 0.6 2.1
5
5
V
0
1.5
14
5
4.4
V
-
-
mA
A
C
transistor
-
-
Tamb
ambient temperature
operating in
free-air
40
-
+85
[1] All typical values are at Tamb = 25 C.
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
5 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
(1)
V
= 3.3 V
pu(D)
3.3 V enable signal
on
off
200 kΩ
(2)
NVT2002
(1)
V
= 1.8 V
8 EN
ref(A)
R
PU
R
PU
VREFA
VREFB
2
7
R
PU
R
PU
V
V
CC
CC
A1
A2
3
4
6
5
B1
B2
SCL
SW
SW
SCL
2
2
I C-BUS
MASTER
I C-BUS
DEVICE
SDA
SDA
GND
1
GND
GND
002aae135
(1) In the Enabled mode, the applied enable voltage VI(EN) and the applied voltage at Vref(A) should be
such that Vref(B) is at least 1 V higher than Vref(A) for best translator operation.
(2) Note that the enable time and the disable time are essentially controlled by the RC time constant of
the capacitor and the 200 k resistor on the EN pin.
Fig 7. Typical application circuit (switch enable control)
1.8 V
1.5 V
5 V
200 kΩ
1.2 V
1.0 V
totem pole or
open-drain I/O
NVT20XX
EN
VREFB
VREFA
V
V
CORE
CC
A1
B1
SW
SW
CPU I/O
CHIPSET I/O
A2
B2
3.3 V
V
CC
A3
A4
A5
A6
B3
B4
B5
B6
SW
SW
SW
SW
CHIPSET I/O
An
Bn
SW
GND
002aae133
Fig 8. Bidirectional translation to multiple higher voltage levels
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
6 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
7.2 Bidirectional translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower
voltage to higher voltage), the EN input must be connected to VREFB and both pins pulled
to HIGH side Vpu(D) through a pull-up resistor (typically 200 k). This allows VREFB to
regulate the EN input. A filter capacitor on VREFB is recommended. The master output
driver can be totem pole or open-drain (pull-up resistors may be required) and the slave
device output can be totem pole or open-drain (pull-up resistors are required to pull the Bn
outputs to Vpu(D)). However, if either output is totem-pole, data must be unidirectional or
the outputs must be 3-stateable and be controlled by some direction-control mechanism
to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no
direction control is needed.
The reference supply voltage (Vref(A)) is connected to the processor core power supply
voltage. When VREFB is connected through a 200 k resistor to a 3.3 V to 5.5 V Vpu(D)
power supply, and Vref(A) is set between 1.0 V and (Vpu(D) 1 V), the output of each An
has a maximum output voltage equal to VREFA, and the output of each Bn has a
maximum output voltage equal to Vpu(D)
.
7.3 Sizing pull-up resistor
The pull-up resistor value needs to limit the current through the pass transistor when it is
in the ON state to about 15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the
current through the pass transistor is higher than 15 mA, the pass voltage also is higher in
the ON state. To set the current through each pass transistor at 15 mA, the pull-up resistor
value is calculated as:
V
puD – 0.35 V
-------------------------------------
=
RPU
0.015 A
Table 5 summarizes resistor reference voltages and currents at 15 mA, 10 mA, and 3 mA.
The resistor values shown in the +10 % column or a larger value should be used to
ensure that the pass voltage of the transistor would be 350 mV or less. The external driver
must be able to sink the total current from the resistors on both sides of the NVT20xx
device at 0.175 V, although the 15 mA only applies to current flowing through the
NVT20xx device.
Table 5.
Pull-up resistor values
Calculated for VOL = 0.35 V; assumes output driver VOL = 0.175 V at stated current.
Vpu(D)
Pull-up resistor value ()
64 mA
32 mA
15 mA
10 mA
3 mA
Nominal +10 %[1] Nominal +10 %[1] Nominal +10 %[1] Nominal +10 %[1] Nominal +10 %[1]
5 V
310
197
143
97
341
217
158
106
85
465
295
215
145
115
85
512
325
237
160
127
94
1550
983
717
483
383
283
1705
1082
788
3.3 V
2.5 V
1.8 V
1.5 V
1.2 V
532
77
422
57
63
312
[1] +10 % to compensate for VCC range and resistor tolerance.
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
7 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
7.3.1 Maximum frequency calculation
The maximum frequency is totally dependent upon the specifics of the application and the
device can operate > 33 MHz. Basically, the NVT20xx behaves like a wire with the
additional characteristics of transistor device physics and should be capable of performing
at higher frequencies if used correctly.
Here are some guidelines to follow that will help maximize the performance of the device:
• Keep trace length to a minimum by placing the NVT20xx close to the processor.
• The trace length should have a time of flight less than half of the transition time to
reduce ringing and reflections.
• The faster the edge of the signal, the higher the chance for ringing.
• The higher the drive strength (up to 15 mA), the higher the frequency the device can
use.
In a 3.3 V to 1.8 V direction level shift, if the 3.3 V side is being driven by a totem pole type
driver no pull-up resistor is needed on the 3.3 V side. The capacitance and line length of
concern is on the 1.8 V side since it is driven through the ON resistance of the NVT20xx.
If the line length on the 1.8 V side is long enough there can be a reflection at the
chip/terminating end of the wire when the transition time is shorter than the time of flight of
the wire because the NVT20xx looks like a high-impedance compared to the wire. If the
wire is not too long and the lumped capacitance is not excessive the signal will only be
slightly degraded by the series resistance added by passing through the NVT20xx. If the
lumped capacitance is large the rise time will deteriorate, the fall time is much less
affected and if the rise time is slowed down too much the duty cycle of the clock will be
degraded and at some point the clock will no longer be useful. So the principle design
consideration is to minimize the wire length and the capacitance on the 1.8 V side for the
clock path. A pull-up resistor on the 1.8 V side can also be used to trade a slower fall time
for a faster rise time and can also reduce the overshoot in some cases.
7.3.1.1 Example maximum frequency
Question — We need to make the PLL area of a new line card backwards compatible and
need to need to convert one GTL signal to LVTTL, invert it, and convert it back to GTL.
The signal we want to convert is random in nature but will mostly be around 19 MHz with
very long periods of inactivity where either a HIGH or LOW state will be maintained. The
traces are 1 or 2 inches long with trace capacitance of about 2 pF per inch.
Answer — The frequency of the NVT20xx is limited by the capacitance of the part, the
capacitance of the traces and the pull-up resistors used. The limiting case is probably the
LOW-to-HIGH transition in the GTL to LVTTL direction, and there the use of the lowest
acceptable resistor values will minimize the rise time delay. Assuming 50 pF capacitance
and 220 resistance, the RC time constant is 11 ns (50 pF 220 ). With 19 MHz
corresponding to 50 ns period the NVT20xx will support this application.
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
8 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Over operating free-air temperature range.
Symbol
Vref(A)
Vref(B)
VI
Parameter
Conditions
Min
0.5
0.5
0.5[1]
0.5[1]
-
Max
+6
Unit
V
reference voltage (A)
reference voltage (B)
input voltage
+6
V
+6
V
VI/O
Ich
voltage on an input/output pin
channel current (DC)
input clamping current
output clamping current
storage temperature
+6
V
128
-
mA
mA
mA
C
IIK
VI < 0 V
50
[2]
IOK
50
+50
+150
Tstg
65
[1] The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp
current ratings are observed.
[2] Low duty cycle pulses, not DC because of heating.
9. Recommended operating conditions
Table 7.
Symbol
Operating conditions
Parameter
voltage on an input/output pin An, Bn
Conditions
Min
0
Max
5.5
5.4
5.5
5.5
64
Unit
V
VI/O
[1]
[1]
Vref(A)
Vref(B)
VI(EN)
Isw(pass)
Tamb
reference voltage (A)
reference voltage (B)
input voltage on pin EN
pass switch current
ambient temperature
VREFA
VREFB
0
V
0
V
0
V
-
mA
C
operating in free-air
40
+85
[1] Vref(A) Vref(B) 1 V for best results in level shifting applications.
10. Static characteristics
Table 8.
Static characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
V
VIK
input clamping voltage
II = 18 mA; VI(EN) = 0 V
VI = 5 V; VI(EN) = 0 V
VI = 3 V or 0 V
-
-
-
-
-
1.2
IIH
HIGH-level input current
-
5
-
A
pF
pF
Ci(EN)
Cio(off)
input capacitance on pin EN
off-state input/output capacitance
7.1
4
An, Bn; VO = 3 V or 0 V;
VI(EN) = 0 V
6
Cio(on)
on-state input/output capacitance
An, Bn; VO = 3 V or 0 V;
VI(EN) = 3 V
-
9.3
12.5[2] pF
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
9 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
Table 8.
Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
[3][4][5]
[3][4]
Ron
ON-state resistance
An, Bn; VI = 0 V; IO = 64 mA;
VI(EN) = 4.5 V
1
2.4
5.0
VI = 2.4 V; IO = 15 mA;
-
4.8
7.5
VI(EN) = 4.5 V
[1] All typical values are at Tamb = 25 C.
[2] Not production tested, maximum value based on characterization data of typical parts.
[3] Measured by the voltage drop between the An and Bn terminals at the indicated current through the switch. ON-state resistance is
determined by the lowest voltage of the two terminals.
[4] See curves in Figure 9 for typical temperature and VI(EN) behavior.
[5] Guaranteed by design.
002aaf313
002aaf314
10
8
R
on(typ)
(Ω)
8
R
on(typ)
(Ω)
V
= 1.5 V
2.3 V
3.0 V
4.5 V
I(EN)
6
4
2
0
6
4
2
0
−40
−20
0
20
40
60
80
amb
100
(°C)
−40
−20
0
20
40
60
80
amb
100
(°C)
T
T
a. IO = 64 mA; VI = 0 V
b. IO = 15 mA; VI = 2.4 V; VI(EN) = 4.5 V
002aaf315
002aaf316
80
80
R
on(typ)
R
on(typ)
(Ω)
(Ω)
60
60
40
20
0
40
20
0
−40
−20
0
20
40
60
80
amb
100
(°C)
−40
−20
0
20
40
60
80
amb
100
(°C)
T
T
c. IO = 15 mA; VI = 2.4 V; VI(EN) = 3.0 V
d. IO = 15 mA; VI = 1.7 V; VI(EN) = 2.3 V
Fig 9. Typical ON-state resistance versus ambient temperature
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
10 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
11. Dynamic characteristics
11.1 Open-drain drivers
Table 9.
Dynamic characteristics for open-drain drivers
Tamb = 40 C to +85 C; VI(EN) = Vref(B); Rbias(ext) = 200 k; CVREFB = 0.1 F; unless otherwise
specified.
Symbol Parameter
Refer to Figure 12
Conditions
Min
Typ
Max
Unit
[1]
tPLH
LOW to HIGH
propagation delay
from (input) Bn
to (output) An
Ron (CL + Cio(on)
)
)
ns
ns
tPHL
HIGH to LOW
propagation delay
from (input) Bn
to (output) An
Ron (CL + Cio(on)
[1] See graphs based on Ron typical and Cio(on) + CL = 50 pF.
5.5 V
002aaf348
1 V/div
200 kΩ
6.6 V
0.1 μF
EN VREFB
DUT
500 Ω
1.5 V swing
SIGNAL
Bn
An
50 pF
GENERATOR
GND
GND
450 Ω
VREFA
1.5 V
40 ns/div
002aaf347
Fig 10. AC test setup
Fig 11. Example of typical AC waveform
V
V
V
V
IH
V
TT
input
V
V
V
M
M
M
M
IL
R
L
S1
S2 (open)
OH
OL
from output under test
output
V
C
L
002aab846
002aab845
a. Load circuit
b. Timing diagram; high-impedance scope probe
used
S2 = translating down, and same voltage.
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr 2 ns; tf 2 ns.
The outputs are measured one at a time, with one transition per measurement.
Fig 12. Load circuit for outputs
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
11 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
12. Performance curves
tPLH up-translation is typically dominated by the RC time constant, i.e.,
CL(tot) RPU = 50 pF 197 = 9.85 ns, but the Ron CL(tot) = 50 pF 5 = 0.250 ns.
tPHL is typically dominated by the external pull-down driver + Ron, which is typically small
compared to the tPLH in an up-translation case.
Enable/disable times are dominated by the RC time constant on the EN pin since the
transistor turn off is on the order of ns, but the enable RC is on the order of ms.
Fall time is dominated by the external pull-down driver with only a slight Ron addition.
Rise time is dominated by the RPU CL.
Skew time within the part is virtually non-existent, dominated by the difference in bond
wire lengths, which is typically small compared to the board-level routing differences.
Maximum data rate is dominated by the system capacitance and pull-up resistors.
002aaf349
0.8
t
PD
(ns)
0.6
(1)
(2)
(3)
0.4
0.2
0
(4)
(5)
0
20
40
60
80
100
C (pF)
(1) VI(EN) = 1.5 V; IO = 64 mA; VI = 0 V.
(2) VI(EN) = 4.5 V; IO = 15 mA; VI = 2.4 V.
(3) VI(EN) = 2.3 V; IO = 64 mA; VI = 0 V.
(4) VI(EN) = 3.0 V; IO = 64 mA; VI = 0 V.
(5)
VI(EN) = 4.5 V; IO = 64 mA; VI = 0 V.
Fig 13. Typical capacitance versus propagation delay
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
12 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
13. Package outline
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L
1
e
6
5
4
e
1
e
1
6×
A
(2)
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
A
1
UNIT
b
D
E
e
e
L
L
1
1
max max
0.25
0.17
1.5
1.4
1.05
0.95
0.35 0.40
0.27 0.32
mm
0.5 0.04
0.6
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
04-07-15
04-07-22
SOT886
MO-252
Fig 14. Package outline SOT886 (XSON6)
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
13 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
8
A
(A )
2
A
3
A
1
pin 1 index
θ
L
p
L
1
4
detail X
e
w M
b
p
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
A
A
A
b
c
D
E
e
H
E
L
L
p
UNIT
v
w
y
Z
θ
1
2
3
p
max.
0.15
0.05
0.95
0.80
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
5.1
4.7
0.7
0.4
0.70
0.35
6°
0°
mm
1.1
0.65
0.25
0.94
0.1
0.1
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-04-09
03-02-18
SOT505-1
Fig 15. Package outline SOT505-1 (TSSOP8)
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
14 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A
1
detail X
terminal 1
index area
e
1
C
M
M
v
C A
C
B
b
e
L
1
y
1
y
w
C
1
4
L
2
L
8
5
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
b
D
E
e
e
1
L
L
L
v
w
y
y
1
1
1
2
max
0.05 0.35
0.00 0.15
2.1
1.9
3.1
2.9
0.5
0.3
0.15
0.05
0.6
0.4
mm
0.5
0.5
1.5
0.1
0.05 0.05
0.1
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
- - -
JEDEC
JEITA
07-12-18
07-12-21
SOT996-2
- - -
Fig 16. Package outline SOT996-2 (XSON8U)
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
15 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm
SOT1089
E
terminal 1
index area
D
A
A
1
detail X
(2)
(4×)
e
L
(2)
(8×)
b
4
5
e
1
1
8
terminal 1
index area
L
1
X
0
0.5
1 mm
scale
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
L
1
1
max 0.5 0.04 0.20 1.40 1.05
0.35 0.40
0.15 1.35 1.00 0.55 0.35 0.30 0.35
0.12 1.30 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1089_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
10-04-09
10-04-12
SOT1089
MO-252
Fig 17. Package outline SOT1089 (XSON8)
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
16 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
17 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 18) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and 11
Table 10. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 11. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 18.
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
18 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 18. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
15. Soldering: reflow soldering footprint for SOT1089
Footprint information for reflow soldering of XSON8 package
SOT1089
0.15
0.25
(8×)
(8×)
0.5
(8×)
0.7
1.4
0.6
(8×)
Dimensions in mm
solder paste = solder land
0.35
(3×)
1.4
solder resist
occupied area
sot1089_fr
Fig 19. SOT1089 reflow soldering footprint
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
19 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
16. Abbreviations
Table 12. Abbreviations
Acronym
CDM
ESD
Description
Charged Device Model
ElectroStatic Discharge
Gunning Transceiver Logic
Human Body Model
Inter-Integrated Circuit bus
Input/Output
GTL
HBM
I2C-bus
I/O
LVTTL
MM
Low Voltage Transistor-Transistor Logic
Machine Model
PRR
Pulse Repetition Rate
RC
Resistor-Capacitor network
17. Revision history
Table 13. Revision history
Document ID
Release date
20111026
Data sheet status
Change notice
Supersedes
NVT2001_NVT2002 v.2
Modifications:
Product data sheet
-
NVT2001_NVT2002 v.1
• Section 2 “Features and benefits”, 10th bullet item: removed phrase “200 V MM per
JESD22-A115”
• Type number NVT2002GM (XQFN8U, SOT902-1) removed from data sheet; this affects:
–
Section 2 “Features and benefits”, last bullet item: removed “XQFN”
–
Section 5.1.2 “2-bit in TSSOP8, XSON8U and XSON8 packages”: removed pin
configuration for XQFN8U
–
–
Table 2 “Pin description”, Table note [2]: removed “XQFN8U”
Section 13 “Package outline”: removed package outline SOT902-1
• Type number NVT2002TL (HXSON8U, SOT983-1) removed from data sheet; this affects:
–
Section 2 “Features and benefits”, last bullet item: removed “HXSON”
–
Section 5.1.2 “2-bit in TSSOP8, XSON8U and XSON8 packages”: removed pin
configuration for HXSON8U
–
–
Table 2 “Pin description”, Table note [2]: removed “HXSON8U”
Section 13 “Package outline”: removed package outline SOT983-1
NVT2001_NVT2002 v.1
20100830
Product data sheet
-
-
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
20 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
18.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
18.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
21 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NVT2001_NVT2002
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 October 2011
22 of 23
NVT2001; NVT2002
NXP Semiconductors
Bidirectional voltage level translator
20. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.1.1
5.1.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1-bit in XSON6 package . . . . . . . . . . . . . . . . . . 3
2-bit in TSSOP8, XSON8U and
XSON8 packages . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2
6
Functional description . . . . . . . . . . . . . . . . . . . 4
6.1
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
7.1
7.2
7.3
7.3.1
7.3.1.1
Application design-in information . . . . . . . . . . 5
Enable and disable. . . . . . . . . . . . . . . . . . . . . . 5
Bidirectional translation . . . . . . . . . . . . . . . . . . 7
Sizing pull-up resistor . . . . . . . . . . . . . . . . . . . . 7
Maximum frequency calculation . . . . . . . . . . . . 8
Example maximum frequency . . . . . . . . . . . . . 8
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended operating conditions. . . . . . . . 9
Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
Dynamic characteristics . . . . . . . . . . . . . . . . . 11
Open-drain drivers . . . . . . . . . . . . . . . . . . . . . 11
Performance curves . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
9
10
11
11.1
12
13
14
Soldering of SMD packages . . . . . . . . . . . . . . 17
Introduction to soldering . . . . . . . . . . . . . . . . . 17
Wave and reflow soldering . . . . . . . . . . . . . . . 17
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 17
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 18
14.1
14.2
14.3
14.4
15
Soldering: reflow soldering footprint for
SOT1089 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16
17
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 26 October 2011
Document identifier: NVT2001_NVT2002
相关型号:
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明