NVT2003DP_技术文档

NVT2003/04/06

Bidirectional voltage-level translator for open-drain and

push-pull applications

Rev. 4 — 7 September 2012

Product data sheet

1. General description

The NVT2003/04/06 is a family of bidirectional voltage level translators operational from

1.0 V to 3.6 V (V_ref(A)) and 1.8 V to 5.5 V (V_ref(B)), which allow bidirectional voltage

translations between 1.0 V and 5 V without the need for a direction pin in open-drain or

push-pull applications. Bit widths ranging from 3-bit to 6-bit are offered for level translation

application with transmission speeds < 33 MHz for an open-drain system with a 50 pF

capacitance and a pull-up of 197 .

When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance

connection exists between the An and Bn ports. The low ON-state resistance (R_on) of the

switch allows connections to be made with minimal propagation delay. Assuming the

higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is

limited to the voltage set by VREFA. When the An port is HIGH, the Bn port is pulled to the

drain pull-up supply voltage (V_pu(D)) by the pull-up resistors. This functionality allows a

seamless translation between higher and lower voltages selected by the user without the

need for directional control.

When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn I/O,

respectively, allowing bidirectional data flow between ports. When EN is LOW, the

translator switch is off, and a high-impedance state exists between ports. The EN input

circuit is designed to be supplied by V_ref(B). To ensure the high-impedance state during

power-up or power-down, EN must be LOW.

All channels have the same electrical characteristics and there is minimal deviation from

one output to another in voltage or propagation delay. This is a benefit over discrete

transistor voltage translation solutions, since the fabrication of the switch is symmetrical.

The translator provides excellent ESD protection to lower voltage devices, and at the

same time protects less ESD-resistant devices.

2. Features and benefits

 Provides bidirectional voltage translation with no direction pin

 Less than 1.5 ns maximum propagation delay

 Allows voltage level translation between:

 1.0 V V_ref(A)and 1.8 V, 2.5 V, 3.3 V or 5 V V_ref(B)

 1.2 V V_ref(A)and 1.8 V, 2.5 V, 3.3 V or 5 V V_ref(B)

 1.8 V V_ref(A)and 3.3 V or 5 V V_ref(B)

 2.5 V V_ref(A)and 5 V V_ref(B)

 3.3 V V_ref(A)and 5 V V_ref(B)

NVT2003/04/06

NXP Semiconductors

Bidirectional voltage-level translator

 Low 3.5  ON-state connection between input and output ports provides less signal

distortion

 5 V tolerant I/O ports to support mixed-mode signal operation

 High-impedance An and Bn pins for EN = LOW

 Lock-up free operation

 Flow through pinout for ease of printed-circuit board trace routing

 ESD protection exceeds 3.5 kV HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

 Packages offered: TSSOP10, HXSON12, DHVQFN16, HVQFN16, TSSOP16

3. Ordering information

Table 1.

Ordering information

T_amb= 40 C to +85 C.

Type number

Topside

mark

Number Package

of bits

Name

Description

Version

NVT2003DP

NVT2004TL

N2003

N04

3

4

TSSOP10

HXSON12

plastic thin shrink small outline package; 10 leads;

body width 3 mm

SOT552-1

plastic, thermal enhanced extremely thin small outline SOT973-2

package; no leads; 12 terminals;

body 1.35  2.5  0.5 mm

NVT2006BQ

N2006

6

DHVQFN16 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads;16 terminals;

body 2.5  3.5  0.85 mm

SOT763-1

NVT2006BS

NVT2006PW

N06

6

HVQFN16

plastic thermal enhanced very thin quad flat package; SOT758-1

no leads; 16 terminals; body 3  3  0.85 mm

NVT2006

TSSOP16

plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT403-1

4. Functional diagram

VREFA

VREFB

NVT20xx

EN

B1

A1

An

SW

Bn

GND

002aae132

Fig 1. Logic diagram of NVT2003/04/06 (positive logic)

NVT2003_04_06

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Product data sheet

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NVT2003/04/06

NXP Semiconductors

Bidirectional voltage-level translator

5. Pinning information

5.1 Pinning

5.1.1 3-bit in TSSOP10 package

1

2

3

4

5

10

9

GND

EN

VREFA

A1

VREFB

B1

8

NVT2003DP

7

A2

B2

6

A3

B3

002aae836

Fig 2. Pin configuration for TSSOP10

5.1.2 4-bit in HXSON12 package

NVT2004TL

GND

VREFA

A1

1

2

3

4

5

6

12 EN

11 VREFB

10 B1

A2

9

8

7

B2

B3

A3

A4

B4

002aae219

Transparent top view

Fig 3. Pin configuration for HXSON12U

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NVT2003/04/06

NXP Semiconductors

Bidirectional voltage-level translator

5.1.3 6-bit in TSSOP16, DHVQFN16 and HVQFN16 packages

terminal 1

index area

2

3

4

5

6

7

15

14

13

12

11

10

VREFA

A1

VREFB

B1

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

EN

VREFB

B1

VREFA

A1

A2

B2

NVT2006BQ

A3

B3

A2

B2

NVT2006PW

A3

B3

A4

B4

A4

B4

A5

B5

A5

B5

A6

B6

002aae221

Transparent top view

002aae220

Fig 4. Pin configuration for TSSOP16

Fig 5. Pin configuration for DHVQFN16

terminal 1

index area

1

2

3

4

12

11

10

9

A1

A2

A3

A4

B1

B2

B3

B4

NVT2006BS

002aae222

Transparent top view

Fig 6. Pin configuration for HVQFN16

NVT2003_04_06

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Product data sheet

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NVT2003/04/06

NXP Semiconductors

Bidirectional voltage-level translator

5.2 Pin description

Table 2.

Symbol

Pin description

Description

NVT2003DP^[1]NVT2004TL^[2]NVT2006BQ,

NVT2006PW^[3]

NVT2006BS^[3]

GND

1

2

1

2

1

2

15

16

ground (0 V)

VREFA

low-voltage side reference

supply voltage for An

A1

3

4

5

-

3

4

5

6

-

3

1

low-voltage side; connect to VREFA

through a pull-up resistor

A2

4

2

A3

5

3

A4

6

4

A5

-

7

5

A6

-

8

6

B1

8

7

6

-

10

9

8

7

-

14

13

12

11

10

9

12

11

10

9

high-voltage side; connect to VREFB

through a pull-up resistor

B2

B3

B4

B5

-

8

B6

-

7

VREFB

9

11

15

13

high-voltage side reference

supply voltage for Bn

EN

10

12

16

14

switch enable input; connect to VREFB

and pull-up through a high resistor

[1] 3-bit NVT2003 available in TSSOP10 package.

[2] 4-bit NVT2004 available in HXSON12 package.

[3] 6-bit NVT2006 available in TSSOP16, DHVQFN16, HVQFN16 packages.

NVT2003_04_06

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Product data sheet

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NVT2003/04/06

NXP Semiconductors

Bidirectional voltage-level translator

6. Functional description

Refer to Figure 1 “Logic diagram of NVT2003/04/06 (positive logic)”.

6.1 Function table

Table 3.

Function selection (example)

H = HIGH level; L = LOW level.

Input EN^[1]

Function

An = Bn

H

L

disconnect

[1] EN is controlled by the V_ref(B)logic levels and should be at least 1 V higher than V_ref(A)for best translator

operation.

7. Application design-in information

The NVT2003/04/06 can be used in level translation applications for interfacing devices or

systems operating at different interface voltages with one another. The NVT2003/04/06 is

ideal for use in applications where an open-drain driver is connected to the data I/Os. The

NVT2003/04/06 can also be used in applications where a push-pull driver is connected to

the data I/Os.

7.1 Enable and disable

The NVT20xx has an EN input that is used to disable the device by setting EN LOW,

which places all I/Os in the high-impedance state.

(1)

V

= 3.3 V

pu(D)

200 kΩ

NVT2002

(1)

V

= 1.8 V

8 EN

ref(A)

R

PU

R

PU

VREFA

VREFB

2

3

4

7

6

5

R

PU

R

PU

V

CC

A1

A2

B1

B2

SCL

SW

SCL

2

I C-BUS

MASTER

I C-BUS

DEVICE

SDA

GND

1

GND

002aae134

(1) The applied voltages at V_ref(A)and V_pu(D)should be such that V_ref(B)is at least 1 V higher than

V_ref(A)for best translator operation.

Fig 7. Typical application circuit (switch always enabled)

NVT2003_04_06

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Product data sheet

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NVT2003/04/06

NXP Semiconductors

Bidirectional voltage-level translator

Table 4.

Application operating conditions

Refer to Figure 7.

Symbol

V_ref(B)

V_I(EN)

V_ref(A)

I_sw(pass)

I_ref

Parameter

Conditions

Min

Typ^[1]

Max

Unit

V

reference voltage (B)

input voltage on pin EN

reference voltage (A)

pass switch current

reference current

V_ref(A)+ 0.6 2.1

5

V

0

1.5

14

5

4.4

V

-

mA

A

C

transistor

-

T_amb

ambient temperature

operating in

free-air

40

-

+85

[1] All typical values are at T_amb= 25 C.

(1)

V

= 3.3 V

pu(D)

3.3 V enable signal

on

off

200 kΩ

(2)

NVT2002

(1)

V

= 1.8 V

8 EN

ref(A)

R

PU

R

PU

VREFA

VREFB

2

7

R

PU

R

PU

V

CC

A1

A2

3

4

6

5

B1

B2

SCL

SW

SCL

2

I C-BUS

MASTER

I C-BUS

DEVICE

SDA

SW

1

GND

002aae135

(1) In the Enabled mode, the applied enable voltage V_I(EN)and the applied voltage at V_ref(A)should be

such that V_ref(B)is at least 1 V higher than V_ref(A)for best translator operation.

(2) Note that the enable time and the disable time are essentially controlled by the RC time constant of

the capacitor and the 200 k resistor on the EN pin.

Fig 8. Typical application circuit (switch enable control)

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Product data sheet

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NVT2003/04/06

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Bidirectional voltage-level translator

1.8 V

1.5 V

1.2 V

1.0 V

5 V

200 kΩ

totem pole or

open-drain I/O

NVT20XX

EN

VREFA

VREFB

V

CORE

CC

A1

B1

SW

CPU I/O

CHIPSET I/O

A2

B2

3.3 V

V

CC

A3

A4

A5

A6

B3

B4

B5

B6

SW

CHIPSET I/O

An

Bn

SW

GND

002aae133

Fig 9. Bidirectional translation to multiple higher voltage levels

7.2 Bidirectional translation

For the bidirectional clamping configuration (higher voltage to lower voltage or lower

voltage to higher voltage), the EN input must be connected to VREFB and both pins pulled

to HIGH side V_pu(D)through a pull-up resistor (typically 200 k). This allows VREFB to

regulate the EN input. A filter capacitor on VREFB is recommended. The master output

driver can be totem pole or open-drain (pull-up resistors may be required) and the slave

device output can be totem pole or open-drain (pull-up resistors are required to pull the Bn

outputs to V_pu(D)). However, if either output is totem-pole, data must be unidirectional or

the outputs must be 3-stateable and be controlled by some direction-control mechanism

to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no

direction control is needed.

The reference supply voltage (V_ref(A)) is connected to the processor core power supply

voltage. When VREFB is connected through a 200 k resistor to a 3.3 V to 5.5 V V_pu(D)

power supply, and V_ref(A)is set between 1.0 V and (V_pu(D) 1 V), the output of each An

has a maximum output voltage equal to VREFA, and the output of each Bn has a

maximum output voltage equal to V_pu(D)

.

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NVT2003/04/06

NXP Semiconductors

Bidirectional voltage-level translator

7.3 Bidirectional level shifting between two different power domains

nominally at the same potential

The less obvious application for the NVT2003 is for level shifting between two different

power domains that are nominally at the same potential, such as a 3.3 V system where

the line crosses power supply domains that under normal operation would be at 3.3 V, but

one could be at 3.0 V and the other at 3.6 V, or one could be experiencing a power failure

while the other domain is trying to operate. One of the NVT2003 three channel transistors

is used as a second reference transistor with its B side connected to a voltage supply that

is at least 1 V (and preferably 1.5 V) above the maximum possible for either V_pu(A)or

V

_pu(B). Then if either pull-up voltage is at 0 V, the channels are disabled, and otherwise the

channels are biased such that they turn OFF at the lower pull-up voltage, and if the two

pull-up voltages are equal, the channel is biased such that it just turns OFF at the

common pull-up voltage.

V

= 3.3 V

pu(B)

V

pu(H)

200 kΩ

NVT2003

V

= 3.3 V

10 EN

pu(A)

R

PU

R

PU

VREFA

VREFB

2

3

9

V

R

PU

pu(B)

PU

V

CC

A1

8

B1

SCL

SW

SCL

2

I C-BUS

MASTER

I C-BUS

DEVICE

A2

A3

4

5

7

6

B2

B3

SDA

SW

GND

1

002aae967

GND

The applied enable voltage V_pu(H)and the applied voltage at V_ref(A)and V_ref(B)should be such that V_ref(H)is at least 1 V higher

than V_ref(A)and V_ref(B)for best translator operation.

Fig 10. Bidirectional level shifting between two different power domains

7.4 Sizing pull-up resistor

The pull-up resistor value needs to limit the current through the pass transistor when it is

in the ON state to about 15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the

current through the pass transistor is higher than 15 mA, the pass voltage also is higher in

the ON state. To set the current through each pass transistor at 15 mA, the pull-up resistor

value is calculated as:

V_puD– 0.35 V

-------------------------------------

0.015 A

R_PU

=

Table 5 summarizes resistor reference voltages and currents at 15 mA, 10 mA, and 3 mA.

The resistor values shown in the +10 % column or a larger value should be used to

ensure that the pass voltage of the transistor would be 350 mV or less. The external driver

NVT2003_04_06

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Product data sheet

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NVT2003/04/06

NXP Semiconductors

Bidirectional voltage-level translator

must be able to sink the total current from the resistors on both sides of the NVT20xx

device at 0.175 V, although the 15 mA only applies to current flowing through the

NVT20xx device.

Table 5.

Pull-up resistor values

Calculated for V_OL= 0.35 V; assumes output driver V_OL= 0.175 V at stated current.

V_pu(D)

Pull-up resistor value ()

64 mA

32 mA

15 mA

10 mA

3 mA

Nominal +10 %^[1]Nominal +10 %^[1]Nominal +10 %^[1]Nominal +10 %^[1]Nominal +10 %^[1]

5 V

310

197

143

97

341

217

158

106

85

465

295

215

145

115

85

512

325

237

160

127

94

1550

983

717

483

383

283

1705

1082

788

3.3 V

2.5 V

1.8 V

1.5 V

1.2 V

532

77

422

57

63

312

[1] +10 % to compensate for V_CCrange and resistor tolerance.

7.4.1 Maximum frequency calculation

The maximum frequency is totally dependent upon the specifics of the application and the

device can operate > 33 MHz. Basically, the NVT20xx behaves like a wire with the

additional characteristics of transistor device physics and should be capable of performing

at higher frequencies if used correctly.

Here are some guidelines to follow that will help maximize the performance of the device:

• Keep trace length to a minimum by placing the NVT20xx close to the processor.

• The trace length should have a time of flight less than half of the transition time to

reduce ringing and reflections.

• The faster the edge of the signal, the higher the chance for ringing.

• The higher the drive strength (up to 15 mA), the higher the frequency the device can

use.

In a 3.3 V to 1.8 V direction level shift, if the 3.3 V side is being driven by a totem pole type

driver no pull-up resistor is needed on the 3.3 V side. The capacitance and line length of

concern is on the 1.8 V side since it is driven through the ON resistance of the NVT20xx.

If the line length on the 1.8 V side is long enough there can be a reflection at the

chip/terminating end of the wire when the transition time is shorter than the time of flight of

the wire because the NVT20xx looks like a high-impedance compared to the wire. If the

wire is not too long and the lumped capacitance is not excessive the signal will only be

slightly degraded by the series resistance added by passing through the NVT20xx. If the

lumped capacitance is large the rise time will deteriorate, the fall time is much less

affected and if the rise time is slowed down too much the duty cycle of the clock will be

degraded and at some point the clock will no longer be useful. So the principle design

consideration is to minimize the wire length and the capacitance on the 1.8 V side for the

clock path. A pull-up resistor on the 1.8 V side can also be used to trade a slower fall time

for a faster rise time and can also reduce the overshoot in some cases.

NVT2003_04_06

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Product data sheet

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NVT2003/04/06

NXP Semiconductors

Bidirectional voltage-level translator

7.4.1.1 Example maximum frequency

Question — We need to make the PLL area of a new line card backwards compatible and

need to convert one GTL signal to LVTTL, invert it, and convert it back to GTL. The signal

we want to convert is random in nature but will mostly be around 19 MHz with very long

periods of inactivity where either a HIGH or LOW state will be maintained. The traces are

1 or 2 inches long with trace capacitance of about 2 pF per inch.

Answer — The frequency of the NVT20xx is limited by the capacitance of the part, the

capacitance of the traces and the pull-up resistors used. The limiting case is probably the

LOW-to-HIGH transition in the GTL to LVTTL direction, and there the use of the lowest

acceptable resistor values will minimize the rise time delay. Assuming 50 pF capacitance

and 220  resistance, the RC time constant is 11 ns (50 pF  220 ). With 19 MHz

corresponding to 50 ns period the NVT20xx will support this application.

8. Limiting values

Table 6.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Over operating free-air temperature range.

Symbol

V_ref(A)

V_ref(B)

V_I

Parameter

Conditions

Min

0.5

0.5^[1]

-

Max

+6

Unit

V

reference voltage (A)

reference voltage (B)

input voltage

+6

V

+6

V

V_I/O

I_ch

voltage on an input/output pin

channel current (DC)

input clamping current

output clamping current

storage temperature

+6

V

128

-

mA

C

I_IK

V_I< 0 V

50

[2]

I_OK

50

+50

+150

T_stg

65

[1] The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp

current ratings are observed.

[2] Low duty cycle pulses, not DC because of heating.

9. Recommended operating conditions

Table 7.

Symbol

Operating conditions

Parameter

voltage on an input/output pin An, Bn

Conditions

Min

0

Max

5.5

5.4

5.5

64

Unit

V

V_I/O

[1]

V_ref(A)

V_ref(B)

V_I(EN)

I_sw(pass)

T_amb

reference voltage (A)

reference voltage (B)

input voltage on pin EN

pass switch current

ambient temperature

VREFA

VREFB

0

V

0

V

0

V

-

mA

C

operating in free-air

40

+85

[1] V_ref(A) V_ref(B) 1 V for best results in level shifting applications.

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Product data sheet

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NVT2003/04/06

NXP Semiconductors

Bidirectional voltage-level translator

10. Static characteristics

Table 8.

Static characteristics

T_amb= 40 C to +85 C, unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ^[1]Max

Unit

V

V_IK

input clamping voltage

I_I= 18 mA; V_I(EN)= 0 V

V_I= 5 V; V_I(EN)= 0 V

V_I= 3 V or 0 V

-

1.2

I_IH

HIGH-level input current

-

5

-

A

pF

C_i(EN)

C_io(off)

input capacitance on pin EN

off-state input/output capacitance

12

5

An, Bn; V_O= 3 V or 0 V;

V_I(EN)= 0 V

7

C_io(on)

R_on

on-state input/output capacitance

ON-state resistance

An, Bn; V_O= 3 V or 0 V;

-

11.5

2.4

13^[2]

5.0

pF



V

_I(EN)= 3 V

An, Bn; V_I= 0 V; I_O= 64 mA;

_I(EN)= 4.5 V

[3][4][5]

[3][4]

1

-

V

V_I= 2.4 V; I_O= 15 mA;

V_I(EN)= 4.5 V

4.8

7.5



[1] All typical values are at T_amb= 25 C.

[2] Not production tested, maximum value based on characterization data of typical parts.

[3] Measured by the voltage drop between the An and Bn terminals at the indicated current through the switch. ON-state resistance is

determined by the lowest voltage of the two terminals.

[4] See curves in Figure 11 for typical temperature and V_I(EN)behavior.

[5] Guaranteed by design.

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Product data sheet

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NVT2003/04/06

NXP Semiconductors

Bidirectional voltage-level translator

002aaf680

002aaf681

10

8

R

on(typ)

(Ω)

8

R

on(typ)

(Ω)

V

= 1.5 V

2.3 V

3.0 V

4.5 V

I(EN)

6

4

2

0

6

4

2

0

−40

−20

0

20

40

60

80

amb

100

(°C)

−40

−20

0

20

40

60

80

amb

100

(°C)

T

a. I_O= 64 mA; V_I= 0 V

b. I_O= 15 mA; V_I= 2.4 V; V_I(EN)= 4.5 V

002aaf682

002aaf683

80

R

on(typ)

R

on(typ)

(Ω)

60

40

20

0

40

20

0

−40

−20

0

20

40

60

80

amb

100

(°C)

−40

−20

0

20

40

60

80

amb

100

(°C)

T

c. I_O= 15 mA; V_I= 2.4 V; V_I(EN)= 3.0 V

d. I_O= 15 mA; V_I= 1.7 V; V_I(EN)= 2.3 V

Fig 11. NVT2006 typical ON-state resistance versus ambient temperature

NVT2003_04_06

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11. Dynamic characteristics

11.1 Open-drain drivers

Table 9.

Dynamic characteristics for open-drain drivers

T_amb= 40 C to +85 C; V_I(EN)= V_ref(B); unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Figure 14

[1]

t_PLH

LOW to HIGH

propagation delay

from (input) Bn

to (output) An

R_on (C_L+ C_io(on)

)

ns

t_PHL

HIGH to LOW

propagation delay

from (input) Bn

to (output) An

R_on (C_L+ C_io(on)

[1] See graphs based on R_ontypical and C_io(on)+ C_L= 50 pF.

5.5 V

002aaf348

1 V/div

200 kΩ

6.6 V

0.1 μF

EN VREFB

DUT

500 Ω

1.5 V swing

SIGNAL

Bn

An

50 pF

GENERATOR

GND

450 Ω

VREFA

1.5 V

40 ns/div

002aaf347

Fig 12. AC test setup

Fig 13. Example of typical AC waveform

V

IH

V

TT

input

V

M

IL

R

L

S1

S2 (open)

OH

OL

from output under test

output

V

C

L

002aab846

002aab845

a. Load circuit

b. Timing diagram; high-impedance scope probe

used

S2 = translating down, and same voltage.

C_Lincludes probe and jig capacitance.

All input pulses are supplied by generators having the following characteristics: PRR  10 MHz; Z_o= 50 ; t_r 2 ns; t_f 2 ns.

The outputs are measured one at a time, with one transition per measurement.

Fig 14. Load circuit for outputs

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12. Performance curves

t_PLHup-translation is typically dominated by the RC time constant, i.e.,

C_L(tot) R_PU= 50 pF  197  = 9.85 ns, but the R_on C_L(tot)= 50 pF  5  = 0.250 ns.

t_PHLis typically dominated by the external pull-down driver + R_on, which is typically small

compared to the t_PLHin an up-translation case.

Enable/disable times are dominated by the RC time constant on the EN pin since the

transistor turn off is on the order of ns, but the enable RC is on the order of ms.

Fall time is dominated by the external pull-down driver with only a slight R_onaddition.

Rise time is dominated by the R_PU C_L.

Skew time within the part is virtually non-existent, dominated by the difference in bond

wire lengths, which is typically small compared to the board-level routing differences.

Maximum data rate is dominated by the system capacitance and pull-up resistors.

002aaf708

002aaf707

3

2

1

0

0.6

(1)

t

PD

(ns)

(3)

(2)

0.4

(4)

(5)

0.2

0

20

40

60

80

100

0

20

40

60

80

100

C (pF)

(1) V_I(EN)= 1.5 V; I_O= 64 mA; V_I= 0 V.

(1)

V

_I(EN)= 3.0 V; I_O= 15 mA; V_I= 2.4 V.

(2) V_I(EN)= 4.5 V; I_O= 15 mA; V_I= 2.4 V.

(3) V_I(EN)= 2.3 V; I_O= 64 mA; V_I= 0 V.

(2) V_I(EN)= 2.3 V; I_O= 15 mA; V_I= 1.7 V.

(4)

V_I(EN)= 3.0 V; I_O= 64 mA; V_I= 0 V.

(5) V_I(EN)= 4.5 V; I_O= 64 mA; V_I= 0 V.

Fig 15. NVT2006 typical capacitance versus propagation delay

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13. Package outline

TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm

SOT552-1

D

E

A

X

c

y

H

v

M

A

E

Z

6

10

A

(A )

2

A

3

A

1

pin 1 index

θ

L

p

L

1

5

detail X

e

w M

b

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

A

b

c

D

E

e

H

L

UNIT

v

w

y

Z

θ

1

2

3

p

E

p

max.

0.15

0.05

0.95

0.80

0.30

0.15

0.23

0.15

3.1

2.9

3.1

2.9

5.0

4.8

0.7

0.4

0.67

0.34

6°

0°

mm

1.1

0.5

0.25

0.95

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-07-29

03-02-18

SOT552-1

Fig 16. Package outline SOT552-1 (TSSOP10)

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HXSON12: plastic, thermal enhanced extremely thin small outline package; no leads;

12 terminals; body 1.35 x 2.5 x 0.5 mm

SOT973-2

X

D

B

A

E

A

1

c

terminal 1

index area

detail X

e

1

terminal 1

index area

C

e

v

C A

C

B

b

y

w

C

1

6

L

k

E

h

12

7

D

h

0

1

2 mm

v

scale

Dimensions

(1)

Unit

A

b

c

D

h

E

e

1

k

L

w

y

1

h

max 0.5 0.05 0.25

mm nom

min

2.6 2.1 1.45 0.45

0.20 0.127 2.5 2.0 1.35 0.40 0.4

0.00 0.15 2.4 1.9 1.25 0.35

0.30

2

0.2 0.25 0.1 0.05 0.05 0.05

0.20

Note

1. Plastic or metal protrusions 0.0075 mm maximum per side are not included.

sot973-2_po

References

Outline

version

European

projection

Issue date

IEC

- - -

JEDEC

- - -

JEITA

- - -

10-03-23

10-03-25

SOT973-2

Fig 17. Package outline SOT973-2 (HXSON12)

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DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

16 terminals; body 2.5 x 3.5 x 0.85 mm

SOT763-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

e

b

v

M

C

A

B

C

1

w

M

2

7

L

1

8

9

E

h

e

16

15

10

D

h

X

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

3.6

3.4

2.15

1.85

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

2.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT763-1

- - -

MO-241

- - -

Fig 18. Package outline SOT763-1 (DHVQFN16)

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HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;

16 terminals; body 3 x 3 x 0.85 mm

SOT758-1

B

A

D

terminal 1

index area

A

E

A

1

c

detail X

e

C

1

1/2 e

y

v

M

C

A B

C

1

e

b

w

M

C

5

8

L

4

9

e

E

2

h

1/2 e

12

1

16

13

terminal 1

index area

D

h

X

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

2

D

E

L

y

1

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

3.1 1.75

2.9 1.45

3.1

2.9

1.75

1.45

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

1.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-03-25

02-10-21

SOT758-1

- - -

MO-220

- - -

Fig 19. Package outline SOT758-1 (HVQFN16)

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TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig 20. Package outline SOT403-1 (TSSOP16)

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14. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

14.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

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14.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 21) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 10 and 11

Table 10. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 11. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 21.

NVT2003_04_06

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 21. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

15. Abbreviations

Table 12. Abbreviations

Acronym

CDM

ESD

Description

Charged Device Model

ElectroStatic Discharge

Human Body Model

HBM

I²C-bus

I/O

Inter-Integrated Circuit bus

Input/Output

PRR

Pulse Repetition Rate

Resistor-Capacitor network

RC

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16. Revision history

Table 13. Revision history

Document ID

Release date

20120907

Data sheet status

Change notice

Supersedes

NVT2003_04_06 v.4

Modifications:

Product data sheet

-

NVT2003_04_06 v.3

• Figure 6 “Pin configuration for HVQFN16”: pin arrangement updated

• Table 2 “Pin description”:

–

added separate column for NVT2006BS pinning

added package suffix to type number column headings under “Pin”

inserted rows to show every signal separately

NVT2003_04_06 v.3

NVT2003_04_06 v.2

NVT2003_04_06 v.1

20111025

20110329

20101004

Product data sheet

-

NVT2003_04_06 v.2

NVT2003_04_06 v.1

-

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17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

17.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

17.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

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Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NVT2003_04_06

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 7 September 2012

26 of 27

NVT2003/04/06

NXP Semiconductors

Bidirectional voltage-level translator

19. Contents

1

2

3

4

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.1.1

5.1.2

5.1.3

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3-bit in TSSOP10 package . . . . . . . . . . . . . . . . 3

4-bit in HXSON12 package. . . . . . . . . . . . . . . . 3

6-bit in TSSOP16, DHVQFN16 and HVQFN16

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2

6

Functional description . . . . . . . . . . . . . . . . . . . 6

6.1

Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7

Application design-in information . . . . . . . . . . 6

Enable and disable. . . . . . . . . . . . . . . . . . . . . . 6

Bidirectional translation . . . . . . . . . . . . . . . . . . 8

Bidirectional level shifting between two different

power domains nominally at the same potential 9

Sizing pull-up resistor . . . . . . . . . . . . . . . . . . . . 9

Maximum frequency calculation . . . . . . . . . . . 10

Example maximum frequency . . . . . . . . . . . . 11

7.1

7.2

7.3

7.4

7.4.1

7.4.1.1

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11

Recommended operating conditions. . . . . . . 11

Static characteristics. . . . . . . . . . . . . . . . . . . . 12

Dynamic characteristics . . . . . . . . . . . . . . . . . 14

Open-drain drivers . . . . . . . . . . . . . . . . . . . . . 14

Performance curves . . . . . . . . . . . . . . . . . . . . 15

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

9

10

11

11.1

12

13

14

Soldering of SMD packages . . . . . . . . . . . . . . 21

Introduction to soldering . . . . . . . . . . . . . . . . . 21

Wave and reflow soldering . . . . . . . . . . . . . . . 21

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 21

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 22

14.1

14.2

14.3

14.4

15

16

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 23

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 24

17

Legal information. . . . . . . . . . . . . . . . . . . . . . . 25

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 26

17.1

17.2

17.3

17.4

18

19

Contact information. . . . . . . . . . . . . . . . . . . . . 26

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 7 September 2012

Document identifier: NVT2003_04_06


型号：	NVT2003DP
厂家：	NXP
描述：	GTL TO TTL TRANSCEIVER, TRUE OUTPUT, PDSO10, 3 MM, PLASTIC, SOT552-1, TSSOP-10 光电二极管输出元件接口集成电路锁存器
文件：	总27页 (文件大小：313K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NVT2003DP [NXP]

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