NX3L2267SGU [NXP]
Low-ohmic dual single-pole double-throw analog switch; 低电阻双单刀双掷模拟开关
| 型号： | NX3L2267SGU |
| 厂家： | 
NXP |
| 描述： | Low-ohmic dual single-pole double-throw analog switch |
| 文件： | 总20页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NX3L2267S
Low-ohmic dual single-pole double-throw analog switch
Rev. 2 — 8 November 2011
Product data sheet
1. General description
The NX3L2267S is a dual low-ohmic single-pole double-throw analog switch suitable for
use as an analog or digital 2 : 1 multiplexer/demultiplexer. Each switch has a digital select
input (nS), two independent inputs/outputs (nY0 and nY1) and a common input/output
(nZ).
The NX3L2267S includes termination resistors that improve noise immunity during
overshoot excursions, off-isolation coupling, or pop-minimization.
Schmitt trigger action at the digital inputs makes the circuit tolerant to slower input rise and
fall times. Low threshold digital inputs allows this device to be driven by 1.8 V logic levels
in 3.3 V applications without significant increase in supply current ICC. This makes it
possible for the NX3L2267S to switch 4.3 V signals with a 1.8 V digital controller,
eliminating the need for logic level translation. The NX3L2267S allows signals with
amplitude up to VCC to be transmitted from nZ to nY0 or nY1, or from nY0 or nY1 to nZ. Its
low ON resistance (0.5 ) and flatness (0.13 ) ensures minimal attenuation and
distortion of transmitted signals.
2. Features and benefits
Wide supply voltage range from 1.4 V to 4.3 V
Very low ON resistance (peak):
1.65 (typical) at VCC = 1.4 V
0.95 (typical) at VCC = 1.65 V
0.55 (typical) at VCC = 2.3 V
0.50 (typical) at VCC = 2.7 V
0.50 (typical) at VCC = 4.3 V
Break-before-make switching
High noise immunity
ESD protection:
HBM JESD22-A114F Class 3A exceeds 7500 V
MM JESD22-A115-A exceeds 200 V
CDM AEC-Q100-011 revision B exceeds 1000 V
CMOS low-power consumption
Latch-up performance exceeds 100 mA per JESD78B Class II Level A
1.8 V control logic at VCC = 3.6 V
Control input accepts voltages above supply voltage
Very low supply current, even when input is below VCC
High current handling capability (350 mA continuous current under 3.3 V supply)
NX3L2267S
NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Cell phone
PDA
Portable media player
4. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
Type number
Description
Version
NX3L2267SGU 40 C to +125 C
XQFN10
plastic, extremely thin quad flat package; no leads;
SOT1160-1
10 terminals; body 1.40 1.80 0.50 mm
5. Marking
Table 2.
Marking
Type number
Marking code
NX3L2267SGU
MS
6. Functional diagram
1Y0
1S
2Y0
2S
1Z
2Z
1Y1
2Y1
aaa-000295
Fig 1. Logic symbol
NX3L2267S
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 8 November 2011
2 of 20
NX3L2267S
NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
7. Pinning information
7.1 Pinning
NX3L2267S
terminal 1
index area
1Y1
2Y0
1
2
7
6
1S
2S
aaa-000296
Transparent top view
Fig 2. Pin configuration SOT1160-1 (XQFN10)
7.2 Pin description
Table 3.
Symbol
1Y0
1Y1
2Y0
2Y1
GND
2Z
Pin description
Pin
10
1
Description
independent input or output
independent input or output
independent input or output
independent input or output
ground (0 V)
2
3
4
5
common output or input
select input
2S
6
1S
7
select input
1Z
8
common output or input
supply voltage
VCC
9
NX3L2267S
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 8 November 2011
3 of 20
NX3L2267S
NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
8. Functional description
Table 4.
Function table[1]
Input nS
Channel on
L
nY0 = nZ; nY1 terminated to GND
nY1 = nZ; nY0 terminated to GND
H
[1] H = HIGH voltage level; L = LOW voltage level.
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
Parameter
Conditions
Min
0.5
0.5
0.5
0
Max
+4.6
+4.6
Unit
V
supply voltage
input voltage
switch voltage
[1]
[2]
VI
select input nS
nZ ON or OFF; nYn ON
nYn OFF
V
VSW
VCC + 0.5 V
1.4
-
V
IIK
input clamping current
VI < 0.5 V
50
-
mA
mA
mA
ISK
ISW
switch clamping current VI < 0.5 V or VI > VCC + 0.5 V
50
350
switch current
VSW > 0.5 V or VSW < VCC + 0.5 V;
-
source or sink current
VSW > 0.5 V or VSW < VCC + 0.5 V;
pulsed at 1 ms duration, < 10 % duty cycle;
peak current
-
500
mA
Tstg
Ptot
storage temperature
total power dissipation
65
+150
250
C
[3]
Tamb = 40 C to +125 C
-
mW
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed but may not
exceed 4.6 V.
[3] For XQFN10 package: above 133 C the value of Ptot derates linearly with 11.5 mW/K.
10. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol Parameter
Conditions
Min
1.4
0
Max
4.3
Unit
V
VCC
VI
supply voltage
input voltage
select input nS
4.3
V
[1]
[2]
VSW
Tamb
t/V
switch voltage
switch input nY0 or nY1
0
VCC
+125
200
V
ambient temperature
input transition rise and fall rate
40
-
C
ns/V
VCC = 1.4 V to 4.3 V
[1] To avoid sinking GND current from terminal nZ when switch current flows in terminal nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nYn. In this case, there
is no limit for the voltage drop across the switch.
[2] Applies to select input nS signal levels.
NX3L2267S
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 8 November 2011
4 of 20
NX3L2267S
NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
11. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter
Conditions
Tamb = 25 C
Tamb = 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Max
(85 C) (125 C)
VIH
HIGH-level
input voltage
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 4.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 4.3 V
0.9
0.9
1.1
1.3
1.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.9
0.9
1.1
1.3
1.4
-
-
-
-
-
V
V
V
V
V
V
V
V
V
V
A
-
-
-
-
-
-
-
-
-
VIL
LOW-level
input voltage
0.3
0.4
0.5
0.5
0.6
-
0.3
0.4
0.5
0.5
0.6
0.5
0.3
0.3
0.4
0.5
0.6
1
-
-
-
-
-
-
-
-
II
input leakage select input nS;
-
-
current
VI = GND to 4.3 V;
VCC = 1.4 V to 4.3 V
IS(ON)
ON-state
leakage
current
nZ port; see Figure 3
VCC = 1.4 V to 4.3 V
-
-
50
-
150
1500 nA
ICC
supply current VI = VCC or GND;
VSW = GND or VCC
VCC = 3.6 V
VCC = 4.3 V
-
-
-
-
100
150
-
-
300
500
3000 nA
5000 nA
ICC
additional
supply current
VSW = GND or VCC
VI = 2.6 V; VCC = 4.3 V
VI = 2.6 V; VCC = 3.6 V
VI = 1.8 V; VCC = 4.3 V
VI = 1.8 V; VCC = 3.6 V
VI = 1.8 V; VCC = 2.5 V
VSW = 1.0 V; VCC = 3.0 V
-
-
-
-
-
-
2.0
0.35
7.0
4.0
0.7
10.0
4.0
200
-
-
-
-
-
-
-
7
1
7
1
A
A
A
A
nA
15
5
15
5
2.5
50
300
-
500
-
[1]
RT
CI
termination
resistance
200
input
-
-
-
1.0
35
-
-
-
-
-
-
-
-
-
-
-
-
pF
pF
pF
capacitance
CS(OFF) OFF-state
capacitance
port nYn
port nYn
CS(ON)
ON-state
135
capacitance
[1] Guaranteed by characterization, not production tested.
NX3L2267S
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 8 November 2011
5 of 20
NX3L2267S
NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
11.1 Test circuits
switch nS
V
CC
1
2
V
IH
V
IL
nS
nZ
nY0
nY1
1
2
V
or V
IH
IL
switch
I
S
V
V
I
O
GND
012aaa001
VI = 0.3 V or VCC 0.3 V; VO = VCC 0.3 V or 0.3 V.
Fig 3. Test circuit for measuring ON-state leakage current
11.2 ON resistance
Table 8.
ON resistance
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 5 to Figure 11.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min Typ[1] Max
Min
Max
RON(peak) ON resistance (peak)
port nYn;
VI = GND to VCC
ISW = 100 mA;
see Figure 4
;
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 4.3 V
-
-
-
-
-
1.65
0.95
0.55
0.50
0.50
3.7
1.6
-
-
-
-
-
4.1
1.7
0.9
0.9
0.9
0.8
0.75
0.75
[2]
RON
ON resistance mismatch VI = GND to VCC;
between channels
ISW = 100 mA
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 4.3 V
-
-
-
-
-
0.20
0.20
0.09
0.09
0.09
0.35
0.25
-
-
-
-
-
0.35
0.30
0.15
0.15
0.15
0.13
0.125
0.125
NX3L2267S
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 8 November 2011
6 of 20
NX3L2267S
NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
Table 8.
ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 5 to Figure 11.
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C Unit
Min Typ[1] Max
Min
Max
[3]
RON(flat)
ON resistance (flatness) port nYn;
VI = GND to VCC
;
I
SW = 100 mA
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 4.3 V
-
-
-
-
-
1.05
0.55
0.20
0.18
0.23
3.35
1.25
0.35
0.35
0.40
-
-
-
-
-
3.65
1.35
0.40
0.40
0.45
[1] Typical values are measured at Tamb = 25 C.
[2] Measured at identical VCC, temperature and input voltage.
[3] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
11.3 ON resistance test circuit and graphs
001aag564
1.6
R
ON
(Ω)
1.2
(1)
V
SW
V
0.8
0.4
0
switch nS
(2)
V
CC
1
2
V
V
IL
(3)
(4)
nS
nZ
IH
(5)
nY0
nY1
1
2
V
or V
IH
IL
(6)
switch
V
I
SW
I
GND
0
1
2
3
4
5
V (V)
I
012aaa002
RON = VSW / ISW
.
(1) VCC = 1.5 V.
(2) VCC = 1.8 V.
(3)
VCC = 2.5 V.
(4) VCC = 2.7 V.
(5) VCC = 3.3 V.
(6)
V
CC = 4.3 V.
Measured at Tamb = 25 C.
Fig 4. Test circuit for measuring ON resistance
Fig 5. Typical ON resistance as a function of input
voltage (nYn port)
NX3L2267S
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 8 November 2011
7 of 20
NX3L2267S
NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
001aag565
001aag566
1.6
1.0
R
(Ω)
ON
R
(Ω)
ON
0.8
1.2
(1)
(2)
(3)
(4)
0.6
0.4
0.2
0
(1)
(2)
(3)
(4)
0.8
0.4
0
0
1
2
3
0
1
2
3
V (V)
I
V (V)
I
(1) Tamb = 125 C.
(2) amb = 85 C.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 6. ON resistance as a function of input voltage;
VCC = 1.5 V (nYn port)
Fig 7. ON resistance as a function of input voltage;
VCC = 1.8 V (nYn port)
001aag567
001aag568
1.0
1.0
R
ON
R
ON
(Ω)
(Ω)
0.8
0.8
0.6
0.4
0.2
0
0.6
0.4
0.2
0
(1)
(2)
(3)
(4)
(1)
(2)
(3)
(4)
0
1
2
3
0
1
2
3
V (V)
V (V)
I
I
(1) Tamb = 125 C.
(2) amb = 85 C.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 8. ON resistance as a function of input voltage;
VCC = 2.5 V (nYn port)
Fig 9. ON resistance as a function of input voltage;
VCC = 2.7 V (nYn port)
NX3L2267S
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 8 November 2011
8 of 20
NX3L2267S
NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
001aag569
001aaj896
1.0
1.0
R
ON
R
ON
(Ω)
(Ω)
0.8
0.8
(1)
(2)
(3)
(4)
0.6
0.4
0.2
0
0.6
0.4
0.2
0
(1)
(2)
(3)
(4)
0
1
2
3
4
0
1
2
3
4
5
V (V)
I
V (V)
I
(1) Tamb = 125 C.
(2) amb = 85 C.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 10. ON resistance as a function of input voltage;
VCC = 3.3 V
Fig 11. ON resistance as a function of input voltage;
VCC = 4.3 V
12. Dynamic characteristics
Table 9.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 14.
Symbol Parameter
Conditions
Tamb = 25 C
Tamb = 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Max
(85 C) (125 C)
ten
enable time
nS to nZ or nYn;
see Figure 12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 4.3 V
-
-
-
-
-
50
36
24
22
22
90
70
45
40
40
-
-
-
-
-
120
80
120
90
ns
ns
ns
ns
ns
50
55
45
45
50
50
tdis
disable time
nS to nZ or nYn;
see Figure 12
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 4.3 V
-
-
-
-
-
32
20
12
10
10
70
55
25
20
20
-
-
-
-
-
80
60
30
25
25
90
65
35
30
30
ns
ns
ns
ns
ns
NX3L2267S
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 8 November 2011
9 of 20
NX3L2267S
NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
Table 9.
Dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 14.
Symbol Parameter
Conditions
Tamb = 25 C
Tamb = 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Max
(85 C) (125 C)
[2]
tb-m
break-before-make see Figure 13
time
VCC = 1.4 V to 1.6 V
-
-
-
-
-
19
17
13
10
10
-
-
-
-
-
9
7
4
3
2
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 4.3 V
[1] Typical values are measured at Tamb = 25 C and VCC = 1.5 V, 1.8 V, 2.5 V, 3.3 V and 4.3 V respectively.
[2] Break-before-make guaranteed by design.
12.1 Waveform and test circuits
V
I
V
nS input
M
t
GND
t
en
dis
V
OH
V
V
X
X
nZ output
OFF to HIGH
HIGH to OFF
nY1 connected to V
EXT
GND
t
t
en
dis
V
OH
V
V
X
X
nZ output
nY0 connected to V
HIGH to OFF
OFF to HIGH
EXT
001aak762
GND
Measurement points are given in Table 10.
Logic level: VOH is typical output voltage level that occurs with the output load.
Fig 12. Enable and disable times
Table 10. Measurement points
Supply voltage
VCC
Input
VM
Output
VX
1.4 V to 4.3 V
0.5VCC
0.9VOH
NX3L2267S
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 8 November 2011
10 of 20
NX3L2267S
NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
V
CC
nS
nZ
nY0
nY1
G
V
= 1.5 V
EXT
V
V
R
L
C
L
V
I
O
GND
012aaa004
a. Test circuit.
V
I
0.5V
I
0.9V
O
0.9V
O
V
O
t
b-m
001aag572
b. Input and output measurement points
Fig 13. Test circuit for measuring break-before-make timing
V
CC
nS
nZ
nY0
nY1
1
2
switch
G
V
V
V
R
L
C
L
V
= 1.5 V
EXT
I
O
GND
012aaa005
Test data is given in Table 11.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
VEXT = External voltage for measuring switching times.
Fig 14. Test circuit for measuring switching times
Table 11. Test data
Supply voltage
VCC
Input
VI
Load
CL
tr, tf
2.5 ns
RL
1.4 V to 4.3 V
VCC
35 pF
50
NX3L2267S
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 8 November 2011
11 of 20
NX3L2267S
NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
12.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise
specified); tr = tf 2.5 ns.
Symbol Parameter
Conditions
Tamb = 25 C
Unit
Min
Typ
Max
[1]
THD
total harmonic
distortion
fi = 20 Hz to 20 kHz; RL = 32 ; see Figure 15
VCC = 1.4 V; VI = 1 V (p-p)
-
-
-
-
-
-
0.15
0.10
0.02
0.02
0.02
0.01
-
-
-
-
-
-
%
%
%
%
%
%
VCC = 1.65 V; VI = 1.2 V (p-p)
VCC = 2.3 V; VI = 1.5 V (p-p)
VCC = 2.7 V; VI = 2 V (p-p)
VCC = 4.3 V; VI = 2 V (p-p)
VCC = 3.0 V; VI = 1 V (p-p); RL = 600
RL = 50 ; see Figure 16
[1]
[1]
f(3dB)
3 dB frequency
response
port nYn; VCC = 1.4 V to 4.3 V
fi = 100 kHz; RL = 50 ; see Figure 17
VCC = 1.4 V to 4.3 V
-
-
60
-
-
MHz
dB
iso
isolation (OFF-state)
crosstalk voltage
90
Vct
between digital inputs and switch;
fi = 1 MHz; CL = 50 pF; RL = 50 ; see Figure 18
VCC = 1.4 V to 3.6 V
VCC = 3.6 V to 4.3 V
-
-
0.21
0.30
-
-
V
V
[1]
Xtalk
Qinj
crosstalk
between switches;
fi = 100 kHz; RL = 50 ; see Figure 19
VCC = 1.4 V to 4.3 V
-
90
-
dB
charge injection
fi = 1 MHz; CL = 0.1 nF; RL = 1 M; Vgen = 0 V;
Rgen = 0 ; see Figure 20
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 4.3 V
-
-
-
-
-
4
-
-
-
-
-
pC
pC
pC
pC
pC
6
16
24
37
[1] fi is biased at 0.5VCC
.
NX3L2267S
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Product data sheet
Rev. 2 — 8 November 2011
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NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
12.3 Test circuits
V
0.5V
CC
CC
switch nS
R
L
1
2
V
IL
nS
nZ
nY0
nY1
1
2
V
or V
IH
IL
switch
V
IH
f
D
i
GND
012aaa006
Fig 15. Test circuit for measuring total harmonic distortion
V
0.5V
CC
CC
switch nS
R
L
1
2
V
IL
nS
nZ
nY0 1
nY1 2
V
or V
IH
IL
switch
V
IH
f
dB
i
GND
012aaa007
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB.
Fig 16. Test circuit for measuring the frequency response when channel is in ON-state
0.5V
V
0.5V
CC
CC
CC
switch nS
R
L
R
L
1
2
V
IH
nS
nZ
nY0
nY1
1
2
V
or V
IH
IL
switch
V
IL
f
dB
i
GND
012aaa008
Adjust fi voltage to obtain 0 dBm level at input.
Fig 17. Test circuit for measuring isolation (OFF-state)
NX3L2267S
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Product data sheet
Rev. 2 — 8 November 2011
13 of 20
NX3L2267S
NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
switch nS
V
CC
1
2
V
IL
V
IH
nS
nZ
nY0
nY1
1
2
switch
0.5V
logic
input
G
V
R
L
R
L
C
L
V
O
V
I
0.5V
CC
CC
012aaa009
a. Test circuit
logic
input (nS)
off
on
off
V
V
O
ct
012aaa010
b. Input and output pulse definitions
Fig 18. Test circuit for measuring crosstalk voltage between digital inputs and switch
0.5V
CC
1S
1Y0 or 1Z
50
V
IH
R
L
1Z or 1Y0
CHANNEL
ON
f
V
V
O1
i
0.5V
CC
2S
V
IL
R
L
2Y0 or 2Z
2Z or 2Y0
CHANNEL
OFF
R
50
i
V
V
O2
001aaj088
20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2).
Fig 19. Test circuit for measuring crosstalk between switches
NX3L2267S
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Product data sheet
Rev. 2 — 8 November 2011
14 of 20
NX3L2267S
NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
V
CC
nS
nZ
nY0
nY1
1
2
switch
R
gen
G
V
V
R
L
C
L
I
O
V
gen
GND
012aaa011
a. Test circuit.
logic
input
(nS) off
on
off
V
O
ΔV
O
012aaa012
b. Input and output pulse definitions
Definition: Qinj = VO CL.
VO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
Fig 20. Test circuit for measuring charge injection
NX3L2267S
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Product data sheet
Rev. 2 — 8 November 2011
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NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
13. Package outline
XQFN10: plastic, extremely thin quad flat package; no leads;
10 terminals; body 1.40 x 1.80 x 0.50 mm
SOT1160-1
X
D
B
A
terminal 1
index area
E
A
A
1
A
3
detail X
e
1
e
C
v
C A
B
b
y
C
1
y
w
C
3
5
L
2
1
6
7
e
2
terminal 1
index area
10
8
L
1
0
1
2 mm
w
scale
Dimensions
(1)
Unit
A
A
A
b
D
E
e
e
e
2
L
L
1
v
y
y
1
1
3
1
max 0.5 0.05
mm nom
min
0.25 1.5 1.9
0.127 0.20 1.4 1.8 0.4 0.8 0.4 0.40 0.50 0.1 0.05 0.05 0.05
0.15 1.3 1.7 0.35 0.45
0.45 0.55
0.00
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot1160-1_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
- - -
JEITA
- - -
09-12-28
09-12-29
SOT1160-1
Fig 21. Package outline SOT1160-1 (XQFN10)
NX3L2267S
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Product data sheet
Rev. 2 — 8 November 2011
16 of 20
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NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
14. Abbreviations
Table 13. Abbreviations
Acronym
CDM
CMOS
ESD
Description
Charged Device Model
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 14. Revision history
Document ID
NX3L2267S v.2
Modifications:
NX3L2267S v.1
Release date
20111108
Data sheet status
Change notice
Supersedes
Product data sheet
-
NX3L2267S v.1
• Legal pages updated.
20110823 Product data sheet
-
-
NX3L2267S
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Product data sheet
Rev. 2 — 8 November 2011
17 of 20
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NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
16.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
NX3L2267S
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Product data sheet
Rev. 2 — 8 November 2011
18 of 20
NX3L2267S
NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NX3L2267S
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Product data sheet
Rev. 2 — 8 November 2011
19 of 20
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NXP Semiconductors
Low-ohmic dual single-pole double-throw analog switch
18. Contents
1
2
3
4
5
6
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
8
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
9
10
11
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance test circuit and graphs. . . . . . . . 7
11.1
11.2
11.3
12
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveform and test circuits . . . . . . . . . . . . . . . 10
Additional dynamic characteristics . . . . . . . . . 12
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12.1
12.2
12.3
13
14
15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 November 2011
Document identifier: NX3L2267S
相关型号：
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