NX3L4053HR,115 [NXP]
NX3L4053 - Triple low-ohmic single-pole double-throw analog switch QFN 16-Pin;
| 型号： | NX3L4053HR,115 |
| 厂家： | 
NXP |
| 描述： | NX3L4053 - Triple low-ohmic single-pole double-throw analog switch QFN 16-Pin |
| 文件： | 总22页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NX3L4053
Triple low-ohmic single-pole double-throw analog switch
Rev. 5 — 25 June 2012
Product data sheet
1. General description
The NX3L4053 is a triple low-ohmic single-pole double-throw analog switch, suitable for
use as an analog or digital multiplexer/demultiplexer. Each switch has a digital select input
(nS), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All
three switches share an enable input (E). A digital enable pin E is common to all
switches.When E is HIGH, the switches are turned off.
Schmitt trigger action at the digital inputs makes the circuit tolerant to slower input rise and
fall times. Low threshold digital inputs allows this device to be driven by 1.8 V logic levels
in 3.3 V applications without significant increase in supply current ICC. This makes it
possible for the NX3L4053 to switch 4.3 V signals with a 1.8 V digital controller,
eliminating the need for logic level translation. The NX3L4053 allows signals with
amplitude up to VCC to be transmitted from nZ to nY0 or nY1; or from nY0 or nY1 to nZ. Its
low ON resistance (0.5 ) and flatness (0.13 ) ensures minimal attenuation and
distortion of transmitted signals.
2. Features and benefits
Wide supply voltage range from 1.4 V to 4.3 V
Very low ON resistance (peak):
1.8 (typical) at VCC = 1.4 V
1.0 (typical) at VCC = 1.65 V
0.6 (typical) at VCC = 2.3 V
0.6 (typical) at VCC = 2.7 V
0.5 (typical) at VCC = 4.3 V
Break-before-make switching
High noise immunity
ESD protection:
HBM JESD22-A114F Class 3A exceeds 4000 V
MM JESD22-A115-A exceeds 200 V
CDM AEC-Q100-011 revision B exceeds 1000 V
IEC61000-4-2 contact discharge exceeds 6000 V for switch ports
CMOS low-power consumption
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
1.8 V control logic at VCC = 3.6 V
Control input accepts voltages above supply voltage
Very low supply current, even when input is below VCC
High current handling capability (350 mA continuous current under 3.3 V supply)
Specified from 40 C to +85 C and from 40 C to +125 C
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
3. Applications
Cell phone
PDA
Portable media player
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
4. Ordering information
Table 1.
Ordering information
Type number Package
Temperature range Name
Description
Version
NX3L4053HR 40 C to +125 C
HXQFN16
plastic thermal enhanced extremely thin quad flat
package; no leads; 16 terminals; body 3 3 0.5 mm
SOT1039-2
NX3L4053PW 40 C to +125 C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
5. Marking
Table 2.
Marking codes
Type number
NX3L4053HR
NX3L4053PW
Marking code
M43
X3L4053
NX3L4053
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 June 2012
2 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
6. Functional diagram
V
CC
16
13
1Y1
11
10
9
1S
2S
3S
12
14
1
1Y0
1Z
11
10
9
1S
2S
3S
1Y0
1Y1
1Z
12
13
14
2
2Y1
2Y0
2Y1
2Z
DECODER
LOGIC
1
2
15
3
2Y0
2Z
15
5
3Y0
3Y1
3Z
3
6
E
4
3Y1
001aal735
6
5
4
E
3Y0
3Z
8
GND
001aal736
Pin numbers are shown for TSSOP16 package only.
Pin numbers are shown for TSSOP16 package only.
Fig 1. Logic symbol
Fig 2. Logic diagram
7. Pinning information
7.1 Pinning
terminal 1
index area
NX3L4053
3Y1
3Z
1
2
3
4
12 1Z
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Y1
2Y0
3Y1
3Z
V
CC
2Z
11 1Y1
10 1Y0
1Z
NX3L4053
1Y1
1Y0
1S
3Y0
E
3Y0
E
9
1S
n.c.
GND
2S
3S
001aal738
001aal737
Transparent top view
Fig 3. Pin configuration SOT1039-2 (HXQFN16)
Fig 4. Pin configuration SOT403-1 (TSSOP16)
NX3L4053
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 June 2012
3 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
7.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SOT403-1
SOT1039-2
E
4
6
enable input (active LOW)
not connected
n.c.
5
7
GND
6
8
ground (0 V)
1S, 2S, 3S
1Y0, 2Y0, 3Y0
1Y1, 2Y1, 3Y1
1Z , 2Z, 3Z
VCC
9, 8, 7
10, 16, 3
11, 15, 1
12, 13, 2
14
11, 10 ,9
12, 2, 5
13, 1, 3
14, 15, 4
16
select input
independent input or output
independent input or output
independent output or input
supply voltage
8. Functional description
Table 4.
Function table
Inputs
Channel on
E
L
nS
L
nY0 to nZ
nY1 to nZ
switches off
L
H
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
VI
Parameter
Conditions
nS and E
Min
0.5
0.5
0.5
50
-
Max
+4.6
+4.6
Unit
V
supply voltage
input voltage
[1]
[2]
V
VSW
IIK
switch voltage
input clamping current
VCC + 0.5 V
VI < 0.5 V
-
mA
ISK
switch clamping current VI < 0.5 V or VI > VCC + 0.5 V
50
350
mA
mA
ISW
switch current
VSW > 0.5 V or VSW < VCC + 0.5 V;
-
source or sink current
VSW > 0.5 V or VSW < VCC + 0.5 V;
pulsed at 1 ms duration, < 10 % duty cycle;
peak current
-
500
mA
Tstg
Ptot
storage temperature
total power dissipation
65
+150
C
Tamb = 40 C to +125 C
HXQFN16
[3]
[4]
-
-
250
500
mW
mW
TSSOP16
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
NX3L4053
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 June 2012
4 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed but may not
exceed 4.6 V.
[3] For HXQFN16 package: above 135 C the value of Ptot derates linearly with 16.9 mW/K.
[4] For TSSOP16 package: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
10. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol Parameter
Conditions
Min
1.4
0
Max
4.3
Unit
V
VCC
VI
supply voltage
input voltage
nS and E
4.3
V
[1]
VSW
Tamb
t/V
switch voltage
0
VCC
+125
200
V
ambient temperature
input transition rise and fall rate
40
-
C
ns/V
nS and E; VCC = 1.4 V to 4.3 V
[1] To avoid sinking GND current from terminal nZ when switch current flows in terminal nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nYn. In this case, there
is no limit for the voltage drop across the switch.
11. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter
Conditions
Tamb = 25 C
Tamb = 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Max
(85 C) (125 C)
VIH
HIGH-level
input voltage
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 4.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 4.3 V
0.9
0.9
1.1
1.3
1.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.9
0.9
1.1
1.3
1.4
-
-
-
-
-
V
V
V
V
V
V
V
V
V
V
A
-
-
-
-
-
-
-
-
-
VIL
LOW-level
input voltage
0.3
0.4
0.4
0.5
0.6
-
0.3
0.4
0.4
0.5
0.6
0.5
0.3
0.3
0.4
0.5
0.6
1
-
-
-
-
-
-
-
-
II
input leakage nS and E;
-
-
current
VI = GND to 4.3 V;
VCC = 1.4 V to 4.3 V
IS(OFF)
OFF-state
leakage
current
nY0 and nY1 port;
see Figure 5
VCC = 1.4 V to 3.6 V
VCC = 3.6 V to 4.3 V
-
-
-
-
5
-
-
50
50
500 nA
500 nA
10
NX3L4053
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 June 2012
5 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter
Conditions
Tamb = 25 C
Tamb = 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Max
(85 C) (125 C)
IS(ON)
ON-state
leakage
current
nZ port;
VCC = 1.4 V to 3.6 V;
see Figure 6
VCC = 1.4 V to 3.6 V
VCC = 3.6 V to 4.3 V
-
-
-
-
5
-
-
50
50
500 nA
10
500 nA
ICC
supply current VI = VCC or GND;
VSW = GND or VCC
VCC = 3.6 V
-
-
-
-
100
150
-
-
500
800
5000 nA
6000 nA
VCC = 4.3 V
ICC
additional
supply current
VSW = GND or VCC
VI = 2.6 V; VCC = 4.3 V
VI = 2.6 V; VCC = 3.6 V
VI = 1.8 V; VCC = 4.3 V
VI = 1.8 V; VCC = 3.6 V
VI = 1.8 V; VCC = 2.5 V
nS and E
-
-
-
-
-
-
2.0
0.35
7.0
2.5
50
4.0
0.7
10.0
4.0
200
-
-
-
-
-
-
-
7
1
7
1
A
A
A
A
nA
pF
15
5
15
5
300
-
500
-
CI
input
1.0
capacitance
CS(OFF) OFF-state
capacitance
-
-
35
-
-
-
-
-
-
-
-
pF
pF
CS(ON)
ON-state
130
capacitance
11.1 Test circuits
V
CC
switch nS
E
V
V
V
IH
1
2
IL
nS
nZ
nY0
nY1
1
2
V
or V
V
IL
IH
V
switch
IH
IH
I
S
E
GND
IH
V
V
O
I
001aal739
VI = 0.3 V or VCC 0.3 V; VO = VCC 0.3 V or 0.3 V.
Fig 5. Test circuit for measuring OFF-state leakage current
NX3L4053
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 June 2012
6 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
V
CC
switch nS
E
V
V
V
1
2
IL
IL
IL
nS
nZ
nY0
nY1
1
2
V
or V
IH
IL
V
switch
IH
I
S
E
GND
V
IL
V
V
O
I
001aal740
VI = 0.3 V or VCC 0.3 V; VO = VCC 0.3 V or 0.3 V.
Fig 6. Test circuit for measuring ON-state leakage current
11.2 ON resistance
Table 8.
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 8 to Figure 14.
ON resistance[1]
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
Typ[2]
Max
Min
Max
RON(peak) ON resistance VI = GND to VCC
;
(peak)
ISW = 100 mA; see Figure 7
VCC = 1.4 V
-
-
-
-
-
1.8
1.0
0.6
0.6
0.5
3.8
1.7
-
-
-
-
-
4.2
1.8
1.0
1.0
1.0
VCC = 1.65 V
VCC = 2.3 V
0.9
VCC = 2.7 V
0.80
0.80
VCC = 4.3 V
[3]
RON
ON resistance VI = GND to VCC;
mismatch
between
channels
ISW = 100 mA
VCC = 1.4 V; VSW = 0.4 V
VCC = 1.65 V; VSW = 0.5 V
VCC = 2.3 V; VSW = 0.7 V
VCC = 2.7 V; VSW = 0.8 V
VCC = 4.3 V; VSW = 0.8 V
-
-
-
-
-
0.23
0.23
0.12
0.12
0.12
0.38
0.28
0.15
0.15
0.15
-
-
-
-
-
0.38
0.38
0.18
0.18
0.18
[4]
RON(flat)
ON resistance VI = GND to VCC;
(flatness)
ISW = 100 mA
VCC = 1.4 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 4.3 V
-
-
-
-
-
1.0
0.5
3.3
1.2
0.3
0.3
0.4
-
-
-
-
-
3.6
1.3
0.15
0.13
0.2
0.35
0.35
0.45
[1] For NX3L4053PW (TSSOP16 package), all ON resistance values are up to 0.05 higher.
[2] Typical values are measured at Tamb = 25 C.
[3] Measured at identical VCC, temperature and input voltage.
[4] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
NX3L4053
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 June 2012
7 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
11.3 ON resistance test circuit and graphs
001aag564
1.6
R
ON
(Ω)
1.2
(1)
V
0.8
0.4
0
V
switch nS
E
CC
V
SW
V
V
V
1
2
(2)
IL
IL
IL
nS
nZ
nY0
nY1
1
2
V
(3)
IH
V
or V
IH
IL
switch
(4)
(5)
(6)
E
GND
V
IL
V
I
SW
I
0
1
2
3
4
5
V (V)
I
001aal741
RON = VSW / ISW
.
(1) VCC = 1.5 V.
(2) CC = 1.8 V.
V
(3) VCC = 2.5 V.
(4) VCC = 2.7 V.
(5)
(6) VCC = 4.3 V.
Measured at Tamb = 25 C.
VCC = 3.3 V.
Fig 7. Test circuit for measuring ON resistance
Fig 8. Typical ON resistance as a function of input
voltage
NX3L4053
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 June 2012
8 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
001aag565
001aag566
1.6
1.0
R
(Ω)
ON
R
(Ω)
ON
0.8
1.2
(1)
(2)
(3)
(4)
0.6
0.4
0.2
0
(1)
(2)
(3)
(4)
0.8
0.4
0
0
1
2
3
0
1
2
3
V (V)
I
V (V)
I
(1) Tamb = 125 C.
(2) amb = 85 C.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 9. ON resistance as a function of input voltage;
VCC = 1.5 V
Fig 10. ON resistance as a function of input voltage;
VCC = 1.8 V
001aag567
001aag568
1.0
1.0
R
ON
R
ON
(Ω)
(Ω)
0.8
0.8
0.6
0.4
0.2
0
0.6
0.4
0.2
0
(1)
(2)
(3)
(4)
(1)
(2)
(3)
(4)
0
1
2
3
0
1
2
3
V (V)
V (V)
I
I
(1) Tamb = 125 C.
(2) amb = 85 C.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 11. ON resistance as a function of input voltage;
VCC = 2.5 V
Fig 12. ON resistance as a function of input voltage;
VCC = 2.7 V
NX3L4053
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 June 2012
9 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
001aag569
001aaj896
1.0
1.0
R
ON
R
ON
(Ω)
(Ω)
0.8
0.8
(1)
(2)
(3)
(4)
0.6
0.4
0.2
0
0.6
0.4
0.2
0
(1)
(2)
(3)
(4)
0
1
2
3
4
0
1
2
3
4
5
V (V)
I
V (V)
I
(1) Tamb = 125 C.
(2) amb = 85 C.
(1) Tamb = 125 C.
(2) amb = 85 C.
T
T
(3) Tamb = 25 C.
(4) Tamb = 40 C.
(3) Tamb = 25 C.
(4) Tamb = 40 C.
Fig 13. ON resistance as a function of input voltage;
VCC = 3.3 V
Fig 14. ON resistance as a function of input voltage;
VCC = 4.3 V
12. Dynamic characteristics
Table 9.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 17.
Symbol Parameter
Conditions
Tamb = 25 C
Tamb = 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Max
(85 C) (125 C)
ten
enable time
E, nS to nZ or nYn;
see Figure 15
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 4.3 V
-
-
-
-
-
49
35
23
21
21
90
70
45
40
40
-
-
-
-
-
120
80
120
90
ns
ns
ns
ns
ns
50
55
45
45
50
50
tdis
disable time
E, nS to nZ or nYn;
see Figure 15
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 4.3 V
-
-
-
-
-
32
17
11
8
70
55
25
20
20
-
-
-
-
-
80
60
30
25
25
90
65
35
30
30
ns
ns
ns
ns
ns
8
NX3L4053
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 June 2012
10 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
Table 9.
Dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 17.
Symbol Parameter
Conditions
Tamb = 25 C
Tamb = 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
Max
(85 C) (125 C)
[2]
tb-m
break-before-make see Figure 16
time
VCC = 1.4 V to 1.6 V
-
-
-
-
-
19
17
13
10
9
-
-
-
-
-
9
7
4
3
2
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 4.3 V
[1] Typical values are measured at Tamb = 25 C and VCC = 1.5 V, 1.8 V, 2.5 V, 3.3 V and 4.3 V respectively.
[2] Break-before-make guaranteed by design.
12.1 Waveform and test circuits
V
I
V
V
M
nS, E input
M
GND
t
t
dis
en
V
OH
V
V
X
output
OFF to HIGH
HIGH to OFF
X
GND
t
t
en
dis
V
OH
V
X
V
X
output
HIGH to OFF
OFF to HIGH
001aal742
GND
Measurement points are given in Table 10.
Logic level: VOH is typical output voltage level that occurs with the output load.
Fig 15. Enable and disable times
Table 10. Measurement points
Supply voltage
VCC
Input
VM
Output
VX
1.4 V to 4.3 V
0.5VCC
0.9VOH
NX3L4053
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Product data sheet
Rev. 5 — 25 June 2012
11 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
V
CC
nS
nZ
nY0
nY1
E
V
IL
G
V
V
R
L
C
L
V
= 1.5 V
EXT
V
I
O
GND
001aal743
a. Test circuit
V
I
0.5V
I
0.9V
O
0.9V
O
V
O
t
b-m
001aag572
b. Input and output measurement points
Fig 16. Test circuit for measuring break-before-make timing
V
CC
nS
nZ
nY0
nY1
1
2
switch
E
V
IL
G
V
V
R
L
C
L
V
= 1.5 V
EXT
V
I
O
GND
001aal744
Test data is given in Table 11.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
EXT = External voltage for measuring switching times.
V
VI may be connected to nS or E.
Fig 17. Test circuit for measuring switching times
NX3L4053
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Product data sheet
Rev. 5 — 25 June 2012
12 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
Table 11. Test data
Supply voltage
VCC
Input
VI
Load
tr, tf
CL
RL
1.4 V to 4.3 V
VCC
2.5 ns
35 pF
50
12.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise
specified); tr = tf 2.5 ns; Tamb = 25 C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[1]
THD
total harmonic
distortion
fi = 20 Hz to 20 kHz; RL = 32 ; see Figure 18
VCC = 1.4 V; VI = 1 V (p-p)
VCC = 1.65 V; VI = 1.2 V (p-p)
VCC = 2.3 V; VI = 1.5 V (p-p)
VCC = 2.7 V; VI = 2 V (p-p)
VCC = 4.3 V; VI = 2 V (p-p)
RL = 50 ; see Figure 19
VCC = 1.4 V to 4.3 V
-
-
-
-
-
0.15
-
-
-
-
-
%
%
%
%
%
0.10
0.02
0.02
0.02
[1]
[1]
f(3dB)
3 dB frequency
response
-
-
60
-
-
MHz
dB
iso
isolation (OFF-state)
crosstalk voltage
fi = 100 kHz; RL = 50 ; see Figure 20
VCC = 1.4 V to 4.3 V
90
Vct
between digital inputs and switch;
fi = 1 MHz; CL = 50 pF; RL = 50 ; see Figure 21
VCC = 1.4 V to 3.6 V
VCC = 3.6 V to 4.3 V
-
-
0.2
0.3
-
-
V
V
[1]
Xtalk
Qinj
crosstalk
between switches;
fi = 100 kHz; RL = 50 ; see Figure 22
VCC = 1.4 V to 4.3 V
-
90
-
dB
charge injection
fi = 1 MHz; CL = 0.1 nF; RL = 1 M; Vgen = 0 V;
Rgen = 0 ; see Figure 23
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 4.3 V
-
-
-
-
-
3
4
-
-
-
-
-
pC
pC
pC
pC
pC
6
9
15
[1] fi is biased at 0.5VCC
.
NX3L4053
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Product data sheet
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NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
12.3 Test circuits
V
0.5V
CC
CC
switch nS
V
E
R
L
V
1
2
IL
IL
IL
nS
nZ
nY0
nY1
1
2
V
or V
IH
IL
switch
V
V
IH
E
V
IL
f
D
i
GND
001aal745
Fig 18. Test circuit for measuring total harmonic distortion
V
0.5V
CC
CC
switch nS
V
E
R
L
V
IL
1
2
IL
nS
nZ
nY0
nY1
1
2
V
or V
IH
IL
switch
V
V
IL
IH
E
V
IL
f
dB
i
GND
001aal746
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB.
Fig 19. Test circuit for measuring the frequency response when channel is in ON-state
0.5V
V
0.5V
CC
CC
CC
switch nS
V
E
R
L
R
L
V
IH
IH
1
2
IH
nS
nZ
nY0
nY1
1
2
V
V
IL
V
or V
V
IL
IH
switch
E
IH
f
dB
i
GND
001aal747
Adjust fi voltage to obtain 0 dBm level at input.
Fig 20. Test circuit for measuring isolation (OFF-state)
NX3L4053
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Product data sheet
Rev. 5 — 25 June 2012
14 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
V
CC
E
nS
nY0
nY1
V
or V
IL
IH
nZ
logic
input
G
V
R
L
R
L
C
L
V
O
V
I
0.5V
0.5V
CC
CC
001aal748
a. Test circuit
logic input
(nS, E)
off
on
off
V
O
V
ct
001aal749
b. Input and output pulse definitions
Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch
V
CC
0.5V
0.5V
CC CC
R
L
R
L
nS
nZ
nY0
nY1
V
or V
V
IL
IH
E
IH
f
dB
i
GND
001aal750
Fig 22. Test circuit for measuring crosstalk between switches
NX3L4053
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Product data sheet
Rev. 5 — 25 June 2012
15 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
V
CC
nS
nZ
nY0
nY1
1
2
switch
E
R
gen
V
IL
G
V
V
R
L
C
L
V
V
I
O
gen
GND
001aal751
a. Test circuit
logic input
(nS, E)
off
on
off
V
O
V
O
001aal752
b. Input and output pulse definitions
Definition: Qinj = VO CL.
VO = output voltage variation.
Rgen = generator resistance.
V
gen = generator voltage.
VI may be connected to nS or E.
Fig 23. Test circuit for measuring charge injection
NX3L4053
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Product data sheet
Rev. 5 — 25 June 2012
16 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
13. Package outline
HXQFN16: plastic thermal enhanced extremely thin quad flat package; no leads;
16 terminals; body 3 x 3 x 0.5 mm
SOT1039-2
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
e
1
1/2 e
b
C
e
v
C A
B
y
C
1
y
w
C
5
8
L
4
1
9
e
E
e
2
h
1/2 e
12
X
terminal 1
index area
16
13
D
h
0
1
scale
2 mm
Dimensions
Unit
A
A
b
c
D
D
E
E
e
e
e
L
0.40
v
w
y
y
1
1
h
h
1
2
max 0.5 0.05 0.35
mm nom
min
3.1 1.95 3.1 1.95
0.30 0.127 3.0 1.85 3.0 1.85 0.5 1.5 1.5 0.35 0.1 0.05 0.05 0.1
0.00 0.25 2.9 1.75 2.9 1.75 0.30
sot1039-2_po
References
Outline
version
European
projection
Issue date
IEC
- - -
JEDEC
JEITA
- - -
10-07-29
11-03-30
SOT1039-2
Fig 24. Package outline SOT1039-2 (HXQFN16)
NX3L4053
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Product data sheet
Rev. 5 — 25 June 2012
17 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 25. Package outline SOT403-1 (TSSOP16)
NX3L4053
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Product data sheet
Rev. 5 — 25 June 2012
18 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
14. Abbreviations
Table 13. Abbreviations
Acronym
CDM
Description
Charged Device Model
CMOS
ESD
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
PDA
Personal Digital Assistant
15. Revision history
Table 14. Revision history
Document ID
NX3L4053 v.5
Modifications:
NX3L4053 v.4
Modifications:
NX3L4053 v.3
NX3L4053 v.2
NX3L4053 v.1
Release date
20120625
Data sheet status
Change notice
Supersedes
Product data sheet
-
NX3L4053 v.4
• For type number NX3L4053HR the sot code has changed to SOT1039-2.
20111107
Product data sheet
-
NX3L4053 v.3
• Legal pages updated.
20101223
20100811
20100416
Product data sheet
-
-
-
NX3L4053 v.2
Product data sheet
Product data sheet
NX3L4053 v.1
-
NX3L4053
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Product data sheet
Rev. 5 — 25 June 2012
19 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
16.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
NX3L4053
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Product data sheet
Rev. 5 — 25 June 2012
20 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NX3L4053
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 25 June 2012
21 of 22
NX3L4053
NXP Semiconductors
Triple low-ohmic single-pole double-throw analog switch
18. Contents
1
2
3
4
5
6
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
8
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
9
10
11
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 7
ON resistance test circuit and graphs. . . . . . . . 8
11.1
11.2
11.3
12
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveform and test circuits . . . . . . . . . . . . . . . 11
Additional dynamic characteristics . . . . . . . . . 13
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
12.1
12.2
12.3
13
14
15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 21
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 25 June 2012
Document identifier: NX3L4053
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