OM4068 [NXP]
LCD driver for low multiplex rates; 低复用率的LCD驱动器
| 型号： | OM4068 |
| 厂家： | 
NXP |
| 描述： | LCD driver for low multiplex rates |
| 文件： | 总28页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
OM4068
LCD driver for low multiplex rates
1998 Jun 18
Product specification
File under Integrated Circuits, IC12
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
FEATURES
APPLICATIONS
• Single-chip LCD controller/driver
• Telecom equipment
• Portable instruments
• Alarm systems
• Static/duplex/triplex drive modes with up to
32/64/96 LCD segments drive capability per device
• Selectable backplane drive configuration: static or
2 or 3 backplane multiplexing
• Automotive equipment.
• Selectable display bias configuration drive: static, 1⁄2 or
GENERAL DESCRIPTION
1
⁄
3
The OM4068 is a low-power CMOS LCD driver, designed
to drive Liquid Crystal Displays (LCDs) with low multiplex
rates. It generates the drive signals for any static or
multiplexed LCD containing up to three backplanes and up
to 32 segment lines and can be easily cascaded for larger
LCD applications. All necessary functions for the display
are provided in a single chip, including on-chip generation
of LCD bias voltages, resulting in a minimum of external
components and lower power consumption. A 3-line bus
structure enables serial data transfer with most
microprocessors/microcontrollers. All inputs are CMOS
compatible.
• 32 segment drivers
• Serial data input (word length 32 to 96 bits)
• On-chip generation of intermediate LCD bias voltages
• 2 MHz fast serial bus interface
• CMOS compatible
• Compatible with any 4-bit, 8-bit or 16-bit
microprocessors/microcontrollers
• May be cascaded for large LCD applications
• Logic supply voltage range (VDD − VSS) of 2.5 to 5.5 V
• Display supply voltage range (VLCD − VSS) of
3.5 to 6.5 V
• Low power consumption, suitable for battery operated
systems
• No external components needed by the oscillator
• Manufactured in silicon gate CMOS process.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
OM4068H(1)
QFP44
plastic quad flat package; 44 leads (lead length 1.3 mm);
SOT307-2
body 10 × 10 × 1.75 mm
OM4068P
OM4068U/5(2)
DIP40
die
plastic dual in-line package; 40 leads (600 mil)
SOT129-1
unsawn wafer
chip in tray
−
−
OM4068U
tray
Notes
1. Gull Wing package.
2. For details see Chapter “Bonding pad locations”.
1998 Jun 18
2
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
BLOCK DIAGRAM
(1)
BP1
BP2
BP3
SEG1 to SEG32
32
BACKPLANE OUTPUTS
4
DISPLAY SEGMENT OUTPUTS
4
M0
M1
LCD VOLTAGE
SELECTOR
(CONTROL LOGIC)
DISPLAY LATCH
SCE
4
SCLK
SDIN
BIAS
VOLTAGE
GENERATOR
SHIFT REGISTER
V
LCD
SDOUT
OM4068
POWER-ON
RESET
TIMING
OSCILLATOR
GENERATOR
MBK817
V
V
DD
SS
(1) SEG1, SEG6, SEG15 and SEG25 are not available in DIP40 package.
Fig.1 Block diagram.
1998 Jun 18
3
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
PINNING
See notes 1 to 8.
PIN
SYMBOL
DESCRIPTION
QFP44
DIP40
VLCD
4
19
20
21
22
23
24
25
26
27
28
29
30
−
LCD supply voltage
VDD
5
positive supply voltage
VSS
6
ground
M0
7
drive mode select input 0
M1
8
drive mode select input 1
SDIN
9
serial bus data input
SCLK
SCE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
serial bus clock input
serial bus clock enable
SDOUT
BP1
serial bus data output
LCD backplane driver output 1
LCD backplane driver output 2
LCD backplane driver output 3
LCD segment driver output 1
LCD segment driver output 2
LCD segment driver output 3
LCD segment driver output 4
LCD segment driver output 5
LCD segment driver output 6
LCD segment driver output 7
LCD segment driver output 8
LCD segment driver output 9
LCD segment driver output 10
LCD segment driver output 11
LCD segment driver output 12
LCD segment driver output 13
LCD segment driver output 14
LCD segment driver output 15
LCD segment driver output 16
LCD segment driver output 17
LCD segment driver output 18
LCD segment driver output 19
LCD segment driver output 20
LCD segment driver output 21
LCD segment driver output 22
LCD segment driver output 23
LCD segment driver output 24
LCD segment driver output 25
LCD segment driver output 26
BP2
BP3
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
31
32
33
34
−
35
36
37
38
39
40
1
2
−
3
4
5
6
7
8
9
10
11
−
12
1998 Jun 18
4
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
PIN
SYMBOL
DESCRIPTION
LCD segment driver output 27
QFP44
DIP40
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
42
43
44
1
13
14
15
16
17
18
LCD segment driver output 28
LCD segment driver output 29
LCD segment driver output 30
LCD segment driver output 31
LCD segment driver output 32
2
3
Notes
1. SEG1 to SEG32 (LCD segment driver outputs) output the multi-level signals for the LCD segments.
2. BP0, BP1 and BP2 (LCD backplane driver outputs) output the multi-level signals for the LCD backplanes.
3. VLCD (LCD power supply): power supply for the LCD.
4. SDIN (serial data line): input for the bus data line.
5. SCL (serial clock line): input for the bus clock line.
6. SDOUT (serial data output): output of the shift register to allow serial cascading of the OM4068 with other devices.
7. SCE (serial clock enable): input for enable/disable acquisition on the data input line. If disabled, data on the serial
bus are not accepted by the device.
8. M0 and M1 (display mode select inputs): inputs to select the LCD drive configurations; static, duplex or triplex.
1998 Jun 18
5
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
SEG30
SEG31
SEG32
1
2
3
4
5
6
7
8
9
33
32
SEG18
SEG17
31 SEG16
30 SEG15
V
LCD
V
SEG14
29
28
27
26
DD
OM4068H
V
SEG13
SEG12
SEG11
SS
M0
M1
SDIN
25 SEG10
SCLK 10
SCE 11
24
23
SEG9
SEG8
MBK814
Fig.2 Pin configuration (QFP44).
1998 Jun 18
6
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
handbook, halfpage
SEG13
1
40 SEG12
2
3
39
38
SEG14
SEG16
SEG17
SEG18
SEG11
SEG10
4
37 SEG9
36 SEG8
5
6
35
34
SEG19
SEG20
SEG21
SEG22
SEG7
SEG5
7
8
33 SEG4
32 SEG3
9
10
11
31
30
SEG23
SEG24
SEG2
BP3
OM4068P
SEG26 12
SEG27 13
29 BP2
28 BP1
14
15
27
26
SEG28
SEG29
SDOUT
SCE
SEG30 16
SEG31 17
25 SCLK
24 SDIN
18
19
20
23
22
21
SEG32
M1
V
M0
V
LCD
V
DD
SS
MBK815
Fig.3 Pin configuration (DIP40).
1998 Jun 18
7
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
The display configurations possible with the OM4068
depend on the number of active backplane outputs
required; a selection of display configurations is given in
Table 1.
FUNCTIONAL DESCRIPTION
The OM4068 is a low-power LCD driver designed to
interface with any microprocessor/microcontroller and a
wide variety of LCDs. It can drive any static or multiplexed
LCD containing up to three backplanes and
up to 96 segments.
A typical system (MUX 1 : 3) is shown in Fig.4.
Table 1 Selection of display configurations
NUMBER OF
DISPLAY
7-SEGMENTS NUMERIC
DOT MATRIX
INDICATOR
BACKPLANES
DIGITS
SEGMENTS
SYMBOLS
3
2
1
96
64
32
12
8
12
8
96 dots (3 × 32)
64 dots (2 × 32)
32 dots (1 × 32)
4
4
V
DD
V
V
LCD
DD
SDIN
SCLK
SCE
(1)
LCD PANEL
32 segment drivers
HOST
MICROPROCESSOR/
MICROCONTROLLER
(up to 96
elements)
OM4068
3 backplanes
MBK818
M1 M0
V
SS
SDOUT
V
SS
(1) 28 segment drivers for DIP40 package.
Fig.4 Typical system configuration.
The host microprocessor/microcontroller maintains the
3-line bus communication channel with OM4068.
The internal oscillator requires no external components.
The appropriate intermediate biasing voltage for the
multiplexed LCD waveforms are generated on-chip.
The only other connections required to complete the
system are to the power supplies (VSS, VDD and VLCD) and
suitable capacitors to decouple the VLCD and VDD pins to
VSS
.
1998 Jun 18
8
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
The bias levels depend on the multiplex rate and are
selected automatically when the display configuration is
selected using M1 and M0.
Power-on reset
The on-chip power-on reset block initializes the chip after
power-on or power failures. The OM4068 resets to a
starting condition as follows:
LCD voltage selector
• All backplane and segment outputs are set to VSS
The LCD voltage selector (control logic) coordinates the
multiplexing of the LCD in accordance with the selected
drive or display configuration. The operation of the voltage
selector is controlled by the input pins M0 and M1
(see Table 2).
(display off)
• All shift registers and latches are set in 3-state
• SDOUT (allowing serial cascading) is set to logic 0 (with
SCE LOW)
• Power-down mode.
Table 2 Drive mode selection
Data transfers on the serial bus should be avoided for
0.5 ms following power-on to allow completion of the reset
action.
M1
0
M0
0
DRIVE MODE
test mode (not user accessible)
static drive (1 : 1)
0
1
Power-down
1
0
duplex drive (1 : 2)
After power-on the chip is in power-down mode as long as
the serial clock is not active. During power-down all static
currents are switched off (no internal oscillator, no timing
and no bias level generation) and all LCD-outputs are
3-stated. The power-on reset functions remain enabled.
1
1
triplex drive (1 : 3)
For multiplex rates of 1 : 2 three bias levels are used
including VLCD and VSS. Four bias level are used for the
1 : 3 multiplex rate. The various biasing configurations
together with the biasing characteristics as functions of
The power-down mode is disabled at the first rising edge
of the serial clock SCLK.
V
OP = VLCD − VSS and the resulting discrimination ratios
(D), are given in Table 3.
LCD bias voltage generator
A practical value for VOP is determinated by equating
Voff(rms) with a defined LCD threshold voltage (Vth),
typically when the LCD exhibits approximately 10%
contrast. In static mode a suitable choice is VOP > 3Vth.
The intermediate bias voltages for the LCD display are
generated on-chip. This removes the need for an external
resistive bias chain and significantly reduces the system
power consumption. The full-scale LCD voltage VOP
equals VLCD − VSS. The optimum value of VOP depends on
the LCD threshold voltage (Vth) and the number of bias
levels.
Fractional LCD biasing voltages are obtained from an
internal voltage divider of three series resistors (1⁄3bias)
connected between VLCD and VSS. The centre resistor can
be switched out of the circuit to provide a 1⁄2bias voltage
level for the 1 : 2 multiplex configuration.
1998 Jun 18
9
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
Table 3 LCD drive modes: summary of characteristics
NUMBER OF
Voff (rms)
V on (rms)
V on (rms)
LCD DRIVE
MODE
LCD BIAS
CONFIGURATION
D =
-----------------------
VOP
----------------------
VOP
-----------------------
Voff (rms)
BACKPLANES
LEVELS
Static
1 : 2
1 : 3
1
2
3
2
3
4
static
0
1
−
1
⁄
0.354
0.333
0.791
0.638
2.2236
1.915
2
1
⁄
3
LCD drive mode waveforms
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive
waveforms for this mode are shown in Fig.5.
T
frame
V
V
V
LCD
BP1
V
SS
SEG − BP1
V
LCD
0 V
LCD
SEG N
(off)
V
SS
−V
LCD
V
LCD
0 V
LCD
SEG N + 1
(on)
V
SS
−V
LCD
MBK819
SEGMENTS
BACKPLANE
DRIVER OUTPUT
SEG N
off
SEG N + 1
BP1
on
Fig.5 Static drive mode waveforms (VOP = VLCD − VSS).
1998 Jun 18
10
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
1 : 2 MULTIPLEX DRIVE MODE
When two backplanes are provided in the LCD, the 1 : 2 multiplex mode applies, as shown in Fig.6.
T
frame
a n d b o o k , f u l l p a g e w
V
LCD
1/2V
BP1
LCD
V
SS
V
LCD
LCD
BP2
1/2V
SEG - BP1
SEG - BP2
V
SS
V
V
LCD
LCD
0 V
LCD
LCD
0 V
V
1/2V
1/2V
LCD
LCD
SEG N
1/2V
V
−1/2V
−V
−1/2V
−V
SS
LCD
LCD
LCD
LCD
V
V
LCD
LCD
0 V
LCD
LCD
0 V
V
1/2V
1/2V
LCD
LCD
1/2V
SEG N + 1
SEG N + 2
SEG N + 3
V
−1/2V
−V
−1/2V
−V
SS
LCD
LCD
LCD
LCD
V
V
LCD
LCD
0 V
LCD
LCD
0 V
V
1/2V
1/2V
LCD
LCD
1/2V
V
−1/2V
−V
−1/2V
−V
SS
LCD
LCD
LCD
LCD
V
V
LCD
LCD
0 V
LCD
LCD
0 V
V
1/2V
1/2V
LCD
LCD
1/2V
V
−1/2V
−V
−1/2V
−V
SS
LCD
LCD
LCD
LCD
T
T
frame
frame
MBK820
SEGMENTS
SEG N + 1 SEG N + 2 SEG N + 3
BACKPLANE
DRIVER OUTPUTS
SEG N
off
off
BP1
BP2
on
off
off
on
on
on
Fig.6 Waveforms for 1 : 2 multiplex drive mode (VOP = VLCD − VSS).
1 : 3 MULTIPLEX DRIVE MODE
When three backplanes are provided in the LCD, the 1 : 3 multiplex mode applies, as shown in Fig.7.
1998 Jun 18
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Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
SEG N
T
T
T
T
frame
frame
frame
frame
V
V
V
LCD
LCD
LCD
V
LCD
2/3V
2/3V
2/3V
LCD
0 V
LCD
LCD
0 V
LCD
LCD
0 V
LCD
2/3V
1/3V
LCD
LCD
SS
−2/3V
−V
−2/3V
−V
−2/3V
−V
V
LCD
LCD
LCD
LCD
LCD
LCD
V
V
V
V
LCD
2/3V
2/3V
2/3V
LCD
0 V
LCD
LCD
0 V
LCD
LCD
0 V
LCD
2/3V
1/3V
LCD
LCD
SS
SEG N + 1
SEG N + 2
SEG N + 3
SEG N + 4
SEG N + 5
SEG N + 6
SEG N + 7
−2/3V
−V
−2/3V
−V
−2/3V
−V
V
LCD
LCD
LCD
LCD
LCD
LCD
V
V
V
V
LCD
2/3V
2/3V
2/3V
LCD
0 V
LCD
LCD
0 V
LCD
LCD
0 V
LCD
2/3V
1/3V
LCD
LCD
SS
−2/3V
−V
−2/3V
−V
−2/3V
−V
V
LCD
LCD
LCD
LCD
LCD
LCD
V
V
V
V
LCD
2/3V
2/3V
2/3V
LCD
0 V
LCD
LCD
0 V
LCD
LCD
0 V
LCD
2/3V
1/3V
LCD
LCD
SS
−2/3V
−V
−2/3V
−V
−2/3V
−V
V
LCD
LCD
LCD
LCD
LCD
LCD
V
V
V
V
LCD
2/3V
2/3V
2/3V
LCD
0 V
LCD
LCD
0 V
LCD
LCD
0 V
LCD
2/3V
1/3V
LCD
LCD
SS
−2/3V
−V
−2/3V
−V
−2/3V
−V
V
LCD
LCD
LCD
LCD
LCD
LCD
V
V
V
V
LCD
2/3V
2/3V
2/3V
LCD
0 V
LCD
LCD
0 V
LCD
LCD
0 V
LCD
2/3V
1/3V
LCD
LCD
SS
−2/3V
−V
−2/3V
−V
−2/3V
−V
V
LCD
LCD
LCD
LCD
LCD
LCD
V
V
V
V
LCD
2/3V
2/3V
2/3V
LCD
0 V
LCD
LCD
0 V
LCD
LCD
0 V
LCD
2/3V
1/3V
LCD
LCD
SS
−2/3V
−V
−2/3V
−V
−2/3V
−V
V
LCD
LCD
LCD
LCD
LCD
LCD
V
V
V
V
LCD
2/3V
2/3V
2/3V
LCD
0 V
LCD
LCD
0 V
LCD
LCD
0 V
LCD
2/3V
1/3V
LCD
LCD
SS
−2/3V
−V
−2/3V
−V
−2/3V
−V
V
LCD
LCD
LCD
SEG - BP1
SEG - BP2
SEG - BP3
V
V
V
LCD
LCD
LCD
2/3V
1/3V
2/3V
1/3V
2/3V
1/3V
LCD
LCD
SS
LCD
LCD
SS
LCD
LCD
SS
V
V
V
MBK821
BP1
BP2
BP3
SEGMENTS
BACKPLANE
DRIVER OUTPUTS
N
N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7
BP1
BP2
BP3
off
off
off
on
off
off
off
on
off
on
on
off
off
off
on
on
off
on
off
on
on
on
on
on
Fig.7 Waveforms for 1 : 3 multiplex drive motive (VOP = VLCD − VSS).
1998 Jun 18
12
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
Oscillator
Interface to microprocessor unit: serial interface
The internal logic and the multi-level LCD drive signals of
the OM4068 are generated by the built-in RC oscillator.
No external components are required.
A three-line bus structure enables serial unidirectional
data transfer with microprocessors/microcontrollers.
The three lines are a serial data input line (SDIN), a serial
clock line (SCLK) and a data line enable (SCE). All inputs
are CMOS compatible. These lines must always be in a
defined state VSS or VDD.Floating inputs could damage the
chip.
In order to minimize radio frequency interference, the
oscillator operates with symmetrical and slew-rate limited
capacitor charge/discharge.
The oscillator runs continuously once the power down
state after power-on has been left.
On the bus, one data bit is transferred during each clock
pulse. The data on the SDIN line remains stable during the
whole clock period. Data changes arrive with the falling
edge of the serial clock SCLK (see Fig.8).
SDIN
SDOUT
SCLK
data line
stable;
data valid
change
of data
allowed
MBK822
Fig.8 Bit transfer on bus.
numbers and the LCD display segments is shown in
Table 4.
Shift register
Data present on the SDIN pin is shifted into a shift register
with the rising edge of the serial clock SCLK in a
synchronous manner. The shift register serves to transfer
display information from the serial bus to the (display) latch
while previous data is displayed.
Data from the last stage of the register is supplied to the
SDOUT pin to allow serial cascading of the OM4068 with
other peripheral devices. Depending on the display driving
mode selected, SDOUT corresponds to bit 32, 64 or 96 of
the register (see Fig.10). Data on the SDOUT pin is shifted
out with the falling edge of the SCLK clock. SDOUT is
therefore delayed by 1⁄2SCLK cycle before it is applied to
the SDIN pin of the next IC in the serial chain (see Fig.8).
The shift register is organized as three 32-bit shift
registers. Depending on the display driving mode selected
(see Table 3), one, two or three registers are used and
cascaded resulting in a shift register length of 32, 64 or
96 bits. Figure 9 shows the shift register organization with
the display data bits after a shift operation is completed.
The shift sequence begins with data bit D32 and finishes
with data bit D1. The correspondence between the data bit
The clock enable SCE signal must be HIGH in order to
enable the shift operation. SDOUT output is latched with
the last data after SCE returned to HIGH (shift operation
terminated).
SDOUT is in 3-state mode when SCE is LOW.
1998 Jun 18
13
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
Display latch
Timing
The 96-bit display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch and the LCD segment outputs. An LCD segment is
activated when the corresponding data bit in the display
latch is HIGH.
The timing of the OM4068 organizes the internal data flow
of the device. This includes the transfer of display data
from the shift register to the display segments outputs.
The timing also generates the LCD frame frequency which
is derived from the clock frequency generated in the
internal clock generator:
fosc
Display latches are in HOLD mode (SCE HIGH) during the
shift operation to maintain the display data constant.
ffr(LCD)
=
------------
2400
Data are latched into the display latch with the internal
frame clock. Thus there is a delay of up to one half frame
before new data are latched after signal SCE returns to
zero.
Shift register configuration
1
32
64
96
96-bit shift register
32-bit register
SDIN
SDIN
SDIN
SDOUT
D1A
D1A
D1A
D32A
driving mode: static; (M1, M0) = 01
32-bit register
32-bit register
SDOUT
D32A D1B
D32B
driving mode: duplex (1 : 2); (M1, M0) = 10
32-bit register
32-bit register
32-bit register
SDOUT
D32A D1B
D32B D1C
D32C
MBK823
driving mode: triplex (1 : 3); (M1, M0) = 11
Fig.9 Display data bit position in shift register.
1998 Jun 18
14
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
SDIN
D32A
D32B
MUX
D32C
M0
M1
SCLK
MBK825
SDOUT
Fig.10 Shift register structure.
1998 Jun 18
15
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
Table 4 Relationships between data bit numbers and the LCD segment outputs
DRIVING MODE
SEGMENT
NUMBER
STATIC
DUPLEX
TRIPLEX
SEG1
SEG2
D1A
D2A
D1A
D2A
D1B
D2B
D1A
D2A
D1B
D2B
D1C
D2C
SEG3
D3A
D3A
D3B
D3A
D3B
D3C
SEG4
D4A
D4A
D4B
D4A
D4B
D4C
SEG5
D5A
D5A
D5B
D5A
D5B
D5C
SEG6
D6A
D6A
D6B
D6A
D6B
D6C
SEG7
D7A
D7A
D7B
D7A
D7B
D7C
SEG8
D8A
D8A
D8B
D8A
D8B
D8C
SEG9
D9A
D9A
D9B
D9A
D9B
D9C
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
D10A
D11A
D12A
D13A
D14A
D15A
D16A
D17A
D18A
D19A
D20A
D21A
D22A
D23A
D24A
D25A
D26A
D27A
D28A
D29A
D30A
D31A
D32A
D10A
D11A
D12A
D13A
D14A
D15A
D16A
D17A
D18A
D19A
D20A
D21A
D22A
D23A
D24A
D25A
D26A
D27A
D28A
D29A
D30A
D31A
D32A
D10B
D11B
D12B
D13B
D14B
D15B
D16B
D17B
D18B
D19B
D20B
D21B
D22B
D23B
D24B
D25B
D26B
D27B
D28B
D29B
D30B
D31B
D32B
D10A
D11A
D12A
D13A
D14A
D15A
D16A
D17A
D18A
D19A
D20A
D21A
D22A
D23A
D24A
D25A
D26A
D27A
D28A
D29A
D30A
D31A
D32A
D10B
D11B
D12B
D13B
D14B
D15B
D16B
D17B
D18B
D19B
D20B
D21B
D22B
D23B
D24B
D25B
D26B
D27B
D28B
D29B
D30B
D31B
D32B
D10C
D11C
D12C
D13C
D14C
D15C
D16C
D17C
D18C
D19C
D20C
D21C
D22C
D23C
D24C
D25C
D26C
D27C
D28C
D29C
D30C
D31C
D32C
Segment outputs
The LCD drive section includes 32 segment outputs SEG1 to SEG32 which should be connected directly to the LCD.
The segment output signals are generated in accordance with the multiplex backplane signals and with data in the
display latch. When less than 32 segments are required the unused segment outputs should be left open-circuit.
1998 Jun 18
16
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
Backplane outputs
The LCD drive section includes three backplane outputs (BP1 to BP3) which should be connected directly to the LCD.
The backplane output signals are generated in accordance with the selected LCD drive mode. If less than three
backplane outputs are required the unused outputs should be left open-circuit. In 1 : 2 multiplex drive mode, BP3 is set
to 1⁄2VLCD. In static drive mode BP3 and BP2 are set to VSS
.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
supply voltage
CONDITIONS
MIN.
MAX.
+6.5
UNIT
VDD
−0.5
−0.5
−0.5
−0.5
V
VLCD
VI
LCD supply voltage
+7.5
V
V
V
input voltage (any input)
VDD + 0.5
VLCD + 0.5
VO
output voltage
(BP1, BP2, BP3, S1 to S32 and VLCD
)
II
DC input current
−10
−10
−50
−
+10
mA
mA
mA
mW
mW
°C
IO
DC output current
+10
IDD, ISS, ILCD
VDD, VSS or VLCD current
total power dissipation per package
power dissipation per output
operating ambient temperature
storage temperature
+50
Ptot(pack)
P/out
Tamb
Tstg
500
−
10
−40
−65
−
+105
+150
150
°C
Tj
junction temperature
°C
Ves
electrostatic handling
note 1
note 2
−2000
−150
+2000
+150
V
V
Notes
1. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor (human body model).
2. Equivalent to discharging a 200 pF capacitor via a 0.75 µH series inductor (machine model).
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).
1998 Jun 18
17
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
DC CHARACTERISTICS
VDD = 2.5 to 5.5 V; VSS = 0 V; VLCD = 3.5 to 6.5 V; Tamb = −40 to +105 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
VLCD
IDD
supply voltage
VSS + 2.5
VSS + 3.5
−
−
5.5
V
LCD supply voltage
supply current
−
6.5
10
V
power-down state;
note 1
4
µA
normal mode;
fosc = intern;
notes 2 and 3
−
12
25
µA
ILCD
VLCD current
power-down state;
note 1
−
−
−
−
1.5
40
µA
µA
normal mode;
f
osc = intern;
notes 3 and 4
VPOR
power-on reset voltage level
note 5
0.8
1.25
1.6
V
Logic
VIL
LOW-level input voltage
VSS
−
−
−
−
0.3VDD
VDD
−
V
VIH
HIGH-level input voltage
0.7VDD
V
IOL
LOW-level output current (SDOUT)
VOL = 0.5 V; VDD = 5 V 1.0
mA
mA
IOH
HIGH-level output current (SDOUT) VOH = VDD − 0.5 V;
−
−1
VDD = 5 V
Ipu
IL
pull-up current M1 and M0
leakage current
VI = VSS
0.04
0.15
1
µA
µA
VI = VDD or VSS
−1
−
+1
Segment and backplane outputs
R(o)seg
segment output resistance
SEG1 to SEG32
note 6
note 6
−
−
15
15
40
40
kΩ
kΩ
R(o)back
backplane output resistance
BP1 to BP3
Vseg(bias)(tol) bias tolerance SEG1 to SEG32
Vback(bias)(tol) bias tolerance BP1, BP2 and BP3
note 7
note 7
−100
−100
0
0
+100
+100
mV
mV
Notes
1. Power-down state. After power-on the chip is in power-down state as long as the serial clock is not activated. During
power-down all static currents are switched off except the power-on reset block.
2. Output SDOUT is open-circuit; inputs at VDD or VSS; bus inactive.
3. Drive mode: static, duplex and triplex.
4. LCD outputs are open-circuit, CL = 50 pF typical, inputs at VDD or VSS; bus inactive.
5. Resets all logic when VDD < VPOR
.
6. Resistance of output terminal (S1 to S32 and BP1, BP2 and BP3) with a load current of 20 µA; outputs measured
one at a time.
7. LCD outputs open-circuits.
1998 Jun 18
18
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
AC CHARACTERISTICS
VDD = 2.5 to 5.5 V; VSS = 0 V; VLCD = 5.0 V; Tamb = −40 to +105 °C; unless otherwise specified.
SYMBOL
ffr(LCD)
fosc
PARAMETER
MIN.
50
TYP.
84
MAX.
175
UNIT
Hz
LCD frame frequency (internal clock)
oscillator frequency (not available at any pin)
116
224
405
kHz
Bus timing characteristics: serial bus interface; note 1
fSCLK
tSCLKL
tSCLKH
tsu(D)
th(D)
tr
SCLK clock frequency
SCLK clock LOW period
SCLK clock HIGH period
data set-up time
0
−
2.1
−
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
190
190
100
100
−
−
−
−
−
−
data hold time
−
−
SCLK, SDIN rise time
SCLK, SDIN fall time
10
10
−
−
tf
−
−
tsu(en)(SDEH-SCLKH) enable set-up time (SDE HIGH to SCLK HIGH)
tsu(dis)(SCLKL-SDEL) disable set-up time (SCLK LOW to SDE LOW)
250
250
100
−
−
−
tPHL(SDOUT)
SDOUT HIGH-to-LOW propagation delay
−
−
Note
1. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD
.
SDOUT
t
t
t
t
f
SCLKH
SCLKL
r
t
PHL(SDOUT)
SCLK
SDIN
t
t
h(D)
su(D)
t
t
su(en)(SDEH-SCLKH)
su(dis)(SCLKL-SDEL)
SCE
MBK824
Fig.11 Serial data timing.
1998 Jun 18
19
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
BONDING PAD LOCATIONS
1
44 43 42 41 40 39 38 37 36 35
34
SEG31
SEG32
2
3
33
32
SEG18
SEG17
31
30
29
28
27
26
25
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
V
4
5
LCD
2.01
mm
OM4068
V
DD
V
6
7
SS
M0
M1
8
24
23
SEG9
SEG8
SDIN
SCLK
9
10
11
12
13 14 15 16 17 18 19 20 21 22
x
0
0
y
2.03 mm
MBK816
Dimensions in mm.
Bonding pad dimensions: 80 × 80 µm.
Fig.12 Bonding pad locations.
20
1998 Jun 18
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
Table 5 Bonding pad locations (dimensions in µm).
All x/y coordinates are referenced to bottom left
corner of chip (see Fig.12).
SYMBOL
SEG28
SEG29
SEG30
SEG31
SEG32
VLCD
PAD
43
44
1
x
y
SYMBOL
VDD
PAD
x
y
550.550
430.550
300.550
43.100
43.100
43.100
1711.100
1711.100
1711.100
1460.050
1274.950
1158.700
5
43.100
970.500
791.850
661.750
531.750
401.750
271.750
43.100
VSS
6
42.900
M0
7
43.100
2
M1
8
43.100
3
SDIN
9
43.100
4
SCLK
SCE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43.100
310.450
447.350
604.800
714.850
824.850
924.850
1024.850
1124.850
1224.850
1327.250
1432.450
1532.650
1783.600
1783.600
1783.600
1783.600
1783.600
1783.600
1783.600
1783.600
1783.600
1783.600
1783.600
1514.600
1370.550
1270.500
1170.500
1070.500
970.550
870.550
770.550
660.550
Alignment marks
SDOUT
BP1
43.100
C1
C2
F
−
−
−
1769.6
1770.1
172.0
1696.9
58.4
43.100
BP2
43.100
1705.2
BP3
43.100
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
43.100
43.100
43.100
43.100
43.100
43.100
43.100
293.850
458.850
603.850
703.850
803.850
903.850
1003.850
1103.850
1203.850
1323.850
1453.850
1711.100
1711.100
1711.100
1711.100
1711.100
1711.100
1711.100
1711.100
1711.100
1998 Jun 18
21
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
PACKAGE OUTLINES
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
y
X
A
33
23
34
22
Z
E
e
H
E
E
A
2
A
(A )
3
A
1
w M
θ
b
p
L
p
pin 1 index
L
12
44
detail X
1
11
w M
Z
v
M
A
D
b
p
e
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
10o
0o
0.25 1.85
0.05 1.65
0.40 0.25 10.1 10.1
0.20 0.14 9.9 9.9
12.9 12.9
12.3 12.3
0.95
0.55
1.2
0.8
1.2
0.8
mm
2.10
0.25
0.8
1.3
0.15 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-08-01
SOT307-2
1998 Jun 18
22
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
D
M
E
A
2
A
L
A
1
c
e
w M
Z
b
1
(e )
1
b
M
H
40
21
pin 1 index
E
1
20
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
1
1
E
H
max.
min.
max.
max.
1.70
1.14
0.53
0.38
0.36
0.23
52.50
51.50
14.1
13.7
3.60
3.05
15.80
15.24
17.42
15.90
4.7
0.51
4.0
2.54
0.10
15.24
0.60
0.254
0.01
2.25
0.067
0.045
0.021
0.015
0.014
0.009
2.067
2.028
0.56
0.54
0.14
0.12
0.62
0.60
0.69
0.63
inches
0.19
0.020
0.16
0.089
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-14
SOT129-1
051G08
MO-015AJ
1998 Jun 18
23
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For details,
refer to the Drypack information in the “Data Handbook
IC26; Integrated Circuit Packages; Section: Packing
Methods”.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
DIP
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
WAVE SOLDERING
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
CAUTION
Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.
REPAIRING SOLDERED JOINTS
If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
QFP
REFLOW SOLDERING
Reflow soldering techniques are suitable for all QFP
packages.
1998 Jun 18
24
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Jun 18
25
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
NOTES
1998 Jun 18
26
Philips Semiconductors
Product specification
OM4068
LCD driver for low multiplex rates
NOTES
1998 Jun 18
27
Philips Semiconductors – a worldwide company
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Middle East: see Italy
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Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
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Colombia: see South America
Czech Republic: see Austria
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
Slovakia: see Austria
Slovenia: see Italy
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Spain: Balmes 22, 08007 BARCELONA,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Tel. +1 800 234 7381
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
415106/1200/01/pp28
Date of release: 1998 Jun 18
Document order number: 9397 750 03802
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