OQ2536HP [NXP]
SDH/SONET STM16/OC48 demultiplexer; SDH / SONET STM16 / OC48解复用器
| 型号： | OQ2536HP |
| 厂家： | 
NXP |
| 描述： | SDH/SONET STM16/OC48 demultiplexer |
| 文件： | 总20页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
OQ2536HP
SDH/SONET STM16/OC48
demultiplexer
1998 Mar 10
Product specification
File under Integrated Circuits, IC19
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
FEATURES
DESCRIPTION
• Normal and loop (test) modes
The OQ2536HP is a 32-channel demultiplexer intended
for use in STM16/OC48 applications. It demultiplexes a
single 2.5 Gbits/s input channel to 32 × 78 Mbits/s output
channels. The data and clock outputs on the low speed
interface are GTL compatible, while the high speed data
and clock inputs are CML compatible.
• 1.2 V GTL (Gunning Transceiver Logic) level compatible
data and clock outputs (low speed interface)
• Differential CML (Current-Mode Logic) data and clock
inputs
• High input sensitivity (100 mV for the high speed inputs)
• Boundary Scan Test (BST) at low speed interface, in
accordance with “IEEE Std 1149.1-1990”
• Low power dissipation (typically 1.45 W).
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
OQ2536HP
HLQFP100 plastic heat-dissipating low profile quad flat package; 100 leads; body
SOT470-1
14 × 14 × 1.4 mm
BLOCK DIAGRAM
54
DIN
2.5 Gbits/s
78
Mbits/s
622
Mbits/s
53
DINQ
(1)
75
D0
to
D31
4 ×
1 : 8 DMUX
1 : 4 DMUX
56
57
4
CIN
CINQ
ENL
68
69
70
72
71
TRST
TMS
TCK
TDI
OQ2536HP
65
66
DLOOP
TDO
DLOOPQ
622 MHz
78 MHz
12
CDIV
DIVIDE BY 4
DIVIDE BY 8
60
59
CLOOP
2.5 GHz
CLOOPQ
32
31
DIOA
DIOC
BAND GAP
REFERENCE 2
BAND GAP
REFERENCE 1
13, 14, 36,
26, 27, 28, 37, 63, 85,
(2)
11, 38, 39,
62, 88
74
34
51
73
76, 77
86
29
GND
5
7
5
V
V
V
V
BGCAP2
BGCAP1 REFC
MGK346
DD
CC2
EE
CC1
(1) See Chapter “Pinning” for D0 to D31 pin numbers.
(2) Pins 1, 8, 17, 22, 25, 29, 33, 35, 40 to 50, 52, 55, 58, 61, 64, 67, 78, 82, 91 and 96.
Fig.1 Block diagram.
1998 Mar 10
2
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
PINNING
SYMBOL
PIN
TYPE(1)
DESCRIPTION
GND
D29
D25
D21
D17
D13
D9
1
S
O
O
O
O
O
O
S
O
O
S
O
S
S
O
O
S
O
O
O
O
S
O
O
S
I
ground
2
78 Mbits/s data output channel for D29
78 Mbits/s data output channel for D25
78 Mbits/s data output channel for D21
78 Mbits/s data output channel for D17
78 Mbits/s data output channel for D13
78 Mbits/s data output channel for D9
ground
3
4
5
6
7
GND
D5
8
9
78 Mbits/s data output channel for D5
78 Mbits/s data output channel for D1
supply voltage (−4.5 V)
D1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VEE
CDIV
VCC2
VCC2
D28
D24
GND
D20
D16
D12
D8
78 MHz clock output
supply voltage (+1.5 V)
supply voltage (+1.5 V)
78 Mbits/s data output channel for D28
78 Mbits/s data output channel for D24
ground
78 Mbits/s data output channel for D20
78 Mbits/s data output channel for D16
78 Mbits/s data output channel for D12
78 Mbits/s data output channel for D8
ground
GND
D4
78 Mbits/s data output channel for D4
78 Mbits/s data output channel for D0
ground
D0
GND
VDD
supply voltage (+3.3 V)
VDD
I
supply voltage (+3.3 V)
VDD
I
supply voltage (+3.3 V)
GND
i.c.
S
−
ground
internally connected, to be left open-circuit
cathode of temperature diode array
anode of temperature diode array
ground
DIOC
DIOA
GND
BGCAP2
GND
VCC2
VCC2
VEE
A
A
S
A
S
S
S
S
S
S
pin for connecting external band gap decoupling capacitor (4 × 1 : 8 DMUX)
ground
supply voltage (+1.5 V)
supply voltage (+1.5 V)
supply voltage (−4.5 V)
supply voltage (−4.5 V)
ground
VEE
GND
1998 Mar 10
3
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
SYMBOL
PIN
TYPE(1)
DESCRIPTION
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
BGCAP1
GND
DINQ
DIN
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
S
S
S
S
S
S
S
S
S
S
A
S
I
ground
ground
ground
ground
ground
ground
ground
ground
ground
ground
pin for connecting external band gap decoupling capacitor (1 : 4 DMUX)
ground
inverted data input in normal mode
data input in normal mode
I
GND
CIN
S
I
ground
clock input in normal mode
CINQ
GND
CLOOPQ
CLOOP
GND
VEE
I
inverted clock input in normal mode
ground
S
I
inverted clock input from multiplexer IC OQ2535 (loop mode)
clock input from multiplexer IC OQ2535 (loop mode)
ground
I
S
S
S
S
I
supply voltage (−4.5 V)
VCC2
supply voltage (+1.5 V)
GND
DLOOP
DLOOPQ
GND
TRST
TMS
ground
data input from multiplexer IC OQ2535 (loop mode)
inverted data input from multiplexer IC OQ2535 (loop mode)
ground
I
S
I
test RESET input for BST mode (active LOW)
test mode select input for BST
test clock input for BST mode
serial test data output for BST mode
serial test data input for BST mode
I
TCK
I
TDO
O
I
TDI
REFC
A
pin for connecting external reference decoupling capacitor (for standard TTL
reference)
VCC1
ENL
VDD
74
75
76
77
78
79
80
S
I
supply voltage (+5.0 V)
loop mode enable input (active LOW)
supply voltage (+3.3 V)
I
VDD
I
supply voltage (+3.3 V)
GND
D31
D27
S
O
O
ground
78 Mbits/s data output channel for D31
78 Mbits/s data output channel for D27
1998 Mar 10
4
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
SYMBOL
PIN
TYPE(1)
DESCRIPTION
78 Mbits/s data output channel for D23
D23
GND
D19
D15
VCC2
VCC2
D11
VEE
D7
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
O
S
ground
O
O
S
78 Mbits/s data output channel for D19
78 Mbits/s data output channel for D15
supply voltage (+1.5 V)
S
supply voltage (+1.5 V)
O
S
78 Mbits/s data output channel for D11
supply voltage (−4.5 V)
O
O
S
78 Mbits/s data output channel for D7
78 Mbits/s data output channel for D3
ground
D3
GND
D30
D26
D22
D18
GND
D14
D10
D6
O
O
O
O
S
78 Mbits/s data output channel for D30
78 Mbits/s data output channel for D26
78 Mbits/s data output channel for D22
78 Mbits/s data output channel for D18
ground
O
O
O
O
78 Mbits/s data output channel for D14
78 Mbits/s data output channel for D10
78 Mbits/s data output channel for D6
78 Mbits/s data output channel for D2
D2
Note
1. Pin type abbreviations: O = Output, I = Input, S = power Supply, A = Analog function.
1998 Mar 10
5
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
GND
D29
D25
D21
D17
D13
D9
1
2
75 ENL
V
74
73
CC1
3
REFC
4
72 TDI
5
71 TDO
6
TCK
TMS
70
69
68
7
GND
D5
8
TRST
9
67 GND
D1
10
11
12
13
14
15
DLOOPQ
66
65
V
DLOOP
EE
CDIV
64 GND
OQ2536HP
V
V
V
63
62
61
CC2
CC2
EE
V
CC2
D28
GND
D24 16
GND 17
60 CLOOP
59 CLOOPQ
D20
D16
D12
18
19
20
GND
58
57
CINQ
56 CIN
D8 21
GND 22
D4 23
55 GND
DIN
54
53
DINQ
D0 24
52 GND
GND 25
51 BGCAP1
MGK345
Fig.2 Pin configuration.
6
1998 Mar 10
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
IC. If multiple decoupling capacitors are used for a single
supply node, large distance between the capacitances
should be avoided in order to avoid resonance.
FUNCTIONAL DESCRIPTION
The OQ2536HP is a 32-channel demultiplexer, intended
for use in STM16/OC48 applications. It demultiplexes a
single 2.5 Gbits/s input channel to 32 × 78 Mbits/s output
channels.
To minimize low frequency switching noise in the vicinity of
the OQ2536HP, all power supply lines should be filtered
once by an LC-circuit with a low cutoff frequency
(as shown in the application diagram, Fig.7).
The demultiplexing is performed in two stages.
The 2.5 Gbits/s data channel is first demultiplexed to four
622 Mbits/s data channels. Each of these channels is then
fed to a 1 : 8 demultiplexer to generate 32 × 78 Mbits/s
output channels.
Ground connection
The ground connection on the PCB needs to be a large
copper area fill connected to a common ground plane with
low inductance.
The ENL control input is used for switching between
normal and loop modes. When loop mode is enabled
(ENL = LOW), inputs DLOOP, DLOOPQ, CLOOP and
CLOOPQ are selected. In normal mode (ENL = HIGH),
inputs DIN, DINQ, CIN and CINQ are selected.
RF connections
A coupled stripline or microstrip with an odd mode
characteristic impedance of 50 Ω (nominal value) should
be used for the RF connections on the PCB.
The connections should be kept as short as possible. This
applies to the CML differential line pairs CIN and CINQ,
DIN and DINQ, CLOOP and CLOOPQ, and DLOOP and
DLOOPQ. In addition, the following lines should not vary in
length by more than 5 mm:
The signal applied to CIN and CINQ is a 2.5 GHz
recovered clock signal, e.g. coming from the OQ2541 data
and clock recovery IC. The clock is divided down to
78 MHz, which is used for receive logic timing and is
available as a GTL compatible output at pin CDIV.
High bit rate stage: 1 : 4 DMUX
• CIN, CINQ, DIN and DINQ
The 2.5 Gbits/s data stream is fed into a 1 : 4
demultiplexer to generate four 622 Mbits/s channels.
• DLOOP, DLOOPQ, CLOOP and CLOOPQ.
The input pins DIN, DINQ, DLOOP, DLOOPQ, CIN, CINQ,
CLOOP and CLOOPQ are terminated internally with 50 Ω
resistors to GND.
Interface to receive logic
The 78 Mbits/s interface lines, CDIV and D0 to D31,
should not exceed 50 mm in length. The parasitic
capacitance of these lines should be as small as possible
(less than 3 pF is desirable).
Low bit rate part: 4 × 1 : 8 DMUX
The four 622 Mbits/s output channels coming from the
high bit rate stage are loaded into four 8-bit shift registers.
The 622 MHz clock for these shift registers comes from the
preceding stage.
ESD protection
All pads are protected by ESD protection diodes, with the
exception of the high frequency inputs DIN, DINQ,
DLOOP, DLOOPQ, CIN, CINQ, CLOOP and CLOOPQ.
The 32 bits contained in the shift registers are loaded into
latches and made available on outputs D0 to D31. These
outputs are 1.2 V GTL compatible and have internal 100 Ω
pull up resistors. The 78 MHz clock output, CDIV, has an
internal 50 Ω pull up resistor.
Cooling
In many cases it is necessary to mount a special cooling
device on the package. The thermal resistance from
The first serial data bit coming in at DIN or DLOOP is given
out at pin D31 (MSB) and so on.
junction to case, Rth j-c and from junction to ambient, Rth j-a
are given in Chapter “Thermal characteristics”. Since the
heat-slug in the package is connected to the die, the
cooling device should be electrically isolated.
,
The data outputs may not always represent four STM
bytes. This is because the internal load pulse for the output
latches is not synchronized to the STM16 frame.
To calculate if a heatsink is necessary, the maximum
allowed total thermal resistance R is calculated as:
Power supply connections
Tj – Tamb
Rth
=
(1)
-----------------------
The power supply pins need to be individually decoupled
using chip capacitors mounted as close as possible to the
Ptot
1998 Mar 10
7
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
where:
Rth = total thermal resistance from junction to ambient
If for instance Rth c-h = 0.5 K/W and Rth j -a = 33 K/W then:
1
1
Rthh – a
≤
–
–1 – 3.1 ≤ 17.0
[K ⁄ W]
(5)
----------- ------
12.5 33
in the application
Tj = junction temperature
Tamb = ambient temperature.
Built in temperature sensor
Three series-connected diodes have been integrated for
measuring junction temperature. The diode array,
accessed by means of the DIOA (anode) and DIOC
(cathode) pins, has a temperature dependency of
approximately −6 mV/°C. With a diode current of 1 mA,
the voltage will be somewhere in the range 1.7 to 2.5 V,
depending on temperature.
As long as Rth is greater than Rth j-a of the OQ2536HP
including environmental conditions like air flow and board
layout, no heatsink is necessary. For example if
Tj = 120 °C, Tamb = 70 °C and Ptot = 1.45 W, then:
(120 – 70)
Rth
=
= 34.4
[K ⁄ W]
(2)
----------------------------
1.45
which is more than the worst case Rth j-a = 33 K/W, so no
heatsink is necessary.
Boundary Scan Test (BST) interface
Boundary scan test logic has been implemented for all
digital inputs and outputs on the low frequency interface, in
accordance with “IEEE Std 1149.1-1990”. All scan tests
other than SAMPLE mode are available. The boundary
scan test logic consists of a TAP controller, a BYPASS
register, a 2-bit instruction register, a 32-bit identification
register and a 36-bit boundary scan register (the last two
are combined). The architecture of the TAP controller and
the BYPASS register is in accordance with IEEE
recommendations.
Another example; if for safety reasons Tj should stay as
low as 110 °C, while Tamb = 85 °C and Ptot = 2 W, then:
(110 – 85)
Rth
=
= 12.5
[K ⁄ W]
(3)
----------------------------
2.0
In this case extra cooling is needed. The thermal
resistance of the heatsink is calculated as follows:
1
1
Rthh – a
≤
–
–1 – Rthj – c – Rthc – h
(4)
-------- ----------------
Rth R thj – a
The four command modes, selected be means of the
instruction register, are: EXTEST (00), PRELOAD (01),
IDCODE (10) and BYPASS (11).
All boundary scan test inputs, TDI, TMS, TCK and TRST,
have internal pull up resistors. The maximum test clock
frequency at TCK is 12 MHz.
where:
Rth h-a = thermal resistance from heatsink to ambient
Rth c-h = thermal resistance from case to heatsink
Rth j-c = thermal resistance from junction to case,
see Chapter “Thermal characteristics”.
Table 1 BST identifier code
VERSION
OQ
2536 (BINARY)
00 1001 1110 1000
PHILIPS SEMICONDUCTORS
LSB(1)
0001
01
0000 0011 101(2)
1
Notes
1. LSB is shifted out first on the TDO pin.
2. The manufacturer’s code was implemented incorrectly. It should have been 0000 0010 101.
1998 Mar 10
8
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
Table 2 BST bit order
BIT NUMBER
SYMBOL
D31
PIN
33 (MSB)
79
80
81
83
84
87
89
90
92
93
94
95
97
98
99
100
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
D27
D23
D19
D15
D11
D7
D3
D30
D26
D22
D18
D14
D10
D6
D2
D29
D25
D21
D17
D13
D9
3
4
5
6
7
D5
9
D1
10
12
15
16
18
19
20
21
23
24
75
CDIV
D28
D24
D20
D16
D12
D8
8
7
6
5
4
3
2
D4
1
D0
0 (LSB)(1)
ENL
Note
1. LSB is shifted out first on the TDO pin.
1998 Mar 10
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Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
−0.5
MAX.
+6.0
UNIT
VCC1
VEE
VDD
VCC2
Vn
supply voltage
supply voltage
supply voltage
supply voltage
DC voltage
V
V
V
V
−6.0
−0.5
−0.5
+0.5
+5.0
+2.0
pins 2 to 7, 9, 10, 15, 16, 18 to 21, 23, 24, 79, 80, 81, 83, 84, 87, 89, 0.0
90, 92 to 95 and 97 to 100
2.0
V
pins 53, 54, 56, 57, 59, 60, 65 and 66
pins 68, 69, 70, 72, 73 and 75
pins 30, 34 and 51
−1.0
−0.5
+0.5
V
V
V
V
VCC1 + 0.5
VEE − 0.5 0.5
pins 31and 32
VEE − 0.5 VCC1 + 0.5
In
DC current
pins 2 to 7, 9, 10, 15, 16, 18 to 21, 23, 24, 79, 80, 81, 83, 84, 87, 89,
90, 92 to 95, and 97 to 100
−
15
mA
pin 12
−
−
−
−
−
30
mA
mA
mA
W
pins 31 and 32
pin 71
10
50
Ptot
Tj
total power dissipation
junction temperature
storage temperature
2.6
120
°C
Tstg
−65
+150
°C
THERMAL CHARACTERISTICS
SYMBOL
Rth j-c
PARAMETER
CONDITIONS
VALUE
UNIT
thermal resistance from junction to case
2.6
K/W
Rth j-a
thermal resistance from junction to
ambient
see note 1
airflow = 0 ft/min
33
28
25
22
20
K/W
K/W
K/W
K/W
K/W
airflow = 100 ft/min
airflow = 200 ft/min
airflow = 400 ft/min
airflow = 600 ft/min
Note
1. The thermal resistance from junction to ambient is strongly depending on the board design and airflow. The values
given in the table are typical values and are measured on a single sided test board with dimensions of
76 × 114 × 1.6 mm. Better values can be obtained when mounted on multilayer boards with large ground planes.
1998 Mar 10
10
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
DC CHARACTERISTICS
Typical values at Tamb = 25 °C and at typical supply voltages; minimum and maximum values are valid over the entire
ambient temperature range and supply voltage range.
SYMBOL
General
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
VCC1
VEE
VDD
VCC2
ICC1
IEE
supply voltage
supply voltage
supply voltage
supply voltage
supply current
supply current
supply current
supply current
4.75
5.0
5.25
−4.25
3.47
1.6
V
−4.75 −4.5
V
3.14
1.1
−
3.3
1.5
14
V
V
22
mA
mA
mA
mA
W
−
170
100
190
1.45
−
215
185
525
2.6
IDD
−
ICC2
Ptot
note 1
note 1
−
total power dissipation
junction temperature
ambient temperature
−
Tj
−
+120 °C
Tamb
−40
−
+85
°C
TTL input: ENL
VIL
VIH
IIL
LOW-level input voltage
−
−
−
−
−
0.8
−
V
HIGH-level input voltage
LOW-level input current
HIGH-level input current
2.0
−90
-
V
-
µA
µA
IIH
210
TTL inputs: TDI, TCK, TMS and TRST; note 2
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
−
−
−
0.4
V
V
2.0
−
CML inputs: CIN, CINQ, DIN, DINQ, CLOOP, CLOOPQ, DLOOP and DLOOPQ; note 3
Vi(p-p)
VIO
input voltage (peak-to-peak value)
permitted input offset voltage
input voltages
50 Ω measurement 100
250
−
500
+25
mV
mV
system
−25
VI,IQ
Zi
−600
−
+250 mV
single ended input impedance
for DC signal
IOL = 4 mA
−
−
50
−
Ω
TTL output: TDO; note 4
VOL
LOW-level output voltage
0.3
0.5
V
1998 Mar 10
11
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
SYMBOL
VOH
IOZ
Outputs: CDIV and D0 to D31; notes 5 and 6
PARAMETER
HIGH-level output voltage
output current in high impedance state
CONDITIONS
MIN.
2.4
TYP. MAX. UNIT
IOH = −400 µA
4.0
−
V
−
−
1
µA
VOL
VOH
LOW-level output voltage
Open outputs
II(d) = 1 mA
-
0.3
1.5
0.4
1.6
V
V
HIGH-level output voltage; note 7
1.1
Temperature diode array
∆VDIOA-DIOC diode voltage range(8)
−
2.1
−
V
Notes
1. Maximum current ICC2 and maximum power dissipation Ptot are worst case figures i.e. data outputs D0 to D31 remain
in LOW state.
2. TDI, TCK, TMS and TRST are connected via 90 kΩ to VDD
3. See Fig.3 for symbol definitions.
.
4. TDO is switched to high impedance state if BST is inactive.
5. Output CDIV has an internal pull-up resistor of 50 Ω to VCC2. Outputs D0 to D31 have internal pull-up resistors of
100 Ω to VCC2
6. The first serial data bit coming in at DIN or DLOOP is given out at D31 (MSB) and so on.
7. The HIGH-level output voltage depends on the supply voltage VCC2
.
.
8. The temperature diode array can be used to measure the temperature of the die. The temperature dependency of
this voltage is approximately −6 mV/K.
CML INPUT
CML OUTPUT
V
I(max)
GND
GND
V
O(max)
V
V
IQH
OQH
V
V
OH
IH
V
V
i (p-p)
o (p-p)
V
V
V
IQL
V
OQL
OO
IO
V
V
OL
IL
V
V
O(min)
I(min)
MGK144
Fig.3 Logic level symbol definitions for CML.
1998 Mar 10
12
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
TIMING
Typical values at Tamb = 25 °C and at typical supply voltages; minimum and maximum values are valid over the entire
ambient temperature range and supply voltage range.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
CML input timing; note 1; Fig.5
fclk(CIN)
tsu
input clock frequency
input data set-up time
input data hold time
clock slew rate
2.488
140
80
−
−
−
−
−
−
−
−
GHz
ps
th
ps
SRCIN
1
V/ns
TTL output timing; note 2; Fig.6
fclk(CDIV)
δCDIV
tr(CDIV)
tf(CDIV)
output clock frequency
output clock duty factor
output clock rise time
output clock fall time
fclk(CDIV) = 2.488 GHz
−
-
77.76
−
MHz
%
50
−
-
Measured between
10% and 90% levels
of full output swing
−
−
−
−
−
−
2700 ps
1000 ps
5100 ps
1000 ps
2700 ps
2850 ps
−
tr(D0 to D31) data out rise time
tf(D0 to D31) data out fall time
−
−
tCDV
tDI
clock edge to data valid time
data invalid time
−
−
Notes
1. The specified timing characteristics are applicable in both normal and loop modes.
2. A capacitive load of 15 pF was connected at all outputs. An input reference level of 1 V was used.
handbook, halfpage
V
V
handbook, halfpage
CC2
CC2
50 Ω
100 Ω
CDIV
GND
D0 to D31
GND
MBK757
MBK756
Fig.4 GTL output circuits.
1998 Mar 10
13
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
T
cy(CIN)
50%
CIN
100 mV
DIN
MGK347
t
su
valid data
t
h
Fig.5 CML input timing.
T
cy(CDIV)
CDIV
1.0 V
1.1 V
0.9 V
D0 to D31
MGK348
t
DI
t
CDV
Fig.6 Output timing.
14
1998 Mar 10
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
APPLICATION INFORMATION
DATA AND CLOCK RECOVERY
OQ2541
D
DQ
CL
CLQ
DIN
DINQ
53
CINQ
57
CIN
56
V
EE
54
10 nF
BGCAP1
51
V
EE
ENL
75
10 nF
BGCAP2
REFC
micro-
controller
34
73
33 nF
DIOA
DIOC
TDI
32
31
72
70
69
68
71
TCK
TMS
BOUNDARY SCAN
TEST EQUIPMENT
ferrite
bead
TRST
TDO
V
CC2
(1)
74
100
nF
OQ2536
1 µF
ferrite
bead
V
CC1
100
nF
1 µF
1 µF
1 µF
ferrite
bead
V
DD
(2)
DLOOP
DLOOPQ
CLOOP
100
nF
65
66
60
59
DLOOP
DLOOPQ
OQ2535
MUX
ferrite
bead
V
EE
CLOOP
(3)
(4)
CLOOPQ
100
nF
CLOOPQ
GND
D0 to D31
D0 to D31
12
CDIV
C78
RECEIVE LOGIC
MGK349
(1) VCC2 pins 13, 14, 36, 37, 63, 85 and 86 should be connected together, and to the filter network.
(2) VDD pins 26, 27, 28, 76 and 77 should be connected together, and to the filter network.
(3) VEE pins 11, 38, 39, 62 and 8 should be connected together, and to the filter network.
(4) All GND pins (pins 1, 4, 8, 9, 11, 15, 17, 21, 25, 36, 40, 56, 64, 67, 70, 73, 76, 77, 79, 80, 81, 84, 89, 92 to 98 and 100) must be connected directly
to the PCB ground plane.
Fig.7 Application diagram.
1998 Mar 10
15
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
PACKAGE OUTLINE
HLQFP100: plastic heat-dissipating low profile quad flat package;
100 leads; body 14 x 14 x 1.4 mm
SOT470-1
y
X
A
51
75
50
76
Z
E
e
H
E
J
E
A
2
A
(A )
3
w M
p
A
1
b
θ
L
p
pin 1 index
L
detail X
100
26
1
25
Z
D
v
M
A
e
w M
b
p
D
B
H
v M
B
D
0
5
scale
10 mm
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
E
(2)
UNIT
A
A
A
b
c
D
E
e
H
D
H
J
L
L
v
w
y
Z
D
Z
θ
1
2
3
p
E
p
max.
7o
0o
0.20 1.5
0.05 1.3
0.28 0.18 14.1 14.1
0.16 0.12 13.9 13.9
16.25 16.25 10.15
15.75 15.75 9.15
0.75
0.45
1.15 1.15
0.85 0.85
mm
1.6
0.25
0.5
1.0
0.2 0.12 0.1
Notes
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
2. Heatsink intrusion 0.0127 maximum.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
97-01-13
SOT470-1
1998 Mar 10
16
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1998 Mar 10
17
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Mar 10
18
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
NOTES
1998 Mar 10
19
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For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1998
SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
425102/200/01/pp20
Date of release: 1998 Mar 10
Document order number: 9397 750 01623
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