P5CD040 [NXP]

Secure dual interface and contact PKI smart card controller; 安全双接口，并联系PKI智能卡控制器


型号：	P5CD040
厂家：	NXP
描述：	Secure dual interface and contact PKI smart card controller 安全双接口，并联系PKI智能卡控制器控制器
文件：	总18页 (文件大小：80K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

P5Cx012/02x/40/73/80/144

family

Secure dual interface and contact PKI smart card controller

Rev. 03 — 24 January 2008

Objective short data sheet

1. General description

1.1 SmartMX family approach

The new CMOS14 SmartMX family members feature a modular set of devices with:

• 12 KB to 144 KB EEPROM

• 200 KB user ROM

• 6144 B RAM

• High-performance secured Public Key Infrastructure (PKI) coprocessor (RSA, ECC)

• Secured dual/triple-DES coprocessor

• Secured AES coprocessor

• Memory Management Unit (MMU)

• ISO/IEC 7816 contact interface

• Optional ISO/IEC 14443 A Contactless Interface Unit (CIU)

• Optional S²C interface for NFC communication link

• 5-metal-layer 0.14 µm CMOS technology

• EEPROM with typical 500000 cycles endurance and minimum 20 years retention time

• Broad spectrum of delivery types

• Optional certiﬁed crypto library modules for RSA, ECC, DES, AES, SHA and PRNG

1.2 SmartMX family properties

The long-term approved SmartMX family features a signiﬁcantly enhanced secure smart

card IC architecture. Extended instructions for Java and C code, linear addressing, high

speed at low power and a universal memory management unit are among many other

improvements added to the classic 80C51 core architecture. The technology transfer step

from 5-metal-layer 0.18 µm to 5-metal-layer 0.14 µm CMOS technology offers now even

more advantages in terms of security features, memory resources, crypto coprocessor

calculation speed for RSA and ECC as well as availability of secure hardware support for

2/3-key Digital Encryption Standard (DES) and Advanced Encryption Standard (AES)

operations.

The availability of contact interface, optional contactless or S²C interface enables the easy

implementation of native or open platform and multi-application operating systems in

market segments like e.g. banking, E-passport, ID card, Health Card, secure access, Java

card, Near Field Communication (NFC) connectable mobile hand sets as well as Trusted

Platform Modules (TPM).

P5Cx012/02x/40/73/80/144 family

NXP Semiconductors

Secure dual interface and contact PKI smart card controller

1.3 Naming conventions

Table 1.

Naming conventions

P5xyzzz SmartMX platform

Type of category:

C = PKI controller + Triple-DES coprocessor + AES coprocessor on selected products

Interface options:

C = contact interface - ISO/IEC 7816

D = dual interface - ISO/IEC 7816 + ISO/IEC 14443 contactless interface

N = ISO/IEC 7816 + S²C Interface for NFC

zzz

Amount of non-volatile memory in KB, increasing count for further product options

1.4 Cryptographic hardware coprocessors

1.4.1 FameXE coprocessor

The approved and modular FameXE architecture supports the trend of increasing RSA

keys with faster execution speeds as well as Elliptic Curve Cryptography (ECC) based on

GF(p) or GF(2ⁿ) at best performance. FameXE supports RSA with an operand length of

up to 8-kbit (up to 4-kbit with intermediate storage in RAM only).

The FameXE PKI coprocessor supports 192-bit ECC key length that offers the same level

of security as 2048-bit RSA. An ECC GF(2ⁿ) based signature, using a 163-bit key can be

executed in less than 30 ms providing a security level comparable to 1024-bit RSA. The

operand size for ECC, supported by FameXE, is only limited by the 2.5 KB size of the

FXRAM. FameXE is easy to use and the ﬂexible interface provides programmers with the

freedom to implement their own cryptology solutions. A secured and CC EAL5+ certiﬁed

crypto library providing a large range of required functions will be available for all devices

in order to support customers in implementing public key-based solutions.

1.4.2 Triple-DES coprocessor

The DES for widely used symmetric encryption is supported by a dedicated, high

performance, highly attack resistant hardware coprocessor. Single DES and triple-DES,

based on two or three DES keys, can be executed within less than 40 µs. Relevant

standards (ISO/IEC, ANSI, FIPS) and Message Authentication Code (MAC) are fully

supported. A secured crypto library element for DES is available.

1.4.3 AES coprocessor

SmartMX is the ﬁrst smart card microcontroller platform to provide a dedicated high

performance 128-bit parallel processing coprocessor to support secure AES. The

implementation is based on FIPS197 as standardized by the National Institute for

Standards and Technology (NIST), and supports key lengths of 128-bit, 192-bit, and

256-bit with performance levels comparable to DES. AES is the next generation for

symmetric data encryption and recommended successor of DES providing signiﬁcantly

improved security level. A secured crypto library element for AES is available.

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1.5 SmartMX interfaces

1.5.1 SmartMX contact interface

Operating in accordance with ISO/IEC 7816, the SmartMX contact interface is supported

by a built-in Universal Asynchronous Receiver/Transmitter (UART), which enables data

rates of up to 1 Mbit/s allowing for the automatic generation of all typical baud rates and

supports transmission protocols T = 0 and T = 1. Either one or two additional IOs are

available.

1.5.2 SmartMX contactless interface

The optional contactless interface is fully compatible with ISO/IEC 14443 A as well as

NXP Semiconductors ﬁeld proven MIFARE technology. A dedicated Contactless Interface

Unit (CIU) manages and supports communication using data rates of up to 848 kbit/s. A

true anti-collision method (according to ISO/IEC 14443-3) enables multiple cards to be

handled simultaneously.

The optional MIFARE functionality provided in conﬁgurations B1 (MIFARE 1 KB

emulation) and B4 (MIFARE 4 KB emulation) safeguard the interface compatibility with

any installed MIFARE infrastructure. The ability to run the MIFARE protocol concurrently

with other contactless transmission protocols implemented by the user OS (T = CL or self

deﬁned) enables the combination of new services and existing applications based on

MIFARE (e.g. ticketing) on a single dual interface controller based smart card.

A tutorial software library for ISO/IEC 14443-3 and ISO/IEC 14443-4 is available to

support NXP Semiconductors customers for easy integration of the contactless

technology into current system solutions.

1.5.3 SmartMX S²C interface

The S²C interface is intended for use with NXP Semiconductors NFC circuits (e.g. PN511,

PN531) in order to conﬁgure a secure NFC system, e.g. in mobile hand sets.

Operated both in Contact mode (ISO/IEC 7816) and in S²C mode the user deﬁnes the

ﬁnal function of the controller chip with its operating system. This allows the same level of

security, functionality and ﬂexibility for the contact interface as well as for S²C interface.

The S²C interface is connected to the internal ISO 14443 CIU. The CIU handles the

demodulation and the modulation of the S²C signals in a way that a full contactless

communication via this interface and the NFC IC can be enabled. As the S²C interface is

connected to the CIU the power of the P5CN080/P5CN144 has to be supplied via the

VDD and VSS pads to use the S²C interface. The S²C interface does not need any

software adaptation compared to the normal contactless operation.

Connected to the S²C interface of a NFC IC the device is compatible with existing MIFARE

reader infrastructure and the optional emulation modes of MIFARE 1 KB or MIFARE 4 KB

enable fast system integration and backward compatibility to MIFARE based cards. The

communication on the S²C interface supports both the ISO/IEC 14443 A part 3 and the

ISO/IEC 14443 part 4.

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Secure dual interface and contact PKI smart card controller

1.6 Security features

SmartMX incorporates a big range of both inherent and OS controlled security features as

counter measure against all types of attacks. NXP Semiconductors has used the deep

knowledge of chip security, combined with the used handshaking circuit technology, the

very dense 5-metal-layer 0.14 µm technology, glue logic and active shielding methodology

for optimum results in CC EAL5+, EMVCo and other third party certiﬁcations and

approvals.

SmartMX Memory Management Unit (MMU), designed to deﬁne various memory

segments and assign security attributes accordingly, supports a strong ﬁrewall concept

that keeps different applications separate from each other. Only the System mode has full

access privileges to all memory space and on-chip peripherals, while the User mode only

has privileges deﬁned upon card personalization and executed under the control of the

System mode.

1.7 Security evaluation and certiﬁcates

The reached target of the certiﬁcation is CC EAL5+. Also third party approvals like e.g.

EMVCo (Visa, CAST), ZKA and others, depending on the application requirements, are

available.

NXP Semiconductors continues to drive forward third party security evaluations to provide

its customers with the relevant information and documentation needed to execute

subsequent composite evaluations of implemented applications.

1.8 Optional crypto library

NXP Semiconductors will offer for all family types an optional crypto library:

• Various algorithms

– AES encryption and decryption using the AES coprocessor

– DES and Triple-DES encryption and decryption using the DES coprocessor

– RSA encryption and decryption, signature generation and veriﬁcation for

straightforward and CRT keys up to 5024 bits

– RSA key generation

– ECC over GF(p) signature generation and veriﬁcation (ECDSA) and Difﬁe-Hellman

key exchange for keys up to 544 bits

– ECC over GF(p) key generation

– ECC over GF(2ⁿ) signature generation and veriﬁcation (ECDSA) and

Difﬁe-Hellman key exchange for keys up to 571 bits

– ECC over GF(2ⁿ) key generation

– SHA-1, SHA-224 and SHA-256 hash algorithm

– Pseudo-Random Number Generator (PRNG)

• Easy to use API for all algorithms

• Secure operation in contact as well as in the contactless mode

• Latest built-in security features to avoid power (SPA/DPA), timing and fault attacks

(DFA)

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Secure dual interface and contact PKI smart card controller

• Common criteria CC EAL5+ certiﬁcation planned [except ECC over GF(2ⁿ)] according

to BSI-PP-0002 protection proﬁle

2. Features

2.1 Standard family features

I EEPROM: choice of 12 KB, 20 KB, 40 KB, 72 KB, 80 KB or 144 KB

N Data retention time: 20 years minimum

N Endurance: 500000 cycles typical

I ROM: 200 KB

I RAM: 6144 B

N 256 B IRAM + 3.25 KB standard RAM usable for CPU

N 2560 B FXRAM usable for FameXE

I Dedicated Secure_MX51 Smart Card CPU (Memory eXtended/enhanced 80C51)

N 5-metal-layer 0.14 µm CMOS technology

N Operating in Contact and Contactless mode (dependent on family type option)

N Featuring a 24-bit universal memory space, 24-bit program counter

N Combined universal program and data linear address range up to 16 MB

N Additional instructions to improve:

- Pointer operations

- Performance

- Code density of both C and Java source code

I ISO/IEC 7816 contact interface

I PKI coprocessor FameXE

I Support of major Public Key Cryptography (PKC) systems like RSA, Elgamel, DSS,

Difﬁe-Hellman, Guillou-Quisquater, Fiat-Shamir and Elliptic Curves

N 8192 bits maximum key length for RSA with randomly chosen modulus

N 4096 bits maximum key length for calculation within RAM

N 32-bit interface

N Boolean operations for acceleration of standard, symmetric cipher algorithms

I High speed Triple-DES coprocessor (64-bit parallel processing DES engine)

N Two or three keys loadable

N DES3 performance < 40 µs

I High speed AES coprocessor (128-bit parallel processing AES engine)

I Memory Management Unit (MMU)

I Low power and low voltage design using NXP Semiconductors handshaking

technology

I Multiple source vectorized interrupt system with four priority levels

I Watch exception provides software debugging facility

I Multiple source RESET system

I Two 16-bit timers

I High reliable EEPROM for both data storage and program execution

I Bytewise EEPROM programming and read access

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Secure dual interface and contact PKI smart card controller

I Versatile EEPROM programming of 1 B to 64 B at a time or, optionally 1 B to 128 B at

a time

I Typical EEPROM page erasing time: 1.7 ms

I Typical EEPROM page programming time: 1.0 ms

N Power-saving Idle mode

N Wake-up from Idle mode by RESET or any activated interrupt

N Power-saving Sleep (power-down) mode or Clockstop mode

N Wake-up from Sleep or Clockstop mode by RESET or external interrupt

I Contact conﬁguration and serial interface according to ISO/IEC 7816: GND, VDD,

CLK, RST_N, IO1

I ISO/IEC 7816 UART supporting standard protocols T = 0 and T = 1 as well as high

speed personalization up to 1 Mbit/s

I External or internally generated conﬁgurable CPU clock

I 1 MHz to 10 MHz operating external clock frequency range

N Internal CPU clock up to 30 MHz with synchronous operation

N Internal clocking independent of externally applied frequency

I High speed 16-bit CRC engine according to ITU-T polynomial deﬁnition

I Low power Random Number Generator (RNG) in hardware, AIS-31 compliant

I 1.62 V to 5.5 V extended operating voltage range for class C, B and A

I Optional extended Class B operation mode (targeted for battery supplied applications)

I −25 °C to +85 °C ambient temperature

I Broad spectrum of delivery types:

N Wafers

N Modules

2.2 Product speciﬁc family features

I P5CC021, P5CC040, P5CC073, P5CC080 and P5CC144

N ISO/IEC 7816 contact interface

N Two additional IO ports IO2 and IO3 for full-duplex serial data communication

I P5CD012, P5CD020, P5CD040, P5CD080 and P5CD144

N CIU fully compatible with ISO/IEC 14443 A:

- Fully supports the T = CL protocol according ISO/IEC 14443-4

- Data transfer rates supported: 106 kbit/s, 212 kbit/s, 424 kbit/s and 848 kbit/s

N MIFARE contactless interface according ISO/IEC 14443-2:

- 13.56 MHz operating frequency

- Reliable communication due to 100 % ASK

- High speed efﬁcient frame support

- True anticollision

N MIFARE reader infrastructure compatibility

N Optional MIFARE 1 KB and MIFARE 4 KB emulation

N Two additional IO ports IO2 and IO3 for full-duplex serial data communication

I P5CN080 and P5CN144

N S²C interface

N One additional IO port IO2 for full-duplex serial data communication

P5CX012_02X_40_73_80_144_FAM_SDS_3

Objective short data sheet

Rev. 03 — 24 January 2008

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NXP Semiconductors

Secure dual interface and contact PKI smart card controller

2.3 Security features

I Enhanced security sensors:

N Low and high clock frequency sensor

N Low and high temperature sensor

N Low and high supply voltage sensor

N Single Fault Injection (SFI) attack detection

N Light sensors (included integrated memory light sensor functionality)

I Electronic fuses for safeguarded mode control

I Active shielding

I Unique ID for each die

I Clock input ﬁlter for protection against spikes

I Power-up and power-down reset

I Optional programmable card disable feature

I Memory security (encryption and physical measures) for RAM, EEPROM and ROM

I Memory Management Unit (MMU) including memory protection:

N Secure multi application operating systems via two different operation modes:

System mode and User mode

N OS controlled access restriction mechanism to peripherals in User mode

N Memory mapping up to 8-MB code memory

N Memory mapping up to 8-MB (64-kbit) data memory

I Optional disabling of ROM read instructions by code executed in EEPROM

I Optional disabling of any code execution out of RAM

I EEPROM programming:

N No external clock

N Hardware sequencer controlled

N On-chip high voltage generation

N Enhanced error correction mechanism

I 64-B or 128-B EEPROM for customer-deﬁned Security FabKey. Featuring batch, wafer

or die-individual security data, included encrypted diversiﬁcation features on request

I 14 B user write protected security area in EEPROM (byte access, inhibit functionality

per byte)

I 32 B write once security area in EEPROM (bit access)

I 32 B user read only area in EEPROM (byte access)

I Customer speciﬁc EEPROM initialization available

P5CX012_02X_40_73_80_144_FAM_SDS_3

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Secure dual interface and contact PKI smart card controller

2.4 Design-in support

I Approved development tool chain:

N Keil PK51 development tool package inclusive µVision3/dScope C51 simulator,

additional speciﬁc hardware drivers inclusive simulation of contactless interface

and ISO/IEC 7816 card interface board. A SmartMX DBox allows software

debugging and integration tests.

N Ashling Ultra-Emulator platform, stand alone ROM prototyping boards and

ISO/IEC 7816 and ISO/IEC 14443 card interface board. Code coverage and

performance measurement software tools for real time software testing.

N Dual interface dummy modules OM6711 (PDM 1.1 - SOT658) with special antenna

bonding on C4 and C8 for testing the implanting process and antenna connection.

I Software libraries:

N Libraries supporting contactless communication according to ISO 14443,

part 3 and 4

N EEPROM read/write routines

3. Applications

3.1 Application areas

I Banking

I Java cards

I E-passports

I ID cards

I Secure access

I Trusted platform modules

P5CX012_02X_40_73_80_144_FAM_SDS_3

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Secure dual interface and contact PKI smart card controller

4. Quick reference data

Table 2.

Quick reference data

Symbol Parameter

Conditions

Min

4.5

Typ

5.0

3.0

1.8

Max

5.5

Unit

V_DD

supply voltage

Class A: 5 V range

Class B: 3 V range

Class BE: 3 V range

Class C: 1.8 V range

2.7

3.3

[1]

2.2

3.3

1.62

1.98

[1] In case of extended Class B (Class BE) operation mode (targeted for battery supplied applications), the

class C is not supported.

5. Ordering information

Table 3.

Ordering information

Type number

Package

Name

FFC

Description

Version

P5CC021UA

P5CC040UA

P5CC073UA

P5CC080UA

P5CC144UA

P5CD012UA

P5CD020UA

P5CD040UA

P5CD080UA

P5CD144UA

P5CN080UA

P5CN144UA

P5CD012UE

P5CD020UE

P5CD040UE

P5CD080UE

P5CD144UE

P5CC021XS

P5CC040XS

P5CC073XS

P5CC080XS

P5CC144XS

P5CD012X1

P5CD020X1

P5CD040X1

P5CD080X1

P5CD144X1

8 inch wafer (sawn; 150 µm thickness; on ﬁlm

frame carrier; electronic fail die marking according

to SECSII format)

<tbd>

FFC

8 inch wafer (sawn; 75 µm thickness; on ﬁlm frame <tbd>

carrier; electronic fail die marking according to

SECSII format)

PCM1.1

PDM1.1

contact chip card module (super 35 mm format,

8-contact)

SOT658

contactless chip card module (Plug-in type; super SOT658

35 mm format, 8-contact)

P5CX012_02X_40_73_80_144_FAM_SDS_3

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Secure dual interface and contact PKI smart card controller

Table 3.

Ordering information …continued

Type number

Package

Name

Description

Version

P5CD012X0

P5CD020X0

P5CD040X0

P5CD080X0

P5CD144X0

P5CD012A4

P5CD020A4

P5CD040A4

P5CD080A4

P5CD144A4

P5CD012A6

P5CD020A6

P5CD040A6

P5CD080A6

P5CD144A6

PDM1.1

contactless chip card module (super 35 mm format, SOT658

8-contact)

MOB4

MOB6

plastic leadless module carrier package; 35 mm

wide tape

SOT500-2

SOT500-3

plastic leadless module carrier package; 35 mm

wide tape

Table 4.

Feature table

Product EEPROM User

Total

RAM

[KB]

CXRAM FXRAM Coprocessor

ISO 7816 Interface option

IO pads

type

[KB]

ROM

[KB]

FameXE DES

AES

P5CD012

P5CC021

P5CD020

P5CC040

P5CD040

P5CC073

P5CN080

200

3.5

2.5

yes

dual interface

contact

dual interface

contact

dual interface

contact

contact + S²C

interface for NFC

P5CC080

P5CD080

P5CN144

200

3.5

2.5

yes

contact

dual interface

contact + S²C

144

interface for NFC

P5CC144

P5CD144

144

200

3.5

2.5

yes

contact

dual interface

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xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x

ROM

EEPROM

RAM

P5CC021 P5CC040 P5CC073 P5CC080

P5CC144

20 KB/40 KB/

72 KB/80 KB/

144 KB

DATA AND

PROGRAM

MEMORY

200 KB

PROGRAM

MEMORY

6144 B

DATA

MEMORY

FameXE

ENHANCED PUBLIC

KEY

COPROCESSOR e.g.

RSA, ECC

IO1

IO2

IO3

PROGRAMMABLE

IO 1, 2, 3

UART

ISO 7816

MEMORY MANAGEMENT UNIT (MMU)

CLOCK

FILTER

CLOCK

GENERATION

CLK

SECURE_MX51 CPU

TRIPLE-DES

COPROCESSOR

AES

COPROCESSOR

TIMERS

SECURITY SENSORS

RESET GENERATION

RST_N

FAST

CRC16

RNG

16-bit 16-bit

VOLTAGE REGULATOR

VDD

VSS

001aae954

Fig 1. Functional diagram P5CC021/P5CC040/P5CC073/P5CC080/P5CC144

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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

P5CD020 P5CD040 P5CD080 P5CD144

ROM

EEPROM

RAM

CIU

INTERFACE

ISO 14443

20 KB/40 KB/

80 KB/144 KB

DATA AND

PROGRAM

MEMORY

200 KB

PROGRAM

MEMORY

6144 B

DATA

MEMORY

FameXE

ENHANCED PUBLIC

KEY

COPROCESSOR e.g.

RSA, ECC

IO1

IO2

IO3

PROGRAMMABLE

IO 1, 2, 3

UART

ISO 7816

MEMORY MANAGEMENT UNIT (MMU)

CLOCK

FILTER

CLOCK

GENERATION

CLK

SECURE_MX51 CPU

TRIPLE-DES

COPROCESSOR

AES

COPROCESSOR

TIMERS

SECURITY SENSORS

RESET GENERATION

RST_N

FAST

CRC16

RNG

16-bit 16-bit

VOLTAGE REGULATOR

VDD

VSS

001aae953

Fig 2. Functional diagram P5CD012/P5CD020/P5CD040/P5CD080/P5CD144

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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

P5CN080 P5CN144

SIGIN

ROM

EEPROM

RAM

S C

CIU

INTERFACE

ISO 14443

SIGOUT

80 KB/

144 KB

DATA AND

PROGRAM

MEMORY

200 KB

PROGRAM

MEMORY

6144 B

DATA

MEMORY

FameXE

ENHANCED PUBLIC

KEY

COPROCESSOR e.g.

RSA, ECC

IO1

IO2

PROGRAMMABLE

IO 1, 2

UART

ISO 7816

MEMORY MANAGEMENT UNIT (MMU)

CLOCK

FILTER

CLOCK

GENERATION

CLK

SECURE_MX51 CPU

TRIPLE-DES

COPROCESSOR

AES

COPROCESSOR

TIMERS

SECURITY SENSORS

RESET GENERATION

RST_N

FAST

CRC16

RNG

16-bit 16-bit

VOLTAGE REGULATOR

VDD

VSS

001aae955

Fig 3. Functional diagram P5CN080/P5CN144

P5Cx012/02x/40/73/80/144 family

NXP Semiconductors

Secure dual interface and contact PKI smart card controller

7. Limiting values

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to

VSS (ground = 0 V).

Symbol Parameter

Conditions

Min

−0.5

Max

Unit

V_DD

V_I

supply voltage

input voltage

input current

+6.0

any signal pad

V_DD+ 0.5

±15.0

I_I

pad IO1, IO2 or

IO3

I_O

output current

pad IO1, IO2 or

IO3

±15.0

±100

±4.0

I_lu

latch-up current

V_I< 0 V

or V_I> V_DD

[1]

V_esd

electrostatic discharge voltage pads VDD, VSS,

CLK, RST_N, IO1,

IO2, IO3

[1]

[2]

[3]

pads LA, LB

total power dissipation

±2.0

P_tot

T_stg

storage temperature

[1] MIL Standard 883-D method 3015; human body model; C = 100 pF, R = 1.5 kΩ; T_amb= −25 °C to +85 °C.

[2] Depending on appropriate thermal resistance of the package.

[3] Depending on delivery type, refer to NXP Semiconductors General Speciﬁcation for 8” Wafer and to NXP

Semiconductors Contact & Dual Interface Chip Card Module Speciﬁcation.

8. Abbreviations

Table 6.

Abbreviations

Description

Acronym

AES

Advanced Encryption Standard

Application Programming Interface

Amplitude Shift Keying

API

ASK

CIU

Contactless Interface Unit

CRC

CRT

Cyclic Redundancy Check

Chinese Remainder Theorem

Digital Encryption Standard

Differential Fault Analysis

DES

DFA

DPA

Differential Power Analysis

DSS

Digital Signature Standard

ECC

Elliptic Curve Cryptography

Elliptic Curve Digital Signature Algorithm

Electrically Erasable Programmable Read-Only Memory

Galois Function

ECDSA

EEPROM

MAC

MMU

Message Authentication Code

Memory Management Unit

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Table 6.

Abbreviations …continued

Acronym

NFC

Description

Near Field Communication

Operating System

PKC

PKI

Public Key Cryptography

Public Key Infrastructure

Pseudo-Random Number Generator

Random Number Generator

Rivest, Shamir and Adleman

SigIn-SigOut-Connection

Single Fault Injection

PRNG

RNG

RSA

S²C

SFI

SHA

SMD

SPA

Secure Hash Algorithm

Surface Mounted Device

Simple Power Analysis

TPM

UART

Trusted Platform Module

Universal Asynchronous Receiver/Transmitter

9. Revision history

Table 7.

Revision history

Document ID

Release date Data sheet status

Change notice Supersedes

P5CX012_02X_40_73_80_ 20080124

144_FAM_SDS_3

Objective short data sheet

P5CX02X_40_73_80_144_

FAM_SDS_2

Modiﬁcations:

• Type number P5CD012 added

• Table 3 “Ordering information” corrected and new type number added

• Figure 2 added

P5CX02X_40_73_80_144_ 20070424

FAM_SDS_2

Objective short data sheet

P5CX02X_40_80_144_FAM

_SDS_1

P5CX02X_40_80_144_FAM 20070216

_SDS_1

Objective short data sheet

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Rev. 03 — 24 January 2008

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10. Legal information

10.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

to result in personal injury, death or severe property or environmental

10.2 Deﬁnitions

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

10.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

10.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

MIFARE — is a trademark of NXP B.V.

FabKey — is a trademark of NXP B.V.

11. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

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12. Tables

Table 1. Naming conventions . . . . . . . . . . . . . . . . . . . . . .2

Table 2. Quick reference data . . . . . . . . . . . . . . . . . . . . .9

Table 3. Ordering information . . . . . . . . . . . . . . . . . . . . .9

Table 4. Feature table . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 5. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 7. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15

13. Figures

Fig 1. Functional diagram

P5CC021/P5CC040/P5CC073/P5CC080/

P5CC144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Fig 2. Functional diagram

P5CD012/P5CD020/P5CD040/P5CD080/

P5CD144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Fig 3. Functional diagram P5CN080/P5CN144 . . . . . . .13

continued >>

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14. Contents

1.1

General description . . . . . . . . . . . . . . . . . . . . . . 1

SmartMX family approach . . . . . . . . . . . . . . . . 1

1.2

1.3

1.4

SmartMX family properties . . . . . . . . . . . . . . . . 1

Naming conventions . . . . . . . . . . . . . . . . . . . . . 2

Cryptographic hardware coprocessors. . . . . . . 2

FameXE coprocessor . . . . . . . . . . . . . . . . . . . 2

Triple-DES coprocessor . . . . . . . . . . . . . . . . . . 2

AES coprocessor . . . . . . . . . . . . . . . . . . . . . . . 2

SmartMX interfaces . . . . . . . . . . . . . . . . . . . . . 3

SmartMX contact interface . . . . . . . . . . . . . . . . 3

SmartMX contactless interface . . . . . . . . . . . . 3

SmartMX S²C interface . . . . . . . . . . . . . . . . . . 3

Security features. . . . . . . . . . . . . . . . . . . . . . . . 4

Security evaluation and certiﬁcates . . . . . . . . . 4

Optional crypto library. . . . . . . . . . . . . . . . . . . . 4

1.4.1

1.4.2

1.4.3

1.5

1.5.1

1.5.2

1.5.3

1.6

1.7

1.8

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Standard family features. . . . . . . . . . . . . . . . . . 5

Product speciﬁc family features . . . . . . . . . . . . 6

Security features. . . . . . . . . . . . . . . . . . . . . . . . 7

Design-in support . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

2.2

2.3

2.4

3.1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Application areas . . . . . . . . . . . . . . . . . . . . . . . 8

Quick reference data . . . . . . . . . . . . . . . . . . . . . 9

Ordering information. . . . . . . . . . . . . . . . . . . . . 9

Functional diagram . . . . . . . . . . . . . . . . . . . . . 11

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 16

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

10.1

10.2

10.3

10.4

Contact information. . . . . . . . . . . . . . . . . . . . . 16

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 24 January 2008

Document identifier: P5CX012_02X_40_73_80_144_FAM_SDS_3

P5CD040 [NXP]

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