P80C32NBBB [NXP]
CMOS single-chip 8-bit microcontrollers; CMOS单芯片8位微控制器
| 型号： | P80C32NBBB |
| 厂家： | 
NXP |
| 描述： | CMOS single-chip 8-bit microcontrollers |
| 文件： | 总62页 (文件大小：663K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
80C32/87C52
CMOS single-chip 8-bit microcontrollers
Product specification
IC20 Data Handbook
1996 Aug 16
Philips
Semiconductors
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
DESCRIPTION
PIN CONFIGURATIONS
The Philips 80C32/87C52 is a high-performance microcontroller
fabricated with Philips high-density CMOS technology. The Philips
CMOS technology combines the high speed and density
characteristics of HMOS with the low power attributes of CMOS.
Philips epitaxial substrate minimizes latch-up sensitivity.
40
39
V
DD
P1.0/T2
P1.1/T2EX
P1.2
1
2
3
P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
The 87C52 contains an 8k × 8 EPROM and the 80C32 is ROMless.
Both contain a 256 × 8 RAM, 32 I/O lines, three 16-bit
counter/timers, a six-source, two-priority level nested interrupt
structure, a serial I/O port for either multi-processor
communications, I/O expansion or full duplex UART, and on-chip
oscillator and clock circuits.
P1.3
P1.4
4
5
36
P0.3/AD3
35 P0.4/AD4
34
P1.5
P1.6
P1.7
RST
6
7
8
9
P0.5/AD5
33 P0.6/AD6
In addition, the 80C32/87C52 has two software selectable modes of
power reduction—idle mode and power-down mode. The idle mode
freezes the CPU while allowing the RAM, timers, serial port, and
interrupt system to continue functioning. The power-down mode
saves the RAM contents but freezes the oscillator, causing all other
chip functions to be inoperative.
32
31
30
P0.7/AD7
CERAMIC
AND
PLASTIC
DUAL
IN-LINE
PACKAGE
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
INT1/P3.3 13
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
XTAL1 19
V
EA/V
PP
ALE/PROG
29 PSEN
28
P2.7/A15
27 P2.6/A14
26
See 80C52/80C54/80C58 datasheet for ROM device specifications.
P2.5/A13
FEATURES
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
• 80C51 based architecture
• 8032 compatible
– 8k × 8 EPROM (87C52)
22
21
P2.1/A9
P2.0/A8
– ROMless (80C32)
20
SS
– 256 × 8 RAM
SU00060
– Three 16-bit counter/timers
– Full duplex serial channel
– Boolean processor
• Memory addressing capability
– 64k ROM and 64k RAM
• Power control modes:
– Idle mode
– Power-down mode
• CMOS and TTL compatible
• Three speed ranges:
– 3.5 to 16MHz
– 3.5 to 24MHz
– 3.5 to 33MHz
• Five package styles
• Extended temperature ranges
• OTP package available
2
1996 Aug 16
853–1562 17195
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
ORDERING INFORMATION
TEMPERATURE RANGE °C
FREQ
DRAWING
NUMBER
1
ROMless
P80C32EBP N
P80C32EBA A
EPROM
AND PACKAGE
MHz
16
16
16
16
16
16
16
16
16
24
24
24
24
24
24
24
24
24
33
33
33
33
33
33
P87C52EBP N
OTP
OTP
UV
0 to +70, Plastic Dual In-line Package
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Ceramic Dual In-line Package
0 to +70, Ceramic Leaded Chip Carrier
0 to +70, Plastic Quad Flat Pack
SOT129-1
SOT187-2
0590B
P87C52EBA A
P87C52EBF FA
P87C52EBL KA
P87C52EBB B
P87C52EFP N
P87C52EFA A
P87C52EFF FA
P87C52EFB B
P87C52IBP N
P87C52IBA A
UV
1472A
P80C32EBB B
P80C32EFP N
P80C32EFA A
OTP
OTP
OTP
UV
SOT307-2
SOT129-1
SOT187-2
0590B
–40 to +85, Plastic Dual In-line Package
–40 to +85, Plastic Leaded Chip Carrier
–40 to +85, Ceramic Dual In-line Package
–40 to +85, Plastic Quad Flat Pack
0 to +70, Plastic Dual In-line Package
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Quad Flat Pack
P80C32EFB B
P80C32IBP N
P80C32IBA A
P80C32IBB B
OTP
OTP
OTP
SOT307-2
SOT129-1
SOT187-2
SOT307-2
0590B
P87C52IBF FA
P87C52IBL KA
UV
UV
0 to +70, Ceramic Dual In-line Package
0 to +70, Ceramic Leaded Chip Carrier
–40 to +85, Plastic Dual In-line Package
–40 to +85, Plastic Leaded Chip Carrier
–40 to +85, Plastic Quad Flat Pack
–40 to +85, Ceramic Dual In-line Package
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Dual In-line Package
0 to +70, Plastic Quad Flat Pack
1472A
P80C32IFP
P80C32IFA
P80C32IFB
N
A
B
P87C52IFP
P87C52IFA
N
A
OTP
OTP
SOT129-1
SOT187-2
SOT307-2
0590B
P87C52IFF FA
UV
P80C32NBA A
P80C32NBP N
P80C32NBB B
P80C32NFA A
P80C32NFP N
SOT187-2
SOT129-1
SOT307-2
SOT187-2
SOT129-1
SOT307-2
–40 to +85, Plastic Leaded Chip Carrier
–40 to +85, Plastic Dual In-line Package
–40 to +85, Plastic Quad Flat Pack
P80C32NFB B
NOTE:
1. OTP = One Time Programmable EPROM. UV = UV erasable EPROM
2. For 33MHz ROM 80C52 operation, see 80C52/80C54/80C58 data sheet.
3
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
CERAMIC AND PLASTIC LEADED CHIP CARRIER
PIN FUNCTIONS
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
44
34
6
1
40
7
39
29
1
33
23
PQFP
LCC
11
17
12
22
18
28
Pin Function
Pin Function
Pin Function
Pin Function
Pin Function
Pin Function
1
2
P1.5
P1.6
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
NC*
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
SS
1
2
3
NC*
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2
XTAL1
V
SS
NC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
31
P2.7/A15
PSEN
32
33
34
35
36
37
38
39
40
41
42
43
44
T2/P1.0
T2EX/P1.1
P1.2
3
P1.7
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE/PROG
NC*
4
RST
4
5
6
RxD/P3.0
NC*
EA/V
PP
5
P1.3
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
6
P1.4
7
8
9
10
11
12
13
14
15
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2
XTAL1
7
P1.5
V
CC
8
P1.6
NC*
9
P1.7
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
10
11
12
13
14
15
RST
RxD/P3.0
NC*
TxD/P3.1
INT0/P3.2
INT1/P3.3
ALE/PROG
NC*
EA/V
PP
V
CC
P0.7/AD7
* DO NOT CONNECT
* DO NOT CONNECT
SU00061
SU00062
LOGIC SYMBOL
V
V
SS
CC
XTAL1
ADDRESS AND
DATA BUS
XTAL2
RST
T2
T2EX
EA/V
PP
PSEN
ALE/PROG
RxD
TxD
INT0
INT1
T0
ADDRESS BUS
T1
WR
RD
SU00063
4
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
BLOCK DIAGRAM
P0.0–P0.7
P2.0–P2.7
PORT 0
DRIVERS
PORT 2
DRIVERS
V
CC
V
SS
ROM/
EPROM
RAM ADDR
REGISTER
PORT 0
LATCH
PORT 2
LATCH
RAM
B
STACK
POINTER
ACC
REGISTER
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
BUFFER
PCON SCON TMOD TCON
ALU
T2CON
TH0
TL0
TL2 RCAP2H
IE IP
INTERRUPT, SERIAL
TH1
TL1
TH2
PC
INCRE-
MENTER
RCAP2L SBUF
PSW
PORT AND TIMER BLOCKS
PROGRAM
COUNTER
PSEN
ALE
EA
TIMING
AND
CONTROL
DPTR
RST
PORT 1
LATCH
PORT 3
LATCH
PD
OSCILLATOR
PORT 1
DRIVERS
PORT 3
DRIVERS
XTAL1
XTAL2
P1.0–P1.7
P3.0–P3.7
SU00064
5
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
Table 1.
8XC52 Special Function Registers
DIRECT
DESCRIPTION
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
RESET
VALUE
SYMBOL
ADDRESS MSB
LSB
ACC*
B*
Accumulator
B register
E0H
F0H
E7
F7
E6
F6
E5
F5
E4
F4
E3
F3
E2
F2
E1
F1
E0
00H
F0
00H
DPTR:
DPH
DPL
Data pointer (2 bytes)
Data pointer high
Data pointer low
83H
82H
00H
00H
AF
EA
BF
–
AE
–
AD
ET2
BD
AC
ES
BC
PS
AB
ET1
BB
AA
EX1
BA
A9
ET0
B9
A8
EX0
B8
IE*
IP*
Interrupt enable
Interrupt priority
A8H
B8H
0x000000B
xx000000B
BE
–
PT2
PT1
PX1
PT0
PX0
87
86
85
84
83
82
81
80
P0*
P1*
P2*
P3*
Port 0
Port 1
Port 2
80H
90H
A0H
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
FFH
FFH
FFH
97
–
96
–
95
–
94
–
93
–
92
–
91
90
T2
T2EX
A7
A6
A5
A4
A3
A2
A1
A9
A0
A8
A15
A14
A13
A12
A11
A10
B7
RD
B6
WR
–
B5
T1
–
B4
T0
–
B3
B2
B1
TxD
PD
B0
RxD
IDL
Port 3
B0H
87H
INT1
GF1
INT0
GF0
FFH
1
PCON
Power control
SMOD
0xxxxxxxB
D7
CY
D6
AC
D5
F0
D4
D3
D2
D1
–
D0
P
PSW*
Program status word
D0H
RS1
RS0
OV
00H
RCAP2H# Capture high
CBH
CAH
00H
00H
RCAPL#
Capture low
SBUF
Serial data buffer
99H
xxxxxxxxB
9F
9E
9D
9C
9B
9A
99
TI
98
RI
SCON*
SP
Serial controller
Stack pointer
98H
81H
SM0
SM1
SM2
REN
TB8
RB8
00H
07H
8F
8E
8D
8C
8B
8A
89
88
TCON*
Timer control
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00H
CF
CE
CD
CC
CB
CA
C9
C8
T2CON*#
Timer 2 control
C8H
TF2
EXF2 RCLK TCLK
EXEN2
TR2
C/T2
CP/RL2 00H
TH0
TH1
TH2#
TL0
TL1
TL2#
Timer high 0
Timer high 1
Timer high 2
Timer low 0
Timer low 1
Timer low 2
8CH
8DH
CDH
8AH
8BH
CCH
00H
00H
00H
00H
00H
00H
TMOD
Timer mode
89H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
*
#
Bit addressable
SFRs are modified from or added to the 80C51 SFRs.
1. Bits GF1, GF0, PD, and IDL of the PCON register are not implemented in the NMOS 8XC52.
6
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
PIN DESCRIPTION
PIN NO.
MNEMONIC
DIP
20
LCC
22
QFP TYPE NAME AND FUNCTION
V
SS
V
CC
16
38
I
I
Ground: 0V reference.
40
44
Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
P0.0–0.7
39–32 43–36 37–30
I/O
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the
code bytes during program verification in the 87C52. External pull-ups are required during
program verification.
P1.0–P1.7
1–8
2–9
40–44
1–3
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 1 pins that are externally pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I ). Pins P1.0 and P1.1 also. Port 1 also
IL
receives the low-order address byte during program memory verification. Port 1 also serves
alternate functions for timer 2:
1
2
2
3
40
41
I
I
T2 (P1.0): Timer/counter 2 external count input.
T2EX (P1.1): Timer/counter 2 trigger input.
P2.0–P2.7
21–28 24–31 18–25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I ). Port 2 emits the high-order
IL
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
P3.0–P3.7
10–17
11,
5,
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
13–19 7–13
pull-ups. (See DC Electrical Characteristics: I ). Port 3 also serves the special features of
IL
the 80C51 family, as listed below:
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
9
10
11
12
13
RST
9
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V permits a power-on reset using only an external
SS
capacitor to V
.
CC
ALE/PROG
30
33
27
I/O
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.
Note that one ALE pulse is skipped during each access to external data memory. This pin is
also the program pulse input (PROG) during EPROM programming.
PSEN
29
31
32
35
26
29
O
I
Program Store Enable: The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.
EA/V
External Access Enable/Programming Supply Voltage: EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H to
1FFFH. If EA is held high, the device executes from internal program memory unless the
program counter contains an address greater than 1FFFH. This pin also receives the
PP
12.75V programming supply voltage (V ) during EPROM programming.
PP
XTAL1
XTAL2
19
18
21
20
15
14
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
O
Crystal 2: Output from the inverting oscillator amplifier.
7
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
transition at external input T2EX will also trigger the 16-bit reload
and set EXF2. The auto-reload mode is illustrated in Figure 3.
DIFFERENCES FROM THE 80C51
Special Function Registers
The baud rate generation mode is selected by RCLK = 1 and/or
TCLK = 1. It will be described in conjunction with the serial port.
The special function register space is the same as the 80C51 except
that the 80C32/87C52 contains the additional special function
registers T2CON, RCAP2L, RCAP2H, TL2, and TH2. Since the
standard 80C51 on-chip functions are identical in the 8XC52, the
SFR locations, bit locations, and operation are likewise identical.
The only exceptions are in the interrupt mode and interrupt priority
SFRs (see Table 1).
Serial Port
The serial port of the 8XC52 is identical to that of the 80C51 except
that counter/timer 2 can be used to generate baud rates.
In the 8XC52, Timer 2 is selected as the baud rate generator by
setting TCLK and/or RCLK in T2CON (see Figure 1). Note that the
baud rate for transmit and receive can be simultaneously different.
Setting RCLK and/or TCLK puts Timer into its baud rate generator
mode, as shown in Figure 4.
Timer/Counters
In addition to timer/counters 0 and 1 of the 80C51, the 80C32/87C52
contains timer/counter 2. Like timers 0 and 1, timer 2 can operate as
either an event timer or as an event counter. This is selected by bit
C/T2 in the special function register T2CON (see Figure 1). It has
three operating modes: capture, auto-load, and baud rate generator,
which are selected by bits in the T2CON as shown in Table 2.
The baud rate generator mode is similar to the auto-reload mode, in
that a rollover in TH2 causes the Timer 2 registers to be reloaded
with the 16-bit value in registers RCAP2H and RCAP2L, which are
preset by software.
In the Capture Mode there are two options which are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit timer or
counter which upon overflowing sets bit TF2, the Timer 2 overflow
bit, which can be used to generate an interrupt. If EXEN2 = 1, then
Timer 2 still does the above, but with the added feature that a 1-to-0
transition at external input T2EX causes the current value in the
Timer 2 registers, TL2 and TH2, to be captured into registers
RCAP2L and RCAP2H, respectively. (RCAP2L and RCAP2H are
new special function registers in the 80C52.) In addition, the
transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2
like TF2 can generate an interrupt. The Capture Mode is illustrated
in Figure 2.
Now, the baud rates in Modes 1 and 3 are determined by Timer 2’s
overflow rate as follows:
Timer 2 Overflow Rate
Modes 1, 3 Baud Rate +
16
The timer can be configured for either “timer” or “counter” operation.
In the most typical applications, it is configured for “timer” operation
(C/T2 = 0). “Timer” operation is a little different for Timer 2 when it’s
being used as a baud rate generator. Normally, as a timer it would
increment every machine cycle (thus at 1/12 the oscillator
frequency). As a baud rate generator, however, it increments every
state time (thus at 1/2 the oscillator frequency). In that case the
baud rate is given by the formula:
In the auto-reload mode, there are again two options, which are
selected by bit EXEN2 in T2CON. If EXEN2 = 0, then when Timer 2
rolls over it not only sets TF2 but also causes the Timer 2 registers
to be reloaded with the 16-bit value in registers RCAP2L and
RCAP2H, which are preset by software. If EXEN2 = 1, then Timer 2
still does the above, but with the added feature that a 1-to-0
Oscillator Frequency
Modes 1, 3 Baud Rate +
32 [65536 * (RCAP2H, RCAP2L)]
where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L
taken as a 16-bit unsigned integer.
(MSB)
(LSB)
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Symbol
Position
Name and Significance
TF2
T2CON.7
T2CON.6
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1.
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2
interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software.
RCLK
TCLK
T2CON.5
T2CON.4
T2CON.3
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0
causes Timer 1 overflow to be used for the receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0
causes Timer 1 overflows to be used for the transmit clock.
EXEN2
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not
being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2
T2CON.1
Start/stop control for Timer 2. A logic 1 starts the timer.
C/T2
Timer or counter select. (Timer 2)
0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
CP/RL2
T2CON.0
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will
occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is
ignored and the timer is forced to auto-reload on Timer 2 overflow.
SU00065
Figure 1. Timer/Counter 2 (T2CON) Control Register
8
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
OSC
÷ 12
C/T2 = 0
C/T2 = 1
TL2
(8-bits)
TH2
(8-bits)
TF2
T2 Pin
Control
TR2
Capture
Transition
Detector
Timer 2
Interrupt
RCAP2L
RCAP2H
T2EX Pin
EXF2
Control
EXEN2
SU00066
Figure 2. Timer 2 in Capture Mode
OSC
÷ 12
C/T2 = 0
C/T2 = 1
TL2
(8-BITS)
TH2
(8-BITS)
T2 PIN
CONTROL
TR2
RELOAD
TRANSITION
DETECTOR
RCAP2L
RCAP2H
TF2
TIMER 2
INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
SU00067
Figure 3. Timer 2 in Auto-Reload Mode
9
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
Timer 1
Overflow
÷ 2
NOTE: OSC. Freq. is divided by 2, not 12.
“0”
“1”
OSC
÷ 2
C/T2 = 0
C/T2 = 1
SMOD
RCLK
“1”
“0”
TL2
(8-bits)
TH2
(8-bits)
T2 Pin
Control
÷ 16
RX Clock
“1”
“0”
TR2
Reload
TCLK
Transition
Detector
RCAP2L
RCAP2H
÷ 16
TX Clock
Timer 2
Interrupt
T2EX Pin
EXF2
Control
EXEN2
Note availability of additional external interrupt.
SU00068
Figure 4. Timer 2 in Baud Rate Generator Mode
Table 2.
Timer 2 Operating Modes
RCLK + TCLK
CP/RL2
TR2
1
MODE
0
0
1
X
0
1
16-bit Auto-reload
16-bit Capture
1
X
X
1
Baud rate generator
(off)
0
Timer 2 as a baud rate generator is shown in Figure 4. This figure is
valid only if RCLK + TCLK = 1 in T2CON. Note that a rollover in TH2
does not set TF2, and will not generate an interrupt. Therefore, the
Timer 2 interrupt does not have to be disabled when Timer 2 is in
the baud rate generator mode. Note too, that if EXEN2 is set, a
1-to-0 transition in T2EX will set EXF2 but will not cause a reload
from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in
use as a baud rate generator, T2EX can be used as an extra
external interrupt, if desired.
Timer/Counter 2 Set-up
Except for the baud rate generator mode, the values given for
T2CON do not include the setting of the TR2 bit. Therefore, bit TR2
must be set, separately, to turn the timer on. See Table 3 for set-up
of timer 2 as a timer. See Table 4 for set-up of timer 2 as a counter.
Using Timer/Counter 2 to Generate Baud Rates
For this purpose, Timer 2 must be used in the baud rate generating
mode. If Timer 2 is being clocked through pin T2 (P1.0) the baud
rate is:
It should be noted that when Timer 2 is running (TR2 = 1) in “timer”
function in the baud rate generator mode, one should not try to read
or write TH2 or TL2. Under these conditions the timer is being
incremented every state time, and the results of a read or write may
not be accurate. The RCAP registers may be read, but should not
be written to, because a write might overlap a reload and cause
write and/or reload errors. Turn the timer off (clear TR2) before
accessing the Timer 2 or RCAP registers, in this case.
Timer 2 Overflow Rate
Baud Rate +
16
And if it is being clocked internally, the baud rate is:
Oscillator Frequency
Baud Rate +
32 [65536 * (RCAP2H, RCAP2L)]
To obtain the reload value for RCAP2H and RCA02L, the above
equation can be rewritten as:
Oscillator Frequency
RCAP2H, RCAP2L + 65536 *
32 Baud Rate
10
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
by hardware. That is, interrupts can be generated or pending
interrupts can be canceled in software.
Interrupts
The 80C32/87C52 has 6 interrupt sources. All except TF2 and EXF2
are identical sources to those in the 80C51.
The interrupt vector addresses and the interrupt priority for requests
in the same priority level are given in the following:
The Interrupt Enable Register and the Interrupt Priority Register are
modified to include the additional 80C32/87C52 interrupt sources.
The operation of these registers is identical to the 80C51.
Source
Vector Priority Within
Address
0003H
000BH
0013H
001BH
0023H
Level
(highest)
1. IE0
2. TF0
3. IE1
4. TF1
5. RI + TI
In the 80C32/87C52, the Timer 2 Interrupt is generated by the
logical OR of TF2 and EXF2. Neither of these flags is cleared by
hardware when the service routine is vectored to. In fact, the service
routine may have to determine whether it was TF2 or EXF2 that
generated the interrupt, and the bit will have to be cleared in
software.
6. TF2 + EXF2 002BH
(lowest)
Note that they are identical to those in the 80C51 except for the
addition of the Timer 2 (TF1 and EXF2) interrupt at 002BH and at
the lowest priority within a level.
All of the bits that generate interrupts can be set or cleared by
software, with the same result as though it has been set or cleared
Table 3.
Timer 2 as a Timer
MODE
T2CON
INTERNAL CONTROL
(Note 1)
EXTERNAL CONTROL
(Note 2)
16-bit Auto-Reload
00H
01H
34H
24H
14H
08H
09H
36H
26H
16H
16-bit Capture
Baud rate generator receive and transmit same baud rate
Receive only
Transmit only
Table 4.
Timer 2 as a Counter
MODE
TMOD
INTERNAL CONTROL
(Note 1)
EXTERNAL CONTROL
(Note 2)
16-bit
02H
03H
0AH
0BH
Auto-Reload
NOTES:
1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when timer 2 is used in the baud rate
generator mode.
11
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol, page 4.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. the control
bits for the reduced power modes are in the special function register
PCON.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles.
DESIGN CONSIDERATIONS
At power-on, the voltage on V and RST must come up at the
CC
same time for a proper start-up.
Table 5 shows the state of I/O ports during low current operating
modes.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
As a precaution to coming out of an unexpected power down, INT0
and INT1 should be disabled prior to enterring power down.
Table 5. External Pin Status During Idle and Power-Down Modes
MODE
PROGRAM MEMORY
Internal
ALE
PSEN
PORT 0
Data
PORT 1
Data
PORT 2
Data
PORT 3
Data
Idle
Idle
1
1
0
0
1
1
0
0
External
Float
Data
Address
Data
Data
Power-down
Power-down
Internal
Data
Data
Data
External
Float
Data
Data
Data
12
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
Electrical Deviations from Commercial Specifications for Extended Temperature Range (87C52)
DC and AC parameters not included here are the same as in the commercial temperature range table.
DC ELECTRICAL CHARACTERISTICS
T
amb
= –40°C to +85°C, V = 5V ±10%, V = 0V
CC SS
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
–0.5
0
MAX
0.2V –0.15
UNIT
V
V
V
V
V
Input low voltage, except EA
IL
CC
Input low voltage to EA
0.2V –0.35
V
IL1
IH
CC
Input high voltage, except XTAL1, RST
Input high voltage to XTAL1, RST
Logical 0 input current, ports 1, 2, 3
Logical 1-to-0 transition current, ports 1, 2, 3
0.2V +1
V
CC
V
CC
+0.5
+0.5
V
CC
0.7V +0.1
V
IH1
CC
I
I
I
V
= 0.45V
= 2.0V
IN
–75
µA
µA
IL
IN
V
–750
TL
Power supply current:
Active mode
V
CC
= 4.5–5.5V,
CC
Frequency range =
3.5 to 16MHz
32
5
50
mA
mA
µA
Idle mode
Power-down mode
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
°C
°C
V
Operating temperature under bias
Storage temperature range
0 to +70 or –40 to +85
–65 to +150
0 to +13.0
–0.5 to +6.5
15
Voltage on EA/V pin to V
PP
SS
Voltage on any other pin to V
V
SS
Maximum I per I/O pin
mA
W
OL
Power dissipation (based on package heat transfer limitations, not
device power consumption)
1.5
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise
SS
noted.
13
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V (87C52)
CC SS
T
amb
= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V (80C32)
CC SS
TEST
LIMITS
1
SYMBOL
PARAMETER
CONDITIONS
MIN
–0.5
0
TYP
MAX
0.2V –0.1
UNIT
V
7
V
V
V
V
V
V
V
Input low voltage, except EA
IL
CC
7
Input low voltage to EA
0.2V –0.3
V
IL1
IH
CC
7
Input high voltage, except XTAL1, RST
0.2V +0.9
V
CC
V
CC
+0.5
+0.5
V
CC
7
Input high voltage, XTAL1, RST
0.7V
V
IH1
OL
OL1
OH
CC
9
2
Output low voltage, ports 1, 2, 3
I
I
I
= 1.6mA
0.45
0.45
V
OL
OL
OH
9
2
Output low voltage, port 0, ALE, PSEN
= 3.2mA
V
3
Output high voltage, ports 1, 2, 3, ALE, PSEN
= –60µA,
= –25µA
= –10µA
2.4
V
V
V
I
I
0.75V
OH
OH
CC
CC
0.9V
V
OH1
Output high voltage (port 0 in external bus mode)
I
I
= –800µA,
= –300µA
2.4
V
V
V
OH
OH
I
0.75V
CC
CC
= –80µA
0.9V
OH
7
I
I
I
I
Logical 0 input current, ports 1, 2, 3
V
= 0.45V
–50
–650
±10
µA
µA
µA
IL
IN
7
Logical 1-to-0 transition current, ports 1, 2, 3
See note 4
= V or V
IH
TL
LI
Input leakage current, port 0
V
IN
IL
7
Power supply current:
See note 6
CC
5
Active mode @ 16MHz
11.5
1.3
3
32
5
50
mA
mA
µA
Idle mode @ 16MHz
Power-down mode
T
amb
= 0 to 70°C
T
amb
= –40 to +85°C
75
µA
R
C
Internal reset pull-down resistor
50
300
15
kΩ
RST
IO
10
Pin capacitance
pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no
OL
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specification when the
OH
CC
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V is approximately 2V.
IN
5. I
at other frequencies is given by: Active mode: I
= 1.5 × FREQ + 8.0: Idle mode: I
= 0.14 × FREQ +2.31,
CCMAX
CCMAX
CCMAX
where FREQ is the external oscillator frequency in MHz. I
is given in mA. See Figure 12.
CCMAX
6. See Figures 13 through 16 for I test conditions.
CC
7. These values apply only to T
= 0°C to +70°C. For T
= –40°C to +85°C, see table on previous page.
amb
amb
8. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
9. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
15mA (*NOTE: This is 85°C specification.)
OL
Maximum I per 8-bit port:
26mA
67mA
OL
Maximum total I for all outputs:
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
10.This limit is for plastic packages. For ceramic packages, the maximum limit is 20pF.
14
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
AC ELECTRICAL CHARACTERISTICS
1, 2, 3
T
amb
= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V (87C52)
CC SS
16MHz CLOCK
VARIABLE CLOCK
SYMBOL FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/t
5
Oscillator frequency
Speed versions
CLCL
: E
3.5
16
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
5
5
5
5
5
5
5
5
5
5
5
ALE pulse width
85
22
32
2t
–40
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
t
–40
AVLL
LLAX
LLIV
CLCL
CLCL
t
–30
150
82
4t
3t
–100
CLCL
32
t
–30
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
142
3t
–45
CLCL
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–105
CLCL
0
0
37
207
10
t
–25
CLCL
5t
–105
CLCL
10
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
6, 7
6, 7
6, 7
6, 7
6, 7
6, 7
6, 7
6, 7
6, 7
6, 7
6, 7
7
RD pulse width
275
275
6t
–100
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
147
5t
–165
CLCL
0
0
65
2t
–60
CLCL
350
397
239
8t
CLCL
9t
CLCL
–150
–165
AVDV
LLWL
137
122
13
3t
–50
3t
+50
CLCL
CLCL
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
4t
t
–130
–50
AVWL
QVWX
WHQX
QVWH
RLAZ
WHLH
CLCL
CLCL
CLCL
CLCL
13
t
–50
Data valid to WR high
287
7t
–150
6, 7
6, 7
RD low to address float
RD or WR high to ALE high
0
0
23
103
t
–40
t
+40
CLCL
CLCL
External Clock
t
t
t
t
9
9
9
9
High time
Low time
Rise time
Fall time
20
20
20
20
t
–t
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
CLCL CLCX
t
–t
CLCL CHCX
20
20
20
20
Shift Register
t
t
t
t
t
8
8
8
8
8
Serial port clock cycle time
750
492
8
12t
ns
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t
–133
QVXH
XHQX
XHDX
XHDV
CLCL
2t
CLCL
–117
0
0
492
10t
–133
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 80C32/52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. See application note AN457 for external memory interface.
15
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
AC ELECTRICAL CHARACTERISTICS
1, 2, 3
T
amb
= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V
CC SS
24MHz CLOCK
VARIABLE CLOCK
33MHz CLOCK
SYMBOL FIGURE
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
1/t
5
Oscillator frequency
Speed versions : I
: N
CLCL
3.5
24
MHz
3.5
21
5
33
t
t
t
t
t
t
t
t
t
t
t
5
5
5
5
5
5
5
5
5
5
5
ALE pulse width
43
17
17
2t
–40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
t
–25
AVLL
LLAX
LLIV
CLCL
CLCL
–25
5
102
65
4t
3t
–65
56
CLCL
17
80
t
–25
5
0
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
3t
–45
46
31
CLCL
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–60
CLCL
0
0
17
128
10
t
–25
5
CLCL
5t
–80
72
10
CLCL
10
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
6, 7
6, 7
6, 7
6, 7
6, 7
6, 7
6, 7
6, 7
6, 7
6, 7
6, 7
7
RD pulse width
150
150
6t
–100
–100
82
82
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
118
5t
2t
–90
–28
62
CLCL
0
0
0
55
33
92
CLCL
183
210
175
8t
–150
–165
CLCL
CLCL
9t
108
141
AVDV
LLWL
75
92
3t
–50
–75
3t
CLCL
+50
41
46
0.3
5
CLCL
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
4t
AVWL
QVWX
WHQX
QVWH
RLAZ
WHLH
CLCL
12
t
t
–30
CLCL
CLCL
CLCL
17
–25
Data valid to WR high
162
7t
–130
82
6, 7
6, 7
RD low to address float
RD or WR high to ALE high
0
0
0
5
17
67
t
–25
t
+25
5
CLCL
CLCL
External Clock
t
t
t
t
9
9
9
9
High time
Low time
Rise time
Fall time
17
17
17
17
t
–t
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
CLCL CLCX
t
–t
CLCL CHCX
5
5
5
5
Shift Register
t
t
t
t
t
8
8
8
8
8
Serial port clock cycle time
505
283
3
12t
363
170
19
ns
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t –133
CLCL
QVXH
XHQX
XHDX
XHDV
2t
CLCL
–80
0
0
0
283
10t
–133
170
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 8XC52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.
4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz
“AC Electrial Characteristics”, page 15.
16
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
P – PSEN
Q – Output data
R – RD signal
t – Time
A – Address
V – Valid
C – Clock
D – Input data
H – Logic level high
W– WR signal
X – No longer a valid logic level
Z – Float
I – Instruction (program memory contents)
L – Logic level low, or ALE
Examples: t
= Time for address valid to ALE low.
= Time for ALE low to PSEN low.
AVLL
t
LLPL
t
LHLL
ALE
t
t
LLPL
AVLL
t
PLPH
t
LLIV
t
PLIV
PSEN
t
LLAX
t
PXIZ
t
PLAZ
t
PXIX
A0–A7
INSTR IN
A0–A7
PORT 0
PORT 2
t
AVIV
A0–A15
A8–A15
SU00006
Figure 5. External Program Memory Read Cycle
ALE
PSEN
RD
t
WHLH
t
LLDV
t
t
LLWL
RLRH
t
RHDZ
t
LLAX
t
t
RLDV
AVLL
t
RLAZ
t
RHDX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
AVWL
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00025
Figure 6. External Data Memory Read Cycle
17
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
ALE
t
WHLH
PSEN
t
t
WLWH
LLWL
WR
t
LLAX
t
t
WHQX
t
AVLL
QVWX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
INSTR IN
t
AVWL
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00069
Figure 7. External Data Memory Write Cycle
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
0
1
2
3
4
5
6
7
WRITE TO SBUF
t
XHDX
t
SET TI
VALID
XHDV
INPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
SU00027
Figure 8. Shift Register Mode Timing
V
–0.5
CC
0.7V
CC
CC
0.45V
0.2V
–0.1
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
SU00009
Figure 9. External Clock Drive
18
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
V
–0.5
CC
0.2V
0.2V
+0.9
–0.1
CC
CC
0.45V
NOTE:
AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
CC
Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.
IH
IL
SU00010
Figure 10. AC Testing Input/Output
V
V
+0.1V
LOAD
V
V
–0.1V
TIMING
REFERENCE
POINTS
OH
V
LOAD
–0.1V
LOAD
+0.1V
OL
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded V /V level occurs. I /I ≥ ±20mA.
OH OL
OH OL
SU00011
Figure 11. Float Waveform
65
60
55
MAX ACTIVE MODE
MAX = 1.5 X FREQ. + 8.0
I
CC
50
45
40
35
I
mA
CC
30
25
20
15
10
5
TYP ACTIVE MODE
MAX IDLE MODE
TYP IDLE MODE
4MHz 8MHz 12MHz 16MHz 20MHz 24MHz 28MHz 32MHz 36MHz
FREQ AT XTAL1
SU00070B
Figure 12.
I
vs. FREQ
CC
Valid only within frequency specifications of the device under test
19
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
V
V
CC
CC
I
I
CC
CC
V
V
CC
CC
V
RST
V
V
CC
CC
CC
P0
EA
P0
EA
RST
(NC)
XTAL2
XTAL1
(NC)
XTAL2
XTAL1
CLOCK SIGNAL
CLOCK SIGNAL
V
V
SS
SS
SU00719
SU00720
Figure 13.
I
Test Condition, Active Mode
Figure 14.
I
Test Condition, Idle Mode
CC
CC
All other pins are disconnected
All other pins are disconnected
V
–0.5
CC
0.7V
CC
CC
0.45V
0.2V
–0.1
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
SU00009
Figure 15. Clock Signal Waveform for I Tests in Active and Idle Modes
CC
t
= t
= 5ns
CHCL
CLCH
V
CC
CC
I
CC
V
CC
V
RST
P0
EA
(NC)
XTAL2
XTAL1
V
SS
SU00016
Figure 16.
I
Test Condition, Power Down Mode
CC
All other pins are disconnected. V = 2V to 5.5V
CC
20
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
Program Verification
EPROM CHARACTERISTICS
If security bit 2 has not been programmed, the on-chip program
memory can be read out for program verification. The address of the
program memory locations to be read is applied to ports 1 and 2 as
shown in Figure 19. The other pins are held at the ‘Verify Code Data’
levels indicated in Table 6. The contents of the address location will
be emitted on port 0. External pull-ups are required on port 0 for this
operation.
The 87C52 is programmed by using a modified Quick-Pulse
Programming algorithm. It differs from older methods in the value
used for V (programming supply voltage) and in the width and
PP
number of the ALE/PROG pulses.
The 87C52 contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as an 87C52 manufactured by
Philips.
If the encryption table has been programmed, the data presented at
port 0 will be the exclusive NOR of the program byte with one of the
encryption bytes. The user will have to know the encryption table
contents in order to correctly decode the verification data. The
encryption table itself cannot be read out.
Table 6 shows the logic levels for reading the signature byte, and for
programming the program memory, the encryption table, and the
security bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 17 and 18. Figure 19 shows the
circuit configuration for normal program memory verification.
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P3.6 and P3.7
need to be pulled to a logic low. The values are:
(030H) = 15H indicates manufactured by Philips
(031H) = 97H indicates 87C52
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in
Figure 17. Note that the 87C52 is running with a 4 to 6MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 6, and
which satisfies the timing specifications, is suitable.
The address of the EPROM location to be programmed is applied to
ports 1 and 2, as shown in Figure 17. The code byte to be
programmed into that location is applied to port 0. RST, PSEN and
pins of ports 2 and 3 specified in Table 6 are held at the ‘Program
Code Data’ levels indicated in Table 6. The ALE/PROG is pulsed
low 25 times as shown in Figure 18.
Erasure Characteristics
Erasure of the EPROM begins to occur when the chip is exposed to
light with wavelengths shorter than approximately 4,000 angstroms.
Since sunlight and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about
1 week in sunlight, or 3 years in room level fluorescent lighting)
could cause inadvertent erasure. For this and secondary effects,
it is recommended that an opaque label be placed over the
window. For elevated temperature or environments where solvents
are being used, apply Kapton tape Fluorglas part number 2345–5, or
equivalent.
To program the encryption table, repeat the 25 pulse programming
sequence for addresses 0 through 1FH, using the ‘Pgm Encryption
Table’ levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.
To program the security bits, repeat the 25 pulse programming
sequence using the ‘Pgm Security Bit’ levels. After one security bit is
programmed, further programming of the code memory and
encryption table is disabled. However, the other security bit can still
be programmed.
The recommended erasure procedure is exposure to ultraviolet light
(at 2537 angstroms) to an integrated dose of at least 15W-s/cm .
Exposing the EPROM to an ultraviolet lamp of 12,000µW/cm rating
for 20 to 39 minutes, at a distance of about 1 inch, should be
sufficient.
2
Note that the EA/V pin must not be allowed to go above the
2
PP
maximum specified V level for any amount of time. Even a narrow
PP
glitch above that voltage can cause permanent damage to the
device. The V source should be well regulated and free of glitches
PP
Erasure leaves the array in an all 1s state.
and overshoot.
Table 6. EPROM Programming Modes
MODE
Read signature
RST
PSEN
ALE/PROG
EA/V
P2.7
P2.6
P3.7
P3.6
PP
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
Program code data
Verify code data
Pgm encryption table
Pgm security bit 1
0*
1
V
PP
1
0*
0*
0*
V
PP
PP
PP
V
V
Pgm security bit 2
NOTES:
1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. V = 12.75V ±0.25V.
PP
3. V = 5V±10% during programming and verification.
CC
4. *ALE/PROG receives 25 programming pulses while V is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a
PP
minimum of 10µs.
Trademark phrase of Intel Corporation.
21
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
+5V
V
CC
P0
A0–A7
PGM DATA
+12.75V
P1
1
1
1
RST
P3.6
EA/V
PP
25 100µs PULSES TO GROUND
ALE/PROG
PSEN
0
1
87C52
P3.7
XTAL2
P2.7
0
P2.6
4–6MHz
XTAL1
A8–A12
P2.0–P2.4
V
SS
SU00071
Figure 17. Programming Configuration
25 PULSES
1
0
ALE/PROG:
ALE/PROG:
10µs MIN
100µs+10
1
0
SU00018
Figure 18. PROG Waveform
+5V
V
CC
P0
A0–A7
PGM DATA
P1
1
1
1
RST
P3.6
1
1
EA/V
PP
ALE/PROG
PSEN
0
87C52
P3.7
0 ENABLE
XTAL2
P2.7
0
P2.6
4–6MHz
XTAL1
A8–A12
P2.0–P2.4
V
SS
SU00072
Figure 19. Program Verification
22
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
T
amb
= 21°C to +27°C, V = 5V±10%, V = 0V (See Figure 20)
CC SS
SYMBOL
PARAMETER
MIN
MAX
13.0
50
UNIT
V
V
PP
Programming supply voltage
Programming supply current
Oscillator frequency
12.5
I
PP
mA
MHz
1/t
CLCL
4
6
t
t
t
t
t
t
t
t
t
t
t
t
Address setup to PROG low
Address hold after PROG
Data setup to PROG low
Data hold after PROG
48t
AVGL
CLCL
CLCL
CLCL
CLCL
CLCL
48t
48t
48t
48t
GHAX
DVGL
GHDX
EHSH
SHGL
GHSL
GLGH
AVQV
ELQZ
EHQZ
GHGL
P2.7 (ENABLE) high to V
PP
V
PP
V
PP
setup to PROG low
hold after PROG
10
10
90
µs
µs
µs
PROG width
110
Address to data valid
48t
CLCL
CLCL
CLCL
ENABLE low to data valid
Data float after ENABLE
PROG high to PROG low
48t
48t
0
10
µs
PROGRAMMING*
VERIFICATION*
ADDRESS
P1.0–P1.7
P2.0–P2.4
ADDRESS
t
AVQV
PORT 0
DATA IN
DATA OUT
t
t
t
DVGL
GHDX
GHAX
t
AVGL
ALE/PROG
t
t
GLGH
GHGL
t
t
SHGL
GHSL
LOGIC 1
LOGIC 1
EA/V
PP
LOGIC 0
t
t
t
EHSH
ELQV
EHQZ
P2.7
ENABLE
SU00020
NOTE:
*
FOR PROGRAMMING VERIFICATION SEE FIGURE 17.
FOR VERIFICATION CONDITIONS SEE FIGURE 19.
Figure 20. EPROM Programming and Verification
23
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
24
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
25
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
0590B
40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE)
853–0590B 06688
26
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
1472A
44-PIN CERQUAD J-BEND (K) PACKAGE
853-1472A 05854
27
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
28
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
NOTES
29
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1996
All rights reserved. Printed in U.S.A.
Telephone 800-234-7381
INTEGRATED CIRCUITS
80C52/80C54/80C58
CMOS single-chip 8-bit microcontrollers
Product specification
IC20 Data Handbook
1996 Aug 16
Philips
Semiconductors
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
DESCRIPTION
PIN CONFIGURATIONS
The 80C52/80C54/80C58 Single-Chip 8-Bit Microcontroller is
manufactured in an advanced CMOS process and is a derivative of
the 80C51 microcontroller family. The 80C52/80C54/80C58 has the
same instruction set as the 80C51.
T2/P1.0
40
39
V
CC
1
2
3
T2EX/P1.1
P0.0/AD0
P1.2
38 P0.1/AD1
37 P0.2/AD2
This device provides architectural enhancements that make it
applicable in a variety of applications for general control systems.
The 80C52 contains 8k × 8 ROM memory, the 80C54 contains
16k × 8 ROM memory, and 80C58 contains 32k × 8 ROM memory, a
volatile 256 × 8 read/write data memory, four 8-bit I/O ports, three
16-bit timer/event counters, a multi-source, four-priority-level, nested
interrupt structure, an enhanced UART and on-chip oscillator and
timing circuits. For systems that require extra capability, the
80C52/54/58 can be expanded using standard TTL compatible
memories and logic.
P1.3
P1.4
4
5
36
P0.3/AD3
35 P0.4/AD4
34
P1.5
P1.6
P1.7
RST
6
7
8
9
P0.5/AD5
33 P0.6/AD6
32
P0.7/AD7
31 EA
30
DUAL
IN-LINE
PACKAGE
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
Its added features make it an even more powerful microcontroller for
applications that require pulse width modulation, high-speed I/O and
up/down counting capabilities such as motor control. It also has a
more versatile serial channel that facilitates multiprocessor
communications.
ALE
29 PSEN
28
13
INT1/P3.3
P2.7/A15
27 P2.6/A14
26
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
XTAL1 19
See 87C52/80C32 and 87C54/87C58 data sheets for EPROM and
ROMless devices.
P2.5/A13
25 P2.4/A12
24 P2.3/A11
FEATURES
• 80C51 central processing unit
• Full static operation
23
22
P2.2/A10
P2.1/A9
P2.0/A8
21
V
20
SS
• 8k × 8 ROM: 80C52;
SU00740
16k × 8 ROM: 80C54;
32k × 8 ROM: 80C58;
all capable of addressing external memory to 64k bytes
– Two level program security system
– 64 byte encryption array
• 256 × 8 RAM, expandable externally to 64k bytes
• Speed range up to 33MHz
• Operating voltage 5V ±10%
• Three 16-bit timer/counters
– T2 is an up/down counter
• 6 interrupt sources
• 4 level priority
• Four 8-bit I/O ports
• Full-duplex enhanced UART
– Framing error detection
– Automatic address recognition
• Power control modes
– Idle mode
– Power-down mode
• Once (On Circuit Emulation) Mode
• Five package styles
• Programmable clock out
• Low EMI (Inhibit ALE)
• Second DPTR register
• Asynchronous port reset
2
1996 Aug 16
853–1470 17196
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
ORDERING INFORMATION
ROM
8k × 8
ROM
16k × 8
ROM
32k × 8
TEMPERATURE RANGE °C
FREQ DRAWING
AND PACKAGE
MHz
16
16
16
16
16
16
24
24
24
24
24
24
33
33
33
33
33
33
NUMBER
SOT129-1
SOT187-2
SOT307-2
SOT129-1
SOT187-2
SOT307-2
SOT129-1
SOT187-2
SOT307-2
SOT129-1
SOT187-2
SOT307-2
SOT187-2
SOT129-1
SOT307-2
SOT187-2
SOT129-1
SOT307-2
P80C52EBPN P80C54EBPN P80C58EBPN
P80C52EBAA P80C54EBAA P80C58EBAA
P80C52EBBB P80C54EBBB P80C58EBBB
P80C52EFPN P80C54EFPN P80C58EFPN
P80C52EFA A P80C54EFA A P80C58EFA A
P80C52EFBB P80C54EFBB P80C58EFBB
P80C52IBP N P80C54IBP N P80C58IBP N
P80C52IBA A P80C54IBA A P80C58IBA A
P80C52IBB B P80C54IBB B P80C58IBB B
P80C52IFP N P80C54IFP N P80C58IFP N
P80C52IFA A P80C54IFA A P80C58IFA A
P80C52IFB B P80C54IFB B P80C58IFB B
P80C52NBAA P80C54NBAA P80C58NBAA
P80C52NBPN P80C54NBPN P80C58NBPN
P80C52NBBB P80C54NBBB P80C58NBBB
P80C52NFAA P80C54NFAA P80C58NFAA
P80C52NFPN P80C54NFPN P80C58NFPN
P80C52NFBB P80C54NFBB P80C58NFBB
0 to +70, Plastic Dual In-line Package
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Quad Flat Pack
–40 to +85, Plastic Dual In-line Package
–40 to +85, Plastic Leaded Chip Carrier
–40 to +85, Plastic Quad Flat Pack
0 to +70, Plastic Dual In-line Package
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Quad Flat Pack
–40 to +85, Plastic Dual In-line Package
–40 to +85, Plastic Leaded Chip Carrier
–40 to +85, Plastic Quad Flat Pack
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Dual In-line Package
0 to +70, Plastic Quad Flat Pack
–40 to +85, Plastic Leaded Chip Carrier
–40 to +85, Plastic Dual In-line Package
–40 to +85, Plastic Quad Flat Pack
LOGIC SYMBOL
V
V
SS
CC
XTAL1
ADDRESS AND
DATA BUS
XTAL2
T2
T2EX
RST
EA
PSEN
ALE
RxD
TxD
INT0
INT1
T0
ADDRESS BUS
T1
WR
RD
SU00732
3
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
BLOCK DIAGRAM
P0.0–P0.7
P2.0–P2.7
PORT 0
DRIVERS
PORT 2
DRIVERS
V
V
CC
SS
8
8
RAM ADDR
REGISTER
PORT 0
LATCH
PORT 2
LATCH
ROM
RAM
16
B
STACK
POINTER
ACC
REGISTER
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
BUFFER
ALU
SFRs
PC
INCRE-
MENTER
TIMERS
PSW
8
16
PROGRAM
COUNTER
PSEN
ALE
EA
MULTIPLE
DPTRs
TIMING
AND
CONTROL
RST
PORT 1
LATCH
PORT 3
LATCH
PD
OSCILLATOR
PORT 1
DRIVERS
PORT 3
DRIVERS
XTAL1
XTAL2
P1.0–P1.7
P3.0–P3.7
SU00733B
4
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Table 1.
80C52/80C54/80C58 Special Function Registers
DIRECT
DESCRIPTION
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
RESET
VALUE
SYMBOL
ADDRESS MSB
LSB
ACC*
AUXR#
AUXR1#
B*
Accumulator
Auxiliary
E0H
8EH
A2H
F0H
E7
–
E6
–
E5
–
E4
–
E3
–
E2
–
E1
–
E0
00H
AO
DPS
F0
xxxxxxx0B
xxxxxxx0B
00H
Auxiliary 1
B register
–
–
–
–
–
–
–
F7
F6
F5
F4
F3
F2
F1
DPTR:
DPH
DPL
Data Pointer (2 bytes)
Data Pointer High
Data Pointer Low
83H
82H
00H
00H
AF
EA
BF
–
AE
EC
BE
–
AD
ET2
BD
AC
ES
BC
PS
B4
AB
ET1
BB
AA
EX1
BA
A9
ET0
B9
A8
EX0
B8
IE*
Interrupt Enable
Interrupt Priority
Interrupt Priority High
Port 0
A8H
B8H
B7H
80H
90H
A0H
00H
IP*
PT2
B5
PT1
B3
PX1
B2
PT0
B1
PX0
B0
x0000000B
x0000000B
FFH
B7
–
B6
–
IPH#
P0*
P1*
P2*
P3*
PT2H
85
PSH
84
PT1H
83
PX1H PT0H
PX0H
80
87
86
82
AD2
92
81
AD1
91
AD7
97
AD6
96
AD5
95
AD4
94
AD3
93
AD0
90
Port 1
–
–
–
–
–
–
T2EX
A1
T2
FFH
A7
AD15
B7
RD
A6
AD14
B6
WR
A5
A4
A3
A2
A0
Port 2
AD13
B5
AD12
B4
AD11
B3
AD10
B2
AD9
B1
AD8
B0
FFH
Port 3
B0H
87H
T1
T0
INT1
INT0
TxD
RxD
FFH
1
2
PCON#
Power Control
SMOD1
D7
SMOD0
D6
–
POF
GF1
D3
GF0
D2
PD
D1
–
IDL
D0
P
00xx0000B
D5
F0
D4
PSW*
Program Status Word
D0H
CY
AC
RS1
RS0
OV
00H
RACAP2H
#
Timer 2 Capture High
Timer 2 Capture Low
CBH
CAH
00H
00H
RACAP2L
#
SADDR#
SADEN#
Slave Address
Slave Address Mask
A9H
B9H
00H
00H
SBUF
Serial Data Buffer
99H
xxxxxxxxB
9F
9E
9D
9C
9B
9A
99
TI
98
RI
SM0/FE
SCON*
SP
Serial Control
Stack Pointer
98H
81H
SM1
SM2
REN
TB8
RB8
00H
07H
8F
TF1
CF
TF2
–
8E
TR1
CE
8D
TF0
CD
8C
TR0
CC
8B
IE1
8A
IT1
CA
TR2
–
89
IE0
88
IT0
C8
TCON*
Timer Control
88H
00H
CB
C9
T2CON*
Timer 2 Control
C8H
EXF2
–
RCLK
–
TCLK
–
EXEN2
–
C/T2
T2OE
CP/RL2 00H
T2MOD#
TH0
TH1
TH2#
TL0
TL1
Timer 2 Mode Control
Timer High 0
Timer High 1
Timer High 2
Timer Low 0
C9H
8CH
8DH
CDH
8AH
8BH
CCH
DCEN xxxxxx00B
00H
00H
00H
00H
00H
00H
Timer Low 1
Timer Low 2
TL2#
TMOD
Timer Mode
89H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
*
SFRs are bit addressable.
#
–
SFRs are modified from or added to the 80C51 SFRs.
Reserved bits.
1. Reset value depends on reset source.
2. Bit will not be affected by Reset. POF is not present in 80C52.
5
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
PLASTIC QUAD FLAT PACK PIN FUNCTIONS
44
34
6
1
40
7
39
1
33
LCC
PQFP
11
23
17
29
18
28
12
Pin Function
22
Pin Function
Pin Function
Pin Function
Pin Function
Pin Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NC*
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
31
P2.7/A15
PSEN
ALE
NC*
EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
P1.5
P1.6
P1.7
RST
P3.0/RxD
NC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
NC*
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
SS
32
33
34
35
36
37
38
39
40
41
42
43
44
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0/RxD
NC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
NC*
EA
P0.7/AD7
XTAL1
V
SS
NC*
V
CC
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
NC*
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
V
CC
* DO NOT CONNECT
* DO NOT CONNECT
SU00741A
SU00742A
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP
LCC
QFP
16
TYPE NAME AND FUNCTION
V
V
20
40
22
44
I
I
Ground: 0V reference.
SS
38
Power Supply: This is the power supply voltage for normal, idle, and power-down
CC
operation.
P0.0–0.7
39–32 43–36 37–30
I/O
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the
code bytes during program verification. External pull-ups are required during program
verification.
P1.0–P1.7
1–8
2–9
40–44,
1–3
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 1 pins that are externally pulled low will source current because of the internal pull-ups.
(See DC Electrical Characteristics: I ). Port 1 also receives the low-order address byte
IL
during program memory verification. Alternate functions include:
T2 (P1.0): Timer/Counter 2 external count input/Clockout
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
40
41
42
43
44
1
I/O
I
I
I/O
I/O
I/O
I/O
I/O
2
3
P2.0–P2.7
21–28 24–31 18–25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I ). Port 2 emits the high-order address byte
IL
during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit
addresses (MOV @Ri), port 2 emits the contents of the P2 special function register.
6
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
PIN DESCRIPTIONS (Continued)
PIN NUMBER
MNEMONIC DIP
LCC
QFP
TYPE NAME AND FUNCTION
P3.0–P3.7
10–17
11,
5,
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
13–19 7–13
(See DC Electrical Characteristics: I ). Port 3 also serves the special features of the 80C51
IL
family, as listed below:
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
I
O
I
I
I
I
O
O
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
9
10
11
12
13
RST
ALE
9
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V permits a power-on reset using only an external
SS
capacitor to V
.
CC
30
33
27
O
Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or clocking. Note that one ALE
pulse is skipped during each access to external data memory. ALE can be disabled by
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.
PSEN
29
31
32
35
26
29
O
I
Program Store Enable: The read strobe to external program memory. When the
80C52/80C54/80C58 is executing code from the external program memory, PSEN is
activated twice each machine cycle, except that two PSEN activations are skipped during
each access to external data memory. PSEN is not activated during fetches from internal
program memory.
EA
External Access Enable: EA must be externally held low to enable the device to fetch code
from external program memory locations 0000H and 7FFFH. If EA is held high, the device
executes from internal program memory unless the program counter contains an address
greater than 7FFFH. If security bit 1 is programmed, EA will be internally latched on Reset.
XTAL1
19
18
21
20
15
14
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2
O
Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V + 0.5V or V – 0.5V, respectively.
CC
SS
7
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Figure 3). When reset is applied the DCEN=0 which means Timer 2
will default to counting up. If DCEN bit is set, Timer 2 can count up
or down depending on the value of the T2EX pin.
TIMER 2 OPERATION
Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an
event timer or an event counter, as selected by C/T2* in the special
function register T2CON (see Figure 1). Timer 2 has three operating
modes:Capture, Auto-reload (up or down counting) ,and Baud Rate
Generator, which are selected by bits in the T2CON as shown in
Table 2.
Figure 4 shows Timer 2 which will count up automatically since
DCEN=0. In this mode there are two options selected by bit EXEN2
in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH
and sets the TF2 (Overflow Flag) bit upon overflow. This causes the
Timer 2 registers to be reloaded with the 16-bit value in RCAP2L
and RCAP2H.
Capture Mode
The values in RCAP2L and RCAP2H are preset by software means.
If EXEN2=1, then a 16-bit reload can be triggered either by an
overflow or by a 1-to-0 transition at input T2EX. This transition also
sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be
generated when either TF2 or EXF2 are 1.
In the capture mode there are two options which are selected by bit
EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or
counter (as selected by C/T2* in T2CON) which, upon overflowing
sets bit TF2, the timer 2 overflow bit. This bit can be used to
generate an interrupt (by enabling the Timer 2 interrupt bit in the
IE register/SFR table). If EXEN2= 1, Timer 2 operates as described
above, but with the added feature that a 1- to -0 transition at external
input T2EX causes the current value in the Timer 2 registers, TL2
and TH2, to be captured into registers RCAP2L and RCAP2H,
respectively. In addition, the transition at T2EX causes bit EXF2 in
T2CON to be set, and EXF2 like TF2 can generate an interrupt
(which vectors to the same location as Timer 2 overflow interrupt.
The Timer 2 interrupt service routine can interrogate TF2 and EXF2
to determine which event caused the interrupt). The capture mode is
illustrated in Figure 2 (There is no reload value for TL2 and TH2 in
this mode. Even when a capture event occurs from T2EX, the
counter keeps on counting T2EX pin transitions or osc/12 pulses.).
In Figure 5 DCEN=1 which enables Timer 2 to count up or down.
This mode allows pin T2EX to control the direction of count. When a
logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will
overflow at 0FFFFH and set the TF2 flag, which can then generate
an interrupt, if the interrupt is enabled. This timer overflow also
causes the 16–bit value in RCAP2L and RCAP2H to be reloaded
into the timer registers TL2 and TH2.
When a logic 0 is applied at pin T2EX this causes Timer 2 to count
down. The timer will underflow when TL2 and TH2 become equal to
the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets
the TF2 flag and causes 0FFFFH to be reloaded into the timer
registers TL2 and TH2.
Auto-Reload Mode (Up or Down Counter)
The external flag EXF2 toggles when Timer 2 underflows or
overflows. This EXF2 bit can be used as a 17th bit of resolution if
needed. The EXF2 flag does not generate an interrupt in this mode
of operation.
In the 16-bit auto-reload mode, Timer 2 can be configured (as either
a timer or counter (C/T2* in T2CON)) then programmed to count up
or down. The counting direction is determined by bit DCEN(Down
Counter Enable) which is located in the T2MOD register (see
(MSB)
(LSB)
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Symbol
Position
Name and Significance
TF2
T2CON.7
T2CON.6
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set
when either RCLK or TCLK = 1.
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2
interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down
counter mode (DCEN = 1).
RCLK
TCLK
T2CON.5
T2CON.4
T2CON.3
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock
in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock
in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
TR2
T2CON.2
T2CON.1
Start/stop control for Timer 2. A logic 1 starts the timer.
C/T2
Timer or counter select. (Timer 2)
0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
CP/RL2
T2CON.0
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When
cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when
EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload
on Timer 2 overflow.
SU00728
Figure 1. Timer/Counter 2 (T2CON) Control Register
8
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Table 2. Timer 2 Operating Modes
RCLK + TCLK
CP/RL2
TR2
1
MODE
0
0
1
X
0
1
16-bit Auto-reload
16-bit Capture
Baud rate generator
(off)
1
X
X
1
0
OSC
÷ 12
C/T2 = 0
TL2
(8-bits)
TH2
(8-bits)
TF2
C/T2 = 1
T2 Pin
Control
TR2
Capture
Transition
Detector
Timer 2
Interrupt
RCAP2L
RCAP2H
T2EX Pin
EXF2
Control
EXEN2
SU00066
Figure 2. Timer 2 in Capture Mode
T2MOD
Symbol
Address = 0C9H
Not Bit Addressable
—
Reset Value = XXXX XX00B
—
6
—
5
—
4
—
3
—
2
T2OE
DCEN
0
Bit
7
1
Function
—
Not implemented, reserved for future use.*
Timer 2 Output Enable bit. See details in Programmable Clock-Out.
Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.
T2OE
DCEN
*
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.
In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
SU00746
Figure 3. Timer 2 Mode (T2MOD) Control Register
9
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
OSC
÷ 12
C/T2 = 0
C/T2 = 1
TL2
(8-BITS)
TH2
(8-BITS)
T2 PIN
CONTROL
TR2
RELOAD
TRANSITION
DETECTOR
RCAP2L
RCAP2H
TF2
TIMER 2
INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
SU00067
Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)
(DOWN COUNTING RELOAD VALUE)
FFH
FFH
TOGGLE
EXF2
OSC
÷12
C/T2 = 0
OVERFLOW
TL2
TH2
TF2
INTERRUPT
C/T2 = 1
T2 PIN
CONTROL
TR2
COUNT
DIRECTION
1 = UP
0 = DOWN
RCAP2L
RCAP2H
(UP COUNTING RELOAD VALUE)
T2EX PIN
SU00730
Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)
10
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Timer 1
Overflow
÷ 2
NOTE: OSC. Freq. is divided by 2, not 12.
“0”
“0”
“1”
OSC
÷ 2
C/T2 = 0
C/T2 = 1
SMOD
RCLK
“1”
TL2
(8-bits)
TH2
(8-bits)
T2 Pin
Control
÷ 16
RX Clock
“1”
“0”
TR2
Reload
TCLK
Transition
Detector
RCAP2L
RCAP2H
÷ 16
TX Clock
Timer 2
Interrupt
T2EX Pin
EXF2
Control
EXEN2
Note availability of additional external interrupt.
SU00068
Figure 6. Timer 2 in Baud Rate Generator Mode
The baud rates in modes 1 and 3 are determined by Timer 2’s
overflow rate given below:
Table 3. Timer 2 Generated Commonly Used
Baud Rates
Timer 2 Overflow Rate
Modes 1 and 3 Baud Rates +
Timer 2
16
Baud Rate
Osc Freq
RCAP2H
RCAP2L
The timer can be configured for either “timer” or “counter” operation.
In many applications, it is configured for “timer” operation (C/T2*=0).
Timer operation is different for Timer 2 when it is being used as a
baud rate generator.
375K
9.6K
2.8K
2.4K
1.2K
300
110
300
110
12MHz
12MHz
12MHz
12MHz
12MHz
12MHz
12MHz
6MHz
FF
FF
FF
FF
FE
FB
F2
FD
F9
FF
D9
B2
64
C8
1E
AF
8F
57
Usually, as a timer it would increment every machine cycle (i.e., 1/12
the oscillator frequency). As a baud rate generator, it increments
every state time (i.e., 1/2 the oscillator frequency). Thus the baud
rate formula is as follows:
Modes 1 and 3 Baud Rates =
6MHz
Oscillator Frequency
[32 [65536 * (RCAP2H, RCAP2L)]]
Baud Rate Generator Mode
Where: (RCAP2H, RCAP2L)= The content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.
Bits TCLK and/or RCLK in T2CON (Table 2) allow the serial port
transmit and receive baud rates to be derived from either Timer 1 or
Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit
baud rate generator. When TCLK= 1, Timer 2 is used as the serial
port transmit baud rate generator. RCLK has the same effect for the
serial port receive baud rate. With these two bits, the serial port can
have different receive and transmit baud rates – one generated by
Timer 1, the other by Timer 2.
The Timer 2 as a baud rate generator mode shown in Figure 6, is
valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a
rollover in TH2 does not set TF2, and will not generate an interrupt.
Thus, the Timer 2 interrupt does not have to be disabled when
Timer 2 is in the baud rate generator mode. Also if the EXEN2
(T2 external enable flag) is set, a 1-to-0 transition in T2EX
(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but
will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2).
Therefore when Timer 2 is in use as a baud rate generator, T2EX
can be used as an additional external interrupt, if needed.
Figure 6 shows the Timer 2 in baud rate generation mode. The baud
rate generation mode is like the auto-reload mode,in that a rollover
in TH2 causes the Timer 2 registers to be reloaded with the 16-bit
value in registers RCAP2H and RCAP2L, which are preset by
software.
11
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
When Timer 2 is in the baud rate generator mode, one should not try
to read or write TH2 and TL2. As a baud rate generator, Timer 2 is
incremented every state time (osc/2) or asynchronously from pin T2;
under these conditions, a read or write of TH2 or TL2 may not be
accurate. The RCAP2 registers may be read, but should not be
written to, because a write might overlap a reload and cause write
and/or reload errors. The timer should be turned off (clear TR2)
before accessing the Timer 2 or RCAP2 registers.
To obtain the reload value for RCAP2H and RCAP2L, the above
equation can be rewritten as:
fOSC
RCAP2H, RCAP2L + 65536 * ǒ
Ǔ
32 Baud Rate
Timer/Counter 2 Set-up
Except for the baud rate generator mode, the values given for
T2CON do not include the setting of the TR2 bit. Therefore, bit TR2
must be set, separately, to turn the timer on. see Table 4 for set-up
of Timer 2 as a timer. Also see Table 5 for set-up of Timer 2 as a
counter.
Table 3 shows commonly used baud rates and how they can be
obtained from Timer 2.
Summary Of Baud Rate Equations
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked
through pin T2(P1.0) the baud rate is:
3
POWER OFF FLAG
Timer 2 Overflow Rate
Baud Rate +
The Power Off Flag (POF) is set by on-chip circuitry when the V
CC
16
level on the 80C54/80C58 rises from 0 to 5V. The POF bit can be
set or cleared by software allowing a user to determine if the reset is
If Timer 2 is being clocked internally, the baud rate is:
the result of a power-on or a warm start after powerdown. The V
CC
fOSC
level must remain above 3V for the POF to remain unaffected by the
level.
Baud Rate +
[32 [65536 * (RCAP2H, RCAP2L)]]
V
CC
Where f
= Oscillator Frequency
OSC
Table 4. Timer 2 as a Timer
T2CON
MODE
INTERNAL CONTROL
(Note 1)
EXTERNAL CONTROL
(Note 2)
16-bit Auto-Reload
00H
01H
34H
24H
14H
08H
09H
36H
26H
16H
16-bit Capture
Baud rate generator receive and transmit same baud rate
Receive only
Transmit only
Table 5. Timer 2 as a Counter
TMOD
MODE
INTERNAL CONTROL
(Note 1)
EXTERNAL CONTROL
(Note 2)
16-bit
02H
03H
0AH
0BH
Auto-Reload
NOTES:
1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate
generator mode.
3. POF not present in 80C52.
12
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
oscillator but bringing the pin back high completes the exit. Once the
interrupt is serviced, the next instruction to be executed after RETI
will be the one following the instruction that put the device into
Power Down.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
Design Consideration
• When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal rest algorithm takes
control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is terminated by reset,
the instruction following the one that invokes Idle should not be
one that writes to a port pin or to external memory.
Reset
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
ONCE Mode
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems using the 80C52/54/58 without removing the
device from the circuit. The ONCE Mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN is high;
V
CC
and RST must come up at the same time for a proper start-up.
Ports 1, 2, and 3 will asynchronously be driven to their reset
condition when a voltage above V
(min.) is applied to RESET.
IH1
2. Hold ALE low as RST is deactivated.
Idle Mode
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the 80C52/54/58 is
in this mode, an emulator or test CPU can be used to drive the
circuit. Normal operation is restored when a normal reset is applied.
In the idle mode (see Table 6), the CPU puts itself to sleep while all
of the on-chip peripherals stay active. The instruction to invoke the
idle mode is the last instruction executed in the normal operating
mode before the idle mode is activated. The CPU contents, the
on-chip RAM, and all of the special function registers remain intact
during this mode. The idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up at the
interrupt service routine and continued), or by a hardware reset
which starts the processor in the same manner as a power-on reset.
Programmable Clock-Out
The 80C52/54/58 has a new feature. A 50% duty cycle clock can be
programmed to come out on P1.0. This pin, besides being a regular
I/O pin, has two alternate functions. It can be programmed:
1. to input the external clock for Timer/Counter 2, or
2. to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a
16MHz operating frequency.
Power-Down Mode
To save even more power, a Power Down mode (see Table 6) can
be invoked by software. In this mode, the oscillator is stopped and
the instruction that invoked Power Down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
their values until the Power Down mode is terminated.
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in
T2CON) must be cleared and bit T2OE in T2MOD must be set. Bit
TR2 (T2CON.2) also must be set to start the timer.
The Clock-Out frequency depends on the oscillator frequency and
the reload value of Timer 2 capture registers (RCAP2H, RCAP2L)
as shown in this equation:
On the 80C52/54/58 either a hardware reset or external interrupt
can be used to exit from Power Down. Reset redefines all the SFRs
but does not change the on-chip RAM. An external interrupt allows
both the SFRs and the on-chip RAM to retain their values.
Oscillator Frequency
To properly terminate Power Down the reset or external interrupt
4 (65536 * RCAP2H, RCAP2L)
should not be executed before V is restored to its normal
CC
In the Clock-Out mode Timer 2 roll-overs will not generate an
interrupt. This is similar to when it is used as a baud-rate generator.
It is possible to use Timer 2 as a baud-rate generator and a clock
generator simultaneously. Note, however, that the baud-rate and the
Clock-Out frequency will be the same.
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10ms).
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the
Table 6. External Pin Status During Idle and Power-Down Mode
PROGRAM
MEMORY
MODE
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Idle
Idle
Internal
1
1
0
0
1
1
0
0
Data
Float
Data
Float
Data
Data
Data
Data
Data
Address
Data
Data
Data
Data
Data
External
Internal
Power-down
Power-down
External
Data
13
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Slave 1
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1110
1100 000X
Enhanced UART
The UART operates in all of the usual modes that are described in
the first section of Data Handbook IC20, 80C51-Based 8-Bit
Microcontrollers. In addition the UART can perform framing error
detect by looking for missing stop bits, and automatic address
recognition. The 80C52/54/58 UART also fully supports
multiprocessor communication as does the standard 80C51 UART.
In the above example SADDR is the same and the SADEN data is
used to differentiate between the two slaves. Slave 0 requires a 0 in
bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
When used for framing error detect the UART looks for missing stop
bits in the communication. A missing bit will set the FE bit in the
SCON register. The FE bit shares the SCON.7 bit with SM0 and the
function of SCON.7 is determined by PCON.6 (SMOD0) (see
Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When used as FE
SCON.7 can only be cleared by software. Refer to Figure 8.
In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:
Automatic Address Recognition
Slave 0
Slave 1
Slave 2
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1001
1100 0XX0
Automatic Address Recognition is a feature which allows the UART
to recognize certain addresses in the serial bit stream by using
hardware to make the comparisons. This feature saves a great deal
of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART
modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be
automatically set when the received byte contains either the “Given”
address or the “Broadcast” address. The 9 bit mode requires that
the 9th information bit is a 1 to indicate that the received information
is an address and not data. Automatic address recognition is shown
in Figure 9.
SADDR
SADEN
Given
=
=
=
1110 0000
1111 1010
1110 0X0X
SADDR
SADEN
Given
=
=
=
1110 0000
1111 1100
1110 00XX
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary t make bit 2 = 1 to exclude slave 2.
The 8 bit mode is called Mode 1. In this mode the RI flag will be set
if SM2 is enabled and the information received has a valid stop bit
following the 8 address bits and the information is either a Given or
Broadcast address.
Mode 0 is the Shift Register mode and SM2 is ignored.
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are teated as
don’t-cares. In most cases, interpreting the don’t-cares as ones, the
broadcast address will be FF hexadecimal.
Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to define which bits in the
SADDR are to b used and which bits are “don’t care”. The SADEN
mask can be logically ANDed with the SADDR to create the “|Given”
address which the master will use for addressing each of the slaves.
Use of the Given address allows multiple slaves to be recognized
while excluding others. The following examples will help to show the
versatility of this scheme:
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are leaded with 0s. This produces a given address
of all “don’t cares” as well as a Broadcast address of all “don’t
cares”. this effectively disables the Automatic Addressing mode and
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.
Slave 0
SADDR
SADEN
Given
=
=
=
1100 0000
1111 1101
1100 00X0
14
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
SCON Address = 98H
Reset Value = 0000 0000B
Bit Addressable
SM0/FE
SM1
SM2
REN
TB8
RB8
Tl
Rl
Bit:
7
6
5
4
3
2
1
0
(SMOD0 = 0/1)*
Symbol
FE
Function
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
SM0
SM1
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0
SM1
Mode
Description
Baud Rate**
f /12
OSC
0
0
1
1
0
1
0
1
0
1
2
3
shift register
8-bit UART
9-bit UART
9-bit UART
variable
/64 or f
f
/32
OSC
OSC
variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
REN
TB8
RB8
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Tl
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Rl
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
NOTE:
*SMOD0 is located at PCON6.
**f = oscillator frequency
OSC
SU00043
Figure 7. SCON: Serial Port Control Register
D0
D1
D2
D3
D4
D5
D6
D7
D8
START
BIT
DATA BYTE
ONLY IN
MODE 2, 3
STOP
BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)
SM0 TO UART MODE CONTROL
SCON
(98H)
SM0 / FE
SMOD1
SM1
SM2
REN
POF
TB8
GF1
RB8
GF0
TI
RI
PCON
(87H)
SMOD0
–
PD
IDL
0 : SCON.7 = SM0
1 : SCON.7 = FE
SU00747
Figure 8. UART Framing Error Detection
15
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
D0
D1
D2
D3
D4
D5
D6
D7
D8
SCON
(98H)
SM0
SM1
SM2
REN
1
TB8
X
RB8
TI
RI
1
1
1
0
1
RECEIVED ADDRESS D0 TO D7
PROGRAMMED ADDRESS
COMPARATOR
IN UART MODE 2 OR MODE 3 AND SM2 = 1:
INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”
– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES
– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00045
Figure 9. UART Multiprocessor Communication, Automatic Address Recognition
Interrupt Priority Structure
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
The 80C52/54/58 has a 6-source four-level interrupt structure. There
are 3 SFRs associated with the interrupts on the 80C52/54/58. They
are the IE and IP. (See Figures 10 and 11.) In addition, there is the
IPH (Interrupt Priority High) register that makes the four-level
interrupt structure possible. The IPH is located at SFR address B7H.
The structure of the IPH register and a description of its bits is
shown below:
IPH.x
IP.x
0
0
0
1
1
Level 0 (lowest priority)
Level 1
1
0
Level 2
1
Level 3 (highest priority)
IPH (Interrupt Priority High) (B7H)
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except there are four interrupt levels on the
80C52/54/58 rather than two as on the 80C51. An interrupt will be
serviced as long as an interrupt of equal or higher priority is not
already being serviced. If an interrupt of equal or higher level priority
is being serviced, the new interrupt will wait until it is finished before
being serviced. If a lower priority level interrupt is being serviced, it
will be stopped and the new interrupt serviced. When the new
interrupt is finished, the lower priority level interrupt that was
stopped will be completed.
7
–
6
–
5
4
3
2
1
0
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
IPH.0 PX0H External interrupt 0 priority high
IPH.1 PT0H Timer 0 interrupt priority high
IPH.2 PX1H External interrupt 1 priority high
IPH.3 PT1H Timer 1 interrupt priority high
IPH.4 PSH Serial Port interrupt high
IPH.5 PT2H Timer 2 interrupt priority high
IPH.6
IPH.7
—
—
Not implemented
Not implemented
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
Table 7.
Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR?
VECTOR ADDRESS
1
2
X0
T0
1
2
3
4
5
6
7
IE0
TP0
N (L) Y (T)
03H
0BH
13H
1BH
23H
2BH
33H
Y
X1
IE1
N (L) Y (T)
T1
TF1
Y
N
N
N
SP
T2
R1, TI
TF2, EXF2
PCA
CF, CCFn
n = 0–4
NOTES:
1. L = Level activated
2. T = Transition activated
16
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
7
6
5
4
3
2
1
0
IE0 (A8H)
EA
—
ET2
ES
ET1
EX1
ET0
EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
SYMBOL FUNCTION
IE.7
EA
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
—
ET2
ES
ET1
EX1
ET0
EX0
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
SU00743
Figure 10. IE Registers
7
6
5
4
3
2
1
0
IP0 (B8H)
—
—
PT2
PS
PT1
PX1
PT0
PX0
Priority Bit = 1 assigns high priority
Priority Bit = 0 assigns low priority
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
SYMBOL FUNCTION
—
Not implemented, reserved for future use.
—
PT2
PS
PT1
PX1
PT0
PX0
Timer 2 interrupt priority bit.
Serial Port interrupt priority bit.
Timer 1 interrupt priority bit.
External interrupt 1 priority bit.
Timer 0 interrupt priority bit.
External interrupt 0 priority bit.
SU00744
Figure 11. IP Registers
17
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.
DPS
BIT0
AUXR1
80C52/80C54/80C58 Reduced EMI Mode
DPTR1
DPTR0
DPL
AUXR (8EH)
DPH
(83H)
(82H)
EXTERNAL
DATA
MEMORY
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
AO
SU00745A
AO: Turns off ALE output.
Figure 12. DPTR Structure
Dual Data Pointer Register (DPTR)
The dual DPTR structure (see Figure 12) is a way by which the
DPTR Instructions
80C52/54/58 will specify the address of an external data memory
location. There are two 16-bit DPTR registers that address the
external memory, and a single bit called DPS = AUXR1/bit0 that
allows the program code to switch between them.
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
INC DPTR
Increments the data pointer by 1
• Register Name: AUXR1#
• SFR Address: A2H
• Reset Value: xxxxxxx0B
MOV DPTR, #data16
MOV A, @ A+DPTR
Loads the DPTR with a 16-bit constant
Move code byte relative to DPTR to
ACC
7
6
5
4
–
3
–
2
–
1
–
0
MOVX A, @ DPTR
MOVX @ DPTR , A
JMP @ A + DPTR
Move external RAM (16-bit address) to
ACC
–
–
–
DPS
Where:
Move ACC to external RAM (16-bit
address)
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
Select Reg
DPTR0
DPS
Jump indirect relative to DPTR
0
1
The data pointer can be accessed on a byte-by-byte basis by
specifying the Low or High byte in an instruction which accesses the
SFRs. See application note AN458 for detailed operation
DPTR1
The DPS bit status whould be saved by software when switching
between DPTR0 and DPTR1.
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Operating temperature under bias
RATING
0 to +70 or –40 to +85
–65 to +150
0 to +13.0
–0.5 to +6.5
15
UNIT
°C
°C
V
Storage temperature range
Voltage on EA/V pin to V
PP
SS
Voltage on any other pin to V
V
SS
Maximum I per I/O pin
mA
W
OL
Power dissipation (based on package heat transfer limitations, not device power consumption)
NOTES:
1.5
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise
SS
noted.
18
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C or –40°C to +85°C, V = 5.0V ±10%; V = 0V
CC SS
LIMITS
TEST
CONDITIONS
SYMBOL
PARAMETER
UNIT
1
MIN
TYP
MAX
0.2V –0.1
V
V
V
Input low voltage
4.5V < V < 5.5V
–0.5
V
V
V
IL
CC
CC
Input high voltage (ports 0, 1, 2, 3, EA)
Input high voltage, XTAL1, RST
0.2V +0.9
V
+0.5
+0.5
IH
CC
CC
CC
0.7V
V
IH1
CC
V
OL
= 4.5V
= 1.6mA
CC
8
V
V
V
V
Output low voltage, ports 1, 2, 3
0.4
V
V
V
OL
2
I
I
V
CC
= 4.5V
8, 7
Output low voltage, port 0, ALE, PSEN
0.4
OL1
OH
2
= 3.2mA
OL
V
CC
= 4.5V
= –30µA
3
Output high voltage, ports 1, 2, 3
V
V
– 0.7
– 0.7
CC
I
OH
Output high voltage (port 0 in external bus mode),
V
CC
= 4.5V
= –3.2mA
V
OH1
CC
9
3
ALE , PSEN
I
OH
I
I
Logical 0 input current, ports 1, 2, 3
V
V
= 0.4V
= 2.0V
–1
–50
–650
±10
µA
µA
µA
IL
IN
IN
6
Logical 1-to-0 transition current, ports 1, 2, 3
TL
See note 4
I
I
Input leakage current, port 0
0.45 < V < V – 0.3
LI
IN
CC
Power supply current (see Figure 20):
See note 5
CC
5
Active mode @ 16MHz
Idle mode @ 16MHz
16
4
50
mA
mA
µA
5
Power-down mode
T
= 0 to +70°C
3
amb
T
amb
= –40 to +85°C
75
µA
R
C
Internal reset pull-down resistor
40
225
15
kΩ
RST
IO
10
Pin capacitance (except EA)
pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due
OL
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no
OL
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the (V –0.7) specification when the
OH
CC
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V is approximately 2V.
IN
5. See Figures 21 through 24 for I test conditions.
CC
Active Mode:
Idle Mode:
I
I
= 0.9 × FREQ + 1.1;
= 0.18 × FREQ +1.0; See Figure 20.
CC
CC
6. This value applies to T
= 0°C to +70°C. For T = –40°C to +85°C, I = –750µA.
amb TL
amb
7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
8. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin:
15mA (*NOTE: This is 85°C specification.)
OL
Maximum I per 8-bit port:
26mA
71mA
OL
Maximum total I for all outputs:
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
9. ALE is tested to V
, except when ALE is off then V is the voltage specification.
OH
OH1
10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF
(except EA it is 25pF).
19
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
AC ELECTRICAL CHARACTERISTICS
1, 2, 3
T
amb
= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V
CC SS
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/t
FIGURE
PARAMETER
Oscillator frequency
MIN
MAX
MIN
MAX
UNIT
13
CLCL
Speed versions : E
3.5
16
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
13
13
13
13
13
13
13
13
13
13
13
ALE pulse width
85
22
32
2t
–40
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
t
–40
AVLL
LLAX
LLIV
CLCL
CLCL
–30
150
82
4t
3t
–100
CLCL
32
t
–30
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
142
3t
–45
CLCL
4
PSEN low to valid instruction in
–105
CLCL
Input instruction hold after PSEN
Input instruction float after PSEN
0
0
37
207
10
t
–25
CLCL
4
Address to valid instruction in
5t
–105
CLCL
PSEN low to address float
10
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
15
RD pulse width
275
275
6t
–100
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
147
5t
–165
CLCL
0
0
Data float after RD
65
2t
–60
CLCL
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
350
397
239
8t
CLCL
9t
CLCL
–150
–165
AVDV
LLWL
137
122
13
3t
–50
3t
+50
CLCL
CLCL
4t
t
–130
–50
AVWL
QVWX
WHQX
QVWH
RLAZ
WHLH
CLCL
CLCL
CLCL
CLCL
13
t
–50
Data valid to WR high
RD low to address float
RD or WR high to ALE high
287
7t
–150
14, 15
14, 15
0
0
23
103
t
–40
t
+40
CLCL
CLCL
External Clock
t
t
t
t
17
17
17
17
High time
Low time
Rise time
Fall time
20
20
20
20
t
–t
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
CLCL CLCX
t
–t
CLCL CHCX
20
20
20
20
Shift Register
t
t
t
t
t
16
16
16
16
16
Serial port clock cycle time
750
492
8
12t
ns
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t
–133
QVXH
XHQX
XHDX
XHDV
CLCL
2t
CLCL
–117
0
0
492
10t
–133
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 80C52/54/58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. See application note AN457 for external memory interfacing.
20
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
AC ELECTRICAL CHARACTERISTICS
1, 2, 3
T
amb
= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V
CC SS
4
24MHz CLOCK
VARIABLE CLOCK
33MHz CLOCK
SYMBOL FIGURE
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
1/t
CLCL
13
Oscillator frequency
3.5
33
Speed versions : I (24MHz)
: N (33MHz)
3.5
24
MHz
3.5
21
5
33
t
t
t
t
t
t
t
t
t
t
t
13
13
13
13
13
13
13
13
13
13
13
ALE pulse width
43
17
17
2t
–40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LHLL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
t
–25
AVLL
LLAX
LLIV
CLCL
CLCL
–25
102
65
4t
3t
–65
55
30
CLCL
17
80
t
–25
5
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
CLCL
PSEN pulse width
3t
CLCL
–45
45
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–60
CLCL
0
0
0
17
128
10
t
–25
5
CLCL
5t
CLCL
–80
70
10
10
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
15
RD pulse width
150
150
6t
–100
–100
82
82
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
CLCL
WR pulse width
6t
CLCL
RD low to valid data in
Data hold after RD
118
5t
2t
–90
–28
60
CLCL
0
0
0
Data float after RD
55
32
90
CLCL
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
183
210
175
8t
–150
–165
CLCL
CLCL
9t
105
140
AVDV
LLWL
75
92
3t
–50
–75
3t
CLCL
+50
40
45
0
CLCL
4t
AVWL
QVWX
WHQX
QVWH
RLAZ
WHLH
CLCL
12
t
t
–30
CLCL
CLCL
CLCL
17
–25
5
Data valid to WR high
RD low to address float
RD or WR high to ALE high
162
7t
–130
80
14, 15
14, 15
0
0
0
17
67
t
–25
t
+25
5
55
CLCL
CLCL
External Clock
t
t
t
t
17
17
17
17
High time
Low time
Rise time
Fall time
17
17
17
17
t
–t
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
CLCL CLCX
t
–t
CLCL CHCX
5
5
5
5
Shift Register
t
t
t
t
t
16
16
16
16
16
Serial port clock cycle time
505
283
3
12t
360
167
ns
ns
ns
ns
ns
XLXL
CLCL
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10t –133
CLCL
QVXH
XHQX
XHDX
XHDV
2t
CLCL
–80
0
0
0
283
10t
–133
167
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 80C52/54/58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz
“AC Electrial Characteristics”, page 20.
21
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
P – PSEN
Q – Output data
R – RD signal
t – Time
A – Address
V – Valid
C – Clock
W– WR signal
D – Input data
H – Logic level high
X – No longer a valid logic level
Z – Float
I – Instruction (program memory contents)
L – Logic level low, or ALE
Examples: t
= Time for address valid to ALE low.
=Time for ALE low to PSEN low.
AVLL
t
LLPL
t
LHLL
ALE
t
t
LLPL
AVLL
t
PLPH
t
LLIV
t
PLIV
PSEN
t
LLAX
t
PXIZ
t
PLAZ
t
PXIX
A0–A7
INSTR IN
A0–A7
PORT 0
PORT 2
t
AVIV
A0–A15
A8–A15
SU00006
Figure 13. External Program Memory Read Cycle
ALE
PSEN
RD
t
WHLH
t
LLDV
t
t
LLWL
RLRH
t
RHDZ
t
LLAX
t
t
RLDV
AVLL
t
RLAZ
t
RHDX
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
AVWL
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00025
Figure 14. External Data Memory Read Cycle
22
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
ALE
t
WHLH
PSEN
t
t
WLWH
LLWL
WR
t
LLAX
t
t
WHQX
t
AVLL
QVWX
t
QVWH
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
INSTR IN
t
AVWL
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00026
Figure 15. External Data Memory Write Cycle
INSTRUCTION
ALE
0
1
2
3
4
5
6
7
8
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
0
1
2
3
4
5
6
7
WRITE TO SBUF
t
XHDX
t
SET TI
VALID
XHDV
INPUT DATA
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
SU00027
Figure 16. Shift Register Mode Timing
V
–0.5
CC
0.7V
CC
CC
0.45V
0.2V
–0.1
t
CHCX
t
t
t
CHCL
CLCX
CLCH
t
CLCL
SU00009
Figure 17. External Clock Drive
23
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
V
–0.5
CC
V
V
+0.1V
LOAD
V
V
–0.1V
TIMING
REFERENCE
POINTS
OH
0.2V
0.2V
+0.9
–0.1
CC
V
LOAD
CC
–0.1V
LOAD
+0.1V
OL
0.45V
NOTE:
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from
load voltage occurs, and begins to float when a 100mV change from the loaded
AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.
CC
IH
IL
V
/V level occurs. I /I ≥ ±20mA.
OH OL
OH OL
SU00717
SU00718
Figure 18. AC Testing Input/Output
Figure 19. Float Waveform
35
30
25
20
MAX ACTIVE MODE
MAX = 0.9 X FREQ. + 1.1
I
CC
I
CC
mA
15
10
5
TYP ACTIVE MODE
MAX IDLE MODE
TYP IDLE MODE
4MHz 8MHz 12MHz 16MHz 20MHz 24MHz 28MHz 32MHz 36MHz
FREQ AT XTAL1
SU00768
Figure 20. I vs. FREQ
CC
Valid only within frequency specifications of the device under test
24
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
V
V
CC
CC
I
I
CC
CC
V
V
CC
CC
V
RST
V
V
CC
CC
CC
P0
EA
P0
EA
RST
(NC)
XTAL2
XTAL1
(NC)
XTAL2
XTAL1
CLOCK SIGNAL
CLOCK SIGNAL
V
V
SS
SS
SU00719
SU00720
Figure 21. I Test Condition, Active Mode
Figure 22. I Test Condition, Idle Mode
CC
CC
All other pins are disconnected
All other pins are disconnected
V
–0.5
CC
0.7V
CC
–0.1
0.45V
0.2V
CC
t
CHCX
t
t
t
CLCH
CHCL
CLCX
t
CLCL
SU00009
Figure 23. Clock Signal Waveform for I Tests in Active and Idle Modes
CC
t
= t
= 5ns
CHCL
CLCH
V
CC
I
CC
V
CC
V
RST
CC
P0
EA
(NC)
XTAL2
XTAL1
V
SS
SU00016
Figure 24. I Test Condition, Power Down Mode
CC
All other pins are disconnected. V = 2V to 5.5V
CC
25
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
internal memory, EA is latched on Reset and all further programming
of the EPROM is disabled. When security bits 1 and 2 are
programmed, in addition to the above, verify mode is disabled.
Security Bits
With none of the security bits programmed the code in the program
memory can be verified. If the encryption table is programmed, the
code will be encrypted when verified. When only security bit 1 (see
Table 8) is programmed, MOVC instructions executed from external
program memory are disabled from fetching code bytes from the
Encryption Array
64 bytes of encryption array are initially unprogrammed (all 1s).
Table 8. Program Security Bits
1, 2
PROGRAM LOCK BITS
SB1
SB2
PROTECTION DESCRIPTION
1
U
U
No Program Security features enabled.
(Code verify will still be encrypted by the Encryption Array if programmed.)
2
P
U
MOVC instructions executed from external program memory are disabled from fetching code bytes from
internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled.
NOTES:
1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.
80C52 ROM CODE SUBMISSION
When submitting ROM code for the 80C52, the following must be specified:
1. 8k byte user ROM data
2. 64 byte ROM encryption key
3. ROM security bits.
ADDRESS
CONTENT
DATA
BIT(S)
7:0
COMMENT
0000H to 1FFFH
2000H to 201FH
User ROM Data
KEY
7:0
ROM Encryption Key
FFH = no encryption
2020H
2020H
SEC
SEC
0
1
ROM Security Bit 1
0 = enable security
1 = disable security
ROM Security Bit 2
0 = enable security
1 = disable security
Security Bit 1: When programmed, this bit has two effects on masked ROM parts:
1. External MOVC is disabled, and
2. EA is latched on Reset.
Security Bit 2: When programmed, this bit inhibits Verify User ROM.
If the ROM Code file does not include the options, the following information must be included with the ROM code.
For each of the following, check the appropriate box, and send to Philips along with the code:
Security Bit #1:
Security Bit #2:
Encryption:
V Enabled
V Enabled
V No
V Disabled
V Disabled
V Yes
If Yes, must send key file.
26
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
80C54 ROM CODE SUBMISSION
When submitting ROM code for the 80C54, the following must be specified:
1. 16k byte user ROM data
2. 64 byte ROM encryption key
3. ROM security bits.
ADDRESS
CONTENT
DATA
BIT(S)
7:0
COMMENT
0000H to 3FFFH
4000H to 401FH
User ROM Data
KEY
7:0
ROM Encryption Key
FFH = no encryption
4020H
4020H
SEC
SEC
0
1
ROM Security Bit 1
0 = enable security
1 = disable security
ROM Security Bit 2
0 = enable security
1 = disable security
Security Bit 1: When programmed, this bit has two effects on masked ROM parts:
1. External MOVC is disabled, and
2. EA is latched on Reset.
Security Bit 2: When programmed, this bit inhibits Verify User ROM.
If the ROM Code file does not include the options, the following information must be included with the ROM code.
For each of the following, check the appropriate box, and send to Philips along with the code:
Security Bit #1:
Security Bit #2:
Encryption:
V Enabled
V Enabled
V No
V Disabled
V Disabled
V Yes
If Yes, must send key file.
27
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
80C58 ROM CODE SUBMISSION
When submitting ROM code for the 80C58, the following must be specified:
1. 32k byte user ROM data
2. 64 byte ROM encryption key
3. ROM security bits.
If submitting a file, the format is as follows:
ADDRESS
CONTENT
DATA
BIT(S)
7:0
COMMENT
0000H to 7FFFH
8000H to 801FH
User ROM Data
KEY
7:0
ROM Encryption Key
FFH = no encryption
8020H
8020H
SEC
SEC
0
1
ROM Security Bit 1
0 = enable security
1 = disable security
ROM Security Bit 2
0 = enable security
1 = disable security
Security Bit 1: When programmed, this bit has two effects on masked ROM parts:
1. External MOVC is disabled, and
2. EA is latched on Reset.
Security Bit 2: When programmed, this bit inhibits Verify User ROM.
If the ROM code file does not include the options, the following information must be included with the ROM code.
For each of the following check the appropriate box and send to Philips along with the code:
Security Bit #1:
Security Bit #2:
Encryption:
V Enabled
V Enabled
V No
V Disabled
V Disabled
V Yes
If Yes, must send key file.
28
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
29
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
30
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
31
1996 Aug 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work
right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only.
Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1996
All rights reserved. Printed in U.S.A.
Telephone 800-234-7381
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