P80C552KBB_技术文档

INTEGRATED CIRCUITS

80C552/83C552

Single-chip 8-bit microcontroller with

10-bit A/D, capture/compare timer,

high-speed outputs, PWM

Product data

2002 Sep 03

Supersedes data of 1998 Aug 13

Philips

Semiconductors

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

FEATURES

• 80C51 central processing unit

• 8k × 8 ROM expandable externally to 64 kbytes

• ROM code protection

• An additional 16-bit timer/counter coupled to four capture registers

and three compare registers

• Two standard 16-bit timer/counters

• 256 × 8 RAM, expandable externally to 64 kbytes

• Capable of producing eight synchronized, timed outputs

• A 10-bit ADC with eight multiplexed analog inputs

• Two 8-bit resolution, pulse width modulation outputs

DESCRIPTION

The 80C552/83C552 (hereafter generically referred to as 8XC552)

Single-Chip 8-Bit Microcontroller is manufactured in an advanced

CMOS process and is a derivative of the 80C51 microcontroller

family. The 8XC552 has the same instruction set as the 80C51.

Three versions of the derivative exist:

• Five 8-bit I/O ports plus one 8-bit input port shared with analog

inputs

2

• I C-bus serial I/O port with byte oriented master and slave

• 83C552—8 kbytes mask programmable ROM

• 80C552—ROMless version of the 83C552

functions

• Full-duplex UART compatible with the standard 80C51

• On-chip watchdog timer

• 87C552—8 kbytes EPROM (described in a separate chapter)

• Three speed ranges:

– 3.5 to 16 MHz

The 8XC552 contains a non-volatile 8k × 8 read-only program

memory (83C552), a volatile 256 × 8 read/write data memory, five

8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters

(identical to the timers of the 80C51), an additional 16-bit timer

coupled to capture and compare latches, a 15-source,

– 3.5 to 24 MHz (ROM, ROMless only)

• Three operating ambient temperature ranges:

– P83C552xBx: 0 °C to +70 °C

two-priority-level, nested interrupt structure, an 8-input ADC, a dual

DAC pulse width modulated interface, two serial interfaces (UART

– P83C552xFx: –40 °C to +85 °C

(XTAL frequency max. 24 MHz)

2

and I C-bus), a “watchdog” timer and on-chip oscillator and timing

circuits. For systems that require extra capability, the 8XC552 can

be expanded using standard TTL compatible memories and logic.

– P83C552xHx: –40 °C to +125 °C

(XTAL frequency max. 16 MHz)

In addition, the 8XC552 has two software selectable modes of

power reduction—idle mode and power-down mode. The idle mode

freezes the CPU while allowing the RAM, timers, serial ports, and

interrupt system to continue functioning. The power-down mode

saves the RAM contents but freezes the oscillator, causing all other

chip functions to be inoperative.

LOGIC SYMBOL

V

SS

DD

XTAL1

XTAL2

EA

ALE

The device also functions as an arithmetic processor having

facilities for both binary and BCD arithmetic plus bit-handling

capabilities. The instruction set consists of over 100 instructions: 49

one-byte, 45 two-byte, and 17 three-byte. With a 16 MHz (24 MHz)

crystal, 58% of the instructions are executed in 0.75 µs (0.5 µs) and

40% in 1.5 µs (1 µs). Multiply and divide instructions require 3 µs

(2 µs).

LOW ORDER

ADDRESS AND

DATA BUS

PSEN

AV

AVref+

AVref–

SS

DD

CT0I

CT1I

CT2I

CT3I

STADC

PWM0

PWM1

T2

RT2

SCL

SDA

ADC0-7

HIGH ORDER

ADDRESS AND

DATA BUS

CMSR0-5

RxD/DATA

TxD/CLOCK

INT0

INT1

T0

T1

CMT0

CMT1

WR

RD

RST

EW

SU01691

2

2002 Sep 03

853-1467 28849

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

PIN CONFIGURATIONS

Plastic Leaded Chip Carrier

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

P4.3/CMSR3 10

P4.4/CMSR4 11

P4.5/CMSR5 12

P4.6/CMT0 13

P4.7/CMT1 14

RST 15

60 AV

SS

59 AV

58 AV

REF+

REF–

57 P0.0/AD0

56 P0.1/AD1

55 P0.2/AD2

54 P0.3/AD3

53 P0.4/AD4

52 P0.5/AD5

51 P0.6/AD6

50 P0.7/AD7

49 EA

P1.0/CT0I 16

P1.1/CT1I 17

P1.2/CT2I 18

P1.3/CT3I 19

P1.4/T2 20

PLASTIC LEADED CHIP CARRIER

P1.5/RT2 21

P1.6/SCL 22

P1.7/SDA 23

P3.0/RxD 24

P3.1/TxD 25

P3.2/INT0 26

48 ALE

47 PSEN

46 P2.7/A15

45 P2.6/A14

44 P2.5/A13

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

SU00932

* Do not connect.

3

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

Plastic Quad Flat Pack

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

P4.1/CMSR1

P4.2/CMSR2

NC*

1

2

3

4

5

6

7

8

9

64 P5.7/ADC7

63 AV

DD

62 NC*

P4.3/CMSR3

P4.4/CMSR4

P4.5/CMSR5

P4.6/CMT0

P4.7/CMT1

RST

61 AV

60 AV

59 AV

SS

REF+

REF–

58 P0.0/AD0

57 P0.1/AD1

56 P0.2/AD2

55 P0.3/AD3

54 P0.4/AD4

53 P0.5/AD5

52 P0.6/AD6

51 P0.7/AD7

50 EA

P1.0/CT0I 10

P1.1/CT1I 11

P1.2/CT2I 12

P1.3/CT3I 13

P1.4/T2 14

P1.5/RT2 15

P1.6/SCL 16

P1.7/SDA 17

P3.0/RxD 18

P3.1/TxD 19

P3.2/INT0 20

NC* 21

PLASTIC QUAD FLAT PACK

49 ALE

48 PSEN

47 P2.7/A15

46 P2.6/A14

45 P2.5/A13

44 NC*

NC* 22

43 NC*

P3.3/INT1 23

PP3.4/T0 24

42 P2.4/A12

41 P2.3/A11

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

SU00931

* Do not connect.

IC = Internally connected (do not use).

4

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

BLOCK DIAGRAM

T0

T1

INT0

INT1

PWM0 PWM1 AV

AV

ADC0-7 SDA SCL

SS

REF

–

+

V

SS

5

1

DD

STADC

3

AV

DD

XTAL1

T0, T1

PROGRAM

MEMORY

8k x 8 ROM

DATA

MEMORY

256 x 8 RAM

DUAL

PWM

SERIAL

C PORT

TWO 16-BIT

TIMER/EVENT

COUNTERS

XTAL2

EA

ADC

2

CPU

I

ALE

80C51 CORE

EXCLUDING

ROM/RAM

PSEN

3

WR

RD

8-BIT INTERNAL BUS

3

0

16

AD0-7

T2

16-BIT

TIMER/

EVENT

FOUR

16-BIT

CAPTURE

LATCHES

16-BIT

COMPARA-

TORS

wITH

REGISTERS

COMPARA-

TOR

OUTPUT

SELECTION

T3

16

PARALLEL I/O

PORTS AND

EXTERNAL BUS

SERIAL

UART

PORT

8-BIT

PORT

WATCHDOG

TIMER

2

COUNTERS

A8-15

3

1

4

P0

P1

P2

P3

TxD

RxD

P5

P4

CT0I-CT3I

T2

RT2

CMSR0-CMSR5

CMT0, CMT1

RST EW

3

4

5

0

1

2

ALTERNATE FUNCTION OF PORT 3

ALTERNATE FUNCTION OF PORT 4

ALTERNATE FUNCTION OF PORT 5

ALTERNATE FUNCTION OF PORT 0

ALTERNATE FUNCTION OF PORT 1

ALTERNATE FUNCTION OF PORT 2

SU01692

5

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

ORDERING INFORMATION

PHILIPS

PART ORDER NUMBER

DRAWING

TEMPERATURE (°C)

AND PACKAGE

FREQ

(MHz)

PART MARKING

NUMBER

1

ROMless

P80C552EBA

ROM

0 to +70,

Plastic Leaded Chip Carrier

P83C552EBA/xxx

SOT188-2

SOT318-2

SOT188-2

SOT318-2

SOT188-2

SOT318-2

SOT188-2

SOT318-2

SOT188-2

SOT318-2

16

24

0 to +70,

Plastic Quad Flat Pack

P80C552EBB

P80C552EFA

P80C552EFB

P80C552EHA

P80C552EHB

P80C552IBA

P80C552IBB

P80C552IFA

P83C552EBB/xxx

P83C552EFA/xxx

P83C552EFB/xxx

P83C552EHA/xxx

P83C552EHB/xxx

P83C552IBA/xxx

P83C552IBB/xxx

P83C552IFA/xxx

P83C552IFB/xxx

–40 to +85,

Plastic Leaded Chip Carrier

–40 to +85,

Plastic Quad Flat Pack

–40 to +125,

Plastic Leaded Chip Carrier

–40 to +125,

Plastic Quad Flat Pack

0 to +70,

Plastic Leaded Chip Carrier

0 to +70,

Plastic Quad Flat Pack

–40 to +85,

Plastic Leaded Chip Carrier

–40 to +85,

Plastic Quad Flat Pack

P80C552IFB

NOTE:

1. xxx denotes the ROM code number.

2. For EPROM device specification, refer to 87C552 datasheet.

6

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

PIN DESCRIPTION

PIN NO.

MNEMONIC

PLCC

QFP

TYPE

NAME AND FUNCTION

V

DD

2

72

I

Digital Power Supply: +5 V power supply pin during normal operation, idle and

power-down mode.

STADC

3

74

I

Start ADC Operation: Input starting analog to digital conversion (ADC operation can also

be started by software). This pin must not float.

PWM0

PWM1

EW

4

5

6

75

76

77

O

I

Pulse Width Modulation: Output 0.

Pulse Width Modulation: Output 1.

Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.

This pin must not float.

P0.0-P0.7

57-50

58-51

I/O

Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written

to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed

low-order address and data bus during accesses to external program and data memory. In

this application it uses strong internal pull-ups when emitting 1s.

P1.0-P1.7

16-23

16-21

22-23

16-19

20

10-17

10-15

16-17

10-13

14

I/O

I

Port 1: 8-bit I/O port. Alternate functions include:

(P1.0-P1.5): Quasi-bidirectional port pins.

(P1.6, P1.7): Open drain port pins.

CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.

T2 (P1.4): T2 event input.

I

21

22

23

15

16

17

I

RT2 (P1.5): T2 timer reset signal. Rising edge triggered.

2

I/O

SCL (P1.6): Serial port clock line I C-bus.

2

SDA (P1.7): Serial port data line I C-bus.

Port 1 is also used to input the lower order address byte during EPROM programming and

verification. A0 is on P1.0, etc.

P2.0-P2.7

P3.0-P3.7

39-46

24-31

38-42,

45-47

I/O

Port 2: 8-bit quasi-bidirectional I/O port.

Alternate function: High-order address byte for external memory (A08-A15).

18-20,

23-27

Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:

24

25

26

27

28

29

30

31

18

19

20

23

24

25

26

27

RxD(P3.0): Serial input port.

TxD (P3.1): Serial output port.

INT0 (P3.2): External interrupt.

INT1 (P3.3): External interrupt.

T0 (P3.4): Timer 0 external input.

T1 (P3.5): Timer 1 external input.

WR (P3.6): External data memory write strobe.

RD (P3.7): External data memory read strobe.

P4.0-P4.7

P5.0-P5.7

7-14

7-12

80, 1-2

4-8

I/O

O

Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:

80, 1-2

4-6

CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with

timer T2.

13, 14

7, 8

O

I

CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.

68-62,

1

71-64,

Port 5: 8-bit input port.

ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC.

RST

15

9

I/O

I

Reset: Input to reset the 8XC552. It also provides a reset pulse as output when timer T3

overflows.

XTAL1

35

32

Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the

internal clock generator. Receives the external clock signal when an external oscillator is

used.

XTAL2

34

31

O

Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit

when an external clock is used.

7

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

PIN DESCRIPTION (Continued)

PIN NO.

MNEMONIC

PLCC

36, 37

47

QFP

34-36

48

TYPE

NAME AND FUNCTION

V

SS

I

Two Digital ground pins.

PSEN

O

Program Store Enable: Active-low read strobe to external program memory.

ALE

EA

48

49

Address Latch Enable: Latches the low byte of the address during accesses to external

memory. It is activated every six oscillator periods. During an external data memory

access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles

CMOS inputs without an external pull-up.

49

50

I

External Access: When EA is held at TTL level high, the CPU executes out of the internal

program ROM provided the program counter is less than 8192. When EA is held at TTL

low level, the CPU executes out of external program memory. EA is not allowed to float.

AV

58

59

60

61

59

60

61

63

I

Analog to Digital Conversion Reference Resistor: Low-end.

Analog to Digital Conversion Reference Resistor: High-end.

Analog Ground

REF–

REF+

SS

Analog Power Supply

DD

NOTE:

1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than V + 0.5 V or V – 0.5 V,

DD

SS

respectively.

service routine and continued), or by a hardware reset which starts

the processor in the same manner as a power-on reset.

OSCILLATOR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an

inverting amplifier. The pins can be configured for use as an on-chip

oscillator, as shown in the logic symbol, page 2.

POWER-DOWN MODE

In the power-down mode, the oscillator is stopped and the

instruction to invoke power-down is the last instruction executed.

Only the contents of the on-chip RAM are preserved. A hardware

reset is the only way to terminate the power-down mode. The control

bits for the reduced power modes are in the special function register

PCON. Table 1 shows the state of the I/O ports during low current

operating modes.

To drive the device from an external clock source, XTAL1 should be

driven while XTAL2 is left unconnected. There are no requirements

on the duty cycle of the external clock signal, because the input to

the internal clock circuitry is through a divide-by-two flip-flop.

However, minimum and maximum high and low times specified in

the data sheet must be observed.

RESET

A reset is accomplished by holding the RST pin high for at least two

machine cycles (24 oscillator periods), while the oscillator is running.

To insure a good power-on reset, the RST pin must be high long

enough to allow the oscillator time to start up (normally a few

milliseconds) plus two machine cycles. At power-on, the voltage on

ROM CODE PROTECTION (83C552)

The 83C552 has an additional security feature. ROM code

protection may be selected by setting a mask–programmable

security bit (i.e., user dependent). This feature may be requested

during ROM code submission. When selected, the ROM code is

protected and cannot be read out at any time by any test mode or by

any instruction in the external program memory space.

V

DD

and RST must come up at the same time for a proper start-up.

IDLE MODE

The MOVC instructions are the only instructions that have access to

program code in the internal or external program memory. The EA

input is latched during RESET and is “don’t care” after RESET

(also if the security bit is not set). This implementation prevents

reading internal program code by switching from external program

memory to internal program memory during a MOVC instruction or

any other instruction that uses immediate data.

In the idle mode, the CPU puts itself to sleep while some of the

on-chip peripherals stay active. The instruction to invoke the idle

mode is the last instruction executed in the normal operating mode

before the idle mode is activated. The CPU contents, the on-chip

RAM, and all of the special function registers remain intact during

this mode. The idle mode can be terminated either by any enabled

interrupt (at which time the process is picked up at the interrupt

Table 1. External Pin Status During Idle and Power-Down Modes

PROGRAM

MEMORY

PWM0/

PWM1

MODE

Idle

ALE

PSEN

PORT 0

Data

PORT 1

Data

PORT 2

Data

PORT 3

Data

PORT 4

Data

Internal

1

0

1

0

1

Idle

External

Internal

Float

Data

Address

Data

Power-down

Data

External

Float

Data

8

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

Serial Control Register (S1CON) – See Table 2

CR2 ENS1 STA

STO

SI

AA

CR1 CR0

S1CON (D8H)

Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.

Table 2. Serial Clock Rates

BIT FREQUENCY (kHz) AT f

OSC

2

CR2

CR1

CR0

6 MHZ

12 MHz

16 MHz

24 MHz

f

DIVIDED BY

OSC

0

1

0

1

0

1

0

1

0

1

0

1

0

1

23

27

31

37

6.25

50

47

54

63

75

12.5

62.5

71

83.3

100

17

94

107

125

150

25

200

400

256

224

192

160

960

120

60

1

100

200

0.49 < 62.5

0 < 254

133

267

1

100

0.24 < 62.5

0 < 255

0.65 < 55.6

0 < 253

0.98 < 50.0

0 <251

96 × (256 – (reload value Timer 1))

reload value Timer 1 in Mode 2.

NOTES:

2

1. These frequencies exceed the upper limit of 100kHz of the I C-bus specification and cannot be used in an I C-bus application.

2

2. At f

= 24 MHz the maximum I C bus rate of 100kHz cannot be realized due to the fixed divider rates.

OSC

1, 2, 3

ABSOLUTE MAXIMUM RATINGS

PARAMETER

RATING

–65 to +150

–0.5 to +6.5

5.0

UNIT

°C

Storage temperature range

Voltage on any other pin to V

V

SS

Input, output DC current on any single I/O pin

mA

W

Power dissipation

1.0

(based on package heat transfer limitations, not device power consumption)

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section

of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise

SS

noted.

DEVICE SPECIFICATIONS

SUPPLY VOLTAGE (V)

FREQUENCY (MHz)

TYPE

MIN

4.5

MAX

5.5

MIN

3.5

MAX

16

TEMPERATURE RANGE (°C)

0 to +70

P83(0)C552EBx

P83(0)C552EFx

P83(0)C552EHx

P83(0)C552IBx

P83(0)C552IFx

16

–40 to +85

16

–40 to +125

24

0 to +70

24

–40 to +85

9

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

DC ELECTRICAL CHARACTERISTICS

V

SS

, AV = 0 V; V , AV = 5 V ± 10%

SS DD DD

TEST

LIMITS

SYMBOL PARAMETER

CONDITIONS

MIN

MAX

UNIT

I

Supply current operating:

P83(0)C552EBx

P83(0)C552EFx

P83(0)C552EHx

P83(0)C552IBx

See notes 1 and 2

DD

f

= 16 MHz

= 24 MHz

45

40

55

mA

OSC

P83(0)C552IFx

Idle mode:

See notes 1 and 3

ID

P83(0)C552EBx

P83(0)C552EFx

P83(0)C552EHx

P83(0)C552IBx

P83(0)C552IFx

f

= 16 MHz

= 24 MHz

10

9

12.5

mA

OSC

Power-down current:

See notes 1 and 4;

2 V < V < V max

PD

DD

P83(0)C552xBx

P83(0)C552xFx

P83(0)C552xHx

50

150

µA

Inputs

V

Input low voltage, except EA, P1.6, P1.7

Input low voltage to EA

–0.5

0.2V –0.1

V

IL

DD

0.2V –0.3

IL1

IL2

IH

DD

5

Input low voltage to P1.6/SCL, P1.7/SDA

0.3V

V

DD

Input high voltage, except XTAL1, RST, P1.6/SCL, P1.7/SDA

Input high voltage, XTAL1, RST

0.2V +0.9

V

DD

V

DD

+0.5

V

DD

0.7V

V

IH1

IH2

DD

5

Input high voltage, P1.6/SCL, P1.7/SDA

6.0

V

I

Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7

Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7

Input leakage current, port 0, EA, STADC, EW

V

= 0.45 V

–50

–650

10

µA

IL

TL

IN

See note 6

0.45 V < V < V

DD

±I

IL1

IL2

IL3

I

0 V < V < 6 V

0 V < V < 5.5 V

I

Input leakage current, P1.6/SCL, P1.7/SDA

Input leakage current, port 5

10

1

µA

DD

0.45 V < V < V

I

DD

Outputs

7

V

Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7

Output low voltage, port 0, ALE, PSEN, PWM0, PWM1

Output low voltage, P1.6/SCL, P1.7/SDA

I

= 1.6mA

= 3.2mA

= 3.0mA

0.45

0.4

V

OL

7

OL1

OL2

OH

Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA

–I = 60µA

–I = 25µA

–I = 10µA

2.4

V

OH

0.75V

OH

DD

0.9V

OH

–I = 400µA

V

Output high voltage (port 0 in external bus mode, ALE,

PSEN, PWM0, PWM1)

2.4

V

OH

OH1

8

–I = 150µA

0.75V

OH

DD

–I = 40µA

OH

0.9V

Output high voltage (RST)

–I = 400µA

2.4

0.8V

V

OH2

OH

–I = 120µA

OH

DD

R

C

Internal reset pull-down resistor

Pin capacitance

50

150

10

kΩ

RST

IO

Test freq = 1 MHz,

pF

T

= 25 °C

amb

10

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

DC ELECTRICAL CHARACTERISTICS (Continued)

TEST

CONDITIONS

LIMITS

SYMBOL

PARAMETER

MIN

MAX

UNIT

Analog Inputs

AI

DD

Analog supply current: operating: (16 MHz)

Analog supply current: operating: (24 MHz)

Port 5 = 0 to AV

1.2

1.0

mA

DD

Idle mode:

AI

ID

P83(0)C552EBx

P83(0)C552EFx

P83(0)C552EHx

P83(0)C552IBx

P83(0)C552IFx

50

100

50

µA

50

Power-down mode:

2 V < AV < AV

AI

PD

DD

max

P83(0)C552xBx

P83(0)C552xFx

P83(0)C552xHx

50

100

µA

AV

Analog input voltage

Reference voltage:

AV –0.2

AV +0.2

V

IN

SS

DD

REF

AV

AV –0.2

V

REF–

REF+

SS

AV +0.2

DD

R

C

Resistance between AV

and AV

REF–

10

50

15

kΩ

pF

REF

REF+

Analog input capacitance

Sampling time

IA

t

8t

CY

µs

ADS

ADC

Conversion time (including sampling time)

50t

µs

CY

10, 11, 12

DL

Differential non-linearity

±1

LSB

%

e

10, 13

IL

e

Integral non-linearity

±2

10, 14

OS

Offset error

e

10, 15

G

Gain error

±0.4

±3

e

10, 16

A

e

Absolute voltage error

LSB

dB

M

CTC

Channel to channel matching

±1

17

C

Crosstalk between inputs of port 5

0–100kHz

–60

t

NOTES FOR DC ELECTRICAL CHARACTERISTICS:

1. See Figures 10 through 15 for I test conditions.

DD

2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10 ns; V = V + 0.5 V;

r

f

IL

SS

V

IH

= V – 0.5 V; XTAL2 not connected; EA = RST = Port 0 = EW = V ; STADC = V

.

DD

SS

3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10 ns; V = V + 0.5 V;

r

f

IL

SS

V

IH

= V – 0.5 V; XTAL2 not connected; Port 0 = EW = V ; EA = RST = STADC = V

.

DD

SS

4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = V

;

DD

EA = RST = STADC = XTAL1 = V

.

SS

2

5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I C specification, so an input voltage below 1.5 V will be recognized as a

logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.

6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition

current reaches its maximum value when V is approximately 2 V.

IN

7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due

OL

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify

ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no

OL

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

8. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9 V specification when the

OH

DD

address bits are stabilizing.

9. The following condition must not be exceeded: V – 0.2 V < AV < V + 0.2 V.

DD

10.Conditions: AV

= 0 V; AV = 5.0 V, AV

(80C552, 83C552) = 5.12 V. ADC is monotonic with no missing codes. Measurement by

REF–

DD

REF+

continuous conversion of AV = –20 mV to 5.12 V in steps of 0.5 mV.

IN

11. The differential non-linearity (DL ) is the difference between the actual step width and the ideal step width. (See Figure 1.)

e

12.The ADC is monotonic; there are no missing codes.

13.The integral non-linearity (IL ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

e

appropriate adjustment of gain and offset error. (See Figure 1.)

11

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

14.The offset error (OS ) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and

e

a straight line which fits the ideal transfer curve. (See Figure 1.)

15.The gain error (G ) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),

e

and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.)

16.The absolute voltage error (A ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

e

ADC and the ideal transfer curve.

17.This should be considered when both analog and digital signals are simultaneously input to port 5.

Offset

error

Gain

error

OS

e

G

e

1023

1022

1021

1020

1019

1018

(2)

7

6

5

(1)

Code

Out

(5)

4

3

(4)

(3)

2

1

0

1 LSB

(ideal)

1

2

3

4

5

6

7

1018

1019

1020

AV

1021

1022

)

1023

1024

AV (LSB

IN

Offset

error

OS

e

ideal

– AV

(1)

Example of an actual transfer curve.

The ideal transfer curve.

REF+

REF–

1 LSB =

(2)

(3)

(4)

(5)

1024

Differential non-linearity (DL ).

e

Integral non-linearity (IL ).

e

SU01693

Center of a step of the actual transfer curve.

Figure 1. ADC Conversion Characteristic

12

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

1, 2

AC ELECTRICAL CHARACTERISTICS

16 MHz version

16 MHz CLOCK

VARIABLE CLOCK

SYMBOL

1/t

FIGURE

PARAMETER

Oscillator frequency

MIN

MAX

MIN

MAX

UNIT

MHz

ns

2

3.5

16

CLCL

t

ALE pulse width

85

8

2t

–40

LHLL

CLCL

Address valid to ALE low

Address hold after ALE low

ALE low to valid instruction in

ALE low to PSEN low

t

–55

ns

AVLL

LLAX

LLIV

CLCL

28

–35

ns

150

83

4t

3t

–100

ns

CLCL

23

t

–40

ns

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

PSEN pulse width

143

3t

–45

ns

CLCL

PSEN low to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address to valid instruction in

PSEN low to address float

–105

ns

CLCL

0

ns

38

208

10

t

–25

ns

CLCL

5t

–105

ns

CLCL

10

ns

Data Memory

t

3

4

RD pulse width

275

6t

–100

ns

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

AVDV

LLWL

AVWL

QVWX

DW

CLCL

WR pulse width

6t

CLCL

3

RD low to valid data in

Data hold after RD

148

5t

–165

CLCL

3

0

3

Data float after RD

55

2t

–70

CLCL

3

ALE low to valid data in

Address to valid data in

ALE low to RD or WR low

Address valid to WR low or RD low

Data valid to WR transition

Data before WR

350

398

238

8t

CLCL

9t

CLCL

–150

–165

3

3, 4

4

138

120

3

3t

–50

3t

+50

CLCL

4t

t

–130

–60

CLCL

4

288

13

7t

t

–150

–50

4

Data hold after WR

WHQX

RLAZ

WHLH

3

RD low to address float

RD or WR high to ALE high

0

3, 4

23

103

t

–40

t

+40

CLCL

External Clock

4

t

5

High time

20

ns

CHCX

CLCX

CLCH

CHCL

4

Low time

4

Rise time

20

4

Fall time

4

Serial Timing – Shift Register Mode (Test Conditions: T

= 0 °C to +70 °C; V = 0 V; Load Capacitance = 80 pF)

SS

amb

t

6

Serial port clock cycle time

0.75

492

8

12t

µs

ns

XLXL

CLCL

Output data setup to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

10t

–133

QVXH

XHQX

XHDX

XHDV

CLCL

2t

CLCL

–117

0

492

10t –133

CLCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.

3. t

= 1/f

= 83.3ns at f

= 62.5ns at f

= one oscillator clock period.

CLCL

OSC

t

= 12 MHz.

= 16 MHz.

OSC

4. These values are characterized but not 100% production tested.

13

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

1, 2

AC ELECTRICAL CHARACTERISTICS (Continued)

24 MHz version

24 MHz CLOCK

VARIABLE CLOCK

SYMBOL

1/t

FIGURE

PARAMETER

Oscillator frequency

MIN

MAX

MIN

MAX

UNIT

MHz

ns

2

3.5

24

CLCL

t

ALE pulse width

43

17

2t

–40

LHLL

CLCL

Address valid to ALE low

Address hold after ALE low

ALE low to valid instruction in

ALE low to PSEN low

t

–25

ns

AVLL

LLAX

LLIV

CLCL

t

–25

ns

102

65

4t

3t

–65

ns

CLCL

17

80

t

–25

ns

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

PSEN pulse width

3t

–45

ns

CLCL

PSEN low to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address to valid instruction in

PSEN low to address float

–60

ns

CLCL

0

ns

17

128

10

t

–25

ns

CLCL

5t

–80

ns

CLCL

10

ns

Data Memory

t

3

4

RD pulse width

150

6t

–100

ns

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

AVDV

LLWL

AVWL

QVWX

DW

CLCL

WR pulse width

6t

CLCL

3

RD low to valid data in

Data hold after RD

118

5t

2t

–90

–28

CLCL

3

0

3

Data float after RDxs

ALE low to valid data in

Address to valid data in

ALE low to RD or WR low

Address valid to WR low or RD low

Data valid to WR transition

Data before WR

55

CLCL

3

183

210

175

8t

–150

–165

CLCL

3

9t

3, 4

4

75

92

3t

–50

–75

3t

CLCL

+50

CLCL

4t

CLCL

12

t

CLCL

7t

CLCL

t

CLCL

–30

4

162

17

–130

–25

4

Data hold after WR

WHQX

RLAZ

WHLH

3

RD low to address float

RD or WR high to ALE high

0

3, 4

17

67

t

–25

t

+25

CLCL

External Clock

3

t

5

High time

17

ns

CHCX

CLCX

CLCH

CHCL

3

Low time

3

Rise time

5

20

3

Fall time

3

Serial Timing – Shift Register Mode (Test Conditions: T

= 0 °C to +70 °C; V = 0 V; Load Capacitance = 80 pF)

SS

amb

t

6

Serial port clock cycle time

0.5

283

23

0

12t

µs

ns

XLXL

CLCL

Output data setup to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

10t

–133

–60

QVXH

XHQX

XHDX

XHDV

CLCL

2t

CLCL

0

283

10t

–133

CLCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.

3. These values are characterized but not 100% production tested.

4. t

t

= 1/f

= 41.7ns at f

= one oscillator clock period.

CLCL

OSC

= 24 MHz.

OSC

14

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

AC ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL

PARAMETER

INPUT

OUTPUT

2

I C Interface (Refer to Figure 9)

1

t

START condition hold time

≥ 14 t

> 4.0 µs

HD;STA

LOW

CLCL

1

SCL low time

≥ 16 t

≥ 14 t

> 4.7 µs

1

SCL high time

> 4.0 µs

HIGH

2

SCL rise time

≤ 1 µs

–

RC

3

SCL fall time

≤ 0.3 µs

≥ 250ns

≥ 0ns

< 0.3 µs

FC

Data set-up time

> 20 t

– t

SU;DAT1

SU;DAT2

SU;DAT3

HD;DAT

SU;STA

SU;STO

BUF

CLCL

RD

1

SDA set-up time (before rep. START cond.)

SDA set-up time (before STOP cond.)

Data hold time

> 1 µs

> 8 t

CLCL

> 8 t

– t

CLCL

FC

1

Repeated START set-up time

STOP condition set-up time

Bus free time

≥ 14 t

> 4.7 µs

> 4.0 µs

> 4.7 µs

CLCL

1

2

SDA rise time

≤ 1 µs

≤ 0.3 µs

–

RD

3

SDA fall time

< 0.3 µs

FD

NOTES:

1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.

2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 µs.

3. Spikes on the SDA and SCL lines with a duration of less than 3 t

SCL = 400 pF.

will be filtered out. Maximum capacitance on bus-lines SDA and

CLCL

4. t

= 1/f

= one oscillator clock period at pin XTAL1. For 62 ns, 42 ns < t

< 285 ns (16 MHz, 24 MHz > f

> 3.5 MHz) the SI01

CLCL

OSC

CLCL

OSC

2

interface meets the I C-bus specification for bit-rates up to 100 kbit/s.

15

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always

Q – Output data

R – RD signal

‘t’ (= time). The other characters, depending on their positions,

indicate the name of a signal or the logical status of that signal. The

t – Time

designations are:

A – Address

V – Valid

W – WR signal

C – Clock

D – Input data

H – Logic level high

X – No longer a valid logic level

Z – Float

Examples: t

= Time for address valid to

AVLL

I

– Instruction (program memory contents)

ALE low.

L – Logic level low, or ALE

P – PSEN

t

= Time for ALE low to

PSEN low.

LLPL

t

LHLL

ALE

t

PLPH

t

LLPL

AVLL

t

LLIV

PSEN

t

PLIV

t

PLAZ

t

PXIZ

t

LLAX

t

PXIX

A0–A7

INSTR IN

A0–A7

PORT 0

PORT 2

t

AVIV

A8–A15

SU01694

Figure 2. External Program Memory Read Cycle

ALE

PSEN

RD

t

WHLH

t

LLDV

t

LLWL

RLRH

t

RHDZ

t

LLAX

t

RLDV

AVLL

t

RLAZ

RHDX

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA IN

A0–A7 FROM PCL

INSTR IN

t

AVWL

t

AVDV

P2.0–P2.7 OR A8–A15 FROM DPH

A8–A15 FROM PCH

SU01695

Figure 3. External Data Memory Read Cycle

16

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

ALE

t

WHLH

PSEN

t

WLWH

LLWL

WR

t

LLAX

WHQX

t

AVLL

QVWX

t

DW

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA OUT

A0–A7 FROM PCL

INSTR IN

t

AVWL

P2.0–P2.7 OR A8–A15 FROM DPH

A8–A15 FROM PCH

SU01696

Figure 4. External Data Memory Write Cycle

t

r

t

f

t

HIGH

V

0.8 V

V

IH1

0.8 V

V

0.8 V

V

IH1

0.8 V

IH1

t

LOW

t

SU01697

CLCL

Figure 5. External Clock Drive XTAL1

INSTRUCTION

ALE

0

1

2

3

4

5

6

7

8

t

XLXL

CLOCK

t

XHQX

t

QVXH

OUTPUT DATA

0

1

2

3

4

5

6

7

WRITE TO SBUF

t

XHDX

XHDV

SET TI

VALID

INPUT DATA

CLEAR RI

VALID

SET RI

SU01678

Figure 6. Shift Register Mode Timing

17

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

V

–0.5

DD

V

+0.1 V

–0.1 V

V

–0.1 V

TIMING

REFERENCE

POINTS

LOAD

OH

0.2 V

+0.9

–0.1

DD

V

LOAD

DD

V

+0.1 V

LOAD

OL

0.45 V

NOTE:

AC INPUTS DURING TESTING ARE DRIVEN AT V

FOR TIMING PURPOSES, A PORT IS NO LONGER FLOATING WHEN A 100MV

CHANGE FROM LOAD VOLTAGE OCCURS, AND BEGINS TO FLOAT WHEN A

100 mV CHANGE FROM THE LOADED V

20mA.

–0.5 FOR A LOGIC ‘1’ AND

DD

0.45 V FOR A LOGIC ‘0’. TIMING MEASUREMENTS ARE MADE AT V MIN FOR A

IH

/V

OH OL

LEVEL OCCURS. I

/I > +

OH OL

LOGIC ‘1’ AND V MAX FOR A LOGIC ‘0’.

IL

SU01700

SU01699

Figure 7. AC Testing Input/Output

Figure 8. Float Waveform

repeated START condition

STOP condition

START or repeated START condition

START condition

t

SU;STA

t

RD

SDA

(INPUT/OUTPUT)

0.7 V

CC

0.3 V

CC

t

BUF

t

FC

FD

RC

t

SU;STO

0.7 V

CC

SCL

(INPUT/OUTPUT)

0.3 V

CC

t

SU;DAT3

t

SU;DAT1

t

SU;DAT2

SU01701

HD;STA

LOW

HIGH

HD;DAT

2

Figure 9. Timing SIO1 (I C) Interface

18

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

50

40

30

(1)

(2)

I

, I mA

D

DD

20

(3)

(4)

10

0

4

8

12

16

(1)

Maximum operating mode; V

= 6 V

= 4 V

DD

(2)

(3)

(4)

f (MHz)

Maximum idle mode; V

= 6 V

DD

NOTE:

These values are valid only within the frequency specifications of the device under test.

= 4 V

SU01702

Figure 10. 16 MHz Version Supply Current (I ) as a Function of Frequency at XTAL1 (f

)

DD

OSC

60

(1)

50

(2)

40

30

I

, I mA

D

DD

20

10

0

(3)

(4)

0

4

8

12

16

20

24

f (MHz)

(1)

5.5 V

Maximum operating mode; V

=

DD

(2)

4.5 V

(3)

Maximum idle mode; V

= 5.5 V

= 4.5 V

NOTE:

These values are valid only within the frequency specifications of the device under test.

DD

(4)

SU01703

Figure 11. 24 MHz Version Supply Current (I ) as a Function of Frequency at XTAL1 (f

)

DD

OSC

19

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

V

DD

I

DD

P1.6

P1.7

V

DD

P0

V

–0.5

DD

0.5 V

V

DD

0.7V

DD

–0.1

0.2V

DD

t

CHCX

RST

t

CHCL

t

CLCX

CLCH

EA

STADC

EW

(NC)

CLOCK SIGNAL

XTAL2

XTAL1

t

CLCL

AV

SS

V

SS

AV

ref–

SU01706

SU01704

Figure 12. I Test Condition, Active Mode

DD

1

Figure 14. Clock Signal Waveform for I Tests in Active and

DD

All other pins are disconnected

Idle Modes t

= t

= 5ns

CHCL

CLCH

V

DD

V

DD

I

DD

I

DD

P1.6

P1.7

V

DD

V

DD

RST

V

DD

V

RST

DD

STADC

P0

EW

EA

(NC)

XTAL2

XTAL1

EW

EA

(NC)

XTAL2

XTAL1

CLOCK SIGNAL

AV

SS

AV

V

SS

AV

V

ref–

SS

AV

ref–

SU01705

SU01707

Figure 13. I Test Condition, Idle Mode

DD

2

All other pins are disconnected

Figure 15. I Test Condition, Power Down Mode

DD

3

All other pins are disconnected. V = 2 V to 5.5 V

DD

NOTES:

1. Active Mode:

a. The following pins must be forced to V : EA, RST, Port 0, and EW.

DD

b. The following pins must be forced to V : STADC, AV , and AV .

ref–

SS

ss

c. Ports 1.6 and 1.7 should be connected to V through resistors of sufficiently high value such that the sink current into these pins cannot

DD

exceed the I

spec of these pins.

OL1

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

2. Idle Mode:

a. The following pins must be forced to V : Port 0 and EW.

DD

b. The following pins must be forced to V : RST, STADC, AV ,, AV , and EA.

SS

ss

ref–

c. Ports 1.6 and 1.7 should be connected to V through resistors of sufficiently high value such that the sink current into these pins cannot

DD

exceed the I

spec of these pins. These pins must not have logic 0 written to them prior to this measurement.

OL1

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

3. Power Down Mode:

a. The following pins must be forced to V : Port 0 and EW.

DD

b. The following pins must be forced to V : RST, STADC, XTAL1, AV ,, AV , and EA.

SS

ss

ref–

c. Ports 1.6 and 1.7 should be connected to V through resistors of sufficiently high value such that the sink current into these pins cannot

DD

exceed the I

spec of these pins. These pins must not have logic 0 written to them prior to this measurement.

OL1

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

20

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

PLCC68: plastic leaded chip carrier; 68 leads

SOT188-2

21

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

SOT318-2

22

2002 Sep 03

Philips Semiconductors

Product data

Single-chip 8-bit microcontroller with 10-bit A/D,

capture/compare timer, high-speed outputs, PWM

80C552/83C552

2

Purchase of Philips I C components conveys a license under the Philips’ I C patent

2

to use the components in the I C system provided the system conforms to the

I C specifications defined by Philips. This specification can be ordered using the

2

code 9398 393 40011.

Data sheet status

Product

status

Definitions

[1]

Data sheet status

[2]

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be

published at a later date. Philips Semiconductors reserves the right to change the specification

without notice, in order to improve the design and supply the best possible product.

Product data

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply.

Changes will be communicated according to the Customer Product/Process Change Notification

(CPCN) procedure SNW-SQ-650A.

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Koninklijke Philips Electronics N.V. 2002

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 09-02

9397 750 10294

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

23

2002 Sep 03


型号：	P80C552KBB
厂家：	NXP
描述：	Single-chip 8-bit microcontroller 单芯片8位微控制器微控制器和处理器外围集成电路时钟
文件：	总23页 (文件大小：185K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

P80C552KBB [NXP]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E