P80C575EHAA-T_技术文档

INTEGRATED CIRCUITS

80C575/83C575/87C575

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator,

failure detect circuitry, watchdog timer

Product specification

1998 May 01

Supersedes data of 1998 Jan 27

IC20 Data Handbook

Philips

Semiconductors

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

DESCRIPTION

FEATURES

PIN CONFIGURATIONS

The Philips 80C575/83C575/87C575 is a

high-performance microcontroller fabricated

with Philips high-density CMOS technology.

The Philips CMOS technology combines the

high speed and density characteristics of

HMOS with the low power attributes of

CMOS. Philips epitaxial substrate minimizes

latch-up sensitivity.

• 80C51 based architecture

– 8k × 8 ROM (83C575)

– 8k × 8 EPROM (87C575)

– ROMless (80C575)

– 256 × 8 RAM

40

39

38

37

1

2

3

V

CMP0+/P1.0/T2

DD

CMP0-/P1.1/T2EX

P0.0/AD0

P0.1/AD1

P0.2/AD2

ECI/P1.2

CMP0/CEX0/P1.3

CMP1/CEX1/P1.4

4

5

– Three 16-bit counter/timers

– Programmable Counter Array

– Enhanced UART

36 P0.3/AD3

35 P0.4/AD4

34 P0.5/AD5

The 8XC575 contains an 8k × 8 ROM

(83C575) EPROM (87C575), a 256 × 8 RAM,

32 I/O lines, three 16-bit counter/timers, a

Programmable Counter Array (PCA), a

seven-source, two-priority level nested

interrupt structure, an enhanced UART, four

analog comparators, power-fail detect and

oscillator fail detect circuits, and on-chip

oscillator and clock circuits.

CMP2/CEX2/P1.5

CMP3/CEX3/P1.6

CEX4/P1.7

6

7

8

9

– Boolean processor

– Oscillator fail detect

– Low active reset

33

32

31

P0.6/AD6

P0.7/AD7

RST

– Asynchronous low port reset

– Schmitt trigger inputs

– 4 analog comparators

– Watchdog timer

RxD/P3.0 10

TxD/P3.1 11

EA/V

PP

DUAL

IN-LINE

PACKAGE

30 ALE/PROG

29 PSEN

INT0/P3.2 12

In addition, the 8XC575 has a low active

reset, and the port pins are reset to a low

level. There is also a fully configurable

watchdog timer, and internal power on clear

circuit. The part includes idle mode and

power-down mode states for reduced power

consumption.

– Low V detect

CC

28

INT1/P3.3 13

P2.7/A15

• Memory addressing capability

– 64k ROM and 64k RAM

27 P2.6/A14

26 P2.5/A13

25 P2.4/A12

24 P2.3/A11

CMPR-/T0/P3.4 14

CMP1+/T1/P3.5 15

CMP2+/WR/P3.6 16

CMP3+/RD/P3.7 17

XTAL2 18

• Power control modes:

– Idle mode

– Power-down mode

23

22

P2.2/A10

P2.1/A9

P2.0/A8

• CMOS and TTL compatible

• 4.0 to 16MHz

XTAL1 19

21

20

V

SS

• Extended temperature ranges

• OTP package available

44

12

34

6

1

40

39

7

1

33

23

PQFP

LCC

17

11

29

18

28

22

SU00234

ORDERING INFORMATION

FREQ DRAWING

(MHz) NUMBER

1

ROMless

ROM

EPROM

TEMPERATURE RANGE °C AND PACKAGE

P80C575EBPN P83C575EBPN P87C575EBPN

P80C575EBAA P83C575EBAA P87C575EBAA

P80C575EHAA P83C575EHAA P87C575EHAA

P80C575EBBB P83C575EBBB P87C575EBBB

OTP

0 to +70, 40-Pin Plastic Dual In-line Package

0 to +70, 44-Pin Plastic Leaded Chip Carrier

–40 to +125, 44-Pin Plastic Leaded Chip Carrier

0 to +70, 44-Pin Plastic Quad Flat Pack

16

SOT129-1

SOT187-2

SOT307-2

NOTE:

1. OTP - One Time Programmable EPROM.

2

1998 May 01

853-1684 19332

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

BLOCK DIAGRAM

P0.0-P0.7

P2.0-P2.7

PORT 0

DRIVERS

PORT 2

DRIVERS

V

CC

SS

ROM/

EPROM

RAM ADDR

REGISTER

PORT 0

LATCH

PORT 2

LATCH

RAM

B

STACK

POINTER

ACC

REGISTER

PROGRAM

ADDRESS

REGISTER

TMP1

TMP2

BUFFER

ALU

SFRs

TIMERS

PCA

PC

INCRE-

MENTER

PSW

PROGRAM

COUNTER

PSEN

ALE

EA

TIMING

AND

CONTROL

DPTR

RST

PORT 1

LATCH

PORT 3

LATCH

PD

OSCILLATOR

PORT 1

DRIVERS

PORT 3

DRIVERS

XTAL1

XTAL2

P1.0-P1.7

P3.0-P3.7

SU00238

3

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

CERAMIC AND PLASTIC LEADED PLASTIC QUAD FLAT PACK

CHIP CARRIER PIN FUNCTIONS

PIN FUNCTIONS

44

34

6

1

40

7

39

29

1

33

23

LCC

PQFP

11

17

18

28

12

22

Pin Function

23 NC*

Pin Function

23 P2.5/A13

24 P2.6/A14

25 P2.7/A15

26 PSEN

1

2

3

4

5

6

7

8

9

NC*

1

2

3

4

5

6

7

8

9

P1.5/CMP2/CEX2

P1.6/CMP3/CEX3

P1.7/CEX4

RST

T2/P1.0/CMP0+

T2EX/P1.1/CMP0–

P1.2/ECI

24 P2.0/A8

25 P2.1/A9

26 P2.2/A10

27 P2.3/A11

28 P2.4/A12

29 P2.5/A13

30 P2.6/A14

31 P2.7/A15

32 PSEN

P1.3/CMP0/CEX0

P1.4/CMP1/CEX1

P1.5/CMP2/CEX2

P1.6/CMP3/CEX3

P1.7/CEX4

RxD/P3.0

NC*

27 ALE/PROG

28 NC*

TxD/P3.1

29 EA/V

PP

INT0/P3.2

INT1/P3.3

30 P0.7/AD7

31 P0.6/AD6

32 P0.5/AD5

33 P0.4/AD4

34 P0.3/AD3

35 P0.2/AD2

36 P0.1/AD1

37 P0.0/AD0

10 RST

10 T0/P3.4/CMPR–

11 T1/P3.5/CMP1+

12 WR/P3.6/CMP2+

13 RD/P3.7CMP3+

14 XTAL2

11 RxD/P3.0

12 NC*

33 ALE/PROG

34 NC*

13 TxD/P3.1

14 INT0/P3.2

15 INT1/P3.3

16 T0/P3.4/CMPR–

17 T1/P3.5/CMP1+

18 WR/P3.6/CMP2+

19 RD/P3.7/CMP3+

20 XTAL2

35 EA/V

PP

36 P0.7/AD7

37 P0.6/AD6

38 P0.5/AD5

39 P0.4/AD4

40 P0.3/AD3

41 P0.2/AD2

42 P0.1/AD1

43 P0.0/AD0

15 XTAL1

16

V

38

V

CC

SS

17 NC*

39 NC*

18 P2.0/A8

19 P2.1/A9

20 P2.2/A10

21 P2.3/A11

22 P2.4/A12

40 T2/P1.0/CMP0+

41 T2EX/P1.1/CMP0–

42 P1.2/ECI

21 XTAL1

43 P1.3/CMP0/CEX0

44 P1.4/CMP1/CEX1

22

V

44

V

CC

SS

* NO INTERNAL CONNECTION

SU00236

SU00235

LOGIC SYMBOL

V

SS

CC

XTAL1

ADDRESS AND

DATA BUS

XTAL2

RST

T2

CMP0+

CMP0–

ECI

T2EX

CMP0/CEX0

EA/V

PP

CMP1/CEX1

CMP2/CEX2

CMP3/CEX3

PSEN

ALE/PROG

RxD

TxD

CEX4

INT0

INT1

T0

T1

WR

RD

ADDRESS BUS

CMPR–

CMP1+

CMP2+

CMP3+

SU00237

4

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC

DIP

20

LCC

22

QFP TYPE NAME AND FUNCTION

V

SS

CC

16

38

I

Ground: 0V reference.

V

40

44

Power Supply: This is the power supply voltage for normal, idle, and power-down

operation.

P0.0-0.7

39-32 43-36 37-30

I/O

Port 0: Port 0 is an open-drain bidirectional I/O port. Port 0 pins that have 1s written to them

float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order

address and data bus during accesses to external program and data memory. In this

application, it uses strong internal pull-ups when emitting 1s. Port 0 also receives code

bytes during EPROM programming and outputs code bytes during program verification.

External pull-ups are required during program verification. During reset, port 0 will be

asynchronously driven low and will remain low until written to by software. All port 0 pins

have Schmitt trigger inputs with 200mV hysteresis. A weak pulldown on port 0 guarantees

positive leakage current (see DC Electrical Characteristics: I ).

L1

P1.0-P1.7

1-8

2-9

40-44

1-3

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port. Port 1 pins have internal pull-ups such that

pins that have 1s written to them can be used as inputs but will source current when

externally pulled low (see DC Electrical Characteristics: I ). Port 1 receives the low-order

IL

address byte during program memory verification and EPROM programming. During reset,

port 1 will be asynchronously driven low and will remain low until written to by software. All

port 1 pins have Schmitt trigger inputs with 50mV hysteresis. Port 1 pins also serve

alternate functions as follows:

1

2

3

40

41

I/O

I

P1.0 T2

Timer 2 external I/O – clockout (programmable)

CMP0+ Comparator 0 positive input

P1.1 T2EX

P1.2 ECI

Timer 2 capture input

CMP0- Comparator 0 negative input

3

4

5

42

43

I

PCA count input

PCA module 0 external I/O

Comparator 0 output

I/O

P1.3 CEX0

CMP0

5

6

7

8

6

7

8

9

44

1

I/O

P1.4 CEX1

CMP1

P1.5 CEX2

CMP2

P1.6 CEX3

CMP3

P1.7 CEX4

PCA module 1 external I/O

Comparator 1 output

PCA module 2 external I/O

Comparator 2 output

PCA module 3 external I/O

Comparator 3 output

PCA module 4 external I/O

2

3

I/O

P2.0-P2.7

21-28 24-31 18-25

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s

written to them can be used as inputs, but will source current when externally pulled low

(see DC Electrical Characteristics: I ). Port 2 emits the high-order address byte during

IL

accesses to external program and data memory that use 16-bit addresses (MOVX

@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. Port 2

receives the high-order address byte during program verification and EPROM programming.

During reset, port 2 will be asynchronously driven low and will remain low until written to by

software. Port 2 can be made open drain by writing to the P2OD register (AIH). In open

drain mode, weak pulldowns on port 2 guarantee positive leakage current (see DC

Electrical Characteristics I ).

L1

P3.0-P3.7

10-17

11,

13-19

5,

7-13

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins except P3.1

that have 1s written to them can be used as inputs but will source current when externally

pulled low (see DC Electrical Characteristics: I ). P3.1 will be a high impedance pin except

IL

while transmitting serial data, in which case the strong pull-up will remain on continuously

when outputting a 1 level. The P3.1 output drive level when transmitting can be set to one of

two levels by the writing to the P3.1 register bit. During reset all pins (except P3.1) will be

asynchronously driven low and will remain low until written to by software. All port 3 pins

have Schmitt trigger inputs with 200mV hysteresis, except P3.2 and P3.3, which have 50mV

hysteresis. Port 3 pins serve alternate functions as follows:

5

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

PIN DESCRIPTIONS (Continued)

PIN NUMBER

MNEMONIC

DIP

LCC

QFP TYPE NAME AND FUNCTION

Port 3: (continued)

10

11

12

13

14

11

13

14

15

16

5

7

8

9

10

I

O

I

P3.0 RxD

P3.1 TxD

P3.2 INT0

P3.3 INT1

P3.4 T0

Serial receive port

Serial transmit port enabled only when transmitting serial data

External interrupt 0

External interrupt 1

Timer/counter 0 input

CMPR- Common - reference to comparators 1, 2, 3

15

16

17

18

19

11

12

13

I

P3.5 T1

Timer/counter 1 input

CMP1+ Comparator 1 positive input

P3.6 WR

CMP2+ Comparator 2 positive input

P3.7 RD

O

External data memory write strobe

External data memory read strobe

CMP3+ Comparator 3 positive input

RST

9

10

4

I

Reset: A low on this pin asynchronously resets all port pins to a low state except P3.1. The

pin must be held low with the oscillator running for 24 oscillator cycles to initialize the

internal registers. An internal diffused resistor to V permits a power on reset using only

CC

an external capacitor to V . RST has a Schmitt trigger input stage to provide additional

SS

noise immunity with a slow rising input voltage.

ALE/PROG

30

33

27

I/O

Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

address during an access to external memory. In normal operation, ALE is emitted at a

constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.

Note that one ALE pulse is skipped during each access to external data memory. ALE is

switched off if the bit 0 in the AUXR register (8EH) is set. This pin is also the program pulse

input (PROG) during EPROM programming.

PSEN

29

31

32

35

26

29

O

I

Program Store Enable: The read strobe to external program memory. When the device is

executing code from the external program memory, PSEN is activated twice each machine

cycle, except that two PSEN activations are skipped during each access to external data

memory. PSEN is not activated during fetches from internal program memory.

EA/V

External Access Enable/Programming Supply Voltage: EA must be externally held low

to enable the device to fetch code from external program memory locations 0000H to

1FFFH. If EA is held high, the device executes from internal program memory unless the

program counter contains an address greater than 1FFFH. This pin also receives the

PP

12.75V programming supply voltage (V ) during EPROM programming.

PP

XTAL1

XTAL2

19

18

21

20

15

14

I

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator

circuits.

O

Crystal 2: Output from the inverting oscillator amplifier.

6

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

Table 1.

87C575 Special Function Registers

DIRECT

ADDRESS MSB

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

RESET

VALUE

SYMBOL

DESCRIPTION

LSB

ACC*

AUXR#

B*

Accumulator

Auxiliary

E0H

8EH

E7

–

E6

–

E5

–

E4

–

E3

–

E2

–

E1

LO

F1

E0

00H

AO

F0

xxxxxx00B

B register

F0H

FAH

FBH

FCH

FDH

FEH

EAH

EBH

ECH

EDH

EEH

F7

F6

F5

F4

F3

F2

00H

CCAP0H# Module 0 Capture High

CCAP1H# Module 1 Capture High

CCAP2H# Module 2 Capture High

CCAP3H# Module 3 Capture High

CCAP4H# Module 4 Capture High

CCAP0L# Module 0 Capture Low

CCAP1L# Module 1 Capture Low

CCAP2L# Module 2 Capture Low

CCAP3L# Module 3 Capture Low

CCAP4L# Module 4 Capture Low

xxxxxxxxB

CCAPM0# Module 0 Mode

CCAPM1# Module 1 Mode

CCAPM2# Module 2 Mode

CCAPM3# Module 3 Mode

CCAPM4# Module 4 Mode

DAH

DBH

DCH

DDH

DEH

–

ECOM

CAPP

CAPN

MAT

TOG

PWM

ECCF

x0000000B

DF

CF

DE

CR

DD

–

DC

DB

DA

D9

D8

CCON*#

CH#

CL#

PCA Counter Control

PCA Counter High

PCA Counter Low

PCA Counter Mode

D8H

F9H

E9H

D9H

CCF4

CCF3

CCF2 CCF1

CCF0

00x00000B

00H

CMOD#

CIDL

EF

WDTE

EE

–

CPS1 CPS0

ECF

00xxx000B

ED

EC

EB

EA

E9

E8

CMP*#

CMPE#

Comparator

E8H

91H

EC3DP EC2DP EC1DP EC0DP C3RO

C2RO C1RO

EC2OD EC1OD

C0RO

EC0OD

00H

Comparator Enable

EC3TDC EC2TDC EC1TDC EC0TDC

EC3OD

DPTR:

DPH

DPL

Data Pointer (2 bytes)

Data Pointer High

Data Pointer Low

83H

82H

00H

AF

EA

BF

–

AE

EC

AD

ET2

BD

AC

ES

BC

PS

AB

ET1

BB

AA

EX1

BA

A9

ET0

B9

A8

EX0

B8

IE*

IP*

Interrupt Enable

Interrupt Priority

A8H

B8H

00H

BE

PPC

PT2

PT1

PX1

PT0

PX0

x0000000B

87

86

85

84

83

82

81

80

P0*

P1*

P2*

P3*

Port 0

Port 1

Port 2

Port 3

80H

90H

A0H

B0H

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

00H

97

CEX4

A7

96

CEX3

A6

95

CEX2

A5

94

CEX1

A4

93

CEX0

A3

92

EXI

A2

91

T2EX

A1

90

T2

A0

AD15

B7

AD14

B6

AD13

B5

AD12

B4

AD11

B3

AD10

B2

AD9

B1

AD8

B0

RD

WR

T1

T0

INT1

INT0

TxD

RxD

*

#

SFRs are bit addressable.

SFRs are modified from or added to the 80C51 SFRs.

1. 87C575 only.

7

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

Table 1.

SYMBOL

P2OD#

87C575 Special Function Registers (Continued)

DIRECT

DESCRIPTION

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

ADDRESS MSB

RESET

VALUE

LSB

Port 2 Pullup Disable

Power Control

A1H

00H

1

PCON#

87H

SMOD1

SMOD0

OSF

POF

LVF

GF0

PD

IDL

00xxx000B

D7

CY

D6

AC

D5

F0

D4

D3

D2

D1

–

D0

P

PSW*

Program Status Word

D0H

RS1

RS0

OV

00H

RACAP2H#

Timer 2 Capture High

Timer 2 Capture Low

CBH

CAH

00H

RACAP2L

#

SADDR#

SADEN#

Slave Address

Slave Address Mask

A9H

B9H

00H

SBUF

Serial Data Buffer

99H

xxxxxxxxB

9F

9E

9D

9C

9B

9A

99

TI

98

RI

SCON*

SP

Serial Control

Stack Pointer

98H

81H

SM0

SM1

SM2

REN

TB8

RB8

00H

07H

8F

8E

8D

8C

8B

8A

89

88

TCON*

Timer Control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00H

CF

TF2

–

CE

EXF2

–

CD

RCLK

–

CC

CB

CA

TR2

–

C9

C8

T2CON*

T2MOD#

Timer 2 Control

C8H

C9H

TCLK EXEN2

C/T2 CP/RL2 00H

2

Timer 2 Mode Control

–

T2OE

DCEN xxxxxxx0B

TH0

TH1

TH2#

TL0

TL1

TL2#

Timer High 0

Timer High 1

Timer High 2

Timer Low 0

Timer Low 1

Timer Low 2

8CH

8DH

CDH

8AH

8BH

CCH

00H

TMOD

Timer Mode

89H

GATE

C7

C/T

C6

M1

C5

M0

C4

GATE

C3

C/T

C2

M1

C1

M0

C0

00H

WDCON*#

WDL#

WFEED1# Watchdog Feed 1

WFEED2# Watchdog Feed 2

Watchdog Timer Control

Watchdog Timer Reload

C0H

PRE2

PRE1

PRE0

LVRE

OFRE WDRUN WDTOF WDMOD 11111101B

C1H

C2H

C3H

00H

xxH

*

#

SFRs are bit addressable.

SFRs are modified from or added to the 80C51 SFRs.

1. Reset value depends on reset source.

2. Programmable clock-out.

8

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

The 8XC575 has an on-chip power-on

detection circuit that sets the POF (PCON.4)

POWER ON CLEAR/

POWER ON FLAG

An on-chip Power On Detect Circuit resets

the 8XC575 and sets the Power Off Flag

(PCON.4) on power up or if V drops to

zero momentarily. The POF can only be

cleared by software. The RST pin is not

driven by the power on detect circuit. The

POF can be read by software to determine

that a power failure has occurred and can

also be set by software.

LOW ACTIVE RESET

One of the most notable features on this part

is the low active reset. At this time this is the

only 80C51 derivative available that has low

active reset. This feature makes it easier to

interface the 8XC575 into an application to

accommodate the power-on and low voltage

conditions that can occur. The low active

reset operates exactly the same as high

active reset with the exception that the part is

put into the reset mode by applying a low

level to the reset pin. For power-on reset it is

also necessary to invert the power-on reset

circuit; connecting the 8.2K resistor from the

flag on power up or if the V level

CC

momentarily drops to 0V. This flag can be

used to determine if the part is being started

from a power-on (cold start) or if a reset has

occurred due to another condition (warm

start).

CC

TIMERS

The 87C575 has four on-chip timers.

Timers 0 and 1 are identical in every way to

Timers 0 and 1 on the 80C51.

LOW VOLTAGE DETECT

An on-chip Low Voltage Detect circuit sets

the Low Voltage Flag (PCON.3) if V drops

reset pin to V and the 10µf capacitor from

CC

Timer 2 on the 8XC575 is identical to the

80C52 Timer 2 (described in detail in the

80C52 overview) with the exception that it is

an up or down counter. To configure the

Timer to count down the DCEN bit in the

T2MOD special function register must be set

and a low level must be present on the T2EX

pin (P1.1).

CC

the reset pin to ground. Figure 1 shows all of

the reset related circuitry.

below V

(see DC Electrical

LOW

Characteristics) and resets the 8XC575 if the

Low Voltage Reset Enable bit (WDCON.4) is

set. If the LVRE is cleared, the reset is

disabled but LVF will still be set if V is low.

The RST pin is not driven by the low voltage

detect circuit. The LVF can be read by

When reset the port pins on the 87C575 are

driven low asynchronously. This is different

from all other 80C51 derivatives.

CC

The 8XC575 also has Low voltage detection

circuitry that will, if enabled, force the part to

software to determine that V was low. The

LVF can be set or cleared by software.

CC

The Watchdog timer operation and

reset when V (on the part) fails below a set

CC

implementation is the same as that for the

8XC550 (described in the 8XC550 overview)

with the exception that the reset values of the

WDCON and WDL special function registers

have been changed. The changes in these

registers cause the watchdog timer to be

level. Low Voltage Reset is enabled by a

normal reset. Low Voltage Reset can be

disabled by clearing LVRE (bit 4 in the

WDCON SFR) then executing a watchdog

feed sequence (A5H to WFEED1 followed

immediately by 5A to WFEED2). In addition

there is a flag (LVF) that is set if a low voltage

condition is detected. The LVF flag is set

even if the Low Voltage detection circuitry is

disabled. Notice that the Low voltage

OSCILLATOR FAIL DETECT

An on-chip Oscillator Fail Detect circuit sets

the Oscillator Fail Flag (PCON.5) if the

oscillator frequency drops below OSCF for

one or more cycles (see AC Electrical

Characteristics: OSCF) and resets the

8XC575 if the Oscillator Fail Reset Enable bit

(WDCON.3) is set. If OFRE is cleared, the

reset is disabled but OSF will still be set if the

oscillator fails. The RST pin is not driven by

the oscillator fail detect circuit. The OSF can

be read by software to determine that an

oscillator failure has occurred. The OSF can

be set or cleared by software.

enabled with a timeout of 98304 × T

OSC

when the part is reset. The watchdog can be

disabled by executing a valid feed sequence

and then clearing WDRUN (bit 2 in the

WDCON SFR).

detection circuitry does not drive the RST#

pin so the LVF flag is the only way that the

microcontroller can determine if it has been

reset due to a low voltage condition.

PCON

(87GH)

V

CC

SMOD1

SMOD0

OSF

POF

LVF

GF0

GF1

IDL

POWER-ON DETECT

8xC575

INTERNAL

RESET

+

–

VLOW

(LOW V

CC

REFERENCE)

OSC FREQ BELOW OSCF

(MIN FREQUENCY)

RST

PCA WATCHDOG

SHADOW REGISTER

FOR WDCON

WATCHDOG TIMER

WATCHDOG FEED

PRE2

WDCON

(C0H)

PRE1

PRE0

LVRE

OFRE

WDRUN

WDTOF WDMOD

SU00239

Figure 1. Reset Circuitry

9

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

The CCON SFR contains the run control bit

for the PCA and the flags for the PCA timer

(CF) and each module (refer to Figure 6). To

the register ECOM (CCAPMn.6) when set

enables the comparator function. Figure 8

shows the CCAPMn settings for the various

PCA functions.

PROGRAMMABLE COUNTER

ARRAY (PCA)

The Programmable Counter Array is a

run the PCA the CR bit (CCON.6) must be

special Timer that has five 16-bit

set by software. The PCA is shut off by

capture/compare modules associated with it.

clearing this bit. The CF bit (CCON.7) is set

Each of the modules can be programmed to

when the PCA counter overflows and an

operate in one of four modes: rising and/or

interrupt will be generated if the ECF bit in

falling edge capture, software timer,

There are two additional registers associated

with each of the PCA modules. They are

CCAPnH and CCAPnL and these are the

registers that store the 16-bit count when a

capture occurs or a compare should occur.

When a module is used in the PWM mode

these registers are used to control the duty

cycle of the output.

the CMOD register is set, The CF bit can only

high-speed output, or pulse width modulator.

be cleared by software. Bits 0 through 4 of

Each module has a pin associated with it in

the CCON register are the flags for the

port 1. Module 0 is connected to P1.3(CEX0),

modules (bit 0 for module 0, bit 1 for module

module 1 to P1.4(CEX1), etc.. The basic

1, etc.) and are set by hardware when either

PCA configuration is shown in Figure 2.

a match or a capture occurs. These flags

PCA Capture Mode

also can only be cleared by software. The

PCA interrupt system shown in Figure 4.

The PCA timer is a common time base for all

five modules and can be programmed to run

at: 1/12 the oscillator frequency, 1/4 the

oscillator frequency, the Timer 0 overflow, or

the input on the ECI pin (P1.2). The timer

count source is determined from the CPS1

and CPS0 bits in the CMOD SFR as follows

(see Figure 3):

To use one of the PCA modules in the

capture mode either one or both of the

CCAPM bits CAPN and CAPP for that

module must be set. The external CEX input

for the module (on port 1) is sampled for a

transition. When a valid transition occurs the

PCA hardware loads the value of the PCA

counter registers (CH and CL) into the

module’s capture registers (CCAPnL and

CCAPnH). If the CCFn bit for the module in

the CCON SFR and the ECCFn bit in the

CCAPMn SFR are set then an interrupt will

be generated. Refer to Figure 9.

Each module in the PCA has a special

function register associated with it. These

registers are: CCAPM0 for module 0,

CCAPM1 for module 1, etc. (see Figure 7).

The registers contain the bits that control the

mode that each module will operate in. The

ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or

4 depending on the module) enables the CCF

flag in the CCON SFR to generate an

interrupt when a match or compare occurs in

the associated module. PWM (CCAPMn.1)

enables the pulse width modulation mode.

The TOG bit (CCAPMn.2) when set causes

the CEX output associated with the module to

toggle when there is a match between the

PCA counter and the module’s

capture/compare register. The match bit MAT

(CCAPMn.3) when set will cause the CCFn

bit in the CCON register to be set when there

is a match between the PCA counter and the

module’s capture/compare register.

CPS1 CPS0 PCA Timer Count Source

0

1

0

1

0

1

1/12 oscillator frequency

1/4 oscillator frequency

Timer 0 overflow

External Input at ECI pin

In the CMOD SFR are three additional bits

associated with the PCA. They are CIDL

which allows the PCA to stop during idle

mode, WDTE which enables or disables the

watchdog function on module 4, and ECF

which when set causes an interrupt and the

PCA overflow flag CF (in the CCON SFR) to

be set when the PCA timer overflows. These

functions are shown in Figure 3.

16-bit Software Timer Mode

The PCA modules can be used as software

timers by setting both the ECOM and MAT

bits in the modules CCAPMn register. The

PCA timer will be compared to the module’s

capture registers and when a match occurs

an interrupt will occur if the CCFn (CCON

SFR) and the ECCFn (CCAPMn SFR) bits for

the module are both set (see Figure 10).

The watchdog timer function is implemented

in module 4 as implemented in other parts

that have a PCA that are available on the

market. However, if a watchdog timer is

required in the target application, it is

recommended to use the hardware watchdog

timer that is implemented on the 87C575

separately from the PCA (see Figure 14).

High Speed Output Mode

The next two bits CAPN (CCAPMn.4) and

CAPP (CCAPMn.5) determine the edge that

a capture input will be active on. The CAPN

bit enables the negative edge, and the CAPP

bit enables the positive edge. If both bits are

set both edges will be enabled and a capture

will occur for either transition. The last bit in

In this mode the CEX output (on port 1)

associated with the PCA module will toggle

each time a match occurs between the PCA

counter and the module’s capture registers.

To activate this mode the TOG, MAT, and

ECOM bits in the module’s CCAPMn SFR

must be set (see Figure 11).

16 BITS

P1.3/CEX0

P1.4/CEX1

P1.5/CEX2

P1.6/CEX3

MODULE 0

MODULE 1

MODULE 2

MODULE 3

MODULE 4

16 BITS

PCA TIMER/COUNTER

TIME BASE FOR PCA MODULES

MODULE FUNCTIONS:

16-BIT CAPTURE

16-BIT TIMER

P1.7/CEX4

SU00032

16-BIT HIGH SPEED OUTPUT

8-BIT PWM

WATCHDOG TIMER (MODULE 4 ONLY)

Figure 2. Programmable Counter Array (PCA)

10

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

TO PCA

MODULES

OSC/12

OVERFLOW

INTERRUPT

OSC/4

CH

CL

16–BIT UP COUNTER

TIMER 0

OVERFLOW

EXTERNAL INPUT

(P1.2/ECI)

00

01

10

11

DECODE

IDLE

CMOD

ECF

CIDL

CF

WDTE

––

CPS1

CCF2

CPS0

(D9H)

CCON

CR

CCF4

CCF3

CCF1

CCF0

(D8H)

SU00033

Figure 3. PCA Timer/Counter

CCON

(D8H)

CF

CR

––

CCF4

CCF3

CCF2

CCF1

CCF0

PCA TIMER/COUNTER

MODULE 0

IE.7

EA

IE.6

EC

TO

MODULE 1

MODULE 2

INTERRUPT

PRIORITY

DECODER

MODULE 3

MODULE 4

CCAPMn.0

ECCFn

CMOD.0

ECF

SU00034

Figure 4. PCA Interrupt System

11

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

CMOD Address = OD9H

Reset Value = 00XX X000B

CIDL

WDTE

–

CPS1

CPS0

ECF

Bit:

Function

7

6

5

4

3

2

1

0

Symbol

CIDL

Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs

it to be gated off during idle.

WDTE

–

Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.

Not implemented, reserved for future use.*

CPS1

CPS0

PCA Count Pulse Select bit 1.

PCA Count Pulse Select bit 0.

CPS1

CPS0

Selected PCA Input**

0

1

0

1

0

1

0

1

2

3

Internal clock, f

÷ 12

÷ 4

OSC

Internal clock, f

OSC

Timer 0 overflow

External clock at ECI/P1.2 pin (max. rate = f

÷ 8)

OSC

ECF

PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables

that function of CF.

NOTE:

*

User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the

new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

**

f

= oscillator frequency

OSC

SU00035

Figure 5. CMOD: PCA Counter Mode Register

CCON Address = OD8H

Reset Value = 00X0 0000B

Bit Addressable

CF

CR

–

CCF4

CCF3

CCF2

CCF1

CCF0

Bit:

7

6

5

4

3

2

1

0

Symbol

CF

Function

PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is

set. CF may be set by either hardware or software but can only be cleared by software.

CR

PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA

counter off.

–

Not implemented, reserved for future use*.

CCF4

CCF3

CCF2

CCF1

CCF0

PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

NOTE:

*

User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the

new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

SU00036

Figure 6. CCON: PCA Counter Control Register

12

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

CCAPMn Address

CCAPM0

CCAPM1

CCAPM2

CCAPM3

CCAPM4

0DAH

0DBH

0DCH

0DDH

0DEH

Reset Value = X000 0000B

Not Bit Addressable

–

ECOMn CAPPn

CAPNn

MATn

TOGn

PWMn

ECCFn

Bit:

7

6

5

4

3

2

1

0

Symbol

Function

–

Not implemented, reserved for future use*.

ECOMn

CAPPn

CAPNn

MATn

Enable Comparator. ECOMn = 1 enables the comparator function.

Capture Positive, CAPPn = 1 enables positive edge capture.

Capture Negative, CAPNn = 1 enables negative edge capture.

Match. When MATn = 1, a match of the PCA counter with this module’s compare/capture register causes the CCFn bit

in CCON to be set, flagging an interrupt.

TOGn

Toggle. When TOGn = 1, a match of the PCA counter with this module’s compare/capture register causes the CEXn

pin to toggle.

PWMn

ECCFn

Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output.

Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt.

NOTE:

*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new

bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

SU00037

Figure 7. CCAPMn: PCA Modules Compare/Capture Registers

–

X

ECOMn CAPPn CAPNn

MATn

TOGn

PWMn

ECCFn

MODULE FUNCTION

0

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

1

0

X

0

No operation

16-bit capture by a positive-edge trigger on CEXn

16-bit capture by a negative trigger on CEXn

16-bit capture by a transition on CEXn

16-bit Software Timer

16-bit High Speed Output

8-bit PWM

X

Watchdog Timer

Figure 8. PCA Module Modes (CCAPMn Register)

13

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

CCON

(D8H)

CF

CR

––

CCF4

CCF3

CCF2

CCF1

CCF0

PCA INTERRUPT

(TO CCFn)

PCA TIMER/COUNTER

CH

CL

CAPTURE

CEXn

CCAPnH

CCAPnL

CCAPMn, n= 0 to 4

(DAH – DEH)

––

ECOMn

0

CAPPn

CAPNn

MATn

0

TOGn

0

PWMn

ECCFn

0

SU00749

Figure 9. PCA Capture Mode

CCON

(D8H)

CF

CR

––

CCF4

CCF3

CCF2

CCF1

CCF0

WRITE TO

CCAPnH

RESET

PCA INTERRUPT

CCAPnH

CCAPnL

WRITE TO

CCAPnL

(TO CCFn)

0

1

ENABLE

MATCH

16–BIT COMPARATOR

CH

CL

PCA TIMER/COUNTER

CCAPMn, n= 0 to 4

(DAH – DEH)

––

ECOMn

CAPPn

0

CAPNn

0

MATn

TOGn

0

PWMn

0

ECCFn

SU00750

Figure 10. PCA Compare Mode

14

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

CCON

CF

CR

––

CCF4

CCF3

CCF2

CCF1

CCF0

(D8H)

WRITE TO

CCAPnH

RESET

PCA INTERRUPT

CCAPnH

CCAPnL

WRITE TO

CCAPnL

(TO CCFn)

0

1

MATCH

ENABLE

16–BIT COMPARATOR

TOGGLE

CEXn

CH

CL

PCA TIMER/COUNTER

CCAPMn, n: 0..4

ECCFn

––

ECOMn

CAPPn

0

CAPNn

0

MATn

TOGn

PWMn

0

(DAH – DEH)

1

SU00751

Figure 11. PCA High Speed Output Mode

Pulse Width Modulator Mode

intervening instruction fetches are allowed,

so interrupts should be disabled before

feeding the watchdog. The instructions

should move A5H to the WFEED1 register

and then 5AH to the WFEED2 register. If

WFEED1 is correctly loaded and WFEED2 is

not correctly loaded, then an immediate

underflow will occur.

(watchdog mode) or time-out flag to be set

(timer mode) if allowed to reach its terminal

count.

All of the PCA modules can be used as PWM

outputs. Figure 12 shows the PWM function.

The frequency of the output depends on the

source for the PCA timer. All of the modules

will have the same frequency of output

because they all share the PCA timer. The

duty cycle of each module is independently

variable using the module’s capture register

CCAPLn. When the value of the PCA CL

SFR is less than the value in the module’s

CCAPLn SFR the output will be low, when it

is equal to or greater than the output will be

high. When CL overflows from FF to 00,

CCAPLn is reloaded with the value in

Programming the Watchdog Timer

Both the EPROM and ROM devices have a

set of SFRs for holding the watchdog

autoload values and the control bits. The

watchdog time-out flag is present in the

watchdog control register and operates the

same in all versions. In the EPROM device,

the watchdog parameters (autoload value

and control) are always taken from the SFRs.

In the ROM device, the watchdog parameters

can be mask programmed or taken from the

SFRs. The selection to take the watchdog

parameters from the SFRs or from the mask

programmed values is controlled by EA

(external access). When EA is high (internal

ROM access), the watchdog parameters are

taken from the mask programmed values. If

the watchdog is mask programmed to the

timer mode, then the autoload values and the

pre-scaler taps are taken from the SFRs.

When EA is low (external access), the

watchdog parameters are taken from the

SFRs. The user should be able to leave code

in his program which initializes the watchdog

SFRs even though he has migrated to the

mask ROM part. This allows no code

The watchdog timer subsystem has two

modes of operation. Its principal function is a

watchdog timer. In this mode it protects the

system from incorrect code execution by

causing a system reset when the watchdog

timer underflows as a result of a failure of

software to feed the timer prior to the timer

reaching its terminal count. If the user does

not employ the watchdog function, the

watchdog subsystem can be used as a timer.

In this mode, reaching the terminal count sets

a flag. In most other respects, the timer mode

possesses the characteristics of the

CCAPHn. the allows updating the PWM

without glitches. The PWM and ECOM bits in

the module’s CCAPMn register must be set

to enable the PWM mode.

WATCHDOG TIMER

watchdog mode. This is done to protect the

integrity of the watchdog function.

The watchdog timer is not directly loadable

by the user. Instead, the value to be loaded

into the main timer is held in an autoload

register or is part of the mask ROM

programming. In order to cause the main

timer to be loaded with the appropriate value,

a special sequence of software action must

take place. This operation is referred to as

feeding the watchdog timer.

The watchdog timer subsystem consists of a

prescaler and a main counter. The prescaler

has 8 selectable taps off the final stages and

the output of a selected tap provides the

clock to the main counter. The main counter

is the section that is loaded as a result of the

software feeding the watchdog and it is the

section that causes the system reset

changes from EPROM prototyping to ROM

coded production parts.

To feed the watchdog, two instructions must

be sequentially executed successfully. No

15

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

CCAPnH

CCAPnL

0

CL < CCAPnL

ENABLE

8–BIT

CEXn

COMPARATOR

CL >= CCAPnL

1

CL

OVERFLOW

PCA TIMER/COUNTER

CCAPMn, n: 0..4

(DAH – DEH)

––

ECOMn

CAPPn

0

CAPNn

MATn

0

TOGn

0

PWMn

ECCFn

0

SU00752

Figure 12. PCA PWM Mode

When the watchdog is in the watchdog mode

and the watchdog underflows, the following

action takes place (see Figure 16):

Mask ROM Device (EA = 1)

Watchdog Detailed Operation

In the mask ROM device, the watchdog

mode bit (WDMOD) is mask programmed

and the bit in the watchdog command register

is read only and reflects the mask

programmed selection. If the mask

programmed mode bit selects the timer

mode, then the watchdog run bit (WDRUN)

operates as described under EPROM

Device. If the mask programmed bit selects

the watchdog mode, then the watchdog run

bit has no effect on the timer operation (see

Figure 15).

EPROM Device (and ROMless Operation:

EA = 0)

In the ROMless operation (ROM part, EA = 0)

and in the EPROM device, the watchdog

operates in the following manner (see

Figure 14).

• Autoload takes place.

• Watchdog time-out flag is set

• Mode bit unchanged.

• Watchdog run bit unchanged.

• Autoload register unchanged.

• Prescaler tap unchanged.

Whether the watchdog is in the watchdog or

timer mode, when external RESET is applied,

the following takes place:

• Watchdog mode bit set to watchdog mode.

• Watchdog run control bit set to ON.

• Autoload register set to 00 (min. count).

• Watchdog time-out flag cleared.

• Prescaler is cleared.

• All other device action same as external

Watchdog Function

reset.

The watchdog consists of a programmable

prescaler and the main timer. The prescaler

derives its clock from the on-chip oscillator.

The prescaler consists of a divide by 12

followed by a 13 stage counter with taps from

stage 6 through stage 13. This is shown in

Figure 17. The tap selection is

programmable. The watchdog main counter

is a down counter clocked (decremented)

each time the programmable prescaler

underflows. The watchdog generates an

underflow signal (and is autoloaded) when

the watchdog is at count 0 and the clock to

decrement the watchdog occurs. The

watchdog is 8 bits long and the autoload

value can range from 0 to FFH. (The

autoload value of 0 is permissible since the

prescaler is cleared upon autoload).

Note that if the watchdog underflows, the

program counter will start from 00H as in the

case of an external reset. The watchdog

time-out flag can be examined to determine if

the watchdog has caused the reset condition.

The watchdog time-out flag bit can be cleared

by software.

• Prescaler tap set to the highest divide.

• Autoload takes place.

The watchdog can be fed even though it is in

the timer mode.

When the watchdog is in the timer mode and

the timer software underflows, the following

action takes place:

Note that the operational concept is for the

watchdog mode of operation, when coming

out of a hardware reset, the software should

load the autoload registers, set the mode to

watchdog, and then feed the watchdog

(cause an autoload). The watchdog will now

be starting at a known point.

• Autoload takes place.

• Watchdog time-out flag is set

• Mode bit unchanged.

• Watchdog run bit unchanged.

• Autoload register unchanged.

• Prescaler tap unchanged.

If the watchdog is in the watchdog mode and

running and happens to underflow at the time

the external RESET is applied, the watchdog

time-out flag will be cleared.

This leads to the following user design

equations. Definitions :t

is the oscillator

OSC

16

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

period, N is the selected prescaler tap value,

W is the main counter autoload value, t is

WDMOD is in the timer mode, WDRUN

functions normally.

Enhanced UART

MIN

The UART operates in all of the usual modes

that are described in the first section of this

book for the 80C51. In addition the UART can

perform framing error detect by looking for

missing stop bits, and automatic address

recognition. The 87C575 UART also fully

supports multiprocessor communication as

does the standard 80C51 UART.

the minimum watchdog time-out value (when

the autoload value is 0), t is the maximum

The parameters written into WDMOD, PRE0,

PRE1, and PRE2 by the program are not

applied directly to the watchdog timer

subsystem. The watchdog timer subsystem is

directly controlled by a second register which

stores these bits. The transfer of these bits

from the user register (WDMOD) to the

second control register takes place when the

watchdog is fed. This prevents random code

execution from directly foiling the watchdog

function. This does not affect the operation

where these bits are taken from mask coded

values.

MAX

time-out value (when the autoload value is

FFH), t is the design time-out value.

D

t

= t

× 12 × 64

OSC

MIN

= t

× 128 × 256

MIN

MAX

PRESCALER

= t

× 2

MIN

× (W + 1)

D

When used for framing error detect the UART

looks for missing stop bits in the

(where prescaler = 0, 1, 2, 3, 4, 5, 6, or 7)

communication. A missing bit will set the FE

bit in the SCON register. The FE bit shares

the SCON.7 bit with SM0 and the function of

SCON.7 is determined by PCON.6 (SMOD0)

(see Figure 19). If SMOD0 is set then

SCON.7 functions as FE. SCON.7 functions

as SM0 when SMOD0 is cleared. When used

as FE SCON.7 can only be cleared by

software. Refer to Figure 18.

Note that the design procedure is anticipated

to be as follows. A t

will be chosen either

MAX

from equipment or operation considerations

and will most likely be the next convenient

value higher than t . (If the watchdog were

The reset values of the WDCON and WDL

registers will be such that the timer resets to

the watchdog mode with a timeout period of

D

inadvertently to start from FFH, an overflow

would be guaranteed, barring other

anomalies, to occur within t

). Then the

12 × 64 × 128 × t

. The watchdog timer

MAX

OSC

value for the prescaler would be chosen

from:

will not generate an interrupt. Additional bits

in WDCON are used to disable reset

generation by the oscillator fail and low

voltage detect circuits. WDCON can be

written by software only by executing a valid

watchdog feed sequence.

Automatic Address Recognition

Automatic Address Recognition is a feature

which allows the UART to recognize certain

addresses in the serial bit stream by using

hardware to make the comparisons. This

feature saves a great deal of software

overhead by eliminating the need for the

software to examine every serial address

which passes by the serial port. This feature

is enabled by setting the SM2 bit in SCON. In

the 9 bit UART modes, mode 2 and mode 3,

the Receive Interrupt flag (RI) will be

automatically set when the received byte

contains either the “Given” address or the

“Broadcast” address. The 9 bit mode requires

that the 9th information bit is a 1 to indicate

that the received information is an address

and not data. Automatic address recognition

is shown in Figure 20.

prescaler = log2 (t

/ (t

× 12 × 256)) - 6

OSC

MAX

This then also fixes t . An autoload value

MIN

would then be chosen from:

W = t / t

- 1

D

MIN

WDCON Register Bit Definitions

WDCON.7 PRE2

WDCON.6 PRE1

WDCON.5 PRE0

WDCON.4 LVRE

Prescaler Select 2,

reset to 1

Prescaler Select 1,

reset to 1

Prescaler Select 0,

reset to 1

Low Voltage Reset

Enable, reset to 1

(enabled)

The software must be written so that a feed

operation takes place every t seconds from

D

the last feed operation. Some tradeoffs may

need to be made. It is not advisable to

include feed operations in minor loops or in

subroutines unless the feed operation is a

specific subroutine.

Watchdog Control Register (WDCON)

(Bit Addressable) Address C0

WDCON.3 OFRE

Oscillator Fail Reset

Enable, reset to 1

(enabled)

The following bits of this register are read

only in the ROM part when EA is high:

WDMOD, PRE0, PRE1, and PRE2. That is,

the register will reflect the mask programmed

values. In the ROM part with EA high, these

bits are taken from mask coded bits and are

not readable by the program. WDRUN is

read only in the ROM part when EA is high

and WDMOD is in the watchdog mode. When

WDCON.2 WDRUN Watchdog Run,

reset to 1 (enabled)

The 8 bit mode is called Mode 1. In this mode

the RI flag will be set if SM2 is enabled and

the information received has a valid stop bit

following the 8 address bits and the

information is either a Given or Broadcast

address.

WDCON.1 WDTOF

Watchdog Timeout

Flag, reset =

Indeterminate

WDCON.0 WDMOD Watchdog Mode,

reset to 1 (watchdog

mode)

Mode 0 is the Shift Register mode and SM2

is ignored.

17

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

CMOD

(D9H)

CIDL

WDTE

––

CPS1

CPS0

ECF

WRITE TO

CCAP4H

RESET

CCAP4H

CCAP4L

WRITE TO

CCAP4L

0

1

ENABLE

MATCH

16–BIT COMPARATOR

RESET

CH

CL

PCA TIMER/COUNTER

CCAPM4

(DEH)

––

ECOMn

CAPPn

0

CAPNn

0

MATn

1

TOGn

X

PWMn

0

ECCFn

X

SU00042

Figure 13. PCA Watchdog Timer

WDL

(C1H)

WATCHDOG FEED SEQUENCE

MOV WFEED1,#0A5H

MOV WFEED2,#5AH

8–BIT DOWN

COUNTER

OSC/12

PRESCALER

RESET

SHADOW REGISTER

FOR WDCON

WDCON

(C0H)

PRE2

PRE1

PRE0

LVRE

OFRE

WDRUN

WDTOF

WDMOD

SU00240

Figure 14. Watchdog Timer in 87C575 and 80C575 / 83C575 (EA = 0)

18

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

ROM–CODE

CONTENT

WD

ADDRESS

2032H

PRE2:0

WDMOD

2031H

2030H

WATCHDOG FEED SEQUENCE

MOV WFEED1,#0A5H

MOV WFEED2,#5AH

8–BIT DOWN

COUNTER

OSC/12

PRESCALER

SHADOW REGISTER

FOR WDCON

1

WDCON

(C0H)

PRE2

PRE1

PRE0

LVRE

OFRE

WDRUN

WDTOF

WDMOD

SU00241

Figure 15. Watchdog Timer of 83C575 in Watchdog Mode (EA = 1, WDMOD = 1)

ROM–CODE

CONTENT

WD

ADDRESS

2032H

PRE2:0

WDMOD

2031H

2030H

WATCHDOG FEED SEQUENCE

MOV WFEED1,#0A5H

MOV WFEED2,#5AH

8–BIT DOWN

COUNTER

OSC/12

PRESCALER

SHADOW REGISTER

FOR WDCON

0

WDCON

(C0H)

PRE2

PRE1

PRE0

LVRE

OFRE

WDRUN

WDTOF

WDMOD

SU00242

Figure 16. Watchdog Timer of 83C575 in Timer Mode (EA = 1, WDMOD = 0)

19

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

OSC/12

÷64

÷2

÷2048

÷2

÷64

÷128

÷256

÷512

÷1024

÷4096

÷8192

TO WATCHDOG

DOWN COUNTER

000

001

010

011

PRE2

PRE1

DECODE 100

101

110

111

PRE0

SU00243

Figure 17. Watchdog Prescaler

SCON Address = 98H

Bit Addressable

SM0/FE

Reset Value = 0000 0000B

SM1

SM2

REN

TB8

RB8

Tl

Rl

Bit:

7

6

5

4

3

2

1

0

(SMOD0 = 0/1)*

Symbol

FE

Function

Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid

frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.

SM0

SM1

Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)

Serial Port Mode Bit 1

SM0

SM1

Mode

Description

Baud Rate**

f /12

OSC

0

1

0

1

0

1

0

1

2

3

shift register

8-bit UART

9-bit UART

variable

/64 or f

f

/32

OSC

variable

SM2

Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the

received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.

In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a

Given or Broadcast Address. In Mode 0, SM2 should be 0.

REN

TB8

RB8

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.

In Mode 0, RB8 is not used.

Tl

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the

other modes, in any serial transmission. Must be cleared by software.

Rl

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in

the other modes, in any serial reception (except see SM2). Must be cleared by software.

NOTE:

*SMOD0 is located at PCON6.

**f = oscillator frequency

OSC

SU00043

Figure 18. SCON: Serial Port Control Register

20

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

D0

D1

D2

D3

D4

D5

D6

D7

D8

START

BIT

DATA BYTE

ONLY IN

MODE 2, 3

STOP

BIT

SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)

SM0 TO UART MODE CONTROL

SCON

(98H)

SM0 / FE

SMOD1

SM1

SM2

REN

POF

TB8

LVF

RB8

GF0

TI

RI

PCON

(87H)

SMOD0

–

GF1

IDL

0 : SCON.7 = SM0

1 : SCON.7 = FE

SU00044

Figure 19. UART Framing Error Detection

Using the Automatic Address Recognition

feature allows a master to selectively

communicate with one or more slaves by

invoking the Given slave address or

slaves can be selected at the same time by

an address which has bit 0 = 0 (for slave 0)

and bit 1 = 0 (for slave 1). Thus, both could

be addressed with 1100 0000.

as don’t-cares. In most cases, interpreting

the don’t-cares as ones, the broadcast

address will be FF hexadecimal.

Upon reset SADDR (SFR address 0A9H) and

SADEN (SFR address 0B9H) are loaded with

0s. This produces a given address of all

“don’t cares” as well as a Broadcast address

of all “don’t cares”. this effectively disables

the Automatic Addressing mode and allows

the microcontroller to use standard 80C51

type UART drivers which do not make use of

this feature.

addresses. All of the slaves may be

In a more complex system the following could

be used to select slaves 1 and 2 while

excluding slave 0:

contacted by using the Broadcast address.

Two special Function Registers are used to

define the slave’s address, SADDR, and the

address mask, SADEN. SADEN is used to

define which bits in the SADDR are to b used

and which bits are “don’t care”. The SADEN

mask can be logically ANDed with the

SADDR to create the “Given” address which

the master will use for addressing each of the

slaves. Use of the Given address allows

multiple slaves to be recognized while

excluding others. The following examples will

help to show the versatility of this scheme:

Slave 0

Slave 1

Slave 2

SADDR

SADEN

Given

=

1100 0000

1111 1001

1100 0XX0

SADDR

SADEN

Given

=

1110 0000

1111 1010

1110 0X0X

Analog Comparators

Four analog comparators are provided on

chip. Three comparators have a common

negative reference CMPR- and independent

positive inputs CMP1+, CMP2+, CMP3+ on

port 3. The fourth comparator has

SADDR

SADEN

Given

=

1110 0000

1111 1100

1110 00XX

Slave 0

SADDR

SADEN

Given

=

1100 0000

1111 1101

1100 00X0

In the above example the differentiation

among the 3 slaves is in the lower 3 address

bits. Slave 0 requires that bit 0 = 0 and it can

be uniquely addressed by 1110 0110. Slave 1

requires that bit 1 = 0 and it can be uniquely

addressed by 1110 and 0101. Slave 2

requires that bit 2 = 0 and its unique address

is 1110 0011. To select Slaves 0 and 1 and

exclude Slave 2 use address 1110 0100,

since it is necessary t make bit 2 = 1 to

exclude slave 2.

independent positive and negative inputs

CMP0+ and CMP0- on port 1. The CMP

register contains an output and enable bit for

each comparator. The CMP register is bit

addressable and is located at SFR address

E8H. Figure 21 shows the connection of the

comparators.

Slave 1

SADDR

SADEN

Given

=

1100 0000

1111 1110

1100 000X

In the above example SADDR is the same

and the SADEN data is used to differentiate

between the two slaves. Slave 0 requires a 0

in bit 0 and it ignores bit 1. Slave 1 requires a

0 in bit 1 and bit 0 is ignored. A unique

address for Slave 0 would be 1100 0010

since slave 1 requires a 0 in bit 1. A unique

address for slave 1 would be 1100 0001

since a 1 in bit 0 will exclude slave 0. Both

Pullups at the comparator input pins will be

disabled by hardware when the comparator is

enabled. In addition, to make inputs high

impedance, the corresponding port SFR bits

must be set by software to disable the

pulldowns.

The Broadcast Address for each slave is

created by taking the logical OR of SADDR

and SADEN. Zeros in this result are treated

21

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

D0

D1

D2

D3

D4

D5

D6

D7

D8

SCON

(98H)

SM0

SM1

SM2

REN

1

TB8

X

RB8

TI

RI

1

0

1

RECEIVED ADDRESS D0 TO D7

PROGRAMMED ADDRESS

COMPARATOR

IN UART MODE 2 OR MODE 3 AND SM2 = 1:

INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”

– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES

– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.

SU00045

Figure 20. UART Multiprocessor Communication, Automatic Address Recognition

CMP Register Bit Definitions

CMP.7 enable comparator 3,

CMPE Register Bit Definitions

CMPE.7 enables comparator 3 to drive

CEX3

CMPE.6 enables comparator 2 to drive

CEX2

CMPE.5 enables comparator 1 to drive

CEX1

CMPE.4 enables comparator 0 to drive

CEX0

CMPE.3 enables comparator 3 output on

P1.6 (open drain)

CMPE.2 enables comparator 2 output on

P1.5 (open drain)

CMPE.1 enables comparator 1 output on

P1.4 (open drain)

CMPE.0 enables comparator 0 output on

P1.3 (open drain)

pin from the comparator output to have the

pin supply the capture trigger.

disable pullups at P3.4, P3.7

CMP.6 enable comparator 2,

disable pullups at P3.4, P3.6

CMP.5 enable comparator 1,

disable pullups at P3.4, P3.5

CMP.4 enable comparator 0,

disable pullups at P1.0, P1.1

CMP.3 comparator 3 output (read only)

CMP.2 comparator 2 output (read only)

CMP.1 comparator 1 output (read only)

CMP.0 comparator 0 output (read only)

There are two special function registers

associated with the comparators. They are

CMP which contains the comparator enables

and a bit that can be read by software to

determine the state of each comparator’s

output, and CMPE which controls whether

the output from each comparator drives the

associated output pin or a capture input

associated with one of the PCA modules.

The CMP registers bits 0–3 can be read by

software to determine the state of the output

of each comparator. To do this the associated

comparator must be enabled but the output in

port 1 can be disabled. This allows easy

polling of the comparator output value without

the need to use up a port pin.

All comparators are disabled automatically in

power down mode, in idle mode unused

comparators should be disabled by software

to save power. A comparator can generate

an interrupt that will terminate idle mode.

When 1s are written to CMPE bits 7-4,

the comparator outputs will drive the

The CMPE register contains bits to enable

each comparator to drive external output pins

or internal PCA capture inputs. Pullups at the

output pins are disabled by hardware when

the external comparator output is enabled.

The comparator output is wire-ORed with the

corresponding port SFR bit, so the SFR bit

must also be set by software to enable the

output.

corresponding capture input. (This function is

not available in the idle or power-down

mode.) When 1s are written to CMPE bits 3-0

the comparator output will also drive the

corresponding port 1 pin. (This function is

available in idle mode.) If the comparator’s

enabled to drive the capture input but not the

port pin, then the port pin can be used for

general purpose I/O. When a comparator

output is enabled, pullups at the output pin

are disabled and the output becomes open

drain. The comparator output can be used to

trigger a capture input in idle mode by

The CMPE register allows the comparator to

drive the associated PCA module capture

input, so that on compare a capture can be

generated in the PCA. Bits 0–3 of this

register enable the comparator output to drive

the associated port 1 output circuitry. Used

as a comparator output this circuitry is open

drain. To enable the comparator output to

drive to port 1, the corresponding port bit

must also be set to disable the pulldown. If

the comparator is not enabled to drive the

port 1 circuitry, the associated port 1 pin can

be used for other I/O. This includes when a

comparator is enabled to drive the capture

input to a PCA module.

programming the CMPE register to drive the

22

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

CMPE

(91H)

EC3TDC

EC2TDC

EC1TDC

EC0TDC

EC3OD *

EC2OD *

EC1OD *

EC0OD *

P1.0 / CMP0+

P1.1 / CMP0–

+

P1.3 / CMP0

P1.4 / CMP1

P1.5 / CMP2

P1.6 / CMP3

–

TO CEX0 INPUT OF

PCA MODULE 0

ENABLE

+

P3.5 / CMP1+

P3.6 / CMP2+

–

TO CEX1 INPUT OF

PCA MODULE 1

ENABLE

+

–

TO CEX2 INPUT OF

PCA MODULE 2

ENABLE

+

P3.7 / CMP3+

P3.4 / CMPR–

–

TO CEX3 INPUT OF

PCA MODULE 3

ENABLE

* : WILL DISABLE PULLUPS

ON RELEVANT PINS

CMP

(E8H)

EC3DP *

EC2DP *

EC1DP *

EC0DP *

C3R0

C2R0

C1R0

C0R0

SU00244

Figure 21. Analog Comparators

Interrupt Priority (IP) Register

IP.7 reserved

PPC IP.6 PCA interrupt priority

PT2 IP.5 Timer 2 interrupt priority

Reduced EMI Mode

INTERNAL RESET

There are two bits in the AUXR register that

can be set to reduce the internal clock drive

and disable the ALE output. AO (AUXR.0)

when set turns off the ALE output. LO

(AUXR.1) when set reduces the drive of the

internal clock circuitry. Both bits are cleared

on Reset. With LO set the 87C575 will still

operate at 12MHz, but will have reduced EMI

in the range above 100MHz.

Internal resets generated by the power on,

low voltage, and oscillator fail detect circuits

are self timed to guarantee proper

PS

IP.4 Serial I/O interrupt priority

initialization of the 8XC575. Reset will be held

approximately 24 oscillator periods after

normal conditions are detected by all enabled

detect circuits. Internal resets do not drive

RST but will cause missing pulses on ALE.

PT1 IP.3 Timer 1 interrupt priority

PX1 IP.2 External interrupt 1 priority

PT0 IP.1 Timer 0 interrupt priority

PX0 IP.0 External interrupt 0 priority

Priority Source

Flag

Vector

Interrupt Enable (IE) Register

1

2

3

4

INT0

IE0

03H highest priority

AUXR (8EH)

EA

EC

IE.7 enable all interrupts

IE.6 enable PCA interrupt

Timer 0 TF0

INT1 IE1

Timer 1 TF1

0BH

13H

1BH

––

LO

AO

ET2 IE.5 enable Timer 2 interrupt

ES IE.4 enable Serial I/O interrupt

ET1 IE.3 enable Timer 1 interrupt

EX1 IE.2 enable External interrupt 1

ET0 IE.1 enable Timer 0 interrupt

EX0 IE.0 enable External interrupt 0

AO:

LO:

Turns off ALE output.

87C575

Reduces drive of internal clock

circuitry. 8XC575 spec’d to 12MHz

when LO set.

5

6

7

PCA

Serial I/O RI,TI

Timer 2

CF,CCFn 33H

23H

TF2/EXF2 2BH lowest priority

80C575/83C575/87C575

5

6

7

Serial I/O RI/TI

23H

Timer 2

PCA

TF2/EXF2 23H

CF, CCF 33H lowest priority

n

Power Control (PCON) Register

SMOD1 PCON.7 double baud rate bit

SMOD0 PCON.6 SCON.7 access control

OSF

POF

LVF

GF0

PD

PCON.5 oscillator fail flag

PCON.4 power off flag

PCON.3 low voltage flag

PCON.2 general purpose flag

PCON.1 power down mode bit

PCON.0 idle mode bit

IDL

Port 2 Pullup Disable Register

23

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

OSCILLATOR

CHARACTERISTICS

XTAL1 and XTAL2 are the input and output,

respectively, of an inverting amplifier. The

pins can be configured for use as an on-chip

oscillator, as shown in the Logic Symbol,

page 4.

IDLE MODE

POWER-DOWN MODE

In idle mode, the CPU puts itself to sleep

while all of the on-chip peripherals stay

active. The instruction to invoke the idle

mode is the last instruction executed in the

normal operating mode before the idle mode

is activated. The CPU contents, the on-chip

RAM, and all of the special function registers

remain intact during this mode. The idle

mode can be terminated either by any

enabled interrupt (at which time the process

is picked up at the interrupt service routine

and continued), or by a hardware reset which

starts the processor in the same manner as a

power-on reset.

In the power-down mode, the oscillator is

stopped and the instruction to invoke

power-down is the last instruction executed.

Only the contents of the on-chip RAM are

preserved. The control bits for the reduced

power modes are in the special function

register PCON. Power-down mode can be

terminated with either a hardware reset or

external interrupt. With an external interrupt

INT0 or INT1 must be enabled and

To drive the device from an external clock

source, XTAL1 should be driven while XTAL2

is left unconnected. There are no

requirements on the duty cycle of the

external clock signal, because the input to

the internal clock circuitry is through a

divide-by-two flip-flop. However, minimum

and maximum high and low times specified in

the data sheet must be observed.

configured as level sensitive. Holding the pin

low restarts to oscillator and bringing the pin

back high completes the exit.

If the watchdog is enabled (WDRUN = 1),

then power-down mode is disabled.

DESIGN CONSIDERATIONS

At power-on, the voltage on V must come

CC

up with RST low for a proper start-up.

Table 2 shows the state of I/O ports during

low current operating modes.

Table 2. External Pin Status During Idle and Power-Down Modes

MODE

PROGRAM MEMORY

Internal

ALE

PSEN

PORT 0

Data

PORT 1

Data

PORT 2

Data

PORT 3

Data

Idle

1

0

1

0

External

Float

Data

Address

Data

Power-down

Internal

Data

External

Float

Data

24

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

ROM CODE SUBMISSION

When submitting ROM code for the 83C575, the following must be specified:

1. 8k byte user ROM data

2. 32 byte ROM encryption key

3. ROM security bits

4. The watchdog timer parameters.

ADDRESS

CONTENT

DATA

BIT(S)

7:0

COMMENT

0000H to 1FFFH

2000H to 201FH

User ROM Data

KEY

7:0

ROM Encryption Key

FFH = no encryption

2020H

Reserved

Security Bit 2

Security Bit 1

2

1

0

Must = 1

0 = enable, 1 = disable

2030H

2031H

2032H

Reserved

7:0

Must = FFH

1

WDL

Watchdog reload value

(see specification)

1

2033H

WDCON

7:5

4

PRE2:0

1

WDCON

LVRE

1

WDCON

3

OFRE

1

WDCON

2

WDRUN=0, not ROM coded

WDTOF=0, not ROM coded

WDMOD

1

WDCON

1

WDCON

0

NOTES:

1. See Watchdog Timer Specification for definition of WDL and WDCON bits.

Security Bit 1: When programmed, this bit has two effects on masked ROM parts:

1. External MOVC is disabled, and

2. EA# is latched on Reset.

Security Bit 2: When programmed, this bit inhibits Verify User ROM.

1, 2, 3

ABSOLUTE MAXIMUM RATINGS

PARAMETER

Operating temperature under bias

Storage temperature range

RATING

UNIT

°C

V

–55 to +125

–65 to +150

0 to +13.0

–0.5 to +6.5

15

Voltage on EA/V pin to V

PP

SS

Voltage on any other pin to V

V

SS

Maximum I per I/O pin

mA

W

OL

Power dissipation (based on package heat transfer limitations, not

device power consumption)

1.5

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section

of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise

SS

noted.

25

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

DC ELECTRICAL CHARACTERISTICS

T

amb

= 0°C to +70°C and –40°C to +125°C, V = 5V ±10%, V = 0V

CC SS

LIMITS

TEST

CONDITIONS

SYMBOL

PARAMETER

UNIT

1

MIN

–0.5

0

TYP

MAX

0.5V –0.6

V

Input low voltage (Ports 0, 2, 3, except 3.2, 3.3)

Input low voltage (Ports 1, 3.2, 3.3, XTAL1, RST)

Input low voltage (EA)

V

IL

CC

0.2V –0.5

IL1

IL2

IH

CC

0.2V –0.45

V

CC

Input high voltage (Ports 0, 2, 3, except 3.2, 3.3)

Input high voltage (Ports 1, 3.2, 3.3)

Input high voltage (EA)

0.5V +0.8

V

CC

V

CC

V

CC

V

CC

+0.5

V

CC

0.8V +0.3

V

IH1

IH2

IH3

CC

0.2V +0.9

V

CC

Input high voltage (XTAL1, RST)

0.7V

V

CC

HYS

Hysteresis (Ports 0, 2, 3, except 3.2, 3.3)

Hysteresis (Ports 1, 3.2, 3.3)

200

50

mV

V

HYS1

V

Output voltage low (Ports 1, 2, 3, except 3.1)

I

= 1.6mA

= 3.2mA

0.45

OL

)

Output voltage low (Ports 0, ALE, PSEN

V

OL1

OL2

OL

Output voltage low

P3.1 with bit cleared

P3.1 with bit set

I

= 10.0mA

= 1.6mA

0.50

0.45

V

OL

I

OL

V

Output voltage high (Ports 1, 2, 3, except P3.1)

I

= –30µA

V

–0.7

V

OH

CC

Output voltage high (Port 0 in external bus mode, ALE, PSEN)

I

= –3.2mA

–0.7

OH1

OH2

OH

CC

Output voltage high

P3.1 with bit cleared

P3.1 with bit set

I

= –10.0mA

= –1.6mA

V

CC

V

CC

–1.5

V

OH

I

OH

V

Offset voltage comparator inputs

–35

+35

mV

V

IO

Common mode range comparator inputs

Logical 0 input current (Ports 1, 2, 3, except 3.1)

Logical 1-to-0 transition current

0

V

CC

CR

I

IL

V

= 0.45V

–75

µA

IN

I

TL

See Note 4

–600

µA

4

(Ports 2, 3, except 3.1, 3.2, 3.3)

I

Logical 1-to-0 transition current (Ports 1, 3.2, 3.3)

–450

40

µA

TL1

9

Input leakage current (Port 0, Port2 in open drain mode)

0.45 < V < V

2

L1

IN

CC

Input leakage current (EA, P3.1)

0.45 < V < V

–10

–1.0

+10

+1.0

L2

IN

Input leakage current comparator inputs

0 < V < V

IN CC

LC

CC

7

Power supply current:

See note 6

5

Active mode @ 16MHz

20

8

5

30

12

75

mA

µA

Idle mode @ 16MHz

Power-down mode

R

Internal reset pull-up resistor

V

= 0V

50

200

4.45

10

kΩ

V

RST

IN

V

LOW

Low V detect voltage

4.0

CC

10

C

Pin capacitance

f = 1MHz

pF

IO

NOTES: (SEE NEXT PAGE)

26

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

NOTES TO THE DC ELECTRICAL CHARACTERISTICS TABLE:

1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due

OL

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify

ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no

OL

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specification when the

OH

CC

address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V is between V and V .

IN

IH

IL

5. I MAX at other frequencies can be determined from Figure 29.

CC

6. See Figures 30 through 33 for I test conditions.

CC

7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

8. Under steady state (non-transient) conditions, I must be externally limited as follows:

OL

Maximum I per port pin:

10mA

26mA

71mA

OL

Maximum I per 8-bit port:

OL

Maximum total I for all outputs:

OL

If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

OL

test conditions.

9. Specification applies to Port 2 when P2OD bit is set.

10.15pF MAX for the EA/V and P0.0 pins.

PP

27

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

AC ELECTRICAL CHARACTERISTICS

1, 2

T

= 0°C to +70°C and –40°C to +125°C, V = 5V ±10%, V = 0V

amb

CC SS

VARIABLE CLOCK

SYMBOL

1/t

FIGURE

PARAMETER

MIN

MAX

UNIT

22

Oscillator frequency: Speed Versions

8XC575

CLCL

E

6

16

5.5

10

MHz

µs

OSCF

TR

Oscillator fail detect frequency

Comparator response time

ALE pulse width

0.6

t

22

2t

–40

ns

LHLL

AVLL

LLAX

LLIV

CLCL

Address valid to ALE low

Address hold after ALE low

ALE low to valid instruction in

ALE low to PSEN low

t

–25

ns

CLCL

ns

4t

3t

–75

ns

CLCL

t

–25

ns

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

PSEN pulse width

3t

–45

ns

CLCL

PSEN low to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address to valid instruction in

PSEN low to address float

–70

ns

CLCL

0

ns

t

–25

ns

CLCL

5t

–85

ns

CLCL

10

ns

Data Memory

t

23, 24

RD pulse width

6t

–100

ns

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

CLCL

WR pulse width

6t

CLCL

RD low to valid data in

Data hold after RD

5t

–110

CLCL

0

Data float after RD

2t

–28

CLCL

ALE low to valid data in

Address to valid data in

ALE low to RD or WR low

Address valid to WR low or RD low

Data valid to WR transition

Data hold after WR

8t

–150

–165

CLCL

9t

AVDV

LLWL

AVWL

QVWX

WHQX

RLAZ

WHLH

3t

–50

–75

3t

+50

CLCL

4t

CLCL

t

–30

–25

CLCL

t

RD low to address float

RD or WR high to ALE high

0

t

–25

t

+25

CLCL

External Clock

t

26

High time

Low time

Rise time

Fall time

12

ns

CHCX

CLCX

CLCH

CHCL

20

Shift Register

t

25

Serial port clock cycle time

12t

ns

XLXL

CLCL

Output data setup to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

10t –133

CLCL

QVXH

XHQX

XHDX

XHDV

2t

CLCL

–60

0

10t

–133

CLCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

3. Interfacing the 80C32/52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0

drivers.

28

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The

first character is always ‘t’ (= time). The other

characters, depending on their positions,

indicate the name of a signal or the logical

status of that signal. The designations are:

A – Address

P – PSEN

Q – Output data

R – RD signal

t – Time

V – Valid

W– WR signal

X – No longer a valid logic level

Z – Float

C – Clock

D – Input data

H – Logic level high

I – Instruction (program memory contents)

L – Logic level low, or ALE

Examples: t

= Time for address valid to

ALE low.

=Time for ALE low to

PSEN low.

AVLL

t

LLPL

t

LHLL

ALE

t

LLPL

AVLL

t

PLPH

t

LLIV

t

PLIV

PSEN

t

LLAX

t

PXIZ

t

PLAZ

t

PXIX

A0–A7

INSTR IN

A0–A7

PORT 0

PORT 2

t

AVIV

A0–A15

A8–A15

SU00006

Figure 22. External Program Memory Read Cycle

ALE

PSEN

RD

t

WHLH

t

LLDV

t

LLWL

RLRH

t

RHDZ

t

LLAX

t

RLDV

AVLL

t

RLAZ

t

RHDX

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA IN

A0–A7 FROM PCL

INSTR IN

t

AVWL

t

AVDV

P2.0–P2.7 OR A8–A15 FROM DPF

A0–A15 FROM PCH

SU00025

Figure 23. External Data Memory Read Cycle

29

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

ALE

t

WHLH

PSEN

t

WLWH

LLWL

WR

t

LLAX

t

WHQX

t

AVLL

QVWX

t

QVWH

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA OUT

A0–A7 FROM PCL

INSTR IN

t

AVWL

P2.0–P2.7 OR A8–A15 FROM DPF

A0–A15 FROM PCH

SU00026

Figure 24. External Data Memory Write Cycle

INSTRUCTION

ALE

0

1

2

3

4

5

6

7

8

t

XLXL

CLOCK

t

XHQX

t

QVXH

OUTPUT DATA

0

1

2

3

4

5

6

7

WRITE TO SBUF

t

XHDX

t

SET TI

VALID

XHDV

INPUT DATA

CLEAR RI

VALID

SET RI

SU00027

Figure 25. Shift Register Mode Timing

V

–0.5

CC

0.7V

CC

0.45V

0.2V

–0.1

t

CHCX

t

CHCL

CLCX

CLCH

t

CLCL

SU00009

Figure 26. External Clock Drive

30

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

V

–0.5

CC

0.2V

+0.9

–0.1

CC

0.45V

NOTE:

AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.

CC

Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.

IH

IL

SU00010

Figure 27. AC Testing Input/Output

V

+0.1V

LOAD

V

–0.1V

TIMING

REFERENCE

POINTS

OH

V

LOAD

–0.1V

LOAD

+0.1V

OL

NOTE:

For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,

and begins to float when a 100mV change from the loaded V /V level occurs. I /I ≥ ±20mA.

OH OL

SU00011

Figure 28. Float Waveform

30

MAX ACTIVE

25

20

TYP ACTIVE

15

10

I

(mA)

CC

MAX IDLE

TYP IDLE

5

0

4

5

10

15 16

20

FREQUENCY (MHz)

SU00245

Figure 29. I vs. FREQ

CC

Valid only within frequency specifications of the device under test

31

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

V

CC

I

CC

V

CC

V

CC

RST

EA

(NC)

XTAL2

XTAL1

CLOCK SIGNAL

V

SS

SU00246

Figure 30. I Test Condition, Active Mode

CC

All other pins are disconnected

V

CC

I

CC

V

CC

V

CC

RST

EA

(NC)

CLOCK SIGNAL

XTAL2

XTAL1

V

SS

SU00247

Figure 31. I Test Condition, Idle Mode

CC

All other pins are disconnected

V

–0.5

CC

0.7V

CC

0.45V

0.2V

–0.1

t

CHCX

t

CHCL

CLCX

CLCH

t

CLCL

SU00009

Figure 32. Clock Signal Waveform for I Tests in Active and Idle Modes

CC

t

= t

= 5ns

CHCL

CLCH

32

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

V

CC

I

CC

V

CC

V

CC

RST

EA

(NC)

XTAL2

XTAL1

V

SS

SU00248

Figure 33. I Test Condition, Power Down Mode

CC

All other pins are disconnected. V = 2V to 5.5V

CC

33

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

The address of the EPROM location to be

Program Verification

EPROM CHARACTERISTICS

If security bit 2 has not been programmed,

the on-chip program memory can be read out

for program verification. The address of the

program memory locations to be read is

applied to ports 1 and 2 as shown in

Figure 36. The other pins are held at the

‘Verify Code Data’ levels indicated in Table 3.

The contents of the address location will be

emitted on port 0. External pull-ups are

required on port 0 for this operation.

programmed is applied to ports 1 and 2, as

shown in Figure 34. The code byte to be

programmed into that location is applied to

port 0. RST, PSEN and pins of ports 2 and 3

specified in Table 3 are held at the ‘Program

Code Data’ levels indicated in Table 3. The

ALE/PROG is pulsed low 25 times as shown

in Figure 35.

To put the 87C575 in the EPROM

programming mode, PSEN must be held high

during power up, then driven low with reset

active. The 87C575 is programmed by using

a modified Quick-Pulse Programming

algorithm. It differs from older methods in the

value used for V (programming supply

PP

voltage) and in the width and number of the

ALE/PROG pulses.

To program the encryption table, repeat the

25 pulse programming sequence for

addresses 0 through 1FH, using the ‘Pgm

Encryption Table’ levels. Do not forget that

after the encryption table is programmed,

verification cycles will produce only encrypted

data.

The 87C575 contains two signature bytes

that can be read and used by an EPROM

programming system to identify the device.

The signature bytes identify the device as an

87C575 manufactured by Philips.

If the encryption table has been programmed,

the data presented at port 0 will be the

exclusive NOR of the program byte with one

of the encryption bytes. The user will have to

know the encryption table contents in order to

correctly decode the verification data. The

encryption table itself cannot be read out.

Table 3 shows the logic levels for reading the

signature byte, and for programming the

program memory, the encryption table, and

the security bits. The circuit configuration and

waveforms for quick-pulse programming are

shown in Figures 34 and 35. Figure 36 shows

the circuit configuration for normal program

memory verification.

To program the security bits, repeat the 25

pulse programming sequence using the ‘Pgm

Security Bit’ levels. After one security bit is

programmed, further programming of the

code memory and encryption table is

disabled. However, the other security bit can

still be programmed.

Reading the Signature Bytes

The signature bytes are read by the same

procedure as a normal verification of

locations 030H and 031H, except that P3.6

and P3.7 need to be pulled to a logic low. The

values are:

(030H) = 15H indicates manufactured by

Philips

(B0H) = 97H indicates 87C575

Note that the EA/V pin must not be allowed

PP

Quick-Pulse Programming

to go above the maximum specified V level

PP

The setup for microcontroller quick-pulse

programming is shown in Figure 34. Note that

the 87C575 is running with a 4 to 6MHz

oscillator. The reason the oscillator needs to

be running is that the device is executing

internal address and program data transfers.

for any amount of time. Even a narrow glitch

above that voltage can cause permanent

damage to the device. The V source

PP

Program/Verify Algorithms

Any algorithm in agreement with the

conditions listed in Table 3, and which

satisfies the timing specifications, is suitable.

should be well regulated and free of glitches

and overshoot.

Table 3.

EPROM Programming Modes

MODE

RST

PSEN

ALE/PROG

EA/V

P2.7

P2.6

P3.7

P3.6

PP

Read signature

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Program code data

Verify code data

0*

1

V

PP

1

Pgm encryption table

Pgm security bit 1

0*

V

PP

V

Pgm security bit 2

NOTES:

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.

2. V = 12.75V ±0.25V.

PP

3. V = 5V±10% during programming and verification.

CC

*

ALE/PROG receives 25 programming pulses while V is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a

PP

minimum of 10µs.

Trademark phrase of Intel Corporation.

34

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

+5V

V

CC

P0

A0–A7

PGM DATA

+12.75V

P1

0

1

RST

P3.6

EA/V

PP

25 100µs PULSES TO GROUND

ALE/PROG

PSEN

0

1

87C575

P3.7

XTAL2

P2.7

0

P2.6

4–6MHz

XTAL1

A8–A12

P2.0–P2.4

V

SS

SU00249

Figure 34. Programming Configuration

25 PULSES

1

0

ALE/PROG:

10µs MIN

100µs+10

1

0

SU00018

Figure 35. PROG Waveform

+5V

V

CC

P0

A0–A7

PGM DATA

P1

0

1

RST

P3.6

1

EA/V

PP

ALE/PROG

PSEN

0

87C575

P3.7

0 ENABLE

XTAL2

P2.7

0

P2.6

4–6MHz

XTAL1

A8–A12

P2.0–P2.4

V

SS

SU00250

Figure 36. Program Verification

35

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

T

amb

= 21°C to +27°C, V = 5V±10%, V = 0V (See Figure 37)

CC SS

SYMBOL

PARAMETER

MIN

MAX

13.0

50

UNIT

V

PP

Programming supply voltage

Programming supply current

Oscillator frequency

12.5

I

PP

mA

MHz

1/t

CLCL

4

6

t

Address setup to PROG low

Address hold after PROG

Data setup to PROG low

Data hold after PROG

48t

AVGL

CLCL

48t

GHAX

DVGL

GHDX

EHSH

SHGL

GHSL

GLGH

AVQV

ELQZ

EHQZ

GHGL

P2.7 (ENABLE) high to V

PP

V

PP

V

PP

setup to PROG low

hold after PROG

10

90

µs

PROG width

110

Address to data valid

48t

CLCL

ENABLE low to data valid

Data float after ENABLE

PROG high to PROG low

48t

0

10

µs

PROGRAMMING*

VERIFICATION*

ADDRESS

P1.0–P1.7

P2.0–P2.4

ADDRESS

t

AVQV

PORT 0

DATA IN

DATA OUT

t

DVGL

GHDX

GHAX

t

AVGL

ALE/PROG

t

GLGH

GHGL

t

SHGL

GHSL

LOGIC 1

EA/V

PP

LOGIC 0

t

EHSH

ELQV

EHQZ

P2.7

ENABLE

SU00020

*

FOR PROGRAMMING VERIFICATION SEE FIGURE 34.

FOR VERIFICATION CONDITIONS SEE FIGURE 36.

Figure 37. EPROM Programming and Verification

36

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

DIP40: plastic dual in-line package; 40 leads (600 mil)

SOT129-1

37

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

38

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

SOT307-2

39

1998 May 01

Philips Semiconductors

Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

80C575/83C575/

87C575

Data sheet status

[1]

Data sheet

status

Product

status

Definition

Objective

specification

Development

This data sheet contains the design target or goal specifications for product development.

Specification may change in any manner without notice.

Preliminary

specification

Qualification

This data sheet contains preliminary data, and supplementary data will be published at a later date.

Philips Semiconductors reserves the right to make chages at any time without notice in order to

improve design and supply the best possible product.

Product

specification

Production

This data sheet contains final specifications. Philips Semiconductors reserves the right to make

changes at any time without notice in order to improve design and supply the best possible product.

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or

at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips

Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or

modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications

do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard

cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409

Copyright Philips Electronics North America Corporation 1998

Sunnyvale, California 94088–3409

Telephone 800-234-7381

Date of release: 05-98

Document order number:

9397 750 03854

Philips

Semiconductors

40

1998 May 01


型号：	P80C575EHAA-T
厂家：	NXP
描述：	IC 8-BIT, 16 MHz, MICROCONTROLLER, PQCC44, PLASTIC, SOT-187-2, LCC-44, Microcontroller 微控制器和处理器外围集成电路装置 PC 时钟
文件：	总40页 (文件大小：386K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

P80C575EHAA-T [NXP]

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