P80CL31HFPN [NXP]
Low-voltage single-chip 8-bit microcontrollers; 低电压的单芯片8位微控制器
| 型号： | P80CL31HFPN |
| 厂家： | 
NXP |
| 描述： | Low-voltage single-chip 8-bit microcontrollers |
| 文件： | 总40页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
80CL31/80CL51
Low-voltage single-chip
8-bit microcontrollers
Product specification
IC20 Data Handbook
1995 January
Philips
Semiconductors
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
FEATURES
• Full static 80C51 CPU
• Wake-up via external interrupts at Port 1
• Single supply voltage of 1.8V to 6.0V (5.0V ±10% for P80C51)
• Frequency range of 0 to 16MHz (3.5MHz to 16MHz for P80C51)
• Very low current consumption
• 8-bit CPU, ROM, RAM, 1/0 in a single 40-lead DIL / mini-pack
• 4K x 8 ROM, expandable externally to 64K bytes
• 128 bytes RAM, expandable externally to 64K bytes
• Four 8-bit ports, 321/0 lines
o
• Operating temperature range: -40 to +85 C
DESCRIPTION
• Two 16-bit timer / event counters
The 80CL51 is manufactured in an advanced CMOS technology.
The instruction set of the 80CL51 is based on that of the 8051. The
80CL51 is a general purpose microcontroller especially suited for
battery-powered applications. The device has low power
consumption and a wide range of supply voltage. For emulation
purposes, the 85CL000 (Piggy-back version) with 256 bytes of RAM
is recommended. The 80CL51 has two software selectable modes
of reduced activity for further power reduction: Idle and Power-down.
The 80CL51 also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 46 two-byte, and 16 three-byte.
• External memory expandable up to 128K, external ROM up to
64K and / or RAM up to 64K
• On-chip oscillator suitable for RC, LC, quartz crystal or ceramic
resonator
• Thirteen source, thirteen vector interrupt structure with two priority
levels
• Full duplex serial port (UART)
• Enhanced architecture with:
– non-page oriented instructions
– direct addressing
The P80CL31 is the ROMless version of the P80CL51. P80C51 is a
5V version of the low voltage P80CL51.
– four eight byte RAM register banks
– stack depth up to 128 bytes
The P80CL31 is the ROMless version of the P80CL51. P80C51 is a
5V version of the low voltage P80CL51.
– multiply, divide, subtract and compare instructions
• Power-Down and IDLE instructions
PIN CONFIGURATIONS
INT2/P1.0
INT3/P1.1
INT4/P1.2
INT5/P1.3
INT6/P1.4
INT7/P1.5
INT8/P1.6
INT9/P1.7
RST
40
39
1
2
3
V
DD
P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
35 P0.4/AD4
4
5
41 40 39 38 37 36 35 34
44 43 42
6
33 P0.4/AD4
1
P1.5/INT7
34
7
P0.5/AD5
32
31
30
29
28
27
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
2
3
P1.6/INT8
P1.7/INT9
RST
33 P0.6/AD6
8
PLASTIC
DUAL
32
9
P0.7/AD7
4
31 EA
10
RXD/DATA/P3.0
5
P3.0/RXD
NC
IN-LINE
AND
NC
PLASTIC QUAD FLAT PACKAGE
6
30
TXD/CLOCK/P3.1 11
INT0/P3.2 12
ALE
29 PSEN
28
ALE
SMALL
7
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
OUTLINE
PACKAGES
26 PSEN
8
13
INT1/P3.3
P2.7/A15
25 P2.7/A15
9
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
XTAL1 19
P2.6/A14
10
11
23
P2.5/A13
12 13 14 15 16 17 18 19 20 21 22
24
P2.3/A11
23 P2.2/A10
22
P2.1/A9
21 P2.0/A8
20
V
SS
2
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
ORDERING INFORMATION
1
PHILIPS PART ORDER
NUMBER PART MARKING
PHILIPS NORTH AMERICA
PART ORDER NUMBER
o
TEMPERATURE RANGE C
DRAWING
NUMBER
AND PACKAGE
ROMless
ROM
ROMless
ROM
–40 to +85;
P80CL31HFP P80CL51HFP P80CL31HFP N P80CL51HFP N
P80CL31HFT P80CL51HFT P80CL31HFT D P80CL51HFT D
SOT129-1
SOT158-1
SOT307-2
SOT129-1
SOT158-1
SOT307-2
40-lead Plastic Dual In-line Package (1.8V to 6V)
–40 to +85;
40-lead Plastic Small Outline Package (1.8V to 6V)
–40 to +85;
P80CL31HFH
P80CL51HFH P80CL31HFH B P80CL51HFH B
44-lead Plastic Quad Flat Package (1.8V to 6V)
–40 to +85;
P80C51HFP
P80C51HFT
P80C51HFH
P80C51HFP N
P80C51HFT D
P80C51HFH B
40-lead Plastic Dual In-line Package (5.0V ±10%)
–40 to +85;
40-lead Plastic Small Outline Package (5.0V ±10%)
–40 to +85;
44-lead Plastic Quad Flat Package (5.0V ±10%)
NOTE:
1. Parts ordered by the Philips North America part number will be marked with the Philips part marking.
3
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
PIN DESCRIPTIONS
PIN
DESIGNATION
FUNCTION
QFP
DIP
40
1
P1.O/INT2
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that have 1s written
to them are pulled HIGH by the internal pullups, and in that state can be used as inputs. The Port 1
output buffer can sink/source 4 LS TTL loads. As inputs, Port 1 pins that are externally pulled LOW
41
42
43
44
1
2
3
4
5
6
7
8
P1.1/lNT3
P1.2/lNT4
P1.3/INT5
P1.4/lNT6
P1.5/lNT7
P1.6/lNT8
P1.7/lNT9
will source current (I in the characteristics) due to the internal pullups. Port 1 also serves the
lL
alternative functions INT2 to INT9.
2
3
4
9
RST
Reset: A high level on this pin for two machine cycles while the oscillator is running resets the
device.
5–13
10-17
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source 4 LS TTL inputs. Port 3 pins that have 1s written to them are pulled HIGH by the
internal pull ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally
pulled LOW will source current (I in the characteristics) due to the internal pull ups.
lL
5
7
8
10
11
12
13
14
15
16
17
P3.0/RXD/data
P3.1/TXD/clock
P3.2/lNT0
P3.3/lNT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
RXD/data: Serial port receiver data input (asynchronous)or data input/output (synchronous)
TXD/clock: Serial port transmitter data output (asynchronous) or clock output (synchronous)
INT0: External interrupt 0.
INT1: External interrupt 1.
T0: Timer 0 external input.
T1: Timer 1 external input.
WR: External data memory write strobe.
RD: External data memory read strobe.
9
10
11
12
13
14
18
XTAL2
Crystal output: Output of the inverting amplifier of the oscillator. Left open when external clock is
used.
Crystal input: Input to the inverting amplifier of the oscillator; also the input for an externally gen-
erated clock source.
15
19
XTAL1
Crystal input: Input to the inverting amplifier of the oscillator; also the input for an externally
generated clock source.
16
20
Vss
Ground: Circuit ground potential.
18-25
21-28
P2.0-P2.7
Port 2: Port 2 is an 8-bit bidirectional 1/0 port with internal pullups. Port 2 pins that have 1s written
to them are pulled HIGH by the internal pullups, and in that state can be used as inputs. The Port 2
output buffer can sink/source 4 LS TTL loads.
Port 2 emits the high-order address byte during accesses to external memory that use 1 6-bit ad-
dresses (MOVX @DPTR). In this application it uses the strong internal pullups when emitting 1s.
During accesses to external memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the con-
tents of the P2 Special Function Register.
26
27
29
30
PSEN
ALE
Program store enable output: Read strobe to external program memory. When executing code
out of external program memory, PSEN is activated twice each machine cycle. However, during
each access to external data memory two PSEN activations are skipped.
Address Latch Enable: Output pulse for latching the low byte of the address during access to
external memory. ALE is emitted at a constant rate of 1/6 of the oscillator frequency, and may be
used for external timing or clocking purposes.
29
31
EA
External Access: When EA is held High the CPU executes out of internal program memory (un-
less the program counter exceeds 0FFFH). Holding EA LOW forces the CPU to execute out of
external memory regardless of the value of the program counter.
30-37
32-39
P0.0-P00.7
Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. As an open drain output port it can sink 8
LS TTL loads. Port 0 pins that have 1s written to them float, and in that state will function as high
impedance inputs. Port 0 is also the multiplexed low order address and data bus during access to
external memory. In this application it uses strong internal pull-ups when emitting logic 1s.
38
40
V
DD
Power supply.
4
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
BLOCK DIAGRAM
1
FREQUENNCY REFERENCE
XTAL2 XTAL1
COUNTER
T0 T1
PROGRAM
MEMORY
(4K BY 8 ROM)
OSCILLATOR
AND TIMING
DATA MEMORY
(128 BY 8 RAM)
TWO 16-BIT TIMER/
EVENT COUNTERS
80CL51
CPU
10
3
PROGRAMMABLE
SERIAL PORT,
FULL DUPLEX UART,
SYNCHRONOUS
64K BYTE BUS
EXPANSION
CONTROL
PROGRAMMABLE
I/O
INTERNAL
INTERRUPTS
SHIFT
CONTROL
PARALLEL PORTS
ADDRESS/DATA BUS
I/O PINS
RXD
TXD
1
EXTERNAL ENTERRUPTS
(1)
1. Pins shared with parallels ports pins.
FUNCTIONAL DIAGRAM
V
DD
V
RST
SS
XTAL1
XTAL2
ADDRESS AND
DATA BUS
PORT 0
PORT 1
EA
PSEN
ALE
INT2/INT9
ALTERNATIVE
FUNCTIONS
RxD/data
TxD/clock
INT0
INT1
T0
PORT 3
PORT 2
ADDRESS BUS
T1
WR
RD
5
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
1.1.1 Program Memory
1.0 FUNCTIONAL DESCRIPTION
The 80CL51 contains 4K bytes of internal ROM. After reset the CPU
begins execution at location 0000H. The lower 4K bytes of Program
Memory can be implemented in either on- chip ROM or external
General
The 80CL51 is a stand-alone high-performance CMOS
microcontroller designed for use in real-time applications such as
instrumentation, industrial control, intelligent computer peripherals
and consumer products.
Memory. If the EA pin is strapped to V , then program memory
DD
fetches from addresses 000H through 0FFFH are directed to the
internal ROM. Fetches from addresses 1000H through FFFFH are
directed to external ROM. Program counter values greater than
0FFFH are automatically addressed to external memory regardless
of the state of the EA pin.
The device provides hardware features, architectural enhancements
and new instructions to function as a controller for applications
requiring up to 64K bytes of program memory and/or up to 64K
bytes of data storage.
1.1.2 Data Memory
The 80CL51 contains 128 bytes of internal RAM and 25 Special
Function Registers (SFR). The Memory Map below shows the
internal Data Memory space divided into the Lower 128, the Upper
128, and the SFR space.
The 80CL51 contains a non-volatile 4K byte × 8 read-only program
memory; a static 128 byte × 8 read/write data memory; 32 1/0 lines;
two 16-bit timer/event counters; a thirteen- source two priority-level,
nested interrupt structure and on-chip oscillator and timing circuit.
The lower 128 bytes of the internal RAM are organized as mapped
in Figure 1. The lowest 32 bytes are grouped into 4 banks of 8
registers. Program instructions refer to these registers R0 through
R7. Two bits in the Program Status Word select which register bank
is in use. The next 16 bytes above the register banks form a block of
bit-addressable memory space. The 128 bits in this area can be
directly addressed by the single-bit manipulation instructions. The
remaining registers (30H to 7FH) are directly and indirectly byte
addressable.
The device has two software selectable modes of reduced activity
for power reduction: IDLE and Power-down. The Idle mode freezes
the CPU while allowing the RAM, timers, serial I/O and interrupt
system to continue functioning. The Power-down mode saves the
RAM contents but freezes the oscillator causing all other chip
functions to be inoperative.
The P80C51 is a 5V version of the low voltage microcontroller
P80CL51. Hereafter the generic term P80CL51 will be used for the
functional description of both types. The special features of the
P80C51 are handled in chapter 1.9.
1.1.3 Special Function Registers
The upper 128 bytes are the address locations of the SFRs. Figure
2 shows the Special Function Register (SFR) space. SFRs include
the port latches, timers, peripheral control, serial I/O registers, etc.
These registers can only be accessed by direct addressing. There
are 128 addressable locations in the SFR address space (SFRs with
addresses divisible by eight).
CPU timing
A machine cycle consists of a sequence of 6 states. Each state time
lasts for two oscillator periods, thus a machine cycle takes 12
oscillator periods or 1µs if the oscillator frequency is 12MHz.
1.1 Memory organization
1.1.4 Addressing
The 80CL51 has five methods for addressing source operands:
– Register
The 80CL51 has a 4K Program Memory (ROM) plus 128 bytes of
Data Memory (RAM) on board. The device has separate address
spaces for Program and Data Memory (see Memory Map). Using
Ports P0 and P2, the 80CL51 can address up to 64K bytes of
external memory. The CPU generates both read and write signals
(RD and WR) for external Data Memory accesses, and the read
strobe (PSEN) for external Program Memory.
– Direct
– Register-lndirect
– Immediate
– Base-Register-plus Index-Register-indirect
MEMORY MAP
64K
64K
EXTERNAL
4096
OVERLAPPED
SPACE
4095
4095
225
127
SPECIAL
FUNCTION
REGISTERS
INTERNAL
(EA = 0)
INTERNAL
(EA = 1)
INTERNAL
DATA RAM
0
0
PROGRAM MEMORY
INTERNAL DATA MEMORY
EXTERNAL
DATA RAM
6
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
7FH
2FH
20H
BIT-ADDRESSABLESPACE
(BIT ADDRESSES 0-7F)
R7
I
1FH
I
R0
18H
17H
R7
I
I
4 BANKS OF 8 REGISTERS
(R0-R)
R0
10H
0FH
R7
I
I
R0
08H
07H
R7
I
I
R0
0
Figure 1. The Lower 128 Bytes of Internal RAM
The first three methods can be used for addressing destination
operands. Most instructions have a “destination/source” filed that
specifies data type, addressing methods and operands involved. For
operations other than MOVs, the destination operand is also a
source operand.
To enable a Port 3 pin alternate function, the Port 3 bit latch in its
SFR must contain a logic 1.
Each port consists of a latch (Special Function Registers P0 to P3),
an output driver and an input buffer. Ports 1,2,3 have internal pull
ups. Figure 3(a) shows that the strong transistor p1 is turned on for
only 2 oscillator periods after a 0-to-1 transition in the port latch.
When on, it turns on p3 (a weak pull up) through the inverter. This
inverter and p3 form a latch which hold the 1. In Port 0 the pull up p1
is only on when emitting 1s for external memory access. Writing a 1
to a Port 0 bit latch leaves both output transistors switched off so the
pin can be used as a high-impedance input.
Access to memory addressing is as follows:
– Registers in one of the four register banks through register,
direct or indirect.
– Internal RAM (128 bytes) through direct or register-indirect.
– Special Function Register through Direct.
– External data memory through Register-lndirect
– Program memory look-up tables through Base-Register-Plus
Index-Register-Indirect.
1.2.2 Port Options
The pins of port 1, port 2, and port 3 may be individually configured
with one of the following options (see Figure 3):
1.2 I/O Facilities
Option 1: Standard Port; quasi-bidirectional I/O with pull up. The
strong booster pull up p1 is turned on for two oscillator
periods after a 0-to-1 transition in the port latch (see
Figure 3(a)).
1.2.1 Ports
The 80CL51 has 32 I/O lines treated as 32 individually addressable
bits or as four parallel 8- bit addressable ports. Port 0, 1, 2 and 3
perform the following alternate functions:
Option 2: Open drain; quasi-bidirectional I/O with n-channel open
drain output. Use as an output requires the connection of
an external pull up resistor (see Figure 3(c)).
Port 0:
provides the multiplexed low-order address and data bus
for expanding the device with standard memories and
peripherals.
Option 3: Push-Pull; output with drive capability in both polarities.
Under this option, pins can only be used as outputs. See
Figure 3(b).
Port 1:
Port 2:
provides the inputs for the external interrupts INT2/lNT9.
provides the high-order address when expanding the
device with external program or data memory.
Port 3:
pins can be configured individually to provide:
(1) external interrupt request inputs
(2) counter input
(3) control signals to read and write to external memories
(4) UART input and output
7
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
DIRECT
BYTE ADDRESS
(HEX)
REGISTER
MNEMONIC
BIT ADDRESS
FF
F7
FE
F6
FD
F5
FC
F4
FB
F3
FA
F2
F9
F1
F8
F8H
F0H
IP1
B
F0
IX1
E9H
E8H
EF
EE
ED
EC
EB
EA
E9
E8
IEN1
ACC
PSW
E7
D7
C7
E6
D6
C6
E5
D5
C5
BD
E4
D4
C4
BC
E3
D3
C3
BB
E2
D2
C2
BA
E1
D1
C1
B9
E0
D0
C0
B8
EOH
D0H
C0H
B8H
IRQ1
IP0
B7
AF
B6
AE
B5
B4
B3
AB
B2
AA
B1
A9
B0
A8
B0H
A8H
P3
AD
AC
IEN0
P2
SFRs CONTAINING DIRECTLY
ADDRESSABLE BITS
A7
A6
A5
A4
A3
A2
A1
A0
A0H
99H
98H
S0BUF
S0CON
9F
97
9E
96
9D
95
9C
94
9B
93
9A
92
99
91
98
90
90H
P1
TH1
TH0
8DH
8CH
8BH
8AH
TL1
TL0
89H
88H
TMOD
8F
8E
8D
8C
8B
8A
89
88
TCON
PCON
87H
83H
82H
DPH
DPL
SP
81H
80H
87
86
85
84
83
82
81
80
P0
Figure 2. Special Function Registers
8
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
STRONG PULL UP
2 OSCILLATOR PERIODS
+5V
P2
P1
P3
I/O PIN
FROM
PORT
LATCH
Q
n
(a)
INPUT DATA
INPUT BUFFER
READ PORT PIN
STRONG PULL UP
+5V
P1
I/O PIN
FROM
PORT
(b)
LATCH
n
Q
+5V
EXT.
PULL UP
I/O PIN
FROM
PORT
LATCH
n
Q
INPUT DATA
(c)
INPUT BUFFER
READ PORT PIN
Figure 3. Ports
The definition of port options for port 0 is slightly different. Two
cases have to be examined. First, accesses to external memory
(EA=0 or access above the built -in memory boundary), second, I/O
accesses.
Option 2: Open drain; quasi-bidirectional I/O with n-channel open
drain output. Use as an output requires the connection of
an external pull up resistor (see Figure 3(c)).
Option 3: Push-Pull; output with drive capability in both polarities.
Under this option, pins can only be used as outputs.
External Memory Accesses
Option 1: True 0 and 1 are written as address to the external
memory (strong pull up is used).
Individual mask selection of the post-reset state is available on any
of the above pins. Make your selection by appending “S” or “R” to
option 1, 2, or 3 above (e.g. 1 S for a standard I/O to be set after
RESET or 2R for an open-drain I/O to be reset after RESET).
Option 2: An external pull up resistor is needed for external
accesses.
Option 3: Not allowed for external memory access as the port can
only be used as output.
1.3 Timer/event counter
The 80CL51 contains two 16-bit Timer/Counter registers, Timer 0
and Timer 1, which can perform the following functions:
– Measure time intervals and pulse durations
I/O Accesses
Option 1: When writing a 1 to the port-latch, the strong pull up p1
will be on for 2 oscillator periods. No weak pull up exists.
Without an external pull up, this option can be used as a
high-impedance input.
– Count events
– Generate interrupts requests
9
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
Timer 0 and Timer 1 can be independently programmed to operate
as follows:
1.4 Idle and Power-down operation
Idle mode operation permits the interrupt, serial port and timer
blocks to continue functioning while the clock to the CPU is halted.
The following functions remain active during Idle mode:
– Timer 0, Timer 1
Mode 0 - 8-bit timer or counter with divide-by-32 prescaler
Mode 1 - 16-bit time-interval or event counter
– UART
Mode 2 - 8-bit time interval or event counter with automatic reload
upon overflow
– External interrupt
Mode 3 - Timer 0 establishes TL0 and TH0 as two separate
counters.
The Power-down operation freezes the oscillator. The Power-down
mode can only be activated by setting the PD bit in the PCON
register.
In the “Timer” function, the register is incremented every machine
cycle. Since a machine cycle consists of 12 oscillator periods, the
count rate is 1/12 of the oscillator frequency.
1.4.1 Power control register
Power-down and Idle modes are activated by software via the
Special Function Register PCON. Its hardware address is 87H.
PCON is byte addressable only.
In the “Counter” function, the register is incremented in response to
a 1-to-0 transition. Since it takes 2 machine cycles (24 oscillator
periods) to recognize a 1-to-0 transition, the maximum count rate is
1/24 of the oscillator frequency. To ensure a given level is sampled,
it should be held for at least one full machine cycle.
PCON
BIT
POSITION
FUNCTION
SMOD
PCON.7
PCON.4-PCON.6
Double baud-rate bit, see description of the UART, chapter 1.5.
(reserved)
GF1
GFO
PD
PCON.3
General purpose flag bit
General purpose flag bit
Power-down activation bit
Idle mode activation bit
PCON.2
PCON.1
IDL
PCON.0
XTAL2
XTAL1
OSCILLATOR
INPUTS
SERIAL PORTS
TIMER BLOCKS
CLOCK
GENERATOR
CPU
PD
IDL
Figure 4. Idle and Power-down Hardware
10
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
1.4.2 Power-down mode
clock is gated away from the CPU, but not from the Interrupt, Timer
and Serial port functions. The CPU status is preserved along with
the Stack Pointer, Program Counter, Program Status Word and
Accumulator. The RAM and all other registers maintain their data
during Idle mode. The port pins retain the logical states they held at
Idle mode activation. ALE and PSEN hold at the logic HIGH level.
The instruction setting PCON.1 is the last executed prior to going
into the Power-down mode. In Power-down mode the oscillator is
stopped. The contents of the on-chip RAM and SFRs are preserved.
The port pins output the values held by their respective SFRs. ALE
and PSEN are held LOW.
In the Power-down mode V may be reduced to minimize power
There are two methods used to terminate the Idle mode. Activation
of any enabled interrupt will cause PCON to be cleared by
hardware, terminating Idle mode. The interrupt is serviced, and
following the instruction RETI, the next instruction to be executed
will be the one following the instruction that put the device in the Idle
mode.
DD
consumption. However, the supply voltage must not be reduced until
Power-down mode is active, and must be restored before the
hardware reset is applied and frees the oscillator. Reset must be
held active until the oscillator has restarted and stabilized.
The wake-up operation after power-down in this controller has two
basic approaches:
Flag bits GF0 and GF1 may be used to determine whether the
interrupt was received during normal execution or Idle mode. For
example, the instruction that writes to PCON.0 can also set or clear
one or both flag bits. When Idle mode is terminated by an interrupt,
the service routine can examine the status of the flag bits.
1.4.2.1 Wake-up using INT2 to INT9
If INT2 to INT9 are enabled, the 80CL51 can be awakened from
power-down mode with the external interrupts. To ensure that the
oscillator is stable before the controller restarts, the internal clock
will remain inactive for 1536 oscillator periods. This is controlled by
an on-chip delay counter.
The second method of terminating the Idle mode is with an external
hardware reset. Since the oscillator is still running, the hardware
reset is required to be active for only two machine cycles to
complete the reset operation.
1.4.2.2 Wake-up using RESET
To wake-up the 80CL51 the RESET pin has to be kept HIGH for a
minimum of 24 oscillator periods. The on-chip delay counter is
inactive. The user has to ensure that the oscillator is stable before
any operation is attempted. Figure 5 illustrates the two possibilities
for wake-up.
Reset redefines all SFRs, but does not affect the on-chip RAM.
The status of the external pins during Idle and Power-down mode is
shown in Table 1. If the Power-down mode is activated while
accessing external memory, port data held in the Special Function
Register P2 is restored to Port 2. If the data is a logic 1, the port pin
is held HIGH during the Power-down mode by the strong pull up
transistor p1 (see Figure 3(a)).
1.4.3 Idle mode
The instruction that sets PCON.0 is the last instruction executed
before going into Idle mode. Once in the Idle mode, the internal
Table 1.
Status of the External Pins During Idle and Power-down Mode
MODE
MEMORY
internal
ALE
PSEN
PORT 0
Port Data
Floating
Port Data
Floating
PORT 1
Port Data
Port Data
Port Data
Port Data
PORT 2
Port Data
Address
PORT 3
Port Data
Port Data
Port Data
Port Data
Idle
1
1
0
0
1
1
0
0
Idle
external
internal
Power-down
Power-down
Port Data
Port Data
external
POWER-DOWN
RESET-PIN
EXTERNAL INTERRUPT
OSCILLATOR
DELAY COUNTER
1536 PERIODS
>24 PERIODS
Figure 5. Wake-up Operation
11
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
1.5.2 Serial port control register
1.5 Standard serial interface SI0: UART
The serial port control and status register is the Special Function
Register S0CON, shown in Figure 6. The register contains not only
the mode selection bits, but also the 9th data bit for transmit and
receive (TB8 and RB8), and the serial port interrupt bits (T1 and
R1). See next page.
This serial port is full duplex, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can
commence reception of a second byte before a previously received
byte has been read from the register. (However, if the first byte still
hasn’t been read by the time reception of the second byte is
complete, one of the bytes will be lost). The serial port receive and
transmit registers are both accessed at Special Function Register
S0BUF. Writing to S0BUF loads the transmit register, and reading
S0BUF loads the transmit register, and reading S0BUF accesses a
physically separate receive register.
Baud Rates
The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator
Frequency /12. The baud rate in Mode 2 depends on the value of bit
SMOD in Special Function Register PCON. If SMOD = 0 (which is
the value on reset), the baud rate is 1/64 the oscillator frequency. If
SMOD = 1, the baud rate is 1/32 the oscillator frequency.
The serial port can operate in 4 modes:
SMOD
Mode 0: Serial data enters and exits through RxD. TxD outputs the
shift clock. 8 bits are transmitted/ received (LSB first). The
baud is fixed at 1/12 the oscillator frequency.
Mode 2 Baud Rate = (2
/64)(Oscillator Frequency)
The baud rates in Modes 1 and 3 are determined by the Timer 1
overflow rate.
Mode 1: 10 bits are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), and a stop bit
(1). On receive, the stop bit goes into RB8 in Special
Function Register SCON. The baud rate is variable.
Using Timer 1 to generate baud rates
When Timer 1 is used as the baud rate generator, the baud rates in
Modes 1 and 3 are determined by the Timer 1 overflow rate and the
value of SMOD as follows:
Mode 2: 11 bits are transmitted (through TxD) or received (through
RxD): start bit (0), 8 data bits (LSB first), a programmable
9th data bit, and a stop bit (1). On Transmit, the 9th data
bit (TB8 in SCON) can be assigned the value of 0 or 1.
Or, for example, the parity bit (P, in the PSW) could be
moved into TB8. On receive, the 9th data bit goes into
RB8 in Special Function Register SCON, while the stop
bit is ignored. The baud rate is programmable to either
1/32 or 1/64 the oscillator frequency.
SMOD
(2
/32)(Timer 1 Overflow Rate)
The Timer 1 interrupt should be disabled in this application. The
Timer itself can be configured for either “timer” or “counter”
operation, and in any of its 3 running modes. In the most typical
applications, it is configured for “timer operation, in the auto-reload
mode (high nibble of TMOD = 0010B). In that case the baud rate is
given by the formula:
Mode 1, 3 Baud Rate =
SMOD
Mode 3: 11 bits are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), a
{(2
/32) (Oscillator Frequency)} / {12 (256 - (TH 1 )}
programmable 9th data bit and a stop bit (1). In fact,
Mode 3 is the same as Mode 2 in all respects except
baud rate. The baud rate in Mode 3 is variable.
One can achieve very low baud rates with Timer 1 by leaving the
Timer 1 interrupt enabled, and configuring this Timer to run as a
16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1
interrupt to do a 16-bit software reload. Table 2 lists various
commonly used baud rates and how they can be obtained from
Timer 1.
In all four modes, transmission is initiated by any instruction that
uses S0BUF as a destination register. Reception is initiated in Mode
0 by the condition Rl = 0 and REN = 1. Reception is initiated in the
other modes by the incoming start bit if REN = 1.
More about Mode 0
Figure 7 shows a simplified functional diagram of the serial port in
Mode 0, and associated timing. Transmission is initiated by any
instruction that uses S0BUF as a destination register. The “write to
S0BUF” signal at S6P2 also loads a 1 into the 9th position of the
transmit shift register and tells the TX Control block to commence a
transmission. The internal timing is such that the one full machine
cycle will elapse between “write to S0BUF”, and activation of SEND.
1.5.1 Multiprocessor communications
Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received. The 9th
one goes into RB8. Then comes a stop bit. The port can be
programmed such that when the stop bit is received, the serial port
interrupt will be activated only if RB8 = 1. This feature is enabled by
setting bit SM2 in SCON. A way to use this feature in multiprocessor
systems is as follows:
SEND enables the output of the shift register to the alternate output
function line of P3.0 and also enables SHIFT CLOCK to the
alternate output function line of P3.1. SHIFT CLOCK is low during
S3, S4, and S5 of every machine cycle, and high during S6, S1 and
S2. At S6P2 of every machine cycle in which SEND is active, the
contents of the transmit shift are shifted to the right one position.
When the master processor wants to transmit a block of data to one
of several slaves, it first sends out an address byte which identifies
the target slave. An address byte differs from a data byte in that the
9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no
slave will be interrupted by a data byte. An address byte, however,
will interrupt all slaves, so that each slave can examine the received
byte and see if it is being addressed. The addressed slave will clear
its SM2 bit and prepare to receive the data bytes that will be coming.
The slaves that weren’t being addressed leave their SM2s set and
go on about their business, ignoring the coming data bytes.
As data bits shift out to the right, zeros come in from the left. When
the MSB of the data byte is at the output position of the shift register,
then the 1 that was initially loaded into the 9th position is just to the
left of the MSB, and all positions to the left of that contain zeros.
This condition flags the TX Control block to do one last shift and
then deactivate SEND and set T1. Both of these actions occur at
S1P1 of the 10th machine cycle after “write to S0BUF”.
SM2 has no effect in Mode 0, and in Mode 1 can be used to check
the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the
receive interrupt will not be activated unless a valid stop bit is
received.
Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2
of the next machine cycle, the RX Control unit writes the bits
11111110 to the receive shift register, and in the next clock phase
activates RECEIVE.
12
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
MSB
LSB
R1
SM0 SM1 SM2 REN TB8 RB8 T1
Where SM0, SM1 specify the serial port mode, as follows:
SM0 SM1 Mode Description Baud Rate
/ 12
0
0
1
0
1
0
0
1
2
shift register
8-bit UART
9-bit UART
f
OSC
variable
f
/64
OSC
or
f
/32
OSC
1
1
3
9-bit variable UART
SM2
Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1 then Rl will not
be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then R1 will not be activated if a valid stopbit
was not received. In Mode 0, SM2 should be 0.
REN
TB8
RB8
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
Is the 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is the stop bit that was received. In
Mode 0, RB8 is not used.
TI
Is transmit interrupt flag. Set by hardware at the end of the 8th time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
RI
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception except (see SM2). Must be cleared by software.
Figure 6. Serial Port control (SCON) Register
Table 2.
Timer 1 Generated Commonly Used Baud Rates
TIMER 1
BAUD RATE
Mode 0 Max: 1.33 Mb/s
Mode 2 Max: 500 Kb/s
Modes 1,3: 83.3 Kb/s
19.2 Kb/s
f
16 MHz
16 MHz
16 MHz
SMOD
C/T
x
MODE
RELOAD VALUE
OSC
x
1
1
1
0
0
0
0
0
0
0
x
x
2
2
2
2
2
2
2
2
1
x
x
x
0
FFH
FDH
FDH
FAH
F4H
E8H
1DH
72H
FEEBH
11.059 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.986 MHz
6 MHz
0
9.6 Kb/s
0
4.8 Kb/s
0
2.4 Kb/s
0
1.2 Kb/s
0
137.5 Kb/s
0
110
0
110
12 MHz
0
13
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
RECEIVE enables SHIFT CLOCK to the alternate output function
line of P3.1. SHIFT Clock makes transitions at S3P1 and S6P1 of
every machine cycle. at S6P2 of every machine cycle in which
RECEIVE is active, the contents of the receive shift register are
shifted to the left one position. The value that comes in from the right
is the value that was sampled at the P3.0 pin at S5P2 of the same
machine cycle.
following conditions are met at the time the final shift pulse is
generated.
1. R1 = 0, and
2. Either SM2 = 0, or the received stop bit = 1
If either of these two conditions is not met, the received frame is
irretrievably lost. If both conditions are met, the stop bit goes into
RB8, the 8 data bits go into S0BUF, and Rl is activated. At this time,
whether the above conditions are met or not, the unit goes back to
looking for a 1-to-0 transition in RxD.
As data bits come in from the right, 1s shift out to the left. When the
0 that was initially loaded into the right-most position arrives at the
left-most position in the shift register, it flags the RX Control block to
do one last shift and load S0BUF. At S1P1 of the 10th machine cycle
after the write to SCON that cleared Rl, RECEIVE is cleared as Rl is
set.
More about modes 2 and 3
Eleven bits are transmitted (through TxD), or received (through
RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data
bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be
assigned the value of 0 or 1. On receive, the 9th data bit goes into
RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64
the oscillator frequency in Mode 2. Mode 3 may have a variable
baud rate generated from Timer 1.
More about Mode 1
Ten bits are transmitted (through TxD), or received (through RxD): a
start bit (0), 8 data bits (LSB first), and a stop bit (1 ). On receive,
the stop bit goes into RB8 in SCON. In the 8051 the baud rate is
determined by the Timer 1 overflow rate.
Figures 9 and 10 show a functional diagram of the serial port in
Modes 2 and 3. The receive portion is exactly the same as in Mode
1. The transmit portion differs from Mode 1 only in the 9th bit of the
transmit shift register.
Figure 8 shows a simplified functional diagram of the serial port in
Mode 1, and associated timings for transmit/receive.
Transmission is initiated by any instruction that uses S0BUF as a
destination register. The “write to S0BUF” signal also loads a 1 into
the 9th bit position of the transmit shift register and flags the TX
Control unit that a transmission is requested. Transmission actually
commences at S1P1 of the machine cycle following the next rollover
in the divide-by-16 counter. (Thus, the bit times are synchronized to
the divide-by-16 counter, not to the “write to S0BUF” signal).
Transmission is initiated by any instruction that uses S0BUF as a
destination register. The “write to S0BUF” signal also loads TB8 into
the 9th bit position of the transmit shift register and flags the TX
Control unit that a transmission is requested. Transmission
commences at S1P1 of the machine cycle following the next rollover
in the divide-by-16 counter (thus, the bit times are synchronized to
the divide-by-16 counter, not to the “write to S0BUF” signal). The
transmission begins with activation of SEND, which puts the start bit
at TxD. One bit time later, DATA is activated, which enables the
output bit of the transmit shift register to TxD. One bit time later,
DATA is activated, which enables the output bit of the transmit shift
register to TxD. The first shift pulse occurs one bit time after that.
The first shift clocks a 1 (the stop bit) into the 9th bit position of the
shift register. Thereafter, only zeros are clocked in. Thus, as data
bits shift out to the right, zeros are clocked in from the left. Then TB8
is at the output position of the shift register, then the stop bit is just to
the left of TB8, and all positions to the left of that contains zeros.
This condition flags the TX Control unit to do one last shift and then
deactivate SEND and set Tl. This occurs at the 11th divide-by-16
rollover after “write to S0BUF”.
The transmission begins with activation of SEND which sends the
start bit to pin TxD. One bit time later, DATA is activated, enabling
the transmission of the output bit of the transmit shift register to TxD.
The first shift pulse occurs one bit time after that.
As data bits shift out to the right, zeros are clocked in from the left.
When the MSB of the data byte is at the output position of the shift
register, then the 1 that was initially loaded into the 9th position is
just to the left of the MSB, and all positions to the left of that contain
zeros. This condition flags the TX Control unit to do one last shift
and then deactivate SEND and set Tl. This occurs at the 10th
divide-by-16 rollover after “write to S0BUF”. Reception is initiated by
a detected 1 -to-0 transition at RxD. For this purpose RxD is
sampled at a rate of 16 times whatever baud rate has been
established. When a transition is detected, the divide-by-16 counter
is immediately reset, and 1FFH is written into the input shift register.
Resetting the divide-by-16 counter aligns its rollovers with the
boundaries of the incoming bit times. The 16 states of the counter
divide each bit time into 16th. At the 7th, 8th, and 9th counter states
of each bit time, the bit detector samples the value of RxD. The
value accepted is the value that was seen in at least 2 of the 3
samples. This is done for noise rejection. If the value accepted
during the first bit time is not 0, the receive circuits are reset and the
unit goes back to looking for another 1-to-0 transition. This is to
provide rejection of false start bits. If the start bit proves valid, it is
shifted into the input shift register, and reception of the rest of the
frame will proceed.
Reception is initiated by a detected 1-to-0 transition at RxD. For this
purpose RxD is sampled at a rate of 16 times whatever baud rate
has been established. When a transition is detected, the
divide-by-16 counter is immediately reset, and 1FFFH is written to
the input shift register.
At the 7th, 8th and 9th counter states of each bit time, the bit
detector samples the value of RxD. The value accepted is the value
that was seen in at least 2 of the 3 samples. If the value accepted
during the first bit time is not 0, the receive circuits are reset and the
unit goes back to looking for another 1-to-0 transition. If the start bit
proves valid, it is shifted into the input shift register, and reception of
the rest of the frame will proceed. As data bits come in from the
right, 1s shift out to the left. When the start bit arrives at the left-most
position in the shift register (which in Modes 2 and 3 is a 9-bit
register), it flags the RX Control block to do one last shift, load
S0BUF and RB8, and set Rl.
As data bits come in from the right, 1s shift out to the left. When the
start bit arrives at the left-most position in the shift register, (which in
mode 1 is a 9-bit register), it flags the RX Control block to do one
last shift, loads S0BUF and RB8, and set Rl. The signal to load
S0BUF and RB8, and to set Rl, will generated if, and only if, the
14
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
80CL51 Internal Bus
Write
to
SBUF
RxD
S
P3.0 Alt
Output
Function
D
Q
SBUF
CL
Zero Detector
Start
Shift
TX Control
T1
S6
TX Clock
Send
Serial
Port
Interrupt
TxD
P3.1 Alt
Output
Function
Shift
Clock
R1
RX Clock
Start
Receive
Shift
RX Control
REN
RI
1
1
1
1
1
1
1
0
RxD
P3.0 Alt
Input
Input Shift Register
Function
Shift
Load
SBUF
SBUF
Read
SBUF
80CL51 Internal Bus
S4 .
ALE
.
S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1 . . . . S6 S1
Write to SBUF
S6P2
T
r
Send
Shift
a
n
s
m
i
RxD (Data Out)
D0
D1
D2
D3
D4
D5
D6
D7
t
TxD (Shift Clock)
TI
S3P1
S6P1
Write to SCON (Clear RI)
RI
R
e
c
e
i
v
e
Receive
Shift
RxD (Data In)
D0
D1
D2
D3
D4
D5
D6
D7
S5P2
TxD (Shift Clock)
Figure 7. Serial Port Mode 0
15
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
Timer 1
Overflow
80CL51 Internal Bus
TB8
Write
to
÷ 2
SBUF
SMOD = 1
S
D
Q
SBUF
TxD
CL
Zero Detector
Start
Shift
Data
TX Control
T1
÷ 16
TX Clock
Send
Serial
Port
Interrupt
÷ 16
Load
SBUF
RX Clock RI
RX Control
Sample
1-to-0
Transition
Detector
Shift
Start
Bit Detector
Input Shift Register
(9 Bits)
Shift
RxD
Load
SBUF
S0 BUFFER
Read
SBUF
80CL51 Internal Bus
TX
Clock
Write to SBUF
T
r
Send
S1P1
a
n
s
m
i
Data
Shift
t
Start Bit
TxD
TI
D0
D1
D2
D3
D4
D5
D6
D7
Stop Bit
÷ 16 Reset
RX
Clock
R
e
c
e
i
Start
Bit
RxD
Bit Detector
Sample Time
D0
D1
D2
D3
D4
D5
D6
D7
Stop Bit
v
e
Shift
RI
Figure 8. Serial Port Mode 1
16
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
80CL51 Internal Bus
TB8
Write
to
SBUF
S
D
Q
SBUF
TxD
CL
Phase 2 Clock
(1/2 f
)
OSC
Zero Detector
Mode 2
Stop Bit
Gen.
Shift
Data
Start
TX Control
÷ 16
TX Clock
T1
Send
SMOD = 1
SMOD = 0
Serial
Port
Interrupt
÷ 2
÷ 16
(SMOD is
PCON.7)
Load
SBUF
R1
RX Clock
Sample
RX Control
1-to-0
Transition
Detector
Shift
Start
1FFH
Bit Detector
Input Shift Register
(9 Bits)
Shift
RxD
Load
SBUF
S0 BUFFER
Read
SBUF
80CL51 Internal Bus
TX
Clock
Write to SBUF
Send
S1P1
T
r
a
n
s
m
i
Data
Shift
Start Bit
TxD
TI
t
D0
D1
D2
D3
D4
D5
D6
D7
TB8
Stop Bit
Stop Bit Gen.
÷ 16 Reset
RX
Clock
R
e
c
e
i
v
e
Start
Bit
RxD
D0
D1
D2
D3
D4
D5
D6
D7
RB8
Stop Bit
Bit Detector
Sample Times
Shift
RI
Figure 9. Serial Port Mode 2
17
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
Timer 1
Overflow
80CL51 Internal Bus
TB8
Write
to
÷ 2
SBUF
SMOD = 1
S
SMOD = 0
D
Q
S0 BUFFER
TxD
CL
Zero Detector
Start
Shift
Data
TX Control
T1
÷ 16
TX Clock
Send
Serial
Port
Interrupt
÷ 16
Load
SBUF
R1
RX Clock
Sample
RX Control
1-to-0
Transition
Detector
Shift
Start
Bit Detector
Input Shift Register
(9 Bits)
Shift
RxD
Load
SBUF
S0 BUFFER
Read
SBUF
80CL51 Internal Bus
TX
Clock
Write to SBUF
Send
S1P1
T
r
a
n
s
m
i
Data
Shift
Start Bit
TxD
TI
t
D0
D1
D2
D3
D4
D5
D6
D7
TB8
Stop Bit
Stop Bit Gen.
÷ 16 Reset
RX
Clock
Start
Bit
R
e
c
e
i
v
e
RxD
D0
D1
D2
D3
D4
D5
D6
D7
RB8
Stop Bit
Bit Detector
Sample Times
Shift
RI
Figure 10. Serial Port Mode 3
18
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
The signal to load S0BUF and RB8, and to set Rl, will be generated
if, and only if, the following conditions are met at the time the final
shift pulse is generated.
– UART serial I/O
– INT2 to INT9 (Port 1)
Each interrupt vectors to a separate location in program memory for
its service routine. Each source can be individually enabled or
disabled by corresponding bits in the Interrupt Enable Registers (IE,
IEO). The priority level is selected via the Interrupt Priority register
(IP0, IP1). All enabled sources can be globally disabled or enabled.
1. Rl = 0, and
2. Either SM2 = 0 or the received 9th data bit = 1
If either of these conditions is not met, the received frame is
irretrievably lost, and Rl is not set. If both conditions are met, the
received 9th data bit goes into RB8, and the first 8 data bits 90 into
S0BUF. One bit time later, whether the above conditions were met or
not, the unit goes back to looking for a 1-to-0 transition at the RxD
input.
1.6.1 External Interrupts INT2/INT9
Port 1 lines serve an alternative purpose as eight additional
interrupts INT2 to INT9. When enabled, each of these lines may
“wake-up” the device from Power-down mode. Using the IX1
register, each pin may be initialized to either active HIGH or LOW.
IRQ1 is the interrupt request flag register. Each flag, if the interrupt
is enabled, will be set on an interrupt request but must be cleared by
software, i.e. via the interrupt software or when the interrupt is
disabled.
1.6 Interrupt System
External events and the real-time-driven on-chip peripherals require
service by the CPU asynchronous to do execution of any particular
section of code. To tie the asynchronous activities of these functions
to normal program execution, a multiple-source, two-priority-level,
nested interrupt system is provided. The 80CL51 acknowledges
interrupt requests from thirteen sources as follows:
– INT0 and INT1
The Port 1 interrupts are level sensitive. A Port 1 interrupt will be
recognized when a level (HIGH or LOW depending on Interrupt
Polarity Register IX1) on P1x is held active for at least one machine
cycle. The Interrupt Request is not served until the next machine
cycle.
– Timer 0 and Timer 1
IEN0/1
IP0/1
REGISTERS
INTERRUPT
SOURCES
PRIORITY
HIGH
X0
S0
X5
T0
X6
LOW
X1
X2
X7
T1
X3
X8
X4
X9
GLOBAL ENABLE
Figure 11. Interrupt System
19
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
IX1
IEN1
IRQ1
X9
P1.7
P1.6
X8
X7
P1.5
P1.4
X6
X5
X4
X3
P1.3
P1.2
P1.1
P1.0
X2
WAKE-UP
Figure 12. External Interrupt Configuration
Interrupt enable register IEN0, IEN1
IEN0 (A8H)
Interrupt priority register IP0, IP1
IP0 (B8H)
EA
-
ES1
ES0
ET1
EX1
ET0
EX0
-
-
PS1
PS0
PT1
PX1
PT0
PX0
Bit
Symbol
Function
Bit Symbol
Function
IEN0.7 EA
General enable/disable control
0 = no interrupt is enabled
IP0.7
IP0.6
-
-
Unused
Unused
1 = any individually enabled interrupt will be accepted
Unused
IEN0.5 ES1 Unused
IP0.5 PS1 Unused
IP0.4 PS0 UART SIO interrupt
IP0.3 PT1 Timer 1 interrupt priority level
IEN0.6
-
IEN0.4 ES0 Enable UART SIO interrupt
IEN0.3 ET1 Enable timer T1 interrupt
IEN0.2 EX1 Enable external interrupt
IEN0.1 ET0 Enable Timer T0 interrupt
IEN0.0 EX0 Enable external interrupt 0
IP0.2 PX1 External interrupt 1 priority level
IP0.1 PT0 Timer 0 interrupt priority level
IP0.0 PX0 External interrupt 0 priority level
IP1 (B8H)
PX9
PX8
PX7
PX6
PX5
PX4
PX3
PX2
IEN1 (E8H)
Bit Symbol
Function
EX9
EX8
EX7
EX6
EX5
EX4
EX3
EX2
IP1.7 PX9 External interrupt 9 priority level
IP1.6 PX8 External interrupt 8 priority level
IP1.5 PX7 External interrupt 7 priority level
IP1.4 PX6 External interrupt 6 priority level
IP1.3 PX5 External interrupt 5 priority level
IP1.2 PX4 External interrupt 4 priority level
IP1.1 PX3 External interrupt 3 priority level
IP1.0 PX2 External interrupt 2 priority level
Bit
Symbol
Function
IEN1.7 EX9
IEN1.6 EX8
IEN1.5 EX7
IEN1.4 EX6
IEN1.3 EX5
IEN1.2 EX4
IEN1.1 EX3
IEN1.0 EX2
Enable external interrupt 9
Enable external interrupt 8
Enable external interrupt 7
Enable external interrupt 6
Enable external interrupt 5
Enable external interrupt 4
Enable external interrupt 3
Enable external interrupt 2
Interrupt priority is as follows:
0 = low priority
1 = high priority
where 0 = interrupt disabled
1 = interrupt enabled
20
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
Interrupt polarity register IX1
IX1 (E9H)
1.7 Oscillator registers
The on-chip circuitry of the 80CL51 is a single-stage inverting
amplifier biased by an internal feedback resistor (Figure 13). For
operation as standard quartz oscillator, no external components are
needed except at 32 KHz. When using external capacitors, ceramic
resonators, coils and RC networks to drive the oscillator, five
different configurations are supported (see Figure 14 and oscillator
options).
IL9
IL8
IL7
IL6
IL5
IL4
IL3
IL2
Bit Symbol
Function
IX1.7 IL9 External interrupt 9 polarity level
IX1.6 IL8 External interrupt 8 polarity level
IX1.5 IL7 External interrupt 7 polarity level
IX1.4 IL6 External interrupt 6 polarity level
IX1.3 IL5 External interrupt 5 polarity level
IX1.2 IL4 External interrupt 4 polarity level
IX1.1 IL3 External interrupt 3 polarity level
IX1.0 IL2 External interrupt 2 polarity level
In the Power-down mode the oscillator is stopped XTAL1 is pulled
HIGH. The oscillator inverter is switched off to ensure no current will
flow regardless of the voltage at XTAL1. To drive the device with an
external clock source, apply the external clock signal to XTAL1, and
leave XTAL2 to float, as shown in Figure 14(f). There are no
requirements on the duty cycle of the external clock, since the input
to the internal clocking circuitry is split sing a flip-flop.
Interrupt request flag register IRQ1
IRQ1 (C0H)
The following options are provided for optimum on-chip oscillator
performance. Please state option when ordering.
IQ9
IQ8
IQ7
IQ6
IQ5
IQ4
IQ3
IQ2
Bit Symbol
Function
1.7.1 Oscillator options (see Figure 14)
IRQ1.7 IQ9 External interrupt 9 request flag
IRQ1.6 IQ8 External interrupt 8 request flag
IRQ1.5 IQ7 External interrupt 7 request flag
IRQ1.4 IQ6 External interrupt 6 request flag
IRQ1.3 IQ5 External interrupt 5 request flag
IRQ1.2 IQ4 External interrupt 4 request flag
IRQ1.1 IQ3 External interrupt 3 request flag
IRQ1.0 IQ2 External interrupt 2 request flag
The following options are provided for optimum on-chip oscillator
performance. Please state option when ordering.
Osc.1: Figure 14(c): An option for 32 kHz clock applications with
external trimmer for frequency adjustment. A 4.7 MQ bias
resistor is needed for use in parallel with the crystal.
Osc. 2: Figure 14(e): An option for low-power, low-frequency
operations using LC components.
1.6.2 Interrupt Vectors
Osc. 3: An option for medium frequency range applications.
Osc. 4: An option for high frequency range applications.
Vector
0003H
0023H
0053H
000BH
005BH
0013H
003BH
0063H
001BH
0043H
006BH
004BH
0073H
Source
X0
S0
X5
T0
X6
X1
X2
X7
T1
X3
X8
X4
X9
External 0
UART SIO
External 5
Timer 0
External 6
External 1
External 2
External 7
Timer 1
External 3
External 8
External 4
External 9
RC:
Figure 14(g): An option for an RC oscillator.
V
DD
80CL51
TO INTERNAL
TIMING CIRCUITS
PD
V
DD
V
DD
Interrupt priority
Each interrupt priority source can be set to either high or low priority.
If both priorities are requested simultaneously, the controller will
branch to the high priority vector.
C
C
1i
2i
R
bias
XTAL1
XTAL2
A low priority interrupt can only be interrupted by a high priority
interrupt. A high priority interrupt routine cannot be interrupted.
1.6.3 Related registers
The following registers are used in conjunction with the interrupt
system:
Figure 13. Oscillator
Register
Function
IX1 Interrupt polarity register
IRQ1 Interrupt enable register
IEN1 Interrupt enable register (INT2-INT9)
IP0 Interrupt priority register
IP1 Interrupt priority register (INT2-INT9)
21
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
QUARTZ OSCILLATOR
STANDARD QUARTZ
OSCILLATOR
WITH EXTERNAL
CAPACITORS
32 kHz OSCILLATOR
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
(a)
(b)
(c)
CERAMIC RESONATOR
LC-OSCILLATOR
XTAL1
XTAL1
(d)
(e)
EXTERNAL CLOCK
RC-OSCILLATOR
XTAL1
XTAL2
XTAL1
N.C.
XTAL2
N.C.
V
DD
(f)
(g)
Figure 14. Alternative Oscillator Configurations
22
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
OSCILLATOR TYPE SELECTION GUIDE
C1 EXT. (pF)
C2 EXT. (pF)
MAX. RESONATOR
RESONATOR
f(MHz)
OPTION
MIN.
MAX.
MIN.
MAX.
SERIES RESISTANCE
1
Quartz
0.032
OSC. 1
0
0
5
0
15
15 kΩ
Quartz
Quartz
Quartz
Quartz
Quartz
Quartz
Quartz
PXE
1.0
3.58
4.0
OSC. 2
OSC. 2
OSC. 2
OSC. 3
OSC. 4
OSC. 4
OSC. 4
OSC. 2
OSC. 2
OSC. 2
OSC. 2
OSC. 2
OSC. 3
OSC. 4
OSC. 2
0
0
30
15
20
10
15
10
15
50
50
40
40
20
15
40
90
30
15
20
10
15
10
15
50
50
40
40
20
15
40
90
600 Ω
100 Ω
75 Ω
60 Ω
60 Ω
40 Ω
20 Ω
10 Ω
100 Ω
10 Ω
10 Ω
5 Ω
0
0
0
6.0
0
0
10.0
12.0
16.0
0.455
1.0
0
0
0
0
0
0
40
15
0
40
15
0
PXE
PXE
3.58
4.0
PXE
0
0
PXE
6.0
0
0
PXE
10.0
12.0
0
0
6 Ω
PXE
10
20
10
20
6 Ω
LC
10 µH = 1 Ω
100 µH = 5 Ω
1 mH = 75 Ω
NOTES:
1. 32 kHz quartz crystals with a series resistance higher than 15 kΩ will reduce the guaranteed supply voltage range to 2.5 -3.5V.
2. The equivalent circuit data of the internal oscillator compares with that of matched crystals.
OSCILLATOR EQUIVALENT CIRCUIT PARAMETERS (SEE FIGURE 15)
SYMBOL
PARAMETER
OPTION
CONDITION
MIN.
TYP.
MAX.
UNIT
g
Osc.1
T = +25 °C; V = 4.5V
-
15
600
1500
4000
-
µs
µs
µs
µs
Transconductance
m
m
m
m
DD
g
g
g
Osc.2
Osc.3
Osc.4
T = +25 °C; V = 4.5V
200
400
1000
1000
4000
10000
DD
T = +25 °C; V = 4.5V
DD
T = +25 °C; V = 4.5V
DD
C1
C1
C1
C1
Osc.1
Osc. 2
Osc. 3
Osc. 4
-
-
-
-
3.0
8.0
8.0
8.0
-
-
-
-
pF
pF
pF
pF
Input Capacitance
Output Capacitance
Output Capacitance
i
i
i
i
C2
C2
C2
C2
Osc.1
Osc. 2
Osc. 3
Osc. 4
-
-
-
-
23
8.0
8.0
8.0
-
-
-
-
pF
pF
pF
pF
i
i
i
i
R2
R2
R2
R2
Osc.1
Osc. 2
Osc. 3
Osc. 4
-
-
-
-
3800
65
18
-
-
-
-
kΩ
kΩ
kΩ
kΩ
5.0
23
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
1.7.2 RC Oscillator (see Figure 16)
The externally adjustable RC-oscillator has a frequency range from 100 kHz to 500 kHz.
R
f
XTAL1
XTAL2
C1
V
g
R
C2
i
i
1
m
2
SCHMITT
TRIGGER
Figure 15. Equivalent Circuit Diagram
600
fosc
(kHz)
400
200
0
0
2
4
6
RC(µs)
Figure 16. Frequency as a Function of RC
24
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
The internal RAM is not affected by reset. When V is turned on
the RAM contents are indeterminate.
1.8 Reset Circuitry
To initialize the 80CL51, a reset is performed by either of two
DD
methods:
– via the RST pin
1.8.1 Power-on reset
The 80CL51 contains on-chip circuitry which switch the port pins to
the customer defined logic level as soon as V exceeds
– via a power-on-reset
DD
1.3V. As soon as the minimum supply voltage is reached, the
oscillator will start up. However, to ensure that the oscillator is stable
before the controller starts, the clock signals are gated away from
the CPU for a further 1536 oscillator periods. During that time the
CPU is held in a reset state.
It leaves the internal registers as follows:
REGISTER
ACC
CONTENT
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
XX00 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0XXX 0000
0000 0000
1111 1111
XXXX XXXX
0000 0000
0000 0111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
B
DPL
DPH
IEN0
IEN1
IP0
IP1
IX1
IRQ1
PCH
PCL
PCON
PSW
P0-P3
S0BUF
S0CPN
SP
TCON
TH0, TH1
TL0, TH1
TL0, TL1
TMOD
A hysteresis of approximately 50 mV at a typical power-on switching
level of 1.3 V will ensure correct operation.
The on-chip Power-on circuitry can be switched off via the mask
option “OFF”. This option reduces the power-down current to
typically 800µA and can be chosen if external reset circuitry is used.
For applications not requiring the internal reset option, “OFF” should
be chosen.
An automatic reset can be obtained at power-on by connecting the
RST pin to V via a 10µF capacitor. At power-on, the voltage on
DD
the RST pin is equal to V minus the capacitor voltage, and
DD
decreases from V as the capacitor discharges through the
DD
internal resistor R
to ground. The larger the capacitor, the more
RST
slowly V
decreases V
must remain above the lower threshold
RST
RST
of the Schmitt trigger long enough to effect a complete reset. The
time required is the oscillator start-up time, plus 2 machine cycles.
1.9 P80CL31: ROMless version of P80CL51
The P80CL31 is a low voltage ROMless version of the P80CL51
microcontroller. The mask options on the P80CL31 are fixed as
follows:
• Port options: all ports have option “1S”, i.e., standard port, high
The reset state of the port pins is mask- programmable and can
therefore be defined by the user.
after reset
• Oscillator option: OSC3
The standard reset value for port P0-P3 is 1111 1111.
• Power-on Reset option: OFF
The reset input to the 80CL51 is RST pin 9. A Schmitt trigger
qualifies the input for noise rejection. The output of the Schmitt
trigger is sampled by the reset circuitry every machine cycle.
1.10 P80C51: 5V standard version
The P80C51 is a 5V version of the low voltage P80CL51
microcontroller. All functional features of the P80CL51 are
maintained in the P80C51 with the exception of the mask options.
The mask options on the P80C51 are as follows:
A reset is accomplished by holding the RST pin HIGH for at least
two machine cycles (24 oscillator periods), while the oscillator is
running. The CPU responds by generating an internal reset. Port
pins adopt their reset state immediately after RST goes HIGH.
During reset ALE and PSEN are held HIGH.
• Port options: all ports have option “1S”, i.e., standard port, high
after reset.
The external reset is asynchronous to the internal clock. The RST
pin is sampled during State 5, Phase 2 of every machine cycle. After
a HIGH is detected at the RST pin, an internal reset is repeated
every cycle until RST goes LOW.
• Oscillator options: OSC3
• Power-on Reset option: OFF
RESET
CIRCUITRY
RST
SCHMITT
TRIGGER
Figure 17. Reset Configuration at RST Pin
25
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
SWITCHING LEVEL
POR
SUPPLY
VOLTAGE
HYSTERESIS
POWER-ON
RESET (INTERNAL)
OSCILLATOR
CPU RUNNING
START-UP
TIME
1536 OSCILLATOR
PERIODS DELAY
Figure 18. Power-on Reset Switching Level
V
CC
V
CC
+
10µF
80CL51
RST
R
RST
Figure 19. Recommended Power-on Reset Circuitry
26
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
2.0 RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
MIN.
-0.5
-0.5
-
MAX.
+ 6.5
+0.5
UNIT
V
V
DD
V
I
Supply voltage (pin 40)
All input voltages
V
DD
V
I , I
I
DC current into any input or output
Total power dissipation
5
mA
mW
°C
O
P
-
300
+150
+85
TOT
STG
T
Storage temperature range
-65
-40
-
T
AMB
Operating ambient temperature range
Operating junction temperature
°C
T
J
125
°C
3.0 DC CHARACTERISTICS P80CL31/P80CL51
V
SS
= 0V; T = -40 to +85°C; all voltages with respect to V unless otherwise specified.
AMB SS
SYMBOL
PARAMETER
Supply voltage
RAM retention in power down mode
CONDITIONS
MIN.
1.8
TYP.
MAX.
6.0
–
UNIT
V
DD
DD
V
SS
= 0V
-
V
V
V
1.0
–
Supply current operating (Note 1, Note 4)
I
OSC 1 option
f
= 32 KHz; V = 1.8V
- 25°C
-
-
50
µA
DD
cIk
DD
T
AMB
I
I
I
OSC 2 option
OSC 3 option
OSC 4 option
f
cIk
f
cIk
f
cIk
= 3.58 MHz; V = 3V
-
-
-
-
-
-
2.5
24
26
mA
mA
mA
DD
DD
DD
DD
= 16 MHz; V = 5V
DD
= 16 MHz; V = 5V
DD
Idle Mode (Note 2, Note 4)
I
OSC 1 option
f
= 32 KHz; V = 1.8V
= 25°C
-
-
25
µA
DD
cIk
DD
T
AMB
I
I
I
OSC 2 option
f
f
f
= 3.58 MHz; V = 3V
-
-
-
-
-
-
-
1.0
10
12
10
mA
mA
mA
µA
DD
DD
DD
cIk
cIk
cIk
DD
OSC 3 option
= 16 MHz; V = 5V
DD
OSC 4 option
= 16 MHz; V = 5V
DD
I
Power down (Note 3, Note 4)
V
= 1.8V,
PD
DD
T
AMB
= 25°C
Inputs
V
Input voltage LOW
Input voltage HIGH
V
-
-
-
-
-
-
-
0.3V
DD
V
V
IL
SS
V
IH
0.7V
V
DD
DD
V
DD
V
DD
V
DD
V
DD
V
SS
= 5V, V = 0.4V
100
50
µA
µA
mA
µA
µA
IN
-
I
IL
Input current logic 0 (Port 1, 2, 3)
= 2.5V, V = 0.4V
IN
-
= 5V, V = V /2
-
1.0
500
10
IN
DD
Input current logic 1 to 0 transition
(Port 1, 2, 3)
I
TL
= 2.5V, V = V /2
-
-
IN
DD
+/I
Input leakage current (Port 0, EA)
< V < V
I DD
IL
Outputs
V
DD
V
DD
V
DD
V
DD
= 5V, V = 0.4V
1.6
0.7
1.6
0.7
10
-
-
-
mA
mA
mA
mA
kΩ
OL
I
Output sink current LOW
OL
= 2.5V, V = 0.4V
-
OL
= 5V; V = V -0.4V
-
-
-
OH
DD
Output source current HIGH
(push-pull options only)
-I
OH
= 2.5V; V = V -0.4V
-
OH
DD
R
RST pull-down resistor
–
200
RST
NOTES:
1. The operating supply current is measured with all output pins disconnected; XTAL 1 driven with t = t = 10ns; V = V ; V = V ;
DD
r
f
IL
SS
IH
XTAL 2 not connected; EA = RST = Port 0 = V ; all open drain outputs connected to V
.
DD
SS
2. The idle mode supply current is measured with all output pins disconnected; XTAL 1 driven with t = t = 10ns; V = V . XTAL 2 not
r
f
IL
SS
connected; EA = Port 0 = V ; RST = V ; all open drain outputs connected to V
DD
SS
SS.
3. The power-down current is measured with all output pins disconnected; XTAL 1 not connected; EA = Port 0 = V ; RST = V ; all open
DD
SS
drain outputs connected to V
SS.
4. Circuits with Power-on Reset option “OFF” are tested at V minimum = 1.8V; with option “ON” (typically 1.3V) they are tested at V
DD
DD
minimum = 2.3V. Please note, option “ON” is only available on P80CL51.
27
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
4.0 DC CHARACTERISTICS P80C51
V
= 0V; V = 5V ± 10%; f = 3.5 to 16MHz; T
= -40 to +85°C; all voltages with respect to V unless otherwise specified.
AMB SS
SS
DD
clk
SYMBOL
PARAMETER
CONDITIONS
= 0V
MIN.
TYP.
MAX.
UNIT
V
DD
Supply voltage
V
SS
4.5
-
5.5
V
Supply Current
I
I
Operating (Note 1)
Idle mode (Note 2)
Power down (Note 3)
f
f
= 16MHz, V = 5V
–
–
–
–
–
–
24
10
50
mA
mA
µA
DD
CLK
DD
= 16MHz, V = 5V
DD
CLK
DD
I
V
= 5V
PD
DD
Inputs
V
Input voltage LOW
V
–
–
–
–
–
0.3V
DD
V
V
IL
IH
IL
IL
IL
SS
V
Input voltage HIGH
0.7V
V
DD
DD
I
I
I
Input current logic 0 (Port 1, 2, 3)
V
V
V
= 0.4V
–
–
–
100
1.0
10
µA
mA
µA
IN
Input current logic 1 to 0 transition (Port 1, 2, 3)
Input leakage current (Port 0, EA)
= V /2
DD
IN
< V < V
SS
I
DD
Outputs
I
Output sink current LOW
V
V
= 0.4V
1.6
1.6
–
–
–
–
mA
mA
OL
OL
I
Output source current HIGH
(push-pull options only)
= V – 0.4V
OH DD
OH
R
RST pull-down resistor
10
–
200
kΩ
RST
NOTES:
1. The operating supply current is measured with all output pins disconnected; XTAL 1 driven with t = t = 10ns;
R
F
V
IL
= V ; V = V ; XTAL 2 not connected; EA = RST = Port 0 = V ; all open drain outputs connected to V
.
SS
IH
DD
DD
SS
2. The idle mode supply current is measured with all output pins disconnected; XTAL 1 driven with t = t = 10ns;
R
F
V
IL
= V . XTAL 2 not connected; EA = Port 0 = V ; RST = V ; all open drain outputs connected to V
SS DD SS SS.
3. The power-down current is measured with all output pins disconnected; XTAL 1 not connected;
EA = Port 0 = V ; RST = V ; all open drain outputs connected to V
.
SS
DD
SS
4. Please note, option “ON” is only available on P80CL51.
28
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
5.0 AC CHARACTERISTICS
V
DD
= 5 V; V = 0V; T
= -40 to +85°C; C = 50 pF for Port 0, ALE and PSEN; C = 40pF for all other outputs, unless otherwise specified.
amb L L
SS
PROGRAM MEMORY (See Figure 20)
VARIABLE CLOCK
SYMBOL
PARAMETER
MIN.
2T -40
TYP.
MAX.
UNIT
ns
t
ALE pulse duration
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LL
AL
LA
LC
CK
t
t
Address set-up time to ALE
T
T
T
-40
-35
-25
ns
CK
CK
Address hold time to ALE
ns
t
Time from ALE to control pulse PSEN
Time from ALE to valid instruction input
Control pulse duration PSEN
ns
CK
t
-
4T -100
CK
ns
LIV
t
3T -35
CK
-
ns
CC
t
Time from PSEN to valid instruction input
Input instruction hold time after PSEN
Input instruction float delay after PSEN
Address to valid instruction input
Address float time to PSEN
-
0
-
3T -125
CK
ns
CIV
t
CI
-
ns
t
t
T
CK
-20
ns
CIF
AIV
-
5T -115
CK
ns
t
0
-
ns
AFC
EXTERNAL DATA MEMORY (See Figures 21 and 22)
SYMBOL PARAMETER
VARIABLE CLOCK
MIN.
TYP.
MAX.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RD pulse duration
WR pulse duration
6T -100
CK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RR
t
6T -100
CK
WW
t
Address hold time after ALE
RD to valid data input
T
T
-35
-35
LA
CK
t
5T -165
CK
RD
CK
t
Data float delay after RD
-
2T -70
CK
DFR
t
Time from ALE to valid data input
Address to valid data input
-
-
8T -150
CK
LD
AD
LW
AW
t
9T -165
CK
t
Time from ALE to RD and WR
Time from address to RD and WR
Time from RD or WR HIGH to ALE HIGH
Data valid to WR transition
3T -50
CK
3T +50
CK
t
4T -130
CK
-
t
T
CK
T
CK
-40
-60
T
CK
-40
WHLH
t
-
DWX
t
t
Data set-up time before WR
Data hold time after WR
T
-150
-
-
DW
CK
T
CK
-50
WD
t
Address float delay after RD (Note 1)
-
12
WAFR
NOTE:
1. Interfacing the 80CL51 or P80C51 to devices with float times up to 75ns is permitted. This limited bus connection will not cause damage to
Port 0 drivers.
29
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
t
CV
t
t
LIV
LL
ALE
t
t
LC
CC
PSEN
t
LA
t
CIF
t
AL
t
CIV
PORT 0
AD0 TO AD7
INST. INPUT
AD0 TO AD7
INST. INPUT
t
AL
t
CI
t
AIV
ADDRESS A8 TO A15
ADDRESS A8 TO A15
PORT 2
Figure 20. Read from Program Memory
t
WHLH
t
LD
ALE
PSEN
RD
t
t
LW
RR
t
t
AL
LA
t
DFR
t
t
AW
RD
PORT 0
AD0 TO AD7
DATA INPUT
t
AFR
t
AD
ADDRESS A8 TO A15 OR PORT 2 OUT
PORT2
Figure 21. Read from Data Memory
30
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
t
WHLH
ALE
PSEN
t
LW
t
WW
WR
t
AW
t
AL
t
WX
t
t
WD
t
DW
LA
AD0 TO AD7
PORT 0
PORT2
DATA OUTPUT
ADDRESS A8 TO A15 OR PORT 2 OUT
Figure 22. Write to Data Memory
31
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
ONE MACHINE CYCLE
ONE MACHINE CYCLE
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
XTAL1
INPUT
DOTTED LINES
ARE VALID WHEN
RD OR WR
ARE ACTIVE
ALE
ONLY ACTIVE
DURING A READ
FROM EXTERNAL
DATA MEMORY
PSEN
RD
ONLY ACTIVE
DURING A WRITE
TO EXTERNAL
DATA MEMORY
WR
INST
IN
ADDRESS
A0-A7
INST
IN
ADDRESS
A0-A7
INST
IN
ADDRESS
A0-A7
INST
IN
ADDRESS
A0-A7
BUS
(PORT 0)
EXTERNAL
PROGRAM
MEMORY
FETCH
PORT 2
ADDRESS A8-A15
ADDRESS A8-A15
ADDRESS A8-A15
ADDRESS A8-A15
INST
IN
ADDRESS
A0-A7
INST
IN
ADDRESS
A0-A7
ADDRESS
A0-A7
DATA OUTPUT OR DATA INPUT
BUS
(PORT 0)
READ OR WRITE
OF EXTERNAL
DATA MEMORY
ADDRESS A8-A15 OR PORT 2 OUT
ADDRESS A8-A15
PORT 2
ADDRESS A8-A15
PORT 0,2,3
OUTPUT
OLD DATA
OLD DATA
NEW DATA
PORT 1
OUTPUT
NEW DATA
PORT 0,2,3
OUTPUT
SAMPLING TIME OF I/O PORT PINS DURING INPUT
PORT 1
OUTPUT
SERIAL
PORT
CLOCK
Figure 23. Instruction Cycle Timing
32
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
6.0 CHARACTERISTICS CURVES
0.7V
0.3V
0.7V
DD
DD
DD
DD
0.9V
0.4V
DD
DD
TEST POINTS
0.3V
Figure 24. AC Testing Input Waveform
-I
L
I
TL
500µA
500µA
I
IL
100µA
V
IN
2.5V
Figure 25. Input Current at V = 5V
DD
33
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
20
16 MHz
18
16
14
12
10
8
16
12 MHz
12
f
XTAL
(MHz)
I
DD
8
(mA)
6
8 MHz
4
2
4
0
3.58 MHz
0
2
4
6
V
(V)
DD
Figure 26. P80CL51/31 Frequency Operating Range
0
0
2
4
6
V
(V)
DD
Figure 27. P80CL51/31 Typical Operating Current vs
o
Frequency and V , T
= 25 C.
DD amb
6
16 MHz
6
5
4
12 MHz
4
3
I
PD
I
idle
(mA)
(µA)
8 MHz
2
1
2
3.58 MHz
0
0
0
2
4
6
0
2
4
6
V
(V)
DD
V
(V)
DD
Figure 29. P80CL51/31 Typical Power-Down Current
Figure 28. P80CL51/31 Typical Idle Current vs
o
o
vs Frequency and V , T
= 25 C.
Frequency and V , T
= 25 C.
DD amb
DD amb
34
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
35
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
36
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
37
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
NOTES
38
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
NOTES
39
January 1995
Philips Semiconductors
Product specification
Low-voltage single-chip 8-bit microcontrollers
80CL31/80CL51
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1995
All rights reserved. Printed in U.S.A.
Telephone 800-234-7381
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