P80CL410HFN [NXP]
Low voltage/low power single-chip 8-bit microcontroller with I2C; 低电压/低功耗的单芯片8位微控制器， I2C
| 型号： | P80CL410HFN |
| 厂家： | 
NXP |
| 描述： | Low voltage/low power single-chip 8-bit microcontroller with I2C |
| 文件： | 总28页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
80CL410/83CL410
Low voltage/low power single-chip
8-bit microcontroller with I2C
Product specification
IC20 Data Handbook
1995 Jan 20
Philips
Semiconductors
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
FEATURES
PIN CONFIGURATION
• Single supply voltage 1.8V to 6.0V
INT2/P1.0
INT3/P1.1
40
39
1
2
3
V
DD
• Frequency from DC to 12MHz
P0.0/AD0
• 80C51 based architecture
– 4k × 8 ROM (64k external)
– 128 × 8 RAM (64k external)
– Four 8-bit I/O ports
INT4/P1.2
38 P0.1/AD1
37
INT5/P1.3
INT6/P1.4
4
5
P0.2/AD2
36 P0.3/AD3
35
– Two 16-bit timer/counters
INT7/P1.5
SCL/INT8/P1.6
SDA/INT9/P1.7
RST
6
7
8
9
P0.4/AD4
34 P0.5/AD5
DESCRIPTION
– A thirteen-source, two-level, nested
priority interrupt structure
The 80CL410/83CL410 (hereafter generically
referred to as 8XCL410) is manufactured in
an advanced CMOS process that allows the
part to operate at supply voltages down to
1.8V and oscillator frequencies down to DC.
The 8XCL410 has the same instruction set
as the 80C51.
33
32
P0.6/AD6
P0.7/AD7
– 10 external interrupts
• Fully static 80C51 CPU
DIP
31 EA
P3.0 10
P3.1 11
2
• I C Serial Interface
VSO
30
29
ALE
• Two power control modes
– Idle mode
INT0
/P3.2
12
13
PSEN
The 8XCL410 features a 4k byte ROM
(83CL410), 128 bytes RAM (both ROM and
RAM are externally expandable to 64k
bytes), four 8-bit ports, two 16-bit
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
INT1/P3.3
– Power-down mode – can be terminated
by reset or external interrupt
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
• Wake-up via external interrupts at port 1
• Single supply voltage 1.8V to 6.0V
• Frequency range of DC to 12MHz
2
timer/counters, an I C serial interface, a
thirteen source, two priority level nested
interrupt structure, and on-chip oscillator
circuitry suitable for quartz crystal, ceramic
resonator, RC, or LC.
25
24
23
22
P2.4/A12
P2.3/A11
P2.2/A10
P2.1/A9
P2.0/A8
RD/P3.7
XTAL2
17
18
• On-chip oscillator (quartz crystal, ceramic
resonator, RC, LC)
The 8XCL410 has two reduced power modes
that are the same as those on the standard
80C51. The special reduced power feature of
this part is that it can be stopped and then
restarted. Running from an external clock
source, the clock can be stopped and after a
period of time restarted. The 8XCL410 will
resume operation from where it was when the
code stopped with no loss of internal state,
RAM contents, or Special Function Register
contents. If the internal oscillator is used the
part cannot be stopped and started, but the
power-down mode, which can be terminated
via an interrupt, can be used to achieve
similar power savings and then restart
without loss of on-chip RAM and Special
Function Register values.
XTAL1 19
20
• Very low power consumption
21
V
SS
• Operating temperature range:
–40 to +85°C
44
34
1
33
23
QFP
11
12
22
SEE NEXT PAGE FOR QFP PIN FUNCTIONS.
ORDERING CODE
PHILIPS PART ORDER NUMBER
PART MARKING
PHILIPS NORTH AMERICA
PART ORDER NUMBER
TEMPERATURE °C
1
Drawing
Number
AND PACKAGE
ROMless
ROM
ROMless ROM
FREQUENCY
–40 to +85,
40-Pin Plastic Dual In-line Package
P80CL410HFP P83CL410HFP P80CL410HF N P83CL410HF N
P80CL410HFT P83CL410HFT P80CL410HF D P83CL410HF D
32kHZ to 12MHz SOT129-1
32kHZ to 12MHz SOT158-1
32kHZ to 12MHz SOT307-2
–40 to +85,
40-Pin Plastic Very Small Outline
Package
–40 to +85,
44-Pin Plastic Quad Flat Pack
P83CL410HFH
NOTE:
1. Parts ordered by the Philips North America part number will be marked with the Philips part marking.
For emulation purposes, the P85CL000 (Piggyback version) with 256 bytes of RAM is recommended.
2
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
LOGIC SYMBOL
V
V
SS
DD
44
34
XTAL1
XTAL2
Address and
Data Bus
1
33
23
QFP
INT2
INT3
11
INT4
INT5
INT6
INT7
INT8/SCL
RST
EA
12
Function
22
Function
PSEN
ALE
Pin
1
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
INT9/SDA
P1.5/INT7
P1.6/INT8/SCL
P1.7/INT9/SDA
RST
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
2
INT0
3
INT1
T0
T1
WR
RD
Address Bus
4
5
P3.0
ALE
6
NC
NC
7
P3.1
EA
8
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
9
10
11
12
13
14
15
16
XTAL1
V
V
SS
DD
17
18
19
20
21
22
NC
39
40
41
42
43
44
NC
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.0/INT2
P1.1/INT3
P1.2/INT4
P1.3/INT5
P1.4/INT6
3
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
BLOCK DIAGRAM
FREQUENCY
REFERENCE
COUNTER (1)
XTAL2
XTAL1
T0
T1
PROGRAM
MEMORY
(4K × 8 ROM)
DATA
MEMORY
(128 × 8 RAM)
OSCILLATOR
TWO 16-BIT
TIMER/EVENT
COUNTERS
AND
TIMING
CPU
10
3
INTERNAL
INTERRUPTS
64K BYTE BUS
EXPANSION
CONTRTOL
PROGRAMMABLE I/O
2
C-BUS SERIAL I/O
I
EXTERNAL
INTERRUPTS
CONTROL
SDA
SCL
PARALLEL PORTS,
ADDRESS/DATA BUS
AND I/O PINS
(1)
(1)
(1) Pins shared with parallel port pins.
4
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
PIN DESCRIPTION
PIN NO.
MNEMONIC
TYPE
NAME AND FUNCTION
DIL40/
VSO40
QFP
V
V
16
38
20
40
I
I
Ground: 0V reference.
SS
Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
DD
P0.0–0.7
30–37
39–32
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data
memory. In this application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7
40–44
1–3
1–8
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 1 pins that are externally pulled low will source current because
of the internal pull-ups. (See DC Electrical Characteristics: I ). Additional functions
IL
include:
2
7
8
1–8
I/O
I/O
I
SCL (P1.6): I C serial bus clock.
SDA (P1.7): I C serial bus data.
2
INT2–INT9 (P1.0–P1.7): Additional external interrupts.
P2.0–P2.7
18–25
21–28
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 2 pins that are externally being pulled low will source current
because of the internal pull-ups. (See DC Electrical Characteristics: I ). Port 2 emits
IL
the high-order address byte during fetches from external program memory and during
accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this
application, it uses strong internal pull-ups when emitting 1s. During accesses to
external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents
of the P2 special function register.
P3.0–P3.7
5, 7–13
10–17
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 3 pins that are externally being pulled low will source current
because of the pull-ups. (See DC Electrical Characteristics: I ). Port 3 also serves the
IL
special features of the 80C51 family, as listed below:
8
9
10
11
12
13
12
13
14
15
16
17
I
I
I
I
O
O
INT0 (P3.2): External interrupt 0
INT1 (P3.3): External interrupt 1
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
RST
ALE
4
9
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets
the device. An internal diffused resistor to V permits a power-on reset using only an
SS
external capacitor to V
.
DD
27
30
O
Address Latch Enable: Output pulse for latching the low byte of the address during
an access to external memory. In normal operation, ALE is emitted at a constant rate
of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note
that one ALE pulse is skipped during each access to external data memory.
PSEN
EA
26
29
29
31
O
I
Program Store Enable: The read strobe to external program memory. When the
device is executing code from the external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each
access to external data memory. PSEN is not activated during fetches from internal
program memory.
External Access Enable: EA must be externally held low to enable the device to
fetch code from external program memory locations 0000H to 0FFFH. If EA is held
high, the device executes from internal program memory unless the program counter
contains an address greater than 0FFFH.
XTAL1
XTAL2
15
14
19
18
I
Crystal 1: Input to the inverting oscillator amplifier and input for an external clock
source.
O
Crystal 2: Output from the inverting oscillator amplifier.
5
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
Table 1. 8XCL410 Special Function Registers
DIRECT
ADDRESS MSB
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
RESET
VALUE
SYMBOL
DESCRIPTION
LSB
ACC*
B*
Accumulator
B register
E0H
F0H
E7
F7
E6
F6
E5
F5
E4
F4
E3
F3
E2
F2
E1
F1
E0
00H
F0
00H
DPTR:
Data pointer
(2 bytes):
High byte
Low byte
DPH
DPL
83H
82H
00H
00H
BF
–
BE
–
BD
PS1
FD
BC
–
BB
PT1
FB
BA
PX1
FA
B9
PT0
F9
B8
PX0
F8
IP0*#
IP1*#
Interrupt priority 0
Interrupt priority 1
B8H
F8H
xx000000B
00H
FF
PX9
FE
PX8
FC
PX6
PX7
PX5
PX4
PX3
PX2
AF
EA
AE
–
AD
ES1
ED
AC
–
AB
ET1
EB
AA
EX1
EA
A9
ET0
E9
A8
EX0
E8
IEN0*#
IEN1*#
Interrupt enable 0
Interrupt enable 1
A8H
E8H
00H
00H
EF
EE
EX8
C6
IQ8
EC
EX6
C4
IQ6
EX9
C7
EX7
C5
EX5
C3
EX4
C2
EX3
C1
EX2
C0
IRQ1*#
IX1#
P0*
Interrupt request flag
Interrupt polarity
Port 0
C0H
E9H
80H
90H
A0H
B0H
IQ9
IQ7
IQ5
IQ4
IQ3
IQ2
00H
00H
FFH
FFH
FFH
FFH
87
97
A7
B7
86
96
A6
B6
85
95
A5
B5
84
94
A4
B4
83
93
A3
B3
82
92
A2
B2
81
91
A1
B1
80
90
A0
B0
P1*
Port 1
P2*
Port 2
P3*
Port 3
PCON
Power control
87H
SMOD
–
–
–
GF1
GF0
PD
IDL
0xxx0000B
D7
CY
D6
AC
D5
F0
D4
D3
D2
D1
–
D0
P
PSW*
Program status word
Slave address
D0H
DBH
D8H
RS1
RS0
OV
00H
S1ADR#
00H
DF
–
DE
DD
DC
DB
SI
DA
AA
D9
D8
S1CON*# Serial control
ENS1
STA
STO
CR1
CR0
x0000000B
S1DAT#
S1STA#
Serial data
Serial status
DAH
D9H
00H
11111000B
SP
Stack pointer
81H
07H
8F
8E
8D
8C
8B
8A
89
88
TCON*
Timer/counter con-
trol
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00H
TMOD
TH0
TH1
TL0
Timer/counter mode
Timer 0 high byte
Timer 1 high byte
Timer 0 low byte
Timer 1 low byte
89H
8CH
8DH
8AH
8BH
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
00H
00H
00H
00H
TL1
*
#
SFRs are bit addressable.
SFRs are modified from or added to the 80C51 SFRs.
6
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
Two cases have to be examined. First,
Option 2: Open drain—quasi-bidirectional
I/O with n-channel open drain
PORT OPTIONS
accesses to external memory (EA = 0 or
access above the built-in memory boundary),
and second, I/O accesses.
The pins of port 1 (not P1.6/SCL or
P1.7/SDA), port 2, and port 3 may be
individually configured with one of the
following port options (see Figure 1):
output. Use as an output requires
the connection of an external
pull-up resistor. See Figure 1(c).
External Memory Accesses
Option 1: True 0 and 1 are written as
address to the external memory
(strong pull-up is used).
Option 3: Push-Pull—output with drive
capability in both polarities. Under
this option, pins can only be used
as outputs.
Option 1: Standard Port—
quasi-bidirectional I/O with pull-up.
The strong booster pull-up p1 is
turned on for two oscillator periods
after a 0-to-1 transition in the port
latch. See Figure 1(a).
Option 2: An external pull-up resistor is
needed for external accesses.
Individual mask selection of the post-reset
state is available on any of the above pins.
Make your selection by appending “S” or “R”
to option 1, 2, or 3 above (e.g., 1S for a
standard I/O to be set after RESET or 2R for
an open-drain I/O to be reset after RESET.
Option 3: Not allowed for external memory
accesses as the port can only be
used as output.
Option 2: Open Drain—quasi-bidirectional
I/O with n-channel open drain
output. Use as an output requires
the connection of an external
pull-up resistor. See Figure 1(b).
I/O Accesses
Option S: Set—after reset, this pin will be
Option 1: When writing a 1 to the port latch,
the strong pull-up p1 will be on for
two oscillator periods. No weak
pull-up exists. Without an external
pull-up, this option can be used as
a high-impedance input.
initialized High.
Option 3: Push-Pull—output with drive
capability in both polarities. Under
this option, pins can only be used
as outputs. See Figure 1(c).
Option R: Reset—after reset, this pin will be
initialized Low.
The definition of port options for port 0 is
slightly different.
STRONG PULL-UP
+5V
TWO OSCILLATOR PERIODS
P2
P1
N
P3
I/O PIN
(a)
Q
FROM PORT LATCH
INPUT DATA
INPUT
BUFFER
READ PORT PIN
+5V
EXTERNAL
PULL-UP
I/O PIN
N
(b)
Q
FROM PORT LATCH
INPUT DATA
INPUT
BUFFER
READ PORT PIN
+5V
STRONG PULL-UP
P1
N
(c)
I/O PIN
Q
FROM PORT LATCH
Figure 1. Ports
7
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
is detected. This is controlled by the on-chip
There are two methods used to terminate the
idle mode. Activation of any interrupt will
cause PCON to be cleared by hardware;
terminating idle mode. The interrupt is
serviced, and following the instruction RETI,
the next instruction to be executed will be the
one following the instruction that put the
device in the the idle mode.
POWER-DOWN MODE
delay counter. After this, the PD flag will be
reset, the controller is now in the Idle mode
and the interrupt will be handled in the normal
way.
The instruction setting PCON.1 is the last
executed prior to going into the power-down
mode. In power-down mode, the oscillator is
stopped. The contents of the the on-chip
RAM and SFRs are preserved. The port pins
output the values held by their respective
SFRs. ALE and PSEN are held low.
Reset Mode
Setting only the PD bit in the PCON register
again forces the controller into the
power-down mode, but in this case it can
only be restored to normal operation with a
direct reset operation.
In the power-down mode, V may be
Flag bits GF0 and GF1 can be used to
determine whether the interrupt was received
during normal execution or idle mode. For
example, the instruction that writes to
PCON.0 can also set or clear one or both flag
bits. When idle mode is terminated by an
interrupt, the service routine can examine the
status of the flag bits.
DD
reduced to minimize power consumption.
However, the supply voltage must not be
reduced until the power-down mode is active,
and must be restored before the hardware
reset is applied and frees the oscillator. Reset
must be held active until the oscillator has
restarted and stabilized.
To restore normal operation, the RESET pin
has to be kept High for a minimum of 24
oscillator periods. The on-chip delay counter
is inactive. The user has to insure that the
oscillator is stable before any operation is
attempted. Figure 2 illustrates the two
possibilities for wake-up.
From the power-down mode the part can be
restarted by using either the wake-up mode
or the Reset Mode.
The second method of terminating the idle
mode is with an external hardware reset.
Since the oscillator is still running, the
hardware reset is required to be active for
only two machine cycles to complete the
reset operation. Reset redefines all SFRs,
but does not affect the state of the on-chip
RAM.
Wake-Up Mode
IDLE MODE
Setting both PD and IDL bits in the PCON
register forces the controller into the
power-down mode. Setting both bits enable
the controller to be woken-up from the
power-down mode via either an enabled
external interrupt INT2–INT9, or a reset
operation.
The instruction that sets PCON.0 is the last
instruction executed before going into idle
mode. In idle mode, the internal clock is
stopped for the CPU, but not for the interrupt,
timer, and serial port functions. The CPU
status is preserved along with the stack
pointer, program counter, program status
word and accumulator. The RAM and all
other registers maintain their data during idle
mode. The port pins retain the logical states
they held at idle mode activation. ALE and
PSEN hold at the logic high level.
The status of the external pins during idle and
power-down mode is shown in Table 2. If the
power-down mode is activated while
accessing external memory, port data held in
the special function register P2 is restored to
port 2. If the data is a logic 1, the port pin is
held high during the power-down mode.
An external interrupt for an enabled interrupt
INT2–INT9 at port 1 starts both the oscillator
and the delay counter. To ensure that the
oscillator is stable before the controller
restarts, the internal clock will remain inactive
for 1536 oscillator periods after the interrupt
Table 2.
External Pin Status During Idle and Power-Down Modes
MODE
PROGRAM MEMORY
Internal
ALE
PSEN
PORT 0
Data
PORT 1
Data
PORT 2
Data
PORT 3
Data
Idle
Idle
1
1
0
0
1
1
0
0
External
Floating
Data
Data
Address
Data
Data
Power-down
Power-down
Internal
Data
Data
External
Floating
Data
Data
Data
POWER-DOWN
RESET PIN
EXTERNAL INTERRUPT
OSCILLATOR
> 24 PERIODS
DELAY COUNTER
1536 PERIODS
Figure 2. Wake-Up Operation
8
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
SLAVE ADDRESS
S1ADR
GC
SHIFT REGISTER
S1DAT
SDA
ARBITRATION LOGIC
BUS CLOCK GENERATOR
SCL
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
S1CON
7
S1STA
Figure 3. Serial I/O
2
AA
Assert acknowledge bit. When
the AA flag is set, an
acknowledge (low level to SDA)
will be returned during the
acknowledge clock pulse on the
SCL line when:
– own slave address is received
– general call address is
received (S1ADR.0 = 1)
– data byte received while
device is programmed as
master
STO
STOP flag. With this bit set while
in master mode, a STOP
I C-BUS SERIAL I/O
2
The serial port supports the twin line I C-bus.
The I C-bus consists of a data line (SDA)
2
condition is generated. When a
STOP condition is detected on
the bus, the SIO hardware clears
the STO flag. In the slave mode,
the STO flag may also be set to
recover from an error condition.
In this case, no STOP condition
and a clock line (SCL). These lines also
function as I/O port lines P1.7 and P1.6
respectively. The system is unique because
data transport, clock generation, address
recognition and bus control arbitration are all
2
controlled by hardware. The I C-bus serial
2
is transmitted to the I C-bus.
I/O has complete autonomy in byte handling
and operates in four modes:
– Master transmitter
However, the SIO hardware
behaves as if a STOP condition
has been received and releases
SDA and SCL. The SIO then
switches to the “not addressed”
slave receiver mode. The STO
flag is automatically cleared by
hardware.
– data byte received while
device is selected slave
– Master receiver
– Slave transmitter
– Slave receiver
With AA = 0, no acknowledge will
be returned. Consequently, no
interrupt is requested when the
“own slave address” or general
call address is received.
These functions are controlled by the S1CON
register. S1STA is the status register whose
contents may also be used as a vector to
various service routines. S1DAT is the data
shift register and S1ADR the slave address
register. Slave address recognition is
performed by hardware.
STA
START flag. When the STA bit is
set in slave mode, the SIO
SI
SIO interrupt flag. When the SI
flag is set, an acknowledge is
returned after any one of the
following conditions:
– a start condition is generated
in master mode
hardware checks the status of
2
the I C-bus and generates a
START condition if the bus is
free. If STA is set while the SIO
is in master mode, SIO transmits
a repeated START condition.
S1CON (D8H)
Serial control register
– own slave address received
during AA = 1
ENS1
When ENS1 = 0, the SIO is
disabled. The SDA and SCL
outputs are in a high-impedance
state; P1.6 and P1.7 function as
open drain ports.
CR2 ENS1 STA STO
SI
AA
CR1 CR0
– general call address received
while S1ADR.0 and AA = 1
– data byte received or
transmitted in master mode
(even if arbitration is lost)
– data byte received or
transmitted as selected slave
– stop or start condition received
as selected slave receiver or
transmitter
CR0, CR1, CR2
These three bits determine the
serial clock frequency when SIO
is in a master mode.
When ENS1 = 1, the SIO is
enabled. The P1.6 and P1.7 port
latches must be set to logic 1.
9
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
S1STA (D9H)
MST/REC mode
SLV/TRX mode
Status register
S1STA value
S1STA value
08H – a START condition has been
transmitted
A8H – Own SLA and R have been received,
ACK returned
SC4 SC3 SC2 SC1 SC0
0
0
0
10H – a repeated START condition has
been transmitted
38H – Arbitration lost while returning ACK
40H – SLA and R have been transmitted,
ACK received
48H – SLA and R have been transmitted,
ACK received
50H – DATA has been received, ACK
returned
B0H – Arbitration lost in SLA, R/W as MST.
Own SLA and R have been received,
ACK returned
B8H – DATA byte has been transmitted,
ACK received
C0H – DATA byte has been transmitted,
ACK received
C8H – Last DATA byte has been transmitted
(AA = logic 0), ACK received
S1STA is an 8-bit read-only special function
register. S1STA.3–S1STA.7 hold a status
code. S1STA.0–S1STA.2 are held LOW. The
contents of S1STA may be used as a vector
to a service routine. This optimizes response
time of the software and consequently that of
2
the I C-bus.
58H – DATA has been received, ACK
returned
The following is a list of the status codes:
Miscellaneous
S1STA value
Abbreviations used:
SLV/REC mode
S1STA value
SLA: 7-bit slave address
00H – Bus error during MST mode or
selected SLV mode, due to an
erroneous START or STOP condition
F8H – No relevant state interruption
available, SI = 0.
R:
W:
Read bit
Write bit
60H – Own SLA and W have been received,
ACK returned
68H – Arbitration lost in SLA, R/W as MST.
Own SLA and W have been received,
ACK returned
ACK: Acknowledgement (acknowledge
bit = 0)
ACK: Not Acknowledge (acknowledge
bit = 1)
DATA: 8-bit byte to or from the I C-bus
MST: Master
SLV: Slave
S1DAT (DAH)
Data Shift Register
2
70H – General CALL has been received,
ACK returned
7
6
5
4
3
2
1
0
78H – Arbitration lost in SLA, R/W as MST.
General CALL has been received
80H – Previously addressed with own SLA.
DATA byte received, ACK returned
88H – Previously addressed with own SLA.
DATA byte received, ACK returned
90H – Previously addressed with general
CALL. DATA byte has been received,
ACK has been returned
98H – Previously addressed with general
CALL. DATA byte has been received,
ACK has been returned
A0H – A STOP condition or repeated START
condition has been received while still
addressed as SLV/REC or SLV/TRX
TRX: Transmitter
REC: Receiver
Data shift register S1DAT
This register contains the serial data to be
transmitted or data that has just been
received. Bit 7 is transmitted or received first,
i.e., data is shifted from left to right.
MST/TRX mode
S1STA value
08H – a START condition has been
transmitted
10H – a repeated START condition has
been transmitted
18H – SLA and W have been transmitted,
ACK received
20H – SLA and W have been transmitted,
ACK received
28H – DATA of S1DAT has been
transmitted, ACK received
30H – DATA of S1DAT has been
transmitted, ACK received
S1ADR (DBH)
Slave Address Register
7
6
5
4
3
2
1
0
S1ADR.0, GC: 0 = general CALL address is
not recognized
1 = general CALL address is
recognized
S1ADR.7-1:
own slave address
38H – Arbitration lost in SLA, R/W or DATA
This 8-bit register may be loaded with the
7-bit slave address, to which the controller
will respond when programmed as a slave
receiver/transmitter. The LSB bit (GC) is used
to determine whether the general CALL
address is recognized.
Table 3.
SCL Frequency
BIT RATE (kHz) at f
6MHz
OSC
CR2
CR1
CR0
f
DIVIDED BY
3.58MHz
12MHz
OSC
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
256
224
192
160
960
120
60
14.0
16.0
18.6
22.4
3.73
29.8
59.7
–
23.4
26.8
31.3
37.5
6.25
50
46.9
53.6
62.5
75.0
12.5
100
–
100
–
not allowed
–
10
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
IEN1 (E8H)
Interrupt enable register
IX1 (E9H)
Interrupt polarity register
INTERRUPT SYSTEM
External events and the real-time-driven
on-chip peripherals require service by the
CPU asynchronous to the execution of any
particular section of code. To tie the
asynchronous activities of these functions to
normal program execution, a multiple-source,
two-priority level, nested interrupt system is
provided. The 8XCL410 acknowledges
interrupt requests from thirteen sources, as
follows:
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
EX9 EX8 EX7 EX6 EX5 EX4 EX3 EX2
IL9 IL8
IL7
IL6
IL5
IL4
IL3
IL2
Bit
Symbol
Function
Bit
Symbol
Function
IEN1.7 EX9
IEN1.6 EX8
IEN1.5 EX7
IEN1.4 EX6
IEN1.3 EX5
IEN1.2 EX4
IEN1.1 EX3
IEN1.0 EX2
Enable external interrupt 9
Enable external interrupt 8
Enable external interrupt 7
Enable external interrupt 6
Enable external interrupt 5
Enable external interrupt 4
Enable external interrupt 3
Enable external interrupt 2
IX1.7
IL9
External interrupt 9 polarity
level
IX1.6
IX1.5
IX1.4
IX1.3
IX1.2
IX1.1
IX1.0
IL8
IL7
IL6
IL5
IL4
IL3
IL2
External interrupt 8 polarity
level
External interrupt 7 polarity
level
External interrupt 6 polarity
level
External interrupt 5 polarity
level
External interrupt 4 polarity
level
External interrupt 3 polarity
level
External interrupt 2 polarity
level
– INT0 and INT1
– Timer 0 and timer 1
2
– I C-bus serial I/O interrupt
– INT2 to INT9 (port 1)
where 0 = interrupt disabled
1 = interrupt enabled
Each interrupt vectors to a separate location
in program memory for its service routine.
Each source can be individually enabled or
disabled by corresponding bits in the internal
enable registers (IEN0, IEN1) The priority
level is selected via the interrupt priority
register (IP0, IP1). All enabled sources can
be globally disabled or enabled.
IP0 (B8H)
Interrupt priority register
7
6
5
4
3
2
1
0
—
—
PS1
—
PT1 PX1 PT0 PX0
Writing either a “1” or “0” to an IX1 register bit
sets the priority level of the corresponding
external interrupt to active High or Low,
respectively.
Bit
Symbol
—
—
Function
IP0.7
IP0.6
IP0.5
(unused)
(unused)
External Interrupts INT2–INT9
Port 1 lines serve an alternative purpose as
eight additional interrupts INT2–INT9. When
enabled, each of these lines can “wake-up”
the device from power-down mode. Using the
IX1 register, each pin may be initialized to
either active high or low. IRQ1 is the interrupt
request flag register. Each flag, if the interrupt
is enabled, will be set on an interrupt request
but it must be cleared by software.
PS1
I C SIO interrupt
2
priority level
(unused)
Timer 1 interrupt
prioity level
External interrupt 1
priority level
Timer 0 interrupt
prioity level
External interrupt 0
priority level
IP0.4
IP0.3
—
PT1
IP0.2
IP0.1
IP0.0
PX1
PT0
PX0
IEN0 (A8H)
Interrupt enable register
7
6
5
4
3
2
1
0
IP1 (F8H)
Interrupt priority register
EA
—
ES1
—
ET1 EX1 ET0 EX0
7
6
5
4
3
2
1
0
Bit
Symbol
Function
PX9 PX8 PX7 PX6 PX5 PX4 PX3 PX2
IEN0.7 EEA
General enable/disable
control
Bit
IP1.7
Symbol
PX9
Function
External interrupt 9 priority
0 = no interrupt is enabled
1 = any individually enabled
interrupt will be
accepted
(unused)
level
IP1.6
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
PX8
PX7
PX6
PX5
PX4
PX3
PX2
External interrupt 8 priority
level
IEN0.6
IEN0.5 ES1
IEN0.4
—
External interrupt 7 priority
Enable I C SIO interrupt
level
2
—
(unused)
External interrupt 6 priority
IEN0.3 ET1
IEN0.2 EX1
IEN0.1 ET0
IEN0.0 EX0
Enable Timer T1 interrupt
Enable external interrupt 1
Enable Timer T0 interrupt
Enable external interrupt 0
level
External interrupt 5 priority
level
External interrupt 4 priority
level
External interrupt 3 priority
level
External interrupt 2 priority
level
Interrupt priority is as follows:
0 – low priority
1 – high priority
11
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
IRQ1 (C0H)
Interrupt request flag register
OSCILLATOR CIRCUITRY
Power-on Reset
The 8XCL410 contains on-chip circuitry
which switch the port pins to the
The on-chip oscillator circuitry of the
7
6
5
4
3
2
1
0
8XCL410 is a single stage inverting amplifier
biased by an internal feedback resistor. (See
Figure 4.) The oscillator can be operated with
a quartz crystal, ceramic resonator, LC
network or RC network. See Figure 5 for
different configurations. When ordering parts,
it is necessary to specify an oscillator option.
The options are: RC when an RC network will
be used, OSC 2 for oscillator operation below
4MHz, OSC 3 for oscillator operation from
4MHz to 10MHz, OSC 4 for oscillator
customer-defined logic level as soon as V
DD
IQ9 IQ8
IQ7
IQ6 IQ5
IQ4
IQ3 IQ2
exceeds 1.3V if the mask option “ON” has
been chosen (see Figures 8 and 9). As soon
as the minimum supply voltage is reached,
the oscillator will start up. However, to ensure
that the oscillator is stable before the
controller starts, the clock signals are gated
away from the CPU for a further 1536
oscillator periods.
Bit
Symbol
Function
IRQ1.7 IQ9
IRQ1.6 IQ8
IRQ1.5 IQ7
IRQ1.4 IQ6
IRQ1.3 IQ5
IRQ1.2 IQ4
IRQ1.1 IQ3
IRQ1.0 IQ2
External interrupt 9 request
flag
External interrupt 8 request
flag
External interrupt 7 request
flag
External interrupt 6 request
flag
External interrupt 5 request
flag
External interrupt 4 request
flag
External interrupt 3 request
flag
External interrupt 2 request
flag
An hysteresis of approximately 50mV at a
typical power-on switching level of 1.3V will
ensure correct operation.
operation above 10MHz, and 32kHz if 32kHz
to 400kHz operation is desired.
For operation as a standard quartz oscillator,
no external components are needed (except
at 32KHz). When using external capacitors,
ceramic resonators, coils, and RC networks
to drive the oscillator, five different
The on-chip power–on reset circuitry can also
be switched off via the mask option “OFF”.
This option reduces the power-down current
to typically 800µA and can be chosen if
external reset circuitry is used. For
configurations are supported (see Figure 5
and Table 4).
applications not requiring the internal reset,
option “OFF” should be chosen.
Priority
X0 (highest) 0003H
Vector
Source
External 0
I C port
External 5
Timer 0
External 6
External 1
External 2
External 7
Timer 1
External 3
External 8
External 4
External 9
In the power-down mode the oscillator is
stopped and XTAL1 is pulled high. The
oscillator inverter is switched off to ensure no
current will flow. To drive the device with an
external clock source, apply the external
clock signal to XTAL1, and leave XTAL2 to
float, as shown in Figure 5(f). There are no
requirements on the duty cycle of the
An automatic reset can be obtained at
power-on by connecting the RST pin to V
via a 10µF capacitor. At power-on, the
DD
2
S1
X5
T0
X6
X1
X2
X7
T1
X3
X8
X4
002BH
0053H
000BH
005BH
0013H
003BH
0063H
001BH
0043H
006BH
004BH
voltage on the RST pin is equal to V minus
DD
the capacitor voltage, and decreases from
V
DD
as the capacitor discharges through the
internal resistor R
to ground. The larger
RST
the capacitor, the more slowly V
RST
external clock, since the input to the internal
clocking circuitry is split using a flip-flop.
decreases. V
must remain above the
RST
lower threshold of the Schmitt trigger long
enough to effect a complete reset. The time
required is the oscillator start-up time, plus 2
machine cycles.
The following options are provided for
optimum on-chip oscillator performance.
Please state option when ordering:
X9 (lowest) 0073H
Osc.1: Figure 5(c). An option for 32kHz
clock applications with external
SFR
Address
E9H
P80CL410:
trimmer for frequency adjustment.
Register
IX1
IRQ1
Function
ROM-less VERSION OF P83CL410
The P80CL410 is a low voltage ROMless
version of the P83CL410. The mask options
on the P80CL410 are fixed as follows:
Interrupt polarity register
Interrupt request flag
register
A 4.7MΩ bias resistor must be
connected in parallel with the
crystal.
C0H
IEN0
IEN1
Interrupt enable register
Interrupt enable register
(INT2–INT9)
A8H
E8H
Osc.2: Figure 5(e). An option for low-power,
low-frequency operations using LC
components or quartz.
• Port Options:
All ports except P16/P17 have option “1S”,
i.e., standard port, High after reset. The
ports P16/P17 have option “2S”, i.e., open
drain, High after reset.
IP0
IP1
Interrupt priority register
Interrupt priority register
(INT2–INT9)
B8H
F8H
Osc.3: An option for medium frequency
range applications.
• Oscillator option: OSC3
Osc.4: An option for high frequency range
applications.
• Power-on Reset option: OFF
RC:
Figure 5(g). An option for an RC
oscillator.
The equivalent circuit data of the internal
oscillator compares with that of matched
crystals.
The externally adjustable RC oscillator has a
frequency range from 100kHz to 500kHz.
(See Figure 7.)
12
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
V
DD
To internal
timing circuits
PD
V
DD
V
DD
R
bias
C2
i
C1
i
XTAL1
XTAL2
Figure 4. Oscillator
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
4.7 MEG
(b) Quartz Oscillator with External
Capacitors
(a) Oscillator Configuration for
Quartz Crystal
(c) Configuration for
32kHz Operation
(d) Configuration for
Ceramic Resonator
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
N.C.
N.C.
V
DD
(e) Configuration for
LC Network
(f) External Clock
Configuration
(g) RC Network
Configuration
Figure 5. Oscillator Configurations
13
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
Table 4.
Oscillator Type Selection Guide
C1 EXT.
C2 EXT.
MAXIMUM RESONATOR
SERIES RESISTANCE
RESONATOR
Quartz
Quartz
Quartz
Quartz
Quartz
Quartz
Quartz
Quartz
PXE
f (MHz)
0.032
1.0
OPTION
Osc.1
Osc.2
Osc.2
Osc.2
Osc.3
Osc.4
Osc.4
Osc.4
Osc.2
Osc.2
Osc.2
Osc.2
Osc.2
Osc.3
Osc.4
Osc.2
MIN
5
MAX
15
30
15
20
10
15
10
15
50
50
40
40
20
15
40
90
MIN
0
MAX
0
1
15kΩ
0
0
30
15
20
10
15
10
15
50
50
40
40
20
15
40
90
600Ω
100Ω
75Ω
60Ω
60Ω
40Ω
20Ω
10Ω
100Ω
10Ω
10Ω
5Ω
3.58
4.0
0
0
0
0
6.0
0
0
10.0
12.0
16.0
0.455
1.0
0
0
0
0
0
0
40
15
0
40
15
0
PXE
PXE
3.58
4.0
PXE
0
0
PXE
6.0
0
0
PXE
10.0
12.0
0
0
6Ω
PXE
10
20
10
20
6Ω
LC
10µH = 1Ω
100µH = 5Ω
1mH = 75Ω
NOTE:
1. 32kHz quartz crystals with a series resistance higher than 15kΩ will reduce the guaranteed supply voltage range to 2.5 to 3.5V.
Table 5.
Oscillator Equivalent Circuit Parameters (see Figure 6)
PARAMETER
OPTION
SYMBOL
CONDITION
MIN
TYP
MAX
UNIT
Transconductance
Input capacitance
Output capacitance
Output resistance
Osc.1
Osc.2
Osc.3
Osc.4
g
g
g
g
T = +25°C; V = 4.5V
–
15
600
1500
4000
–
µs
µs
µs
µs
m
m
m
m
DD
T = +25°C; V = 4.5V
200
400
1000
1000
4000
10000
DD
T = +25°C; V = 4.5V
DD
T = +25°C; V = 4.5V
DD
Osc.1
Osc.2
Osc.3
Osc.4
c1
c1
c1
c1
–
–
–
–
3.0
8.0
8.0
8.0
–
–
–
–
pF
pF
pF
pF
i
i
i
i
Osc.1
Osc.2
Osc.3
Osc.4
c2
c2
c2
c2
–
–
–
–
23.0
8.0
8.0
8.0
–
–
–
–
pF
pF
pF
pF
i
i
i
i
Osc.1
Osc.2
Osc.3
Osc.4
R2
R2
R2
R2
–
–
–
–
3800
65
18
–
–
–
–
kΩ
kΩ
kΩ
kΩ
5.0
14
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
R
f
XTAL1
XTAL2
C1
V
g
R
2
C2
i
i
1
m
Figure 6. Equivalent Circuit Diagram
600
400
f
OSC
(kHz)
200
0
0
2
4
6
RC (µs)
Figure 7. Frequency as a Function of RC
SWITCHING
LEVEL
PDR
HYSTERESIS
SUPPLY VOLTAGE
POWER-ON RESET
(INTERNAL)
OSCILLATOR
CPU RUNNING
START-UP 1536 OSCILLATOR
TIME PERIODS DELAY
Figure 8. Power-on Reset Switching Level
15
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
V
CC
V
CC
+
8XCL410
10µF
RST
R
RST
Figure 9. Recommended Power-on Reset Circuitry
1, 2, 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
–0.5 to +6.5
UNIT
Supply voltage
V
V
All input voltages
–0.5 to V +0.5
DD
DC current into any input or output
Total power dissipation
5
mA
mW
°C
°C
°C
300
Storage temperature range
Operating ambient temperature range
–65 to +150
–40 to +85
125
Operating junction temperature
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise
SS
noted.
16
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
DC ELECTRICAL CHARACTERISTICS
T
amb
= –40°C to +85°C, V = 0V
SS
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
V
DD
Supply voltage
RAM retention voltage in power-down mode
f
(see Figure 13)
1.8
1.0
6.0
—
V
V
CLK
I
Power supply current:
Operating
DD
1
OSC 1 option
OSC 2 option
OSC 2 option
OSC 3 option
OSC 4 option
f
f
= 32kHz, V = 1.8V, T = +25°C
amb
—
—
—
—
—
50
2.5
14
16
20
µA
mA
mA
mA
mA
CLK
DD
f
= 3.58MHz, V = 3V
DD
CLK
f
f
f
= 10MHz, V = 5V
DD
CLK
CLK
CLK
= 12MHz, V = 5V
DD
= 12MHz, V = 5V
DD
2
Idle mode
OSC 1 option
OSC 2 option
OSC 2 option
OSC 3 option
OSC 4 option
= 32kHz, V = 1.8V, T = +25°C
amb
—
—
—
—
—
25
µA
mA
mA
mA
mA
CLK
DD
f
= 3.58MHz, V = 3V
1.0
5.0
7.0
8.5
CLK
DD
f
f
f
= 10MHz, V = 5V
DD
CLK
CLK
CLK
= 12MHz, V = 5V
DD
= 12MHz, V = 5V
DD
3
Power-down mode
V
DD
= 1.8V, T
= +25°C
—
10
µA
V
amb
V
V
Input low voltage
V
SS
0.3V
DD
IL
Input high voltage
0.7V
V
DD
V
IH
DD
I
OL
Output sink current, except SDA, SCL
V
= 5V, V = 0.4V
= 2.5V, V = 0.4V
OL
1.6
0.7
mA
mA
DD
OL
V
DD
I
I
Output sink current, SDA, SCL
V
= 5V, V = 0.4V
3.0
mA
OL1
DD
OL
Output source current (push-pull options only)
V
= 5V, V = V – 0.4V
1.6
0.7
mA
mA
OH
DD
OH
DD
V
DD
= 2.5V, V = V – 0.4V
OH DD
I
I
I
Logical 0 input current, ports 1, 2, 3
V
= 5V,V = 0.4V
= 2.5V,V = 0.4V
IN
–100
–50
µA
µA
IL
DD
IN
V
DD
Logical 1-to-0 transition current, ports 1, 2, 3
V
DD
= 5V, V = V /2
–1.0
–500
mA
µA
TL
LI
IN
DD
V
= 2.5V, V = V /2
DD
IN
DD
Input leakage current, port 0, EA
Internal reset pull-down resistor
V
< V < V
DD
±10
µA
kΩ
SS
I
R
10
200
RST
NOTES:
1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10ns; V = V , V = V ; XTAL2
r
f
IL
SS
IH
DD
not connected; EA = RST = Port 0 = V ; all open drain outputs connected to V
.
DD
SS
2. The idle supply current is measured with all output pins disconnected; XTAL1 driven with t = t = 10ns; V = V , V = V ; XTAL2 not
r
f
IL
SS
IH
DD
connected; EA = Port 0 = V ; RST = V ; all open drain outputs connected to V .
DD
SS
SS
3. The power-down current is measured with all output pins disconnected; XTAL1 not connected; EA = port 0 = V ; RST = V ; all open-drain
DD
SS
outputs connected to V
.
SS
4. The RC-oscillator is not implemented in this version.
5. Circuits with “power-on reset” option “OFF” are tested at V
= 1.8V, with option “ON” (typically 1.3V) are tested at V
= 2.3V.
DDMIN
DDMIN
17
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
1.8
1.6
1.4
1.2
1.0
I
(mA)
DD
1.2MHz
0.8
0.6
0.4
0.2
0
32kHz
0
1
2
3
4
5
6
V
MIN = 1.8V
DD
V
DD
(V)
Typical Operating Current Versus Supply and Frequency (32kHz–1.2MHz) at +25°C
18
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
AC ELECTRICAL CHARACTERISTICS
1, 2
T
amb
= –40°C to +85°C, V = 0V
SS
12MHz CLOCK
VARIABLE CLOCK
SYMBOL
Program Memory
1/t
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
Oscillator frequency
0
20
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLCL
t
t
t
t
t
t
t
t
t
t
t
10
10
10
10
10
10
10
10
10
10
10
ALE pulse width
127
43
2t
–40
LL
CLCL
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
t
t
–40
AL
CLCL
CLCL
48
–35
LA
233
125
4t
3t
–100
LIV
LC
CLCL
58
t
–25
CLCL
PSEN pulse width
215
3t
–35
CC
CIV
CI
CLCL
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
–125
CLCL
0
0
0
63
t
–20
CIF
AVI
AFC
CLCL
302
5t
–115
CLCL
0
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
11
12
RD pulse width
400
400
48
6t
–100
–100
–35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RR
CLCL
CLCL
CLCL
WR pulse width
6t
t
WW
LA
11, 12
11
Address hold time after ALE
RD low to valid data in
Data float after RD
–
–
250
97
5t
–165
RD
CLCL
11
2t
–70
DFR
LD
CLCL
11
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data valid to WR
517
585
300
8t
9t
–150
–165
CLCL
CLCL
11
AD
11, 12
11, 12
12
200
203
23
3t
–50
3t
+50
LW
CLCL
CLCL
4t
–130
–60
AW
CLCL
CLCL
CLCL
CLCL
t
DWX
DW
WD
AFR
WHLH
11
433
33
–
7t
t
–150
–50
–
12
Data hold after WR
3
11
RD low to address float
12
12
11, 12
RD or WR high to ALE high
43
123
t
–40
t
+40
CLCL
CLCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 50pF, load capacitance for all other outputs = 40pF.
3. Interfacing the 8XCL410 to devices with float time up to 75ns is permitted. This limited bus connection will not cause damage to port 0
drivers.
19
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
t
LL
ALE
t
CC
t
AL
t
LC
t
LIV
PSEN
t
CIV
t
LA
t
CIF
t
AFC
t
CI
A0–A7
INSTR IN
A0–A7
PORT 0
PORT 2
t
AVI
A8–A15
A8–A15
Figure 10. External Program Memory Read Cycle
ALE
PSEN
RD
t
WHLH
t
LD
t
t
LW
RR
t
DFR
t
AL
t
LA
t
AFR
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA IN
A0–A7 FROM PCL
INSTR IN
t
t
RD
AW
t
AD
P2.0–P2.7 OR A8–A15 FROM DPH
A8–A15 FROM PCH
Figure 11. External Data Memory Read Cycle
20
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
ALE
t
WHLH
PSEN
t
t
WW
LW
WR
t
DWX
t
WD
t
AL
t
LA
t
DW
A0–A7
FROM RI OR DPL
PORT 0
PORT 2
DATA OUT
A0–A7 FROM PCL
INSTR IN
t
AW
P2.0–P2.7 OR A8–A15 FROM DPH
A8–A15 FROM PCH
Figure 12. External Data Memory Write Cycle
0.7 V
0.7 V
DD
DD
DD
0.9 V
0.4 V
DD
TEST POINTS
DD
0.3 V
0.3 V
DD
Figure 13. AC Testing Input Waveform
I
TL
500µA
–I
IL
I
IL
100µA
0
V
/2
V
DD
DD
Figure 14. Input Current
21
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
16
12
8
100
10
I (mA)
DD
f (MHz)
1
12MHz
4
0.1
8MHz
3.58MHz
0
0.01
1
2
3
4
5
6
0
1
2
3
4
5
6
7
V
(V)
DD
NOTE: Below 32kHz, clock has to be supplied externally.
V
(V)
DD
Figure 16. Typical Operating Current as a Function of
Figure 15. Frequency Operating Range
Frequency and V , T
= 25°C
DD amb
8
6
5
4
3
2
1
f
IDLE
(mA)
I
PD
4
2
(µA)
12MHz
8MHz
3.58MHz
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
V
(V)
V
(V)
DD
DD
Figure 17. Typical Idle Current as a Function of
Frequency and V , T = 25°C
Figure 18. Typical Power-Down Current Vs.
o
Frequency and V , T
= 25 C
DD amb
DD amb
22
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
PIGGYBACK SPECIFICATION
The differences between the masked version
and the piggyback are described herein.
Features
• Full static 80C51 CPU
• Enhanced architecture with:
– non-page oriented instructions
– direct addressing
• 8-bit CPU, RAM, I/O in a single
– four eight byte RAM register banks
– stack depth up to 128 bytes
General Description
40-lead DIP
The P85CL000HFZ is a piggy-back version
with 256 bytes of RAM used for emulation of
the P83CL410 microcontroller. The
P85CL000HFZ is manufactured in an
advanced CMOS technology. The instruction
set of the P85CL000HFZ is based on that of
the 8051. The device has low power
consumption and a wide supply voltage
range. The P85CL000HFZ has two software
selectable modes of reduced activity for
further power reduction: Idle and
• Socket for up to 16k external EPROM
– multiply, divide, subtract and compare
instructions
• 256 bytes RAM, expandable externally to
64K bytes
• STOP and IDLE instructions
• Four 8-bit ports, 32 I/O lines
• Wake-up via external interrupts at port 1
• Single supply voltage of 1.8V to 6.0V
• On-chip oscillator (option: oscillator 4)
• Very low current consumption
• Two 16-bit timer/event counters
• External memory expandable up to 128K,
external ROM up to 64K and/or RAM up to
64K
Power-down. For timing and AC/DC
characteristics, please refer to the P83CL410
specifications.
• Thirteen source, thirteen vector interrupt
• Operating temperature range:
–40 to +85°C
structure with two priority levels
• Full duplex serial port (UART)
2
• I C-bus interface for serial transfer on two
lines
STANDARD PIGGYBACK
Types: P85CL000HFZ
Emulation for: P83CL410, P80CL51
List of differences between masked microcontroller and corresponding piggyback:
PARAMETER
RAM size
MASKED CONTROLLER
PIGGYBACK
128
256
ROM size
4k
EPROM size dependent (max 16k)
Port option
1, 2, 3
1
Oscillator option
Mech. dimensions
Current cons.
Voltage range
ESD
Osc. 1, 2, 3, 4, RC
Osc. 4
Standard Dual In-Line, Small Outline
See SOT158A
I
I (OSC. 4) + I
DD EPROM
DD
full
full, limited by EPROM
specification
not tested (different package)
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
23
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
24
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
VSO40: plastic very small outline package; 40 leads
SOT158-1
25
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
26
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
NOTES
27
1995 Jan 20
Philips Semiconductors
Product specification
Low voltage/low power single-chip
8-bit microcontroller with I2C
80CL410/83CL410
DEFINITIONS
Data Sheet Identification
Product Status
Definition
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Objective Specification
Formative or in Design
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Preliminary Specification
Product Specification
Preproduction Product
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. PhilipsSemiconductorsmakesnorepresentationorwarrantythatsuchapplicationswillbesuitableforthespecifiedusewithoutfurthertesting
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
orsystemswheremalfunctionofaPhilipsSemiconductorsandPhilipsElectronicsNorthAmericaCorporationProductcanreasonablybeexpected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1995
All rights reserved. Printed in U.S.A.
Telephone 800-234-7381
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