P83C528EBP [NXP]
8-bit microcontrollers; 8位微控制器
| 型号： | P83C528EBP |
| 厂家： | 
NXP |
| 描述： | 8-bit microcontrollers |
| 文件： | 总76页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
P83C524; P80C528; P83C528
8-bit microcontrollers
1997 Dec 15
Product specification
File under Integrated Circuits, IC20
Philips Semiconductors
Product specification
P83C524; P80C528;
P83C528
8-bit microcontrollers
CONTENTS
15
IDLE AND POWER-DOWN OPERATION
15.1
15.2
15.3
15.4
Power Control Register (PCON)
Idle Mode
Power-down Mode
1
2
3
4
5
6
7
FEATURES
GENERAL DESCRIPTION
QUICK REFERENCE DATA
ORDERING INFORMATION
BLOCK DIAGRAM
Wake-up from Power-down Mode
16
OSCILLATOR CIRCUIT
RESET CIRCUIT
17
17.1
18
Power-on reset
FUNCTIONAL DIAGRAM
PINNING INFORMATION
INSTRUCTION SET
LIMITING VALUES
DC CHARACTERISTICS
AC CHARACTERISTICS
19
7.1
7.2
Pinning
Pin description
20
8
FUNCTIONAL DESCRIPTION
21
8.1
8.2
General
Instruction Set Execution
21.1
21.2
AC Characteristics 16 MHz version
AC Characteristics 24 MHz version
9
MEMORY ORGANIZATION
22
I2C CHARACTERISTICS (BIT-LEVEL)
XTAL1 CHARACTERISTICS
SERIAL PORT CHARACTERISTICS
TIMING DIAGRAMS
9.1
9.2
9.3
Program Memory
Internal Data Memory
Addressing
23
24
25
10
11
I/O FACILITIES
25.1
26
Timing symbol definitions
PACKAGE OUTLINES
TIMERS/COUNTERS
11.1
Timer 0 and Timer 1
27
SOLDERING
11.1.1
11.1.2
11.2
Timer/Counter Mode Control register (TMOD)
Timer/Counter Control Register (TCON)
Timer 2
27.1
27.2
Introduction
DIP
11.2.1
11.2.2
11.2.3
11.2.4
11.3
Timer 2 Control Register (T2CON)
Capture Mode
Automatic Reload Mode
Baud Rate Generator Mode
Watchdog Timer T3
27.2.1
27.2.2
27.3
27.3.1
27.3.2
27.3.3
Soldering by dipping or by wave
Repairing soldered joints
PLCC and QFP
Reflow soldering
Wave soldering
Repairing soldered joints
12
SERIAL PORT (UART)
28
29
30
DEFINITIONS
12.1
12.2
Serial Port Control Register (SCON)
SM0 and SM1 operating modes (SCON)
BIT-LEVEL I2C INTERFACE
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
13
13.1
13.2
I2C Interrupt Register (S1INT)
Single-bit Data Register with I2C Auto-clock
(S1BIT)
13.2.1
13.3
Reading or Writing the S1BIT SFR
Control and Status Register for the I2C-bus
(S1SCS)
14
INTERRUPT SYSTEM
14.1
14.2
14.3
Interrupt Enable Register (IE)
Interrupt Priority Register (IP)
Interrupt Vectors
1997 Dec 15
2
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
1
FEATURES
2
GENERAL DESCRIPTION
• 80C51 CPU
The P83C524 and P83C528 single-chip 8-bit
microcontrollers are manufactured in an advanced CMOS
process and are derivatives of the PCB80C51
microcontroller family. These devices provide architectural
enhancements that make them applicable in a variety of
applications in general control systems, especially in those
systems which need a large ROM and RAM capacity on
chip.
• 32 kbytes on-chip ROM, expandable externally to
64 kbytes Program Memory address space
• P83C524:
– 16 kbytes on-chip ROM, expandable externally from
32 kbytes to 64 kbytes Program Memory address
space (address space 16 k to 32 k not usable)
• P80C528:
The P83C524 and P83C528 contain a non-volatile
16 k × 8 respectively 32 k × 8 read-only program memory,
a volatile 512 bytes × 8 read/write data memory, four 8-bit
I/O ports, two 16-bit timer/event counters (identical to the
timers of the 80C51), a 16-bit timer (identical to the timer 2
of the 8052), a multi-source, two-priority-level, nested
interrupt structure, two serial interfaces (UART and
bit-level I2C-bus), a watchdog timer (WDT) with a separate
oscillator, an on-chip oscillator and timing circuits. For
systems that require extra capability, the P83C524 and
P83C528 can be expanded using standard TTL
– ROMless version of P83C528
• P83C528:
– 32 kbytes on-chip ROM, expandable externally from
32 kbytes to 64 kbytes Program Memory address
space
• EPROM versions are available: see separate data sheet
P87C524 and P87C528
• 512 bytes on-chip RAM, expandable externally to
64 kbytes Data Memory address space
compatible memories and logic.
• Four 8-bit I/O ports
The device also functions as an arithmetic processor
having facilities for both binary and BCD arithmetic plus
bit-handling capabilities. The P83C524 and P83C528
have the same instruction set as the PCB80C51 which
consists of over 100 instructions: 49 one-byte, 46 two-byte
and 16 three-byte. With a 16 MHz crystal, 58% of the
instructions are executed in 750 ns and 40% in 1.5 µs.
Multiply and divide instructions require 3 µs.
• Full-duplex UART compatible with the standard 80C51
and the 8052
• Two standard 16-bit timer/counters
• An additional 16-bit timer (functionally equivalent to the
timer 2 of the 8052)
• On-chip Watchdog Timer (WDT) with an own oscillator
• Bit-level I2C-bus hardware serial I/O Port
• 7-source and 7-vector interrupt structure with 2 priority
levels
• Up to 3 external interrupt request inputs
• Two programmable power reduction modes (Idle and
Power-down)
• Termination of Idle mode by any interrupt, external or
WDT (watchdog) reset
• Wake-up from Power-down by external interrupt,
external or WDT reset
• ROM code protection
• XTAL frequency range: 3.5 MHz to 16 MHz and
3.5 MHz to 24 MHz
• All packaging pin-outs fully compatible to the standard
8051/8052.
1997 Dec 15
3
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
3
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITION
MIN.
MAX.
UNIT
P83C524, P80C528, P83C528 (see characteristics tables for extended temperature range versions)
VDD
IDD
supply voltage range
4.5
−
5.5
33
V
supply current: operating modes 16 MHz
supply current: Idle mode 16 MHz
supply current: Power-down mode
total power dissipation
VDD = 5.5 V, fCLK = 16 MHz
VDD = 5.5 V, fCLK = 16 MHz
2V ≤ VPD ≤ VDD max.
mA
mA
µA
W
IID
−
6
IPD
−
100
1
Ptot
Tstg
Tamb
−
storage temperature range
−65
−40
+150
+85
°C
operating ambient temperature range
°C
4
ORDERING INFORMATION
EXTENDED
PACKAGE
TEMPERATURE
RANGE (°C)
FREQ.
(MHZ)
TYPE NUMBER
NAME
DESCRIPTION
VERSION
ROMless
P80C528EBP
P80C528EFP
P80C528IBP
P80C528IFP
P80C528EBA
P80C528EFA
P80C528IBA
P80C528IFA
P80C528EBB
P80C528EFB
P80C528IBB
P80C528IFB
DIP40
plastic dual in-line package;
40 leads (600 mil)
SOT129-1 0 to +70
3.5 to 16
3.5 to 24
3.5 to 16
3.5 to 24
3.5 to 16
3.5 to 24
−40 to +85
0 to +70
−40 to +85
PLCC44 plastic leaded chip carrier; 44 leads
SOT187-2 0 to +70
−40 to +85
0 to +70
−40 to +85
QFP44
DIP40
plastic quad flat package;
44 leads (lead length 1.3 mm);
body 10 × 10 × 1.75 mm
SOT307-2 0 to +70
−40 to +85
0 to +70
−40 to +85
ROM
P83C524EBP
P83C524EFP
P83C524IBP
P83C524IFP
P83C524EBA
P83C524EFA
P83C524IBA
P83C524IFA
P83C524EBB
P83C524EFB
P83C524IBB
P83C524IFB
plastic dual in-line package;
40 leads (600 mil)
SOT129-1 0 to +70
−40 to +85
3.5 to 16
3.5 to 24
3.5 to 16
3.5 to 24
3.5 to 16
3.5 to 24
0 to +70
−40 to +85
PLCC44 plastic leaded chip carrier; 44 leads
SOT187-2 0 to +70
−40 to +85
0 to +70
−40 to +85
QFP44
plastic quad flat package;
44 leads (lead length 1.3 mm);
body 10 × 10 × 1.75 mm
SOT307-2 0 to +70
−40 to +85
0 to +70
−40 to +85
1997 Dec 15
4
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
PACKAGE
EXTENDED
TYPE NUMBER
TEMPERATURE
RANGE (°C)
FREQ.
(MHZ)
NAME
DESCRIPTION
VERSION
P83C528EBP
P83C528EFP
P83C528IBP
P83C528IFP
P83C528EBA
P83C528EFA
P83C528IBA
P83C528IFA
P83C528EBB
P83C528EFB
P83C528IBB
P83C528IFB
DIP40
plastic dual in-line package;
40 leads (600 mil)
SOT129-1 0 to +70
−40 to +85
3.5 to 16
3.5 to 24
3.5 to 16
3.5 to 24
3.5 to 16
3.5 to 24
0 to +70
−40 to +85
PLCC44 plastic leaded chip carrier; 44 leads
SOT187-2 0 to +70
−40 to +85
0 to +70
−40 to +85
QFP44
plastic quad flat package;
44 leads (lead length 1.3 mm);
body 10 × 10 × 1.75 mm
SOT307-2 0 to +70
−40 to +85
0 to +70
−40 to +85
1997 Dec 15
5
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frequency
reference
counters
T0 T1
T2
T2EX
XTAL2 XTAL1
RST
AUX - RAM
RAM
PROGRAM
OSCILLATOR
AND
DATA
MEMORY
(256 x 8 RAM)
DATA
MEMORY
(256 x 8 RAM)
TWO 16-BIT
TIMER/EVENT
COUNTERS
MEMORY
16-BIT
TIMER
WATCHDOG
TIMER
(32 K x 8 ROM
TIMING
or 16 K x 8 ROM)
CPU
P83C524
P80C528
P83C528
PROGRAMMABLE
SERIAL PORT
FULL DUPLEX UART
SYNCHRONOUS
SHIFT
BIT-LEVEL
2
64K-BYTE BUS
EXPANSION
CONTROL
PROGRAMMABLE I/O
I
C
INTERFACE
internal
interrupts
MBC455
control
parallel ports,
address/data bus
and I/O pins
serial in
shared with Port 3
serial out
INT0 INT1
external interrupts
SDA SCL
Fig.1 Block diagram.
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Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
6
FUNCTIONAL DIAGRAM
V
V
DD
RST
SS
XTAL1
XTAL2
address and
data bus
Port 0
Port 1
Port 2
EA
T2
PSEN
ALE
T2EX
P83C524
P80C528
P83C528
SCL
SDA
RXD / data
TXD / clock
INT0
INT1
alternative
functions
address bus
Port 3
T0
T1
WR
RD
MBC454 - 1
Fig.2 Functional diagram.
1997 Dec 15
7
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
7
PINNING INFORMATION
Pinning
7.1
handbook, halfpage
V
T2 P1.0
1
2
3
4
5
6
7
8
9
40
DD
T2EX P1.1
P1.2
39 P0.0 AD0
38 P0.1 AD1
37 P0.2 AD2
36 P0.3 AD3
35 P0.4 AD4
34 P0.5 AD5
33 P0.6 AD6
32 P0.7 AD7
31 EA
P1.3
P1.4
P1.5
SCL P1.6
SDA P1.7
RST
P83C524
RXD / data P3.0 10
TXD / clock P3.1 11
INT0 P3.2 12
P80C528
P83C528
30 ALE
29 PSEN
INT1 P3.3 13
T0 P3.4 14
T1 P3.5 15
WR P3.6 16
RD P3.7 17
XTAL2 18
28 P2.7 A15
27 P2.6 A14
26 P2.5 A13
25 P2.4 A12
24 P2.3 A11
23 P2.2 A10
22 P2.1 A9
21 P2.0 A8
XTAL1 19
V
20
SS
MBC453
Fig.3 Pin configuration DIP40 (SOT129-1).
1997 Dec 15
8
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
P1.5
SCL / P1.6
SDA / P1.7
7
8
39 P0.4 / AD4
38 P0.5 / AD5
33
1
9
37 P0.6 / AD6
32
2
RST 10
36 P0.7 / AD7
31
3
RXD / data / P3.0 11
35 EA
4
30
P83C524
P80C528
P83C528
n.c. 12
34 n.c.
29
5
TXD / clock / P3.1 13
33 ALE
6
28
INT0 / P3.2 14
32 PSEN
7
27
15
31 P2.7 / A15
INT1 / P3.3
8
26
T0 / P3.4 16
30 P2.6 / A14
9
25
29 P2.5 / A13
T1 / P3.5 17
24
10
11
23
MBC452
Fig.4 Pin configuration QFP44 (SOT307-2).
1997 Dec 15
9
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
P1.5
SCL / P1.6
SDA / P1.7
7
8
9
39 P0.4 / AD4
38 P0.5 / AD5
37 P0.6 / AD6
36 P0.7 / AD7
35 EA
RST 10
RXD / data / P3.0 11
n.c. 12
P83C524
P80C528
34 n.c.
P83C528
TXD / clock / P3.1 13
INT0 / P3.2 14
33 ALE
32 PSEN
15
31 P2.7 / A15
30 P2.6 / A14
29 P2.5 / A13
INT1 / P3.3
T0 / P3.4 16
T1 / P3.5 17
MBC452
Fig.5 Pin configuration PLCC44 (SOT187-2).
1997 Dec 15
10
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
7.2
Pin description
Table 1 Pin description for P83C524, P80C528 and P83C528; see note 1
PIN
SYMBOL
DESCRIPTION
SOT 129-1 SOT 187-2 SOT 307-2
P1.0−P1.7 1 to 8
2−9
1−3,
40−44
Port 1: 8-bit quasi-bidirectional I/O Port. Port 1 can sink/source
one TTL (= 4 LSTTL) input. It can drive CMOS inputs without
external pull-ups, except P1.6 and P1.7 which have open drain
outputs.
(1 n.c.)
(39 n.c.)
Port 1 alternative functions:
T2
1
2
2
3
40
41
P1.0
Timer/event counter 2 external event counter input
(falling edge triggered)
T2EX
P1.1
Timer/event counter 2 capture/reload trigger or external
interrupt 2 input (falling edge triggered)
SCL
SDA
RST
7
8
9
8
2
3
4
P1.6
P1.7
I2C-bus Serial Port clock line
I2C-bus Serial Port data line.
9
10
RESET: a HIGH level on this pin for two machine cycles while the
oscillator is running, resets the device. An internal pull-down
resistor permits power-on reset using only a capacitor connected
to VDD. After a WDT overflow this pin is pulled HIGH while the
internal reset signal is active.
P3.0−P3.7 10−17
11, 13−19 5, 7−13
Port 3: 8-bit quasi-bidirectional I/O Port with internal pull-ups.
(12 n.c.)
(6 n.c.)
Port 3 can sink/source one TTL (= 4 LSTTL) input. It can drive
CMOS inputs without external pull-ups.
Port 3 alternative functions:
RXD/data 10
TXD/clock 11
11
13
14
15
5
7
8
9
P3.0
P3.1
P3.2
P3.3
Serial Port data input (asynchronous) or data
input/output (synchronous)
Serial Port data output (asynchronous) or clock output
(synchronous)
INT0
INT1
12
13
external interrupt 0 or gate control input for timer/event
counter 0
external interrupt 1 or gate control input for timer/event
counter 1
T0
14
15
16
17
16
17
18
19
10
11
12
13
P3.4
P3.5
P3.6
P3.7
external input for timer/event counter 0
external input for timer/event counter 1
external data memory write strobe
external data memory read strobe.
T1
WR
RD
The generation or use of a Port 3 pin as an alternative function is
carried out automatically by the P83C528 provided the associated
Special Function Register (SFR) bit is set HIGH.
XTAL2
18
20
14
Crystal input 2: output of the inverting amplifier that forms the
oscillator. This pin left open-circuit when an external oscillator
clock is used (see Figures 22 and 23).
1997 Dec 15
11
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
PIN
SYMBOL
DESCRIPTION
SOT 129-1 SOT 187-2 SOT 307-2
XTAL1
19
21
15
Crystal input 1: input to the inverting amplifier that forms the
oscillator, and input to the internal clock generator. Receives the
external oscillator clock signal when an external oscillator is used
(see Figures 22 and 23).
VSS
20
22
16
Ground: circuit ground potential.
P2.0-P2.7 21−28
24−31
18−25
Port 2: 8-bit quasi-bidirectional I/O Port with internal pull-ups.
During access to external memories (RAM/ROM) that use 16-bit
addresses (MOVX @DPTR) Port 2 emits the high-order address
byte (A8 to A15). Port 2 can sink/source one TTL (= 4 LSTTL)
input. It can drive CMOS inputs without external pull-ups.
(23 n.c.)
(17 n.c.)
PSEN
29
32
26
Program Store Enable output: read strobe to the external
program memory via Port 0 and Port 2. It is activated twice each
machine cycle during fetches from external program memory.
When executing out of external program memory two activations of
PSEN are skipped during each access to external data memory.
PSEN is not activated (remains HIGH) during no fetches from
external program memory. PSEN can sink/source 8 LSTTL inputs.
It can drive CMOS inputs without external pull-ups.
ALE
EA
30
31
33
27
Address Latch Enable output: latches the LOW byte of the
address during access to external memory in normal operation. It
is activated every six oscillator periods except during an external
data memory access. ALE can sink/source 8 LSTTL inputs. It can
drive CMOS inputs without an external pull-up.
35
29
External Access input: when during RESET, EA is held at a TTL
HIGH level, the CPU executes out of the internal program ROM,
provided the program counter is less than 32768. When EA is held
at a TTL LOW level during RESET, the CPU executes out of
external program memory via Port 0 and Port 2. EA is not allowed
to float.
(34 n.c.)
(28 n.c.)
P0.0-P0.7 32−39
36−43
30−37
Port 0: 8-bit open drain bidirectional I/O Port. It is also the
multiplexed low-order address and data bus during accesses to
external memory (AD0 to AD7). During these accesses internal
pull-ups are activated. Port 0 can sink/source 8 LSTTL inputs.
VDD
40
44
38
Power supply: +5 V power supply pin during normal operation,
Idle mode and Power-down mode.
Note
1. To avoid a 'latch-up' effect at power-on, the voltage on any pin (at any time) must not be higher than VDD +0.5 V or
lower than VSS −0.5 V respectively.
1997 Dec 15
12
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
8
FUNCTIONAL DESCRIPTION
General
9.1
Program Memory
The program memory address space of the P83C528
comprises an internal and an external memory portion.
The P83C528 has 32 kbyte of program memory on-chip.
The program memory can be externally expanded up to 64
kbyte. If the EA pin is held HIGH, the P83C528 executes
out of the internal program memory unless the address
exceeds 7FFFH. Locations 8000H through 0FFFFH are
then fetched from the external program memory. If the EA
pin is held LOW, the P83C528 fetches all instructions from
the external program memory. Fig.6 illustrates the
program memory address space.
8.1
The P83C524, P80C528 and P83C528 are stand-alone
high-performance microcontrollers designed for use in real
time applications such as instrumentation, industrial
control, medium to high-end consumer applications and
specific automotive control applications.
In addition to the 80C51 standard functions, the devices
provide a number of dedicated hardware functions for
these applications. The P83C524 and P83C528 are
control-oriented CPUs with on-chip program and data
memory. They can be extended with external program
memory up to 64 kbytes. They can also access up to
64 kbytes of external data memory. For systems requiring
extra capability, the P83C524 and P83C528 can be
expanded using standard memories and peripherals.
By setting a mask programmable security bit the ROM
content is protected i.e. it cannot be read out by any test
mode or by any instruction in the external program
memory space. The MOVC instructions are the only ones
which have access to program code in the internal or
external program memory. The EA input is latched during
RESET and is 'don't care' after RESET. This
implementation prevents reading from internal program
code by switching from external program memory to
internal program memory during MOVC instruction or an
instruction that handles immediate data. Table 2 lists the
access to the internal and external program memory by the
MOVC instructions when the security bit has been set to a
logical one. If the security bit has been set to a logical 0
there are no restrictions for the MOVC instructions.
The P83C524, P80C528 and P83C528 have two software
selectable modes of reduced activity for further power
reduction: Idle and Power-down. The Idle mode freezes
the CPU while allowing the RAM, timers, serial ports and
interrupt system to continue functioning. The Power-down
mode saves the RAM contents but freezes the oscillator
causing all other chip functions to be inoperative except
the WDT if it is enabled. The Power-down mode can be
terminated by an external reset, a WDT overflow, and in
addition, by either of the two external interrupts.
8.2
Instruction Set Execution
64 K
handbook, halfpage
The P83C524, P80C528 and P83C528 use the powerful
instruction set of the 80C51. Additional SFRs are
incorporated to control the on-chip peripherals. The
instruction set consists of 49 single-byte, 46 two-byte and
16 three-byte instructions. When using a 16 MHz
oscillator, 64 instructions execute in 750 ns and 45
instructions execute in 1.5 s. Multiply and divide
instructions execute in 3 µs (see Chapter 18).
EXTERNAL
32768
9
MEMORY ORGANIZATION
32767
32767
The central processing unit (CPU) manipulates operands
in three memory spaces; these are the 64 kbyte external
data memory (of which the lower 256 bytes reside in the
internal AUX-RAM), 512 byte internal data memory
(consisting of 256 bytes standard RAM and 256 bytes
AUX-RAM) and the 64 kbyte internal and external program
memory.
INTERNAL
(EA = 1)
EXTERNAL
((EEAA == 00))
(EA = 1)
16383 (1)
0
0
MBC456 - 1
PROGRAM MEMORY
(1) Only for P83C524.
Fig.6 Program Memory Address Space.
1997 Dec 15
13
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
Table 2 Internal and external program memory access with security bit set
ACCESS TO INTERNAL
INSTRUCTION
ACCESS TO EXTERNAL
PROGRAM MEMORY
PROGRAM MEMORY
MOVC in internal program memory
MOVC in external program memory
YES
NO
YES
YES
An access to external data memory locations higher than
255 will be performed with the MOVX DPTR instructions in
the same way as in the 80C51 structure, i.e. with P0 and
P2 as data/address bus and P3.6 and P3.7 as write and
read timing signals (see Figures 7, 8, 9 and 10). Note that
the external data memory cannot be accessed with R0 and
R1 as address pointer.
9.2
Internal Data Memory
The internal data memory is divided into three physically
separated parts: 256 byte of RAM, 256 byte of AUX-RAM,
and a 128 byte special function area (SFR). These parts
can be addressed as follows (see Table 3 and Fig.11):
• RAM 0 to 127 can be addressed directly and indirectly
as in the 80C51. Address pointers are R0 and R1 of the
selected register bank.
Fig.11 shows the internal and external data memory
address space. Fig.12 shows the Special Function
Register (SFR) memory map. Four 8-bit register banks
occupy locations 0 through 31 in the lower RAM area. Only
one of these banks may be enabled at a time. The next 16
bytes, locations 32 through 47, contain 128 directly
addressable bit locations.
• RAM 128 to 255 can only be addressed indirectly.
Address pointers are R0 and R1 of the selected register
bank.
• AUX-RAM 0 to 255 is indirectly addressable as the
external data memory locations 0 to 255 with the MOVX
instructions. Address pointers are R0 and R1 of the
selected register bank and DPTR. When executing from
internal program memory, an access to AUX-RAM 0 to
255 will not affect the ports P0, P2, P3.6 and P3.7.
The stack can be located anywhere in the internal 256 byte
RAM. The stack depth is only limited by the available
internal RAM space of 256 bytes. All registers except the
Program Counter and the four 8-bit register banks reside
in the SFR address space.
• the SFRs can only be addressed directly in the address
range from 128 to 255.
Table 3 Internal data memory access
LOCATION
ADDRESSED
RAM 0 to 127
DIRECT and INDIRECT
INDIRECT only
RAM 128 to 255
AUX-RAM 0 to 255
INDIRECT only with MOVX
DIRECT only
Special Function Register (SFR) 128 to 255
1997 Dec 15
14
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
one machine cycle
S3 S4
one machine cycle
S1
S2
S5
S6
S1
S2
S3
S4
S5
S6
ALE
PSEN
RD
WR
P2
P2 OUT
P0
P0 OUT
MBC457
a. Without a MOVX.
cycle 1
cycle 2
S3
S1
S2
S3
S4
S5
S6
S1
S2
S4
S5
S6
ALE
PSEN
RD
WR
P2
P2 OUT
P0
P0 OUT
MBC458
b. With a MOVX to the AUX-RAM (read and write).
Fig.7 Internal program memory execution.
15
1997 Dec 15
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
cycle 1
cycle 2
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
ALE
PSEN
RD
WR
P2
P2 OUT
P2 OUT
P0 OUT
DPH OUT
DPL
OUT
DATA
IN
P0
MBC459
a. With a MOVX to the External Data Memory (read).
cycle 1
cycle 2
S3
S1
S2
S3
S4
S5
S6
S1
S2
S4
S5
S6
ALE
PSEN
RD
WR
P2
P2 OUT
P2 OUT
P0 OUT
DPH OUT
DPL
OUT
P0
DATA OUT
MBC460
b. With a MOVX to the External Data Memory (write).
Fig.8 Internal program memory execution (continued).
16
1997 Dec 15
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
one machine cycle
one machine cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
ALE
PSEN
RD
WR
P2
P0
PCH OUT
PCH OUT
PCH OUT
PCH OUT
PCH OUT
INST
IN
PCL
OUT
INST
PCL
OUT
INST
IN
PCL
OUT
INST
PCL
OUT
IN
IN
MBC461
a. Without a MOVX.
cycle 1
cycle 2
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
ALE
PSEN
RD
WR
P2
P0
PCH OUT
PCH OUT
ADDRH OUT
PCH OUT
INST
IN
PCL
OUT
INST
IN
ADDRL
OUT
PCL
OUT
(read)
P2
P0
PCH OUT
PCH OUT
ADDRH OUT
PCH OUT
INST
IN
PCL
OUT
INST
IN
ADDRL
OUT
PCL
OUT
DATA OUT
(write)
MBC462
b. With a MOVX to the AUX-RAM (read and write).
Fig.9 External program memory execution.
1997 Dec 15
17
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
cycle 1
cycle 2
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
ALE
PSEN
RD
WR
P2
PCH OUT
PCH OUT
DPH OUT
PCH OUT
INST
IN
PCL
OUT
INST
IN
DPL
OUT
DATA
IN
PCL
OUT
P0
MBC463
a. With a MOVX to the External Data Memory (read).
cycle 1
cycle 2
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
ALE
PSEN
RD
WR
P2
P0
PCH OUT
PCH OUT
DPH OUT
PCH OUT
INST
IN
PCL
OUT
INST
IN
DPL
OUT
PCL
OUT
DATA OUT
MBC464
b. With a MOVX to the External Data Memory (write).
Fig.10 External program memory execution (continued).
18
1997 Dec 15
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
SHARED
ADDRESS LOCATION
FF
FF
FF
FFFF
UPPER
128 BYTES
INTERNAL
RAM
SPECIAL
FUNCTION
REGISTERS
80
7F
80
EXTERNAL
DATA
MEMORY
AUX - RAM
256 BYTES
LOWER
128 BYTES
INTERNAL
RAM
00
00
0100
DATA MEMORY
register
indirect
addressing
direct byte
addressing
MBC466 - 1
Fig.11 Internal and external data memory address space.
1997 Dec 15
19
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
REGISTER
MNEMONIC
BIT MNEMONIC /
BIT ADDRESS (HEX)
DIRECT BYTE
ADDRESS (HEX)
T3
B
FFH
F7
E7
F6
E6
F5
E5
F4
E4
F3
E3
F2
E2
F1
E1
F0
E0
F0H
E0H
ACC
S1INT
S1BIT
DAH
D9H
SDI/
SDO
DF
SCI/
SCO
DE
CLH
DO
BB
DC
RBF
DB
WBF
DA
STR
D9
ENS
D8
S1SCS
PSW
D8H
D0H
CY
D7
AC
D6
FO
D5
RSI
D4
RSO
D3
OV
D2
FI
D1
P
D0
TH2
TL2
CDH
CCH
CBH
CAH
RCAP2H
RCAP2L
TF2
CF
EXF2 RCLK TCLK EXEN2 TR2
C/T2 CP/RL2
CE
CD
CC
CB
CA
T2CON
C8H
C9
C8
- - -
BF
PS1
BE
PT2
BD
PS
BC
PT1
BB
PX1
BA
PT0
B9
PX0
B8
IP
B8H
B0H
P3
B7
B6
B5
B4
B3
B2
B1
B0
EA
AF
ES1
AE
ET2
AD
ES
AC
ET1
AB
EX1
AA
ET0
A9
EX0
A8
IE
A8H
A5H
WDCON
P2
A7
A6
A5
A4
A3
A2
A1
A0
A0H
SBUF
SCON
99H
98H
SM0
9F
SM1
9E
SM2
9D
REN
9C
TB8
9B
RB8
9A
TI
99
RI
98
P1
97
96
95
94
93
92
91
90
90H
TH1
TH0
8DH
8CH
8BH
8AH
89H
TL1
TL0
TMOD
TF1
8F
TR1
8E
TF0
8D
TR0
8C
IE1
8B
IT1
8A
IE0
89
IT0
88
TCON
PCON
88H
87H
DPH
DPL
SP
83H
82H
81H
P0
87
86
85
84
83
82
81
80
80H
MBC465 - 1
Fig.12 Special Function Register (SFR) memory map.
20
1997 Dec 15
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
9.3
Addressing
The P83C528 has five modes for addressing:
• Register
• Direct
• Register-Indirect
• Immediate
• Base-Register plus Index-Register-Indirect.
The first three methods can be used for addressing
destination operands. Most instructions have a
'destination/source' field that specifies the data type,
addressing methods and operands involved. For
operations other than MOVs, the destination operand is
also a source operand.
Access to memory addresses is as follows:
• Register in one of the four 8-bit register banks through
Register, Direct or Register-Indirect addressing.
• 512 bytes of internal RAM through Direct or
Register-Indirect addressing. Bytes 0-127 of internal
RAM may be addressed directly/indirectly. Bytes
128-255 of internal RAM share their address location
with the SFRs and so may only be addressed indirectly
as data RAM. Bytes 0-255 of AUX-RAM can only be
addressed indirectly via MOVX.
• SFR through Direct addressing at address locations
128-255.
• External data memory through Register-Indirect
addressing.
• Program memory look-up tables through Base-Register
plus Index-Register-Indirect addressing.
1997 Dec 15
21
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
• Port 2: provides the high-order address bus when
expanding the P83C528 with external program memory
and/or external data memory.
10 I/O FACILITIES
The P83C528 has four 8-bit ports. Ports 0-3 are the same
as in the 80C51, with the exception of the additional
function of Port 1. Port lines P1.0 and P1.1 may be used
as inputs for Timer 2, P1.1 may also be used as an
additional (third) external interrupt request input. Port lines
P1.6 and P1.7 may be selected as the SCL and SDA lines
of Serial Port SIO1 (I2C). Because the I2C-bus may be
active while the device is disconnected from VDD, these
pins are provided with open drain drivers. Pins P1.6 and
P1.7 do not have pull-up devices when used as ports.
• Port 3: pins can be configured individually to provide:
external interrupt request inputs (external interrupt 0/1);
external inputs for Timer/counter 0 and
Timer/counter 1; Serial Port receiver input and
transmitter output control-signals to read and write
external data memory.
Bits which are not used for the alternative functions may be
used as normal bidirectional I/O pins. The generation or
use of a Port 1 or Port 3 pin as an alternative function is
carried out automatically by the P83C528 provided the
associated SFR bit is HIGH. Otherwise the port pin is held
at a logical LOW level.
Ports 0, 1, 2, and 3 perform the following alternative
functions:
• Port 0: provides the multiplexed low-order address and
data bus used for expanding the P83C528 with standard
memories and peripherals.
• Port 1: pins can be configured individually to provide:
external interrupt request input (external interrupt 2);
external inputs for Timer/counter 2; SCL and SDA for
the I2C interface.
+5 V
strong pull-up
h
2 oscillator
periods
p2
p3
p1
n
I/O PIN
PORT
Q
from port latch
I1
input data
read port pin
INPUT
BUFFER
MLA513
Fig.13 I/O buffers in the P83C528 (Ports 1, 2 and 3 except P1.6 and P1.7).
1997 Dec 15
22
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
When Timer 0 is in Mode 3, Timer 1 can be programmed
to operate in Modes 0, 1 or 2 but cannot set an interrupt
request flag and generate an interrupt. However, the
overflow from Timer 1 can be used to pulse the Serial Port
transmission-rate generator. With a 16 MHz crystal, the
counting frequency of these timer/counters is as follows:
11 TIMERS/COUNTERS
The P83C528 contains three 16-bit timer/counters, Timer
0, Timer 1 and Timer 2, and one 8-bit timer, the Watchdog
Timer T3. Timer 0, Timer 1 and Timer 2 may be
programmed to carry out the following functions:
• measure time intervals and pulse durations
• count events
• in the timer function, the timer is incremented at a
frequency of 1.33 MHz (oscillator frequency divided by
12).
• generate interrupt requests.
• in the counter function, the frequency handling range for
11.1 Timer 0 and Timer 1
external inputs is 0 Hz to 0.66 MHz.
Timers 0 and 1 each have a control bit in TMOD SFR that
selects the timer or counter function of the corresponding
timer. In the timer function, the register is incremented
every machine cycle. Thus, one can think of it as counting
machine cycles. Since a machine cycle consists of 12
oscillator periods, the count rate is 1⁄12 of the oscillator
frequency.
Both internal and external inputs can be gated to the timer
by a second external source for directly measuring pulse
duration.
The timers are started and stopped under software control.
Each one sets its interrupt request flag when it overflows
from all logic 1's to all logic 0's (respectively, the automatic
reload value), with the exception of Mode 3 as previously
described.
In the counter function, the register is incremented in
response to a HIGH-to-LOW transition at the
corresponding external input pin, T0 or T1. In this function,
the external input is sampled during S5P2 of every
machine cycle. When the samples show a HIGH in one
cycle and a LOW in the next cycle, the counter is
incremented. Thus, it takes two machine cycles (24
oscillator periods) to recognize a HIGH-to-LOW transition.
There are no restrictions on the duty cycle of the external
input signal, but to ensure that a given level is sampled at
least once before it changes, it should be held for at least
one full machine cycle.
Timer 0 and Timer 1 can be programmed independently to
operate in one of four modes:
Mode 0 8-bit timer/counter with divide-by-32 prescaler
Mode 1 16-bit timer/counter
Mode 2 8-bit timer/counter with automatic reload
Mode 3 Timer 0: one 8-bit timer/counter and one 8-bit
timer. Timer 1: stopped.
1997 Dec 15
23
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
11.1.1 TIMER/COUNTER MODE CONTROL REGISTER (TMOD)
Table 4 Timer/Counter Mode Control register (address 89H)
7
6
5
4
3
2
1
0
TIMER 1
TIMER 0
GATE
C/T
M1
M0
GATE
C/T
M1
M0
Table 5 Description of the TMOD bits
BIT
SYMBOL
FUNCTION
TIMER 1
7
GATE
Timer 1 gating control: when set, Timer/counter '1' is enabled only while 'INT1' pin is
HIGH and 'TR1' control bit is set. When cleared, Timer/counter '1' is enabled whenever
'TR1' control bit is set.
6
C/T
Timer or counter selector: cleared for timer operation (input from internal system
clock). Set for counter operation (input from 'T1' input pin).
5
4
M1
M0
operating mode: see Table 6.
operating mode: see Table 6.
TIMER 0
3
GATE
C/T
Timer 0 gating control: when set, Timer/counter '0' is enabled only while 'INT0' pin is
HIGH and 'TR0' control bit is set. When cleared, Timer/counter '0' is enabled whenever
'TR0' control bit is set.
2
Timer or counter selector: cleared for timer operation (input from internal system
clock). Set for counter operation (input from 'T0' input pin).
1
0
M1
M0
operating mode: see Table 6.
operating mode: see Table 6.
Table 6 TMOD M1 and M0 operating modes
M1
M0
FUNCTION
8-bit timer/counter: 'THx' with 5-bit prescaler.
0
0
1
0
1
0
16-bit timer/counter: 'THx' and 'TLx' are cascaded, there is no prescaler.
8-bit autoload timer/counter: 'THx' holds a value which is to be reloaded into 'TLx'
each time it overflows.
1
1
1
1
Timer 0: TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer controlled by Timer 1 control bits.
Timer 1: Timer/counter 1 stopped.
1997 Dec 15
24
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
11.1.2 TIMER/COUNTER CONTROL REGISTER (TCON)
Table 7 Timer/Counter Control register (address 88H)
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Table 8 Description of the TCON bits
BIT
SYMBOL
TF1
FUNCTION
7
Timer 1 overflow flag: set by hardware on timer/counter overflow. Cleared when
interrupt is processed.
6
5
TR1
TF0
Timer 1 run control bit: set/cleared by software to turn timer/counter ON/OFF.
Timer 0 overflow flag: set by hardware on timer/counter overflow. Cleared when
interrupt is processed.
4
3
TR0
IE1
Timer 0 run control bit: set/cleared by software to turn timer/counter ON/OFF.
Interrupt 1 edge flag: set by hardware when external interrupt is detected. Cleared
when interrupt is processed.
2
1
0
IT1
IE0
IT0
Interrupt 1 type control bit: set/cleared by software to specify falling edge/LOW level
triggered external interrupt.
Interrupt 0 edge flag: set by hardware when external interrupt is detected. Cleared
when interrupt is processed.
Interrupt 0 type control bit: set/cleared by software to specify falling edge/LOW level
triggered external interrupt.
1997 Dec 15
25
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
11.2 Timer 2
Timer 2 is functionally similar to the Timer 2 of the 8052AH. Timer 2 is a 16-bit timer/counter which is formed by two
SFRs, TL2 and TH2. Another pair of SFRs, RCAP2L and RCAP2H, form a 16-bit capture register or a 16-bit reload
register. Like Timer 0 and 1, Timer 2 can operate either as timer or as event counter. This is selected by bit C/T2 in the
T2CON SFR. The timer has three operating modes: 'capture', 'autoload' and 'baud rate generator', which are selected
by bits in the T2CON SFR (see Table 9).
Table 9 Timer 2 operating modes
RCLK + TCLK
CP/RL2
TR2
MODE
0
0
1
X
0
1
1
1
1
0
16-bit automatic reload
16-bit capture
X
X
baud rate generator
OFF
11.2.1 TIMER 2 CONTROL REGISTER (T2CON)
Table 10 Timer 2 Control register (address C8H)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Table 11 Description of the T2CON bits
MNEMONIC POSITION
FUNCTION
TF2
T2CON.7
T2CON.6
T2CON.5
T2CON.4
T2CON.3
Timer 2 overflow flag: set by a Timer 2 overflow and must be cleared by software. TF2
will not be set when either RCLK = 1 or TCLK = 1. When Timer 2 interrupt is enabled,
TF2 = 1 (see EXF2).
EXF2
RCLK
TCLK
EXEN2
Timer 2 external flag: set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will
cause the CPU to vector to Timer 2 interrupt routine.
Receive clock flag: when set, causes the Serial Port to use Timer 2 overflow pulses for
its receive clock in Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for
the receive clock.
Transmit clock flag: when set, causes the Serial Port to use Timer 2 overflow pulses
for its transmit clock in Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used
for the transmit clock.
Timer 2 external enable flag: when set, allows a capture or reload to occur as a result
of a negative transition on T2EX if Timer 2 is not being used to clock the Serial Port.
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2
T2CON.1
Start/stop control: a logic 1 starts Timer 2. A logic 0 stops Timer 2.
C/T2
Timer/counter select: 0 = internal timer (OSC/12). 1 = external event counter (falling
edge triggered).
CP/RL2
T2CON.0
Capture/reload flag: when set, capture will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, reloads will occur upon either Timer 2 overflows or negative
transitions at T2EX if EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored
and the timer is forced to reload upon overflow.
1997 Dec 15
26
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
11.2.2 CAPTURE MODE
11.2.4 BAUD RATE GENERATOR MODE
In the capture mode (see Fig.14) there are two options
which are selected by bit EXEN2 in T2CON. If EXEN2 = 0,
then Timer 2 is a 16-bit timer/counter which on overflow
sets bit TF2 (Timer 2 overflow bit). TF2 can be used to
generate an interrupt. If EXEN2 = 1, Timer 2 operates as
above, with the added feature that a HIGH-to-LOW
transition at the external input T2EX causes the current
value in Timer 2 registers (TL2 and TH2) to be captured
into registers RCAP2L and RCAP2H, respectively. The
HIGH-to-LOW transition of T2EX also causes bit EXF2 in
T2CON to be set. EXF2 can be used to generate an
interrupt.
The baud rate generator mode (see Fig.16) is selected by
RCLK = 1 and/or TCLK = 1 in T2CON. Overflows of either
Timer 2 or Timer 1 can be used independently for
generating baud rates for transmit and receive. The baud
rate generation by Timer 1 and/or Timer 2 is used for the
Serial Port in Mode 1 and Mode 3. The baud rate
generation mode is similar to the automatic reload mode,
in that a rollover in TH2 causes the Timer 2 registers to be
reloaded with the 16-bit value in registers RCAP2L and
RCAP2H, which are preset by software. The baud rate for
the Serial Port in Modes 1 and 3 are determined by
Timer 2's overflow rate as follows:
Timer 2 overflow rate
Baud Rate =
-------------------------------------------------------
11.2.3 AUTOMATIC RELOAD MODE
16
In the automatic reload mode (see Fig.15)there are two
options which are selected by bit EXEN2 in T2CON. If
EXEN2 = 0, then a Timer 2 overflow sets TF2 and causes
the Timer 2 registers to be reloaded with the 16-bit value
in registers RCAP2L and RCAP2H, which are preset by
software.
Timer 2 can be configured for either 'timer' or 'counter'
operation. In timer operation a prescaler divides the
oscillator frequency by 2 (by 12 in the previous modes) and
the baud rate is given by the formula:
oscillator frequency
Baud Rate =
-------------------------------------------------------------------------------------------------------
32 × [65536 – (RCAP2H,RCAP2L) ]
If EXEN2 = 1, Timer 2 operates as above, with the added
feature that a HIGH-to-LOW transition at the external input
T2EX triggers the 16-bit reload and sets EXF2.
In this mode an overflow of Timer 2 does not set TF2. If
EXEN2 = 1, a HIGH-to-LOW transition at pin T2EX sets
EXF2 and can be used to generate an interrupt.
OSC
12
C/T2 = 0
C/T2 = 1
TL2
(8 BITS)
TH2
(8 BITS)
TF2
control
TR2
T2 PIN
timer 2
interrupt
transition
detector
RCAP2L
RCAP2H
T2EX PIN
EXF2
MBC468 - 1
control
EXEN2
Fig.14 Timer 2 in capture mode.
1997 Dec 15
27
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
OSC
12
C/T2 = 0
C/T2 = 1
TL2
(8 BITS)
TH2
TF2
(8 BITS)
control
TR2
T2 PIN
timer 2
interrupt
reload
RCAP2L
RCAP2H
transition
detector
T2EX PIN
EXF2
MBC469 - 1
control
EXEN2
Fig.15 Timer 2 in automatic reload mode.
TIMER 1
overflow
2
(note: divided by 2
not by 12)
0
1
OSC
2
SMOD
RCLK
C/T2 = 0
1
0
0
TL2
(8 BITS)
TH2
(8 BITS)
C/T2 = 1
control
TR2
T2 PIN
16
RX CLOCK
1
TCLK
16
RCAP2L
EXF2
RCAP2H
transition
detector
TX CLOCK
"TIMER 2"
interrupt
(additional external
interrupt)
T2EX PIN
MBC470 - 1
control
EXEN2
Fig.16 Timer 2 in baud rate generator mode.
28
1997 Dec 15
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
inhibited to prevent timing problems due to asynchronous
increments of T3. To prevent an overflow of the WDT, the
user program has to reload T3 within periods that are
shorter than the programmed Watchdog time interval. This
time interval is determined by the 8-bit reload value that is
written into register T3.
11.3 Watchdog Timer T3
The Watchdog Timer (WDT) see Fig.17, consists of an
11-bit prescaler and an 8-bit timer formed by SFR T3. The
prescaler is incremented by an on-chip oscillator with a
fixed frequency of 1 MHz. The maximum tolerance on this
frequency is −50% and +100%. The 8-bit timer increments
every 2048 cycles of the on-chip oscillator. When a timer
overflow occurs, the microcontroller is reset and a
reset-output-pulse of 16 x 2048 cycles of the on-chip
oscillator is generated at pin RST. The internal RESET
signal is not inhibited when the external RST pin is kept
LOW by e.g. an external reset circuit. The RESET signal
drives Ports 1, 2 and 3 outputs into the High state and Port
0 into high impedance, no matter if the XTAL-clock is
running or not.
[256 – (T3 ) ] × 2048
on-chip oscillator frequency
Watchdog time interval =
------------------------------------------------------------------------
The advantages of this implementation are:
• Only an internal reset connection to the microcontroller
core
• The Power-down mode and the Watchdog (WDT)
function can be used concurrently
• The WDT also monitors the XTAL oscillator. In case of a
failure the port outputs are forced to a defined High state
The WDT is controlled by WDCON SFR with the direct
address location A5H. WDCON can be read and written by
software. A value of A5H in WDCON halts the on-chip
oscillator and clears both the prescaler and Timer T3. After
RESET, WDCON contains A5H. Every value other than
A5H in WDCON enables the WDT. When the WDT is
enabled it runs independent of the XTAL-clock.
• Interference will not disable the WDT because it is
unlikely that it will force WDCON to A5H
• Tolerances of the on-chip oscillator can be adjusted by
testing the T3 value and adapting the reload value
• The WDT can be enabled and disabled under control of
the user software. This gives the possibility to use both
the Watchdog function and the Power-down function
Timer T3 can be read on the fly. Timer T3 can be written
only if WDCON has previously been loaded with 5AH,
otherwise T3 and the prescaler are not affected. A
successful write operation to T3 also clears the prescaler
and clears WDCON. During a read or write operation
addressing T3, the output of the on-chip oscillator is
• The direct address A5H of WDCON and its disable value
A5H will not unintentionally be present at a random
location in the field of program code, except for
immediate data, because the opcode A5H is not used in
the instruction set.
IBS
8 - BIT TIMER
T3
over-flow
11 - BIT
PRESCALER
WDCON
(1)
V
DD
(1)
clear
clear
input
read clear
write
5AH
A5H
R
RST
ON - CHIP -
OSCILLATOR
V
SS
WR - T3
RD - T3
halt
RST
internal
RESET
(1)
MBC471 - 1
this signal is active if WDCON
contains this hex value
Fig.17 Watchdog Timer T3.
29
1997 Dec 15
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
In all four modes, transmission is initiated by any
instruction that uses SBUF as a destination register. In
Mode 0, reception is initiated by the condition RI = 0 and
REN = 1. Reception is initiated by incoming start bit if
REN = 1 in the other modes.
12 SERIAL PORT (UART)
The Serial Port is functionally similar to the implementation
in the 8052AH, with the possibility of two different baud
rates for receive and transmit with Timer 1 and Timer 2 as
baud rate generators. It is full duplex, meaning it can
receive and transmit simultaneously. It is also
receive-buffered, meaning it can commence reception of a
second byte before a previously received byte has been
read from the receive register. However, if the first byte still
has not been read by the time the reception of the second
byte is complete, one of the bytes will be lost. The Serial
Port receive and transmit registers are both accessed as
SBUF SFR. Writing to SBUF loads the transmit register,
and reading SBUF accesses the physically separate
receive register. The Serial Port can operate in one of four
modes:
Mode 0 serial data enters and exits through RXD. TXD
outputs the shift clock. 8 bits are
transmitted/received: 8 data bits (LSB first). The
baud rate is fixed at 1/12 the oscillator frequency.
Mode 1 10 bits are transmitted (through TXD) or received
(through RXD): a start bit (0), 8 data bits (LSB
first), and a stop bit (1). On receive, the stop bit
goes into RB8 in SCON SFR. The baud rate is
variable.
Mode 2 11 bits are transmitted (through TXD) or received
(through RXD): a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit, and a stop bit
(1). On transmit, the 9th data bit (TB8 in SCON)
can be assigned the value of 0 or 1. For example,
the parity bit (P, in the PSW) could be moved into
TB8. On receive, the 9th data bit goes into RB8 in
SCON, while the stop bit is ignored. The baud
rate is programmable to either 1/32 or 1/64 the
oscillator frequency.
Mode 3 11 bits are transmitted (through TXD) or received
(through RXD): a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit, and a stop bit
(1). In fact, Mode 3 is the same as Mode 2 in all
respects except the baud rate. The baud rate in
Mode 3 is variable.
1997 Dec 15
30
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
12.1 Serial Port Control Register (SCON)
Table 12 Serial Port Control register (address 98H)
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Table 13 Description of the SCON bits
BIT
SYMBOL
SM0
FUNCTION
7
6
5
see Table 14.
see Table 14.
SM1
SM2
Enables the multiprocessor communication feature in Modes 2 and 3. In these
modes, if SM2 is set to 1 then RI will not be activated if the received 9th data bit (RB8) is
0. In Mode 1, if SM2 = 1, then RI will not be activated if a valid stop bit is not received. In
Mode 0, SM2 should be 0.
4
3
REN
TB8
Enables serial reception. Set and cleared by software as required.
9th data bit that will be transmitted in Modes 2 and 3. Set and cleared by software
as required.
2
1
0
RB8
TI
In Modes 2 and 3, RB8 is the 9th data bit that is received. In Mode 1, if SM2 = 0,
RB8 is the stop bit that is received. In Mode 0, RB8 is not used.
Transmit interrupt flag. It is set by hardware at the end of the 8th bit time in Mode 0, or
at the beginning of the stop bit in the other modes. TI must be cleared by software.
RI
Receive interrupt flag. It is set by hardware at the end of the 8th bit time in Mode 0, or
halfway through the stop bit time in the other modes (except: see SM2). RI must be
cleared by software.
12.2 SM0 and SM1 operating modes (SCON)
SCON bits SM0 and SM1 can operate in the following modes (see Table 14):
Table 14 SM0 and SM1 operating modes
MODE
SM0
SM1
DESCRIPTION
shift register
BAUD RATE
0
1
2
3
0
0
1
1
0
1
0
1
1⁄12fOSC
8-bit UART
9-bit UART
9-bit UART
variable
1⁄32fOSC, 1⁄64fOSC
variable
1997 Dec 15
31
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
13 BIT-LEVEL I2C INTERFACE
The following functions must be done in software:
• handling the I2C START interrupts
This bit-level serial I/O interface supports the I2C-bus (see
Fig.18). P1.6/SCL and P1.7/SDA are the serial I/O pins.
These two pins meet the I2C specification concerning the
input levels and output drive capability. Consequently,
these pins have an open drain output configuration. All
four modes of the I2C-bus are supported:
• converting serial to parallel data when receiving
• converting parallel to serial data when transmitting
• comparing the received slave address with its own
• interpreting the acknowledge information
• guarding the I2C status if RBF or WBF = 0.
• master transmitter
• master receiver
• slave transmitter
• slave receiver.
additionally, if acting as master:
• generating START and STOP conditions
•
handling bus arbitration
The advantages of the bit-level I2C hardware compared
with a full software I2C implementation are:
• generating serial clock pulses if S1BIT is not used.
Three SFRs control the bit-level I2C interface: S1INT,
S1BIT and S1SCS.
• the hardware can generate the SCL pulse
• testing a single bit (RBF respectively, WBF) is sufficient
as a check for error free transmission.
The bit-level I2C hardware operates on serial bit level and
performs the following functions:
• filtering the incoming serial data and clock signals
• recognizing the START condition
• generating a serial interrupt request SI after reception of
a START condition and the first falling edge of the serial
clock
• recognizing the STOP condition
• recognizing a serial clock pulse on the SCL line
• latching a serial bit on the SDA line (SDI)
• stretching the SCL LOW period of the serial clock to
suspend the transfer of the next serial data bit
• setting Read Bit Finished (RBF) when the SCL clock
pulse has finished and Write Bit Finished (WBF) if there
is no arbitration loss detected (i.e. SDA = 0 while
SDO = 1)
• setting a serial clock LOW-to-HIGH detected (CLH) flag
• setting a Bus Busy (BB) flag on a START condition and
clearing this flag on a STOP condition
• releasing the SCL line and clearing the CLH, RBF and
WBF flags to resume transfer of the next serial data bit
• generating an automatic clock if the single bit data
register S1BIT is used in master mode.
1997 Dec 15
32
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
RSBIT
RSCS
FSDA
SDA
FILTER
D
C
Q
SDI
QN
IB7
Q
Q
S
D
FSCL
SDO
WSBIT
WSCS
C
P1.7 / SDA
P1.7 / SCL
DIS
RSCS
FSCL
SCL
FILTER
IB6
D
SCO
AUTO - CLOCK
GENERATOR
C
Q
Q
WSCS
DIS
RSBIT
WSBIT
RSCS
RSCS
FSCL
IB5
IB4
WSCS
IB5
CLH
EN
STAQ
RSBIT
WSBIT
R
FSCL
STRQ
FSCL
S
R
Q
ST
QN
START
STOP
S
R
BB
RSBIT
WSBIT
START
FSDA
to
FSCL
SI
CLHQ
STAQN
BBQ
RBF
RSCS
interrupt
logic
EN
S
Q
IB3
WSINT
IB7
STA
FSCLN
R
RSBIT
WSBIT
WBF
RSCS
RSCS
IB2
IB1
FSDA
SDIQN
SDOQ
STOP
FSCL
D
Q
Q
STR
IBX : internal data bus
RSCS : read
WSCS
WSCS
C
WSCS : write
S1SCS
RSCS
IB0
RSBIT : read
WSBIT : write
D
S1BIT (with auto-clock)
ENS
DIS
EN
C
WSINT : write S1INT
MBC484
PD
Fig.18 Bit level I2C interface block diagram.
1997 Dec 15
33
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
13.1 I2C Interrupt Register (S1INT)
Table 15 I2C Interrupt register (address DAH) (1)
7
6
5
4
3
2
1
0
SI
X
X
X
X
X
X
X
Note
1. SI bit: writing a logic 0 clears this bit, writing a logic 1 has no effect.
Table 16 Description of the S1INT bits
BIT
SYMBOL
SI
FUNCTION
7
Serial Interrupt request (SI) flag: if a START condition occurs the SI flag in the S1INT
SFR is set on the falling edge of the filtered serial clock. If SI = 1 is detected during a
transfer this can be a 'spurious START' error condition. If no transfer is taking place the
SI = 1 is a START from an external master. Provided the bits EA and ES1 in IE SFR are
set, SI then generates an interrupt so that a slave address receive routine can be
started. SI can be cleared by accessing the S1BIT register or by writing '00' to S1INT.
Also after reception of a START condition, the LOW period of the clock pulse is
stretched, suspending the serial transfer to allow the software to take action. This clock
stretching is ended by a read or write access to S1BIT.
6 to 0
−
X = undefined during read, don't care during write.
13.2 Single-bit Data Register with I2C Auto-clock (S1BIT)
Table 17 Single-bit Data register with I2C Auto-clock (address D9H)(1)
7
6
5
4
3
2
1
0
READ
SDI
WRITE
SDO
0
0
0
0
0
0
0
X
X
X
X
X
X
X
Note
1. Access of the S1BIT SFR clears SI, CLH, RBF and WBF. It starts the auto-clock if SCO = 0.
Table 18 Description of the S1BIT bits
BIT
SYMBOL
FUNCTION
7
SDO/SDI
Serial Data Output (SDO) and the filtered Serial Data Input (SDI). SDI data is latched
on the rising edge of the filtered serial clock. S1BIT.7 accesses the same memory
locations as S1SCS.7. S1BIT SFR is not bit-addressable.
6 to 0
−
X = don't care.
1997 Dec 15
34
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
Every bit I/O should be followed by a RBF or WBF bit test.
A bit transfer has been finished successfully if after reading
a bit the RBF flag is 1 or after writing a bit the WBF flag is
1. When after reading a bit the RBF flag is still 0, the bus
status just before the S1SCS status read can be
determined as follows:
13.2.1 READING OR WRITING THE S1BIT SFR
Reading or writing the S1BIT SFR starts an I2C bit I/O
sequence: some flags are cleared (SI, CLH, RBF, WBF),
clock stretching is finished and the auto-clock is started.
An auto-clock pulse is 'OR-ed' with SCO and thus will be
output only if the SCO flag has been set to 0. SCO = 1
inhibits the auto-clock start, so a dummy read or write of
S1BIT SFR can be used to finish clock stretching and clear
SI, CLH, RBF and WBF if the auto-clock is not used.
• if CLH = 0 then a bus device is still stretching the clock
• if SCI = 1 while CLH = 1 then the SCL pulse is not
finished
• if BB = 0 there has been a STOP condition.
The auto-clock is an active HIGH SCL pulse that starts 28
XTAL clock periods after the SDI read or SDO write via
S1BIT. The duration of the auto-clock pulse is 100 XTAL
clock periods. If the SCL line is kept LOW by any device
that wants to hold up the bus transfer, the auto-clock
counter waits after 20 XTAL clock periods so that the
auto-clock pulse length will be at least 80 XTAL clock
periods (5 µs at fOSC = 16 MHz).
When after writing a bit the WBF flag is still 0 and none of
the 3 status conditions mentioned for RBF are found then
a 'bus arbitration lost' condition will be the cause. This can
be determined also from the states of the received bit and
the last transmitted bit: 'arbitration loss' if SDO = 1 and
SDI = 0.
13.3 Control and Status Register for the I2C-bus (S1SCS)
Table 19 Control and Status register for the I2C-bus (address D8H)
7
6
5
4
3
2
1
0
READ
SDI(1)
WRITE
SDO
SCI(1)
SCO
CLH(2)
CLH(2)
BB
X
RBF(3)
X
WBF(4)
X
STR
STR
ENS
ENS
Notes
1. SDI and SCI bits: read-modify-write operations like 'SETB bit' or 'CLR bit' access SDO and SCO for reading and
writing.
2. CLH bit: writing a logic 0 clears this bit, writing a 1 has no effect.
3. RBF and WBF bits: writing a logic 0 to CLH also clears these bits.
4. X = don't care.
1997 Dec 15
35
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
Table 20 Description of the S1SCS bits
BIT
SYMBOL
FUNCTION
7
SDO/SDI
Serial Data Output and the filtered Serial Data Input. SDI data is latched on the rising
edge of the filtered serial clock. S1SCS.7 accesses the same memory locations as
S1BIT.7. Access of the data bit via S1SCS will not start an auto-clock pulse.
6
5
SCO/SCI
Serial Clock Output and the filtered Serial Clock Input. Serial clock output SCO is
'OR-ed' with the auto-clock. If SCO = 1 the auto-clock output is inhibited. The internal
clock stretching logic and external devices can pull the SCL line LOW. If the auto-clock
is not used, the SCL line has to be controlled by setting SCO = 1, waiting for CLH = 1
and setting SCO = 0 after the specified SCL HIGH time. (Because of the input filter,
CLH will be set at least 8 XTAL clock periods after the SCL LOW-to-HIGH transition.)
CLH
Serial Clock LOW-to-HIGH transition flag: set with a rising edge of the filtered serial
clock. CLH = 1 indicates that, since the last CLH reset, a new valid data bit has been
latched in SDI. CLH can be reset by writing a 0 to S1SCS.5 or by a read/write of S1BIT.
Clearing CLH also clears RBF and WBF.
4
3
BB
Bus Busy flag: indicating that there has been a START condition that was not yet
followed by a STOP condition.
RBF
Read Bit Finished flag: indicating a successful bit read.
RBF = 1 implies the following conditions:
CLH = 1: SCL had a rising edge
SCI = 0: the SCL pulse has finished
SI = 0: no START condition occurred
BB = 1: no STOP condition occurred
The RBF flag can be cleared by clearing the CLH flag.
2
1
WBF
STR
Write Bit Finished flag: indicating a successful bit write. The same conditions as for
RBF are true and also no 'arbitration loss' condition occurred. Arbitration is lost if a
1 data bit in SDO was over-ruled on SDA by an external device. The WBF flag can be
cleared by clearing the CLH flag.
STRetch control flag. STR = 1 enables stretching of all SCL LOW periods. This allows
the processor in I2C slave mode to react on a fast master. The STR flag remains set
until cleared by writing a 0 to S1SCS.1.
The STretch (ST) flag (not readable) pulls the serial clock LOW while ST = 1. The ST
flag is set on the falling edge of the filtered serial clock if STR = 1. It is also set after
reception of a START condition, regardless of the STR contents. ST is cleared with a
read or write of S1BIT.
0
ENS
ENable Serial I/O flag. ENS = 1 enables the START detection and clock stretching
logic. ENS = 0 can be used to switch off the I2C-bus hardware. Note that the SDO and
SCO control flags must be set to 1 before ENS is set to avoid pulling SCL or SDA lines
to 0.
1997 Dec 15
36
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
The I2C interrupt is generated by SI in S1INT. This flag has
to be cleared by software. All of the bits that generate
interrupts can be set or cleared by software, with the same
result as though they had been set or cleared by hardware,
with the exception of the I2C interrupt request flag SI,
which cannot be set by software. That is, interrupts can be
generated or pending interrupts can be cancelled in
software.
14 INTERRUPT SYSTEM
The P83C528 contains the same interrupt structure as the
PCB80C51BH, but with a seven-source interrupt structure
with two priority levels (see Fig.19).
The External Interrupts INT0 and INT1 can each be either
level-activated or transition-activated, depending on bits
IT0 and IT1 in TCON SFR. The flags that actually generate
these interrupts are bits IE0 and IE1 in TCON. When an
external interrupt is generated, the corresponding request
flag is cleared by the hardware when the service routine is
vectored to, only if the interrupt was transition-activated. If
the interrupt was level-activated then the interrupt request
flag remains set until the external interrupt pin INTx goes
high.
handbook, halfpage
INT0
0
1
The Timer 0 and Timer 1 Interrupts are generated by TF0
and TF1, which are set by a rollover in their respective
timer/counter register (except for Timer 0 in Mode 3 of the
serial interface). When a Timer interrupt is generated, the
flag that generated it is cleared by the on-chip hardware
when the service routine is vectored to.
IE0
TF2
EXF2
SI
TF0
The Serial Port Interrupt is generated by the logical 'OR' of
RI and TI. Neither of these flags is cleared by hardware.
The service routine will normally have to determine
whether it was RI or TI that generated the interrupt, and the
bit will have to be cleared by software.
interrupt
sources
0
1
IE1
INT1
The Timer 2 Interrupt is generated by the logical OR of TF2
and EXF2. Neither of these flags is cleared by hardware.
In fact the service routine may have to determine whether
it was TF2 or EXF2 that generated the interrupt, and the bit
will have to be cleared by software.
TF1
TI
RI
MBC481 - 1
An additional (third) external interrupt is available, if Timer
2 is not used as timer/counter or if Timer 2 is used in baud
rate generator mode. That external interrupt 2 is falling
edge triggered. It shares the Timer 2 interrupt vector,
interrupt enable and interrupt priority bits. If bit
T2CON.3/EXEN2 = 1, a HIGH-to-LOW transition at pin
P1.1/T2EX sets the interrupt request flag T2CON.6/EXF2
and can be used to generate an external interrupt.
Fig.19 P83C528 Interrupt Sources.
1997 Dec 15
37
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
14.1 Interrupt Enable Register (IE)
Table 21 Interrupt Enable register (address A8H)
7
6
5
4
3
2
1
0
EA
ES1
ET2
ES
ET1
EX1
ET0
EX0
Table 22 Description of the IE bits
BIT
SYMBOL
EA
FUNCTION
7
general enable/disable control:
0 = NO interrupt is enabled
1 = ANY individually enabled interrupt will be accepted
enable bit-level I2C I/O interrupt
enable Timer 2 interrupt
6
5
4
3
2
1
0
ES1
ET2
ES
enable Serial Port interrupt
enable Timer 1 interrupt
ET1
EX1
ET0
EX0
enable External interrupt 1
enable Timer 0 interrupt
enable External interrupt 0
14.2 Interrupt Priority Register (IP)
Table 23 Interrupt Priority register (address B8H)
7
6
5
4
3
2
1
0
−
PS1
PT2
PS
PT1
PX1
PT0
PX0
1997 Dec 15
38
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
14.3 Interrupt Vectors
The interrupt vectors are listed in Table 25.
Table 24 Description of the IP bits
BIT
SYMBOL
FUNCTION
7
6
5
4
3
2
1
0
−
reserved
PS1
PT2
PS
Bit-level I2C interrupt priority level
Timer 2 interrupt priority level
Serial Port interrupt priority level
Timer 1 interrupt priority level
External interrupt 1 priority level
Timer 0 interrupt priority level
External interrupt 0 priority level
PT1
PX1
PT0
PX0
Table 25 Interrupt vectors
NUMBER
SOURCE
PRIORITY WITHIN LEVEL
VECTOR ADDRESS
1
2
3
4
5
6
7
IE0
(highest)
0003H
002BH
0053H
000BH
0013H
001BH
0023H
TF2+EXF2
SI (I2C)
TF0
−
−
−
IE1
−
TF1
−
RI + TI
(lowest)
1997 Dec 15
39
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
The Power-down operation freezes the oscillator. The
Power-down mode can only be activated by setting the PD
bit in the PCON register (see Fig.20).
15 IDLE AND POWER-DOWN OPERATION
Idle mode operation permits the interrupt, serial ports and
timer blocks to function while the CPU is halted. The
following functions remain active during Idle mode. These
functions may generate an interrupt or reset and thus end
the Idle mode:
• Timer 0, Timer 1, Timer 2, Watchdog Timer
• UART, I2C-Interface
• External interrupt
XTAL2
XTAL1
OSCILLATOR
interrupts
serial ports
timer blocks
CLOCK
GENERATOR
CPU
PD
IDL
MBC477 - 1
Fig.20 Internal Idle and Power-down clock configuration.
1997 Dec 15
40
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
15.1 Power Control Register (PCON)
Special modes are activated by software via the PCON SFR. PCON is not bit addressable. The reset value of PCON is
0XXX0000.
Table 26 Power Control Register (address 87H)
7
6
5
4
3
2
1
0
SMOD
−
−
−
GF1
GF0
PD
IDL
Table 27 Description of the PCON bits
BIT
SYMBOL
SMOD
FUNCTION
7
Double Baud rate bit: when set to logic 1 the baud rate is doubled when Timer 1 is
used to generate baud rate, and the Serial Port is used in modes 1, 2 or 3.
6
5
4
3
2
1
0
−
reserved for future use
−
reserved for future use
−
reserved for future use
GF1
GF0
PD
IDL
general-purpose flag bit
general-purpose flag bit
Power-down bit: setting this bit activates Power-down mode
Idle mode bit: setting this bit activates the Idle mode.
Notes
1. If logic 1s are written to PD and IDL at the same time, PD takes precedence.
2. User software should not write 1s to reserved bits. These bits may be used in future 80C51 family products to invoke
new features.
1997 Dec 15
41
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
• The second way of terminating the Idle mode is with an
external hardware reset. Since the oscillator is still
running, the hardware reset is required to be active for
two machine cycles (24 oscillator periods) to complete
the reset operation.
15.2 Idle Mode
The instruction that sets PCON.0 is the last instruction
executed in the normal operating mode before Idle mode
is activated. Once in the Idle mode, the CPU status is
preserved in its entirety: the Stack Pointer, Program
Counter, Program Status Word, Accumulator, RAM and all
other registers maintain their data during Idle mode. The
status of external pins during Idle mode is shown in
Table 28.
• The third way of terminating the Idle mode is by internal
watchdog reset.
15.3 Power-down Mode
The instruction that sets PCON.1 is the last executed prior
to going into the Power-down mode. The oscillator is
stopped. Note that the Power-down mode also can be
entered when the watchdog has been enabled. The
Power-down mode can be terminated by an external
RESET in the same way as in the 80C51 or in addition by
any one of the two external interrupts, IE0 or IE1 (see
Section 15.4). A reset generated by the WDT terminates
the Power-down mode in the same way as an external
RESET.
There are three ways to terminate the Idle mode:
• Activation of any enabled interrupt will cause PCON.0 to
be cleared by hardware terminating Idle mode. The
interrupt is serviced, and following return from interrupt
instruction RETI, the next instruction to be executed will
be the one which follows the instruction that wrote a
logic 1 to PCON.0.
• The flag bits GF0 and GF1 may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.0 can also set or clear
one or both flag bits. When Idle mode is terminated by
an interrupt, the service routine can examine the status
of the flag bits.
The status of the external pins during Power-down mode
is shown in Table 28. If the Power-down mode is activated
while in external program memory, the port data that is
held in the P2 SFR is restored to Port 2. If the data is a
logic 1, the port pin is held HIGH during the Power-down
mode by the strong pull-up transistor p1 (see Fig.13).
Table 28 Status of the external pins during Idle and Power-down modes
MODE
MEMORY
internal
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Idle
Idle
1
1
0
0
1
1
0
0
port data
floating
port data
port data
port data
port data
port data
address
port data
port data
port data
port data
port data
port data
external
internal
external
Power-down
Power-down
port data
floating
1997 Dec 15
42
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
15.4 Wake-up from Power-down Mode
Table 29 Internal registers status after a RESET
The Power-down mode of the P83C528 can also be
terminated by any one of the two external interrupts, IE0 or
IE1. A termination with an external interrupt does not affect
the internal data memory and does not affect the Special
Function Registers (SFRs). This gives the possibility to
exit Power-down without changing the port output levels.
To terminate the Power-down mode with an external
interrupt, IE0 or IE1 must be switched to be level-sensitive
and must be enabled. The external interrupt input signal
INT0 and INT1 must be kept LOW till the oscillator has
restarted and stabilized (see Fig.21).
REGISTER
CONTENTS
ACC
B
00H
00H
00H
DPH, DPL
IE
0000 0000B
X000 0000B
00H
IP
PCH, PCL
PCON
0XXX 0000B
00H
PSW
P0 to P3
SBUF
FFH
In order to prevent any interrupt priority problems during
wake-up, the priority of the desired wake-up interrupt
should be higher than the priorities of all other enabled
interrupt sources. The instruction following the one that put
the device into the Power-down mode will be the first one
which will be executed after an interrupt has been
serviced.
Indeterminate
00H
SCON
SP
07H
TCON
00H
TMOD
TH0, TL0
TH1, TL1
T2CON
TH2, TL2
RCAP2H, RCAP2L
S1BIT
00H
00H
00H
00H
00H
00H
X000 0000B
0XXX XXXXB
XXX0 0000B
00H
S1INT
S1SCS
T3
WDCON
A5H
internal timing stopped
power down
C1
C1
IDLE MODE
C1
C2
LCALL
interrupt routine
oscillator start up
oscillator stopped
interrupts are polled
min. 20 ms
INT0 2 cycles
INT1 1 cycle
INT0 / INT1
MBC508 - 1
set external
interrupt latch
Fig.21 Wake up by external interrupt input.
1997 Dec 15
43
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
16 OSCILLATOR CIRCUIT
17 RESET CIRCUIT
The oscillator circuit of the P83C528 is a single-stage
inverting amplifier in a Pierce oscillator configuration. The
circuitry between the XTAL1 and XTAL2 is basically an
inverter biased to the transfer point. Either a crystal or
ceramic resonator can be used as the feedback element to
complete the oscillator circuitry. Both are operated in
parallel resonance. XTAL1 is the high gain amplifier input,
and XTAL2 is the output (see Fig.22). To drive the
P83C528 externally, XTAL1 is driven from an external
source and XTAL2 left open-circuit (see Fig.23).
The reset circuitry for the P83C528 is connected to the
reset pin RST. A Schmitt trigger is used at the input for
noise rejection. The output of the Schmitt trigger is
sampled by the reset circuitry every machine cycle.
A reset is accomplished by holding the RST pin HIGH for
at least two machine cycles (24 oscillator periods). The
CPU responds by executing an internal reset. During reset
ALE and PSEN output a HIGH level. In order to perform a
correct reset, this level must not be affected by external
elements.
With the P83C528, the RST line can also be pulled HIGH
internally by a pull-up transistor activated by the WDT T3.
The length of the reset pulse from T3 is 16 x 2048 cycles
of the on-chip watchdog oscillator. If the WDT is also used
to reset external devices, the usual capacitor arrangement
should not be connected to RST pin. Instead, an extra
circuit should be used to perform the Power-on Reset
operation. It should be remembered that a Timer T3
overflow, if enabled, will force a reset condition to the
P83C528 by an internal connection, whether the output
RST is tied LOW or not (see Fig.24).
C1
handbook, halfpage
XTAL1
20 pF
C2
XTAL2
20 pF
MBC473
The internal reset is executed during the second cycle in
which RST is pulled HIGH and is repeated every cycle until
RST goes LOW. It leaves the internal registers as shown
by Table 29.
Fig.22 P83C528 oscillator circuit.
V
DD
handbook, halfpage
handbook, halfpage
overflow
timer T3
XTAL1
external clock
(not TTL compatible)
SCHMITT
TRIGGER
RESET
CIRCUITRY
RST
XTAL2
not connected
MBC476 - 1
on-chip
resistor
R
RST
MBC472
Fig.23 Driving the P83C528 from an
external source.
Fig.24 On-chip reset configuration.
1997 Dec 15
44
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
17.1 Power-on reset
When VDD is turned on, and provided its rise-time does not
exceed 10 ms, an automatic reset can be obtained by
connecting the RST pin to VDD via a 2.2 µF capacitor.
When the power is switched on, the voltage on the RST pin
is equal to VDD minus the capacitor voltage, and
decreases from VDD as the capacitor charges through the
internal resistor (RRST) to ground. The larger the capacitor,
the more slowly VRST decreases. VRST must remain above
the lower threshold of the Schmitt trigger long enough to
effect a complete reset. The time required is the oscillator
start-up time, plus 2 machine cycles, or 16 x 2048 cycles
of the on-chip watchdog oscillator if it is running, whichever
is longer (see Fig.25).
V
DD
handbook, halfpage
V
DD
2.2 µF
P83C528
RST
R
RST
MBC474
Fig.25 Power-on reset.
1997 Dec 15
45
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
18 INSTRUCTION SET
The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 12 MHz
oscillator, 64 instructions execute in 1 cycle (1 µs) and 45 instructions execute in 2 cycles (2 µs). Multiply and divide
instructions execute in 4 cycles (4 µs).
Table 30 Instruction set description: Arithmetic operations
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES CYCLES
Arithmetic operations
ADD
ADD
ADD
ADD
A,Rr
Add register to A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
2*
A,direct
A,@Ri
A,#data
Add direct byte to A
25
Add indirect RAM to A
26, 27
24
Add immediate data to A
Add register to A with carry flag
Add direct byte to A with carry flag
Add indirect RAM to A with carry flag
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment A
ADDC A,Rr
3*
ADDC A,direct
ADDC A,@Ri
ADDC A,#data
SUBB A,Rr
35
36, 37
34
9*
SUBB A,direct
SUBB A,@Ri
SUBB A,#data
95
96, 97
94
INC
INC
INC
INC
DEC
DEC
DEC
DEC
INC
MUL
DIV
A
04
Rr
Increment register
0*
direct
@Ri
A
Increment direct byte
05
Increment indirect RAM
Decrement A
06, 07
14
Rr
Decrement register
1*
direct
@Ri
DPTR
AB
Decrement direct byte
15
Decrement indirect RAM
Increment data pointer
16, 17
A3
Multiply A and B
A4
AB
Divide A by B
84
DA
A
Decimal adjust A
D4
1997 Dec 15
46
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
Table 31 Instruction set description: Logic operations
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES
CYCLES
Logic operations
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
A,Rr
AND register to A
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
5*
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A,Rr
AND direct byte to A
55
AND indirect RAM to A
AND immediate data to A
AND A to direct byte
56, 57
54
52
AND immediate data to direct byte
OR register to A
53
4*
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A,Rr
OR direct byte to A
45
OR indirect RAM to A
46, 47
44
OR immediate data to A
OR A to direct byte
42
OR immediate data to direct byte
Exclusive-OR register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate data to A
Exclusive-OR A to direct byte
Exclusive-OR immediate data to direct byte
Clear A
43
6*
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A
65
66, 67
64
62
63
E4
F4
A
Complement A
A
Rotate A left
23
RLC
RR
A
Rotate A left through the carry flag
Rotate A right
33
A
03
RRC
SWAP
A
Rotate A right through the carry flag
Swap nibbles within A
13
A
C4
1997 Dec 15
47
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
Table 32 Instruction set description: Data transfer
OPCODE
BYTES CYCLES
(HEX)
MNEMONIC
DESCRIPTION
Data transfer
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
A,Rr
Move register to A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
E*
A,direct (note 1)
A,@Ri
Move direct byte to A
E5
Move indirect RAM to A
E6, E7
74
A,#data
Move immediate data to A
Rr,A
Move A to register
F*
Rr,direct
Move direct byte to register
A*
Rr,#data
direct,A
Move immediate data to register
Move A to direct byte
7*
F5
direct,Rr
direct,direct
direct,@Ri
direct,#data
@RI,A
Move register to direct byte
8*
Move direct byte to direct
85
Move indirect RAM to direct byte
Move immediate data to direct byte
Move A to indirect RAM
86, 87
75
F6, F7
A6, A7
76, 77
90
@Ri,direct
@Ri,#data
DPTR,#data 16
Move direct byte to indirect RAM
Move immediate data to indirect RAM
Load data pointer with a 16-bit constant
Move code byte relative to DPTR to A
Move code byte relative to PC to A
Move external RAM (8-bit address) to A
Move external RAM (16-bit address) to A
Move A to external RAM (8-bit address)
Move A to external RAM (16-bit address)
Push direct byte onto stack
MOVC A,@A+DPTR
MOVC A,@A+PC
MOVX A,@Ri
93
83
E2, E3
E0
MOVX A,@DPTR
MOVX @Ri,A
F2, F3
F0
MOVX @DPTR,A
PUSH direct
C0
POP
XCH
XCH
XCH
direct
A,Rr
Pop direct byte from stack
D0
Exchange register with A
C*
A,direct
A,@Ri
Exchange direct byte with A
C5
Exchange indirect RAM with A
Exchange LOW-order digit indirect RAM with A
C6, C7
D6, D7
XCHD A,@Ri
Note
1. MOV A,ACC is not permitted.
1997 Dec 15
48
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
Table 33 Instruction set description: Boolean variable manipulation, Program and machine control
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES
CYCLES
Boolean variable manipulation
CLR
C
Clear carry flag
Clear direct bit
Set carry flag
Set direct bit
1
2
1
2
1
2
2
2
2
2
2
2
1
1
1
1
1
1
2
2
2
2
1
2
C3
C2
D3
D2
B3
B2
82
B0
72
A0
A2
92
CLR
bit
C
SETB
SETB bit
CPL
CPL
ANL
ANL
ORL
ORL
MOV
MOV
C
Complement carry flag
bit
Complement direct bit
C,bit
C,/bit
C,bit
C,/bit
C,bit
bit,C
AND direct bit to carry flag
AND complement of direct bit to carry flag
OR direct bit to carry flag
OR complement of direct bit to carry flag
Move direct bit to carry flag
Move carry flag to direct bit
Program and machine control
ACALL addr11
LCALL addr16
RET
Absolute subroutine call
Long subroutine call
2
3
1
1
2
3
2
1
2
2
2
2
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
•1addr
12
Return from subroutine
22
RETI
Return from interrupt
32
AJMP addr11
LJMP addr16
SJMP rel
Absolute jump
♦ 1addr
02
Long jump
Short jump (relative address)
Jump indirect relative to the DPTR
Jump if A is zero
80
JMP
JZ
@A+DPTR
rel
73
60
JNZ
JC
rel
Jump if A is not zero
70
rel
Jump if carry flag is set
40
JNC
JB
rel
Jump if carry flag is not set
Jump if direct bit is set
50
bit,rel
bit,rel
bit,rel
20
JNB
JBC
Jump if direct bit is not set
Jump if direct bit is set and clear bit
Compare direct to A and jump if not equal
Compare immediate to A and jump if not equal
30
10
CJNE A,direct,rel
CJNE A,#data,rel
CJNE Rr,#data,rel
B5
B4
Compare immediate to register and jump if not
equal
B*
CJNE @Ri,#data,rel
Compare immediate to indirect and jump if not
equal
3
2
B6, B7
DJNZ Rr,rel
DJNZ direct,rel
NOP
Decrement register and jump if not zero
Decrement direct and jump if not zero
No operation
2
3
1
2
2
1
D*
D5
00
1997 Dec 15
49
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
Table 34 Description of the mnemonics in the Instruction set
MNEMONIC
DESCRIPTION
Data addressing modes
Rr
working register R0-R7.
direct
@Ri
128 internal RAM locations and any special function register (SFR).
indirect internal RAM location addressed by register R0 or R1 of the actual register bank.
8-bit constant included in instruction.
#data
#data 16
bit
16-bit constant included as bytes 2 and 3 of instruction.
direct addressed bit in internal RAM or SFR.
addr16
16-bit destination address. Used by LCALL and LJMP. The branch will be anywhere within the
64 kbytes program memory address space.
addr11
rel
11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes
page of program memory as the first byte of the following instruction.
Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is
−128 to +127 bytes relative to first byte of the following instruction.
Hexadecimal opcode cross-reference
*
•
8, 9, A, B, C, D, E, F.
11, 31, 51, 71, 91, B1, D1, F1.
01, 21, 41, 61, 81, A1, C1, E1.
♦
1997 Dec 15
50
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First hexadecimal character of opcode
← Second hexadecimal character of opcode →
↓
0
1
2
3
4
5
6
0
0
7
1
1
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
1
1
1
1
1
1
1
1
1
1
1
A B C D E F
INC Rr
INC @Ri
DEC @Ri
AJMP
addr11
LJMP
addr16
RR
A
INC
A
INC
direct
0
NOP
2
3
4
5
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
DEC Rr
JBC
bit,rel
ACALL
addr11
LCALL
addr16
RRC
A
DEC
A
DEC
direct
1
2
3
4
5
6
7
8
9
A
B
C
D
E
2
3
4
5
ADD A,@Ri
ADD A,Rr
JB
bit,rel
AJMP
addr11
RL
A
ADD
A,#data
ADD
A,direct
RET
0
1
2 3 4 5
ADDC A,@Ri
ADDC A,Rr
JNB
bit,rel
ACALL
addr11
RLC
A
ADDC
A,#data
ADDC
A,direct
RETI
0
1
2 3 4 5
ORL A,@Ri
ORL A,Rr
JC
rel
AJMP
addr11
ORL
direct,A
ORL
direct,#data
ORL
A,#data
ORL
A,direct
0
1
2 3 4 5
ANL A,@Ri
ANL A,Rr
JNC
rel
ACALL
addr11
ANL
direct,A
ANL
direct,#data
ANL
A,#data
ANL
A,direct
0
1
2 3 4 5
XRL A,@Ri
XRL A,Rr
JZ
rel
AJMP
addr11
XRL
direct,A
XRL
direct,#data
XRL
A,#data
XRL
A,direct
0
1
2 3 4 5
MOV @Ri,#data
MOV Rr,#data
JNZ
rel
ACALL
addr11
ORL
C,bit
JMP
@A+DPTR
MOV
A,#data
MOV
direct,#data
0
1
2 3 4 5
MOV direct,@Ri
MOV direct,Rr
SJMP
rel
AJMP
addr11
ANL
C,bit
MOVC
A,@A+PC
DIV
AB
MOV
direct,direct
0
1
2 3 4 5
SUBB A,@Ri
SUB A,Rr
MOV
DTPR,#data16
ACALL
addr11
MOV
bit,C
MOVC
A,@A+DPTR
SUBB
A,#data
SUBB
A,direct
0
1
2 3 4 5
MOV @Ri,direct
MOV Rr,direct
ORL
C,/bit
AJMP
addr11
MOV
bit,C
INC
DPTR
MUL
AB
0
1
2 3 4 5
CJNE @Ri,#data,rel
CJNE Rr,#data,rel
ANL
C,/bit
ACALL
addr11
CPL
bit
CPL
C
CJNE
A,#data,rel
CJNE
A,direct,rel
0
1
1
1
1
1
1
1
2
3
4
5
6
6
6
6
6
XCH A,@Ri
XCH A,Rr
PUSH
direct
AJMP
addr11
CLR
bit
CLR
C
SWAP
A
XCH
A,direct
0
2 3 4 5
XCHD A,@Ri
DJNZ Rr,rel
POP
direct
ACALL
addr11
SETB
bit
SETB
C
DA
A
DJNZ
direct,rel
0
1
1
2 3 4 5
MOVX A,@Ri
MOV A,@Ri
MOV A,Rr
MOVX
A,@DTPR
AJMP
addr11
CLR
A
MOV
A,direct (1)
0
0
1
0
2 3 4 5
MOVX @Ri,A
MOV @Ri,A
MOV Rr,A
MOVX
@DTPR,A
ACALL
addr11
CPL
A
MOV
direct,A
F
1
0
1
2 3 4 5
Note
1. MOV A, ACC is not a valid instruction.
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
19 LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134)
SYMBOL
VDD
PARAMETER
MIN.
−0.5
MAX.
+6.0
UNIT
supply voltage range
all input voltages
V
VI
−0.5
−
VDD +0.5
1
V
Ptot
Tstg
Tamb
total power dissipation
W
°C
storage temperature range
operating ambient temperature range:
version xBx
−65
+150
0
+70
+85
°C
°C
version xFx
−40
1997 Dec 15
52
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
20 DC CHARACTERISTICS
VDD = 5 V ± 10%; VSS = 0 V; Tamb = 0 to +70°C; −40 to +85°C. All voltages with respect to VSS unless otherwise
specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDD
IDD
supply voltage range
4.5
5.5
33
V
supply current operating modes,
note 1
VDDmax, 16 MHz
−
mA
VDDmax, 24 MHz
VDDmax, 16 MHz
43
6
mA
mA
IID
supply current Idle mode, note 2
−
VDDmax, 24MHz
7.5
mA
IPD
supply current Power−down mode
2 V ≤ VDD ≤ VDDmax; note 3
−
100
µA
Inputs
VIL
LOW level input voltage
(except EA, P1.6, P1.7)
−0.5
0.2 VDD−0.1
V
VIL1
VIL2
VIH
LOW level input voltage EA
−0.5
−0.5
0.2 VDD−0.3
V
V
V
LOW level input voltage P1.6, P1.7
note 6
0.3 VDD
HIGH level input voltage
0.2 VDD +0.9 VDD +0.5
(except RST, XTAL1, P1.6, P1.7)
VIH1
VIH2
IIL
HIGH level input voltage RST, XTAL1
HIGH level input voltage P1.6, P1.7
0.7 VDD
0.7 VDD
−
VDD +0.5
5.5
V
note 6
V
LOW level input current
Ports 1, 2 and 3
VI = 0.45 V
−50
µA
(except P1.6 and P1.7)
ITL
input current HIGH-to-LOW transition VI = 2.0 V
Ports 1, 2 and 3
−
−650
µA
(except P1.6 and P1.7)
ILI1
ILI2
input leakage current Port 0, EA
0.45 < VI < VDD
−
−
±10
±10
µA
µA
input leakage current P1.6 and P1.7 0 V < VI < 5.5 V
0 V < VDD < 5.5 V
Outputs
VOL
LOW level output voltage
Ports 1, 2 and 3
IOL = 1.6 mA; notes 6 and 7
−
0.45
V
(except P1.6 and P1.7)
VOL1
VOL2
VOH
LOW level output voltage
Port 0, ALE, PSEN
IOL = 3.2 mA; notes 4 and 7
IOL = 3.0 mA; note 7
−
−
0.45
0.40
V
V
V
LOW level output voltage
P1.6 and P1.7
HIGH level output voltage
Ports 1, 2 and 3
(except P1.6 and P1.7)
IOH = −60 µA;
VDD = 5 V ±10%
2.4
−
−
−
0.75 VDD
0.9 VDD
IOH = −25 µA
IOH = −10 µA
1997 Dec 15
53
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
SYMBOL
PARAMETER
CONDITIONS
IOH = −800 µA;
MIN.
MAX.
UNIT
VOH1
HIGH level output voltage
Port0in in external bus mode,
ALE, PSEN, RST
2.4
−
−
−
V
VDD = 5 V± 10%
0.75VDD
0.9VDD
IOH = −300 µA;
IOH = −80 µA; note 5
RRST
CI/O
RST pull−down resistor
50
150
10
kΩ
I/O pin capacitance
test frequency = 1 MHz;
−
pF
Tamb = 25 °C
Notes to the DC characteristics
1. Conditions for:
a) The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5 ns;
VIL = VSS +0.5 V; VIH = VDD −0.5 V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VDD
;
the WDT is disabled (by the external RESET).
2. Conditions for:
a) The Idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5 ns;
VIL = VSS +0.5 V; VIH = VDD −0.5 V; XTAL2 not connected; the WDT is disabled; EA = RST = VSS
Port 0 = P1.6 = P1.7 = VDD
3. Conditions for:
a) The Power-down current is measured with all output pins disconnected; XTAL2 not connected;
WDT is disabled; EA = RST = XTAL1 = VSS; Port 0 = P1.6 = P1.7 = VDD
;
.
.
4. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW level
output voltage of ALE, Port 1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0
and Port 2 pins when these pins make a HIGH-to-LOW transition during bus operations. In the worst cases
(capacitive loading > 100pF), the noise pulse on the ALE line may exceed 0.8 V. In such cases it may be desirable
to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
5. Capacitive loading on Port 0 and Port 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily
fall below the 0.9 VDD specification when the address bits are stabilizing.
6. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so a voltage below 0.3 VDD will be
recognized as a logic 0 while an input above 0.7 VDD will be recognized as a logic 1.
7. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
a) Maximum IOL per port pin:10 mA.
b) Maximum IOL per 8-bit port:- Port 0: 26 mA; Ports 1, 2 and 3: 15 mA.
c) Maximum total IOL for all output pins: 71 mA. If IOL exceeds the test condition,
VOL may exceed the related specification.
d) Pins are not guaranteed to sink current greater than the listed test conditions.
8. IDD max. at other frequencies can be derived from Fig.26 where f is the external oscillator frequency in MHz;
IDD max. is given in mA.
1997 Dec 15
54
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
MBC478
50
I
DD
(mA)
MAX ACTIVE MODE
TYP ACTIVE MODE
40
30
20
10
0
MAX IDLE MODE
TYP IDLE MODE
0
8
16
24
f (MHz)
Valid only within frequency specifications of device under test.
Fig.26 IDD as a function of frequency.
1997 Dec 15
55
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
21 AC CHARACTERISTICS
21.1 AC Characteristics 16 MHz version
See notes 1, 2 and 3 in Section 21.2; Cl = 100 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless
otherwise specified.
16 MHZ
MIN. MAX.
VARIABLE CLOCK
SYMBOL
PARAMETER
UNIT
MIN.
MAX.
External program memory
tLHLL
tAVLL
tLLAX
tLLIV
ALE pulse duration
85
8
−
2 tCK−40
−
−
−
ns
address set-up time to ALE
−
t
CK−55
CK−35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
address hold time after ALE
28
−
−
t
time from ALE to valid instruction input
time from ALE to control pulse PSEN
control pulse duration PSEN
150
−
−
4 tCK−100
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
23
143
−
tCK−40
−
−
3 tCK−45
−
time from PSEN to valid instruction input
input instruction hold time after PSEN
input instruction float delay after PSEN
address to valid instruction input
address float time to PSEN
83
−
−
0
−
−
−
3 tCK−105
0
−
−
38
208
10
tCK−25
−
5 tCK−105
−
10
External data memory
tLHLL
ALE pulse duration
85
8
−
2 tCK−40
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVLL
address set-up time to ALE
address hold time after ALE
RD pulse duration
−
t
CK−55
CK−35
−
tLLAX
28
275
275
−
−
t
−
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDZ
−
6 tCK−100
−
WR pulse duration
−
6 tCK−100
−
RD to valid data input
148
−
−
5 tCK−165
data hold time after RD
0
0
−
data float delay after RD
time from ALE to valid data input
address to valid data input
time from ALE to RD or WR
time from address to RD or WR
time from RD or WR HIGH to ALE HIGH
data valid to WR transition
data set-up time before WR
data hold time after WR
−
55
350
398
238
−
−
2 tCK−70
−
−
8 tCK−150
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
−
−
9 tCK−165
138
120
23
3
3 tCK−50
4 tCK−130
3 tCK+50
−
103
−
t
CK−40
CK−60
tCK+ 40
t
−
−
−
0
288
13
−
−
7 tCK−150
CK−50
−
t
address float delay after RD
0
−
1997 Dec 15
56
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
21.2 AC Characteristics 24 MHz version
See notes 1, 2 and 3.; Cl = 100 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless otherwise
specified.
24 MHZ
MIN. MAX.
VARIABLE CLOCK
SYMBOL
PARAMETER
UNIT
MIN.
MAX.
External program memory
tLHLL
tAVLL
tLLAX
tLLIV
ALE pulse duration
43
17
17
−
−
2 tCK−40
−
−
−
ns
address set-up time to ALE
−
t
CK−25
CK−25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
address hold time after ALE
−
t
time from ALE to valid instruction input
time from ALE to control pulse PSEN
control pulse duration PSEN
102
−
−
4 tCK−65
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
17
80
−
tCK−25
−
−
3 tCK−45
−
time from PSEN to valid instruction input
input instruction hold time after PSEN
input instruction float delay after PSEN
address to valid instruction input
address float time to PSEN
65
−
−
0
−
−
−
3 tCK−60
0
−
−
17
128
10
tCK−25
−
5 tCK−80
−
10
External data memory
tLHLL
ALE pulse duration
43
17
17
150
150
−
−
2 tCK−40
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVLL
address set-up time to ALE
address hold time after ALE
RD pulse duration
−
t
CK−25
CK−25
−
tLLAX
−
t
−
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDZ
−
6 tCK−100
−
WR pulse duration
−
6 tCK−100
−
RD to valid data input
118
−
−
5 tCK−90
data hold time after RD
0
0
−
data float delay after RD
time from ALE to valid data input
address to valid data input
time from ALE to RD or WR
time from address to RD or WR
time from RD or WR HIGH to ALE HIGH
data valid to WR transition
data set-up time before WR
data hold time after WR
−
55
183
210
175
−
−
2 tCK−28
−
−
8 tCK−150
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
−
−
9 tCK−165
75
92
17
12
162
17
−
3 tCK−50
4 tCK−75
3 tCK+50
−
67
−
t
CK−25
CK−30
tCK+ 25
t
−
−
−
0
−
7 tCK−130
CK−25
−
t
address float delay after RD
0
−
Notes to the AC Characteristics 16 and 24 MHz versions
1. For the AC Characteristics the following conditions are valid:
a) P83C52x EBx: VDD = 5 V ±10%; VSS = 0 V; Tamb = 0 to +70 °C; tCK min. = 63 ns
b) P83C52x EFx: VDD = 5 V ±10%; VSS = 0 V; Tamb = −40 to +85 °C; tCK min. = 63 ns.
2. tCK min. = 1/f max. (maximum operating frequency); tCK = clock period (see section for timing symbol definitions).
3. The maximum operating frequency is limited to 16/24 MHz and the minimum to 3.5 MHz (all versions Ixx/Exx).
1997 Dec 15
57
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
22 I2C CHARACTERISTICS (BIT-LEVEL)
SYMBOL
PARAMETER
INPUT
OUTPUT
I2C SPEC UNIT
SCL timing
tHD;STA
tLOW
tHIGH
tRC
START condition hold time
SCL LOW time
≥ 14 tCK; note 1
≥ 16 tCK
note 2
≥ 4.0
≥ 4.7
≥ 4.0
≤ 1.0
≤ 0.3
µs
µs
µs
µs
µs
note 2
SCL HIGH time
≥ 14 tCK; note 1
≤ 1; note 4
≥ 80 tCK; note 3
note 5
SCL RISE time
tFC
SCL FALL time
≤ 0.3; note 4
≤ 0.3; note 6
SDA timing
tSU;DAT
tHD;DAT
tSU;STA
tSU;STO
tBUF
data set-up time
≥ 250 ns
note 2
≥ 250
≥ 0
ns
ns
µs
µs
µs
µs
µs
data hold time
≥ 0 ns
note 2
repeated START set-up time
STOP condition set−up time
bus free time
≥ 14 tCK; note 1
≥ 14 tCK; note 1
≥ 14 tCK; note 1
≤ 1; note 4
note 2
≥ 4.7
≥ 4.0
≥ 4.7
≤ 1.0
≤ 0.3
note 2
note 2
tRD
SDA RISE time
note 5
tFD
SDA FALL time
≤ 300 ns; note 4
≤ 0.3; note 6
Notes
1. At fCLK = 3.5 MHz, this evaluates to 14 × 286 ns = 4 µs, i.e. the bit-level I2C interface can respond to the I2C protocol
for fCLK ≥3.5 MHz.
2. This parameter is determined by the user software, it has to comply with the I2C specification.
3. This value gives the auto-clock pulse length which meets the I2C specification for the specified XTAL1 clock
frequency range. Alternatively, the SCL pulse may be timed by software.
4. Spikes on SDA and SCL lines with a duration of less than 4 × fCLK will be filtered out.
5. The RISE time is determined by the external bus line capacitance and pull-up resistor, it must be ≤1 µs.
6. The maximum capacitance on bus lines SDA and SCL is 400 pF.
1997 Dec 15
58
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
23 XTAL1 CHARACTERISTICS
Oscillator circuitry: crystal capacitors: C1 = C2 = 20 pF (see Fig.31).
Table 36 External clock drive XTAL
VARIABLE CLOCK
UNIT
SYMBOL
fCLK
PARAMETER
clock frequency
MIN.
MAX.
3.5
42
17
17
−
24
MHz
ns
tCK
tHIGH
tLOW
tr
clock period
HIGH time
286
t
CK − tLOW
CK − tHIGH
ns
LOW time
t
ns
RISE time
5
ns
tf
FALL time
−
5
ns
tCY
cycle time (tCY = 12 tCK
)
0.5
3.43
µs
24 SERIAL PORT CHARACTERISTICS
See Table 37 and Fig.32.
Table 37 Serial Port Timing: Shift Register Mode
VDD = 5 V ±10%; VSS = 0 V; Tamb = 0 °C to 70 °C; Load Capacitance = 80 pF
VARIABLE
OSCILLATOR
24 MHZ OSCILLATOR
SYMBOL
PARAMETER
UNIT
MIN.
MAX.
MIN. MAX.
12 tCK
tXLXL
Serial Port clock cycle time
0.5
283
23
0
−
−
−
−
−
−
−
−
µs
ns
ns
ns
tQVXH
tXHQX
tXHDX
tXHDV
output data setup to clock rising edge
output data hold after clock rising edge
input data hold after clock rising edge
clock rising edge to input data valid
10 tCK−133
2 tCK−60
0
−
283
−
10 tCK−133 ns
1997 Dec 15
59
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repeated START condition
START or repeated START condition
START condition
t
STOP condition
SU;STA
t
RD
0.7 V
DD
SDA
(input / output)
0.3 V
DD
t
BUF
t
t
t
FC
RC
FD
t
SU;STO
0.7 V
DD
SCL
(input / output)
0.3 V
DD
t
SU;DAT3
t
t
t
t
t
HD;DAT
HD;STA
LOW
HIGH
SU;DAT1
t
MBC482
SU;DAT2
Fig.27 I2C interface timing.
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
t
LHLL
ALE
t
LLPL
t
t
t
PLPH
AVLL
LLIV
t
PLIV
PSEN
t
t
PXIZ
LLAX
t
t
PLAZ
PXIX
INSTR IN
PORT 0
A0 - A7
A0 - A7
t
AVIV
PORT 2
A8 - A15
A8 - A15
MBC483 - 1
Fig.28 External program memory read cycle.
1997 Dec 15
61
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ALE
t
WHLH
PSEN
t
LLDV
t
t
RLRH
LLWL
RD
t
t
t
t
RHDZ
AVLL
LLAX
RLDV
t
RHDX
A0 - A7
from RI or DPL
PORT 0
DATA IN
A0 - A7 from PCL
INSTR IN
t
AVWL
t
AVDV
PORT 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MBC485 - 1
ahdnbok,uflapegwidt
Fig.29 External data memory read cycle.
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ALE
t
WHLH
PSEN
t
t
WLWH
LLWL
WR
t
t
WHQX
QVWX
t
t
t
AVLL
LLAX
QVWH
A0 - A7
PORT 0
PORT 2
DATA OUT
A0 - A7 from PCL
INSTR IN
from RI or DPL
t
AVWL
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
MBC486 - 1
Fig.30 External data memory write cycle.
ahdnbok,uflapegwidt
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
2.0 V
0.8 V
2.0 V
0.8 V
2.4 V
test points
0.45 V
(a)
float
2.4 V
2.4 V
2.0 V
0.8 V
2.0 V
0.8 V
0.45 V
0.45 V
MBC480
(b)
AC testing inputs are driven at 2.4 V for a logic 1 and 0.45 V for a logic 0. Timing measurements
are taken at 2.0 V for a logic 1 and 0.8 V for logic 0 see (a). The float state is defined as the point
at which a Port 0 pin sinks 3.2 mA or sources 400 µA at the voltage test levels see (b).
Fig.31 AC testing input, output waveform (a) and float waveform (b).
t
t
t
f
HIGH
r
V
V
V
V
IH1
IH1
IH1
IH1
0.8 V
0.8 V
0.8 V
0.8 V
t
LOW
MBC479
t
CK
See Table 36.
Fig.32 External clock drive XTAL1.
64
1997 Dec 15
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
INSTRUCTION
h
0
1
2
3
4
5
6
7
8
ALE
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
t
XHDX
t
XHDV
SET TI
VALID
WRITE TO SBUF
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
MBC475
CLEAR RI
SET RI
See Table 37.
Fig.33 Shift register mode timing waveforms.
1997 Dec 15
65
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
one machine cycle
one machine cycle
a
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
P1 P2
P1 P2
P1 P2
P1 P2
P1 P2
P1 P2
P1 P2
P1 P2
P1 P2
P1 P2
P1 P2
P1 P2
XTAL1
INPUT
ALE
PSEN
RD
dotted lines
are valid when
RD or WR are
active
only active
during a read
from external
data memory
only active
during a write
to external
WR
data memory
BUS
(PORT 0)
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
external
program
memory
fetch
address A8 - A15
address A8 - A15
address A8 - A15
address A8 - A15
PORT 2
address
A0 - A7
address
A0 - A7
address
A0 - A7
BUS
(PORT 0)
inst.
in
inst.
in
data output or data input
read or
write of
external data
memory
address A8 - A15
address A8 - A15 or Port 2 out
address A8 - A15
PORT 2
PORT
OUTPUT
old data
new data
PORT
INPUT
sampling time of I/O port pins during input (including INT0 and INT1)
SERIAL
PORT
CLOCK
MBC487 - 1
Fig.34 Instruction cycle timing.
66
1997 Dec 15
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
25.1 Timing symbol definitions
Oscillator:
fCLK = clock frequency
tCK = clock period
Timing symbols (acronyms):
Each timing symbol has five characters. The first character
is always a 't' (= time). the remaining four characters of the
symbol (typed in subscript), depending on their relative
positions, indicate the name of a signal or the logical status
of that signal. the designations are as follows:
A =address
C = clock
D = input data
H = logic level HIGH
I = instruction (program memory contents)
L = Logic level LOW or ALE
P = PSEN
Q = output data
R = RD signal
t = time
V = valid
W = WR signal
X = no longer a valid logic level
Z = float
Examples:
tAVLL = time for address valid to ALE LOW
tLLPL = time for ALE LOW to PSEN LOW
1997 Dec 15
67
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
26 PACKAGE OUTLINES
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
D
M
E
A
M
2
A
L
A
1
c
e
w
Z
b
1
(e )
1
b
M
H
40
21
pin 1 index
E
1
20
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
w
UNIT
mm
b
b
c
D
E
e
e
L
M
M
1
1
E
H
max.
min.
max.
max.
1.70
1.14
0.53
0.38
0.36
0.23
52.50
51.50
14.1
13.7
3.60
3.05
15.80
15.24
17.42
15.90
4.7
0.51
4.0
2.54
0.10
15.24
0.60
0.254
0.01
2.25
0.067
0.045
0.021
0.015
0.014
0.009
2.067
2.028
0.56
0.54
0.14
0.12
0.62
0.60
0.69
0.63
inches
0.19
0.020
0.16
0.089
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-01-14
SOT129-1
051G08
MO-015AJ
1997 Dec 15
68
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
e
e
D
E
y
X
A
39
29
Z
E
b
p
28
40
b
1
w
M
44
1
H
E
E
pin 1 index
A
A
1
A
4
e
(A )
3
6
18
k
1
β
L
p
k
detail X
7
17
v
M
A
e
Z
D
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
(1)
(1)
A
min.
A
max.
k
1
max.
Z
Z
E
(1)
(1)
1
4
D
UNIT
mm
A
A
b
D
E
e
e
e
H
H
k
L
p
v
w
y
β
b
D
E
D
E
3
p
1
max. max.
4.57
4.19
0.81 16.66 16.66
0.66 16.51 16.51
16.00 16.00 17.65 17.65 1.22
14.99 14.99 17.40 17.40 1.07
1.44
1.02
0.53
0.33
0.51
0.51 0.25 3.05
0.020 0.01 0.12
1.27
0.05
0.18 0.18 0.10 2.16 2.16
o
45
0.180
0.165
0.032 0.656 0.656
0.026 0.650 0.650
0.630 0.630 0.695 0.695 0.048
0.590 0.590 0.685 0.685 0.042
0.057
0.040
0.021
0.013
inches
0.020
0.007 0.007 0.004 0.085 0.085
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-25
SOT187-2
112E10
MO-047AC
1997 Dec 15
69
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
y
X
A
33
23
34
22
Z
E
e
Q
H
E
E
A
2
A
(A )
3
A
1
w M
θ
b
p
L
p
pin 1 index
L
12
44
detail X
1
11
w M
Z
v
M
A
D
b
p
e
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
10o
0o
0.25 1.85
0.05 1.65
0.40 0.25 10.1 10.1
0.20 0.14 9.9 9.9
12.9 12.9
12.3 12.3
0.95 0.85
0.55 0.75
1.2
0.8
1.2
0.8
mm
2.10
0.25
0.8
1.3
0.15 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT307-2
1997 Dec 15
70
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
27 SOLDERING
27.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
27.3.2 WAVE SOLDERING
27.3.2.1 PLCC
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
27.2 DIP
27.2.1 SOLDERING BY DIPPING OR BY WAVE
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
the downstream corners.
27.3.2.2 QFP
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
27.2.2 REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
CAUTION
Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.
If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
27.3 PLCC and QFP
27.3.1 REFLOW SOLDERING
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
Reflow soldering techniques are suitable for all PLCC and
QFP packages.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
The choice of heating method may be influenced by larger
PLCC or QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
1997 Dec 15
71
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
27.3.2.3 Method (PLCC and QFP)
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
27.3.3 REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
28 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of this specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
29 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
30 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Dec 15
72
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
NOTES
1997 Dec 15
73
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
NOTES
1997 Dec 15
74
Philips Semiconductors
Product specification
8-bit microcontrollers
P83C524; P80C528; P83C528
NOTES
1997 Dec 15
75
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,
Fax. +43 160 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Belgium: see The Netherlands
Brazil: see South America
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500
Colombia: see South America
Czech Republic: see Austria
Slovakia: see Austria
Slovenia: see Italy
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Uruguay: see South America
Vietnam: see Singapore
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Middle East: see Italy
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
457047/25/01/pp76
Date of release: 1997 Dec 15
Document order number: 9397 750 02916
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