P83C562EHA [NXP]
8-bit microcontroller; 8位微控制器
| 型号： | P83C562EHA |
| 厂家： | 
NXP |
| 描述： | 8-bit microcontroller |
| 文件： | 总52页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
P83C562; P80C562
8-bit microcontroller
1997 Apr 16
Product specification
File under Integrated Circuits, IC20
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
CONTENTS
13
14
SERIAL I/O
INTERRUPT SYSTEM
1
2
3
4
5
6
FEATURES
14.1
14.2
14.3
14.3.1
14.3.2
14.3.3
14.3.4
Interrupt Vectors
Interrupt priority
GENERAL DESCRIPTION
ORDERING INFORMATION
BLOCK DIAGRAM
Interrupt Enable and Priority Registers
Interrupt Enable Register 0 (IEN0)
Interrupt Enable register 1 (IEN1)
Interrupt priority register 0 (IP0)
Interrupt Priority Register 1 (IP1)
FUNCTIONAL DIAGRAM
PINNING INFORMATION
6.1
6.2
Pinning
Pin description
15
REDUCED POWER MODES
15.1
Idle and Power-down operation
Idle mode
Power-down mode
7
8
FUNCTIONAL DESCRIPTION
MEMORY ORGANIZATION
15.1.1
15.1.2
15.2
Power Control Register (PCON)
8.1
8.2
Program Memory
Addressing
16
OSCILLATOR CIRCUITRY
RESET CIRCUITRY
Power-on-reset
9
I/O FACILITIES
17
10
PULSE WIDTH MODULATED OUTPUTS
17.1
10.1
10.2
10.3
Prescaler Frequency Control Register (PWMP) 18
INSTRUCTION SET
LIMITING VALUES
DC CHARACTERISTICS
AC CHARACTERISTICS
PACKAGE OUTLINES
SOLDERING
Pulse Width Register 0 (PWM0)
Pulse Width Register 1 (PWM1)
19
20
11
ANALOG-TO-DIGITAL CONVERTER (ADC)
21
11.1
11.2
Analog input pins
ADC Control Register (ADCON)
22
23
12
TIMER/ COUNTERS
23.1
Introduction
Reflow soldering
Wave soldering
12.1
12.2
Timer 0 and Timer 1
23.2
23.3
23.4
Timer T2 Capture and Compare Logic
T2 Control Register (TM2CON)
Capture Control Register (CTCON)
Interrupt Flag Register (TM2IR)
Set Enable Register (STE)
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.3
Repairing soldered joints
24
25
DEFINITIONS
LIFE SUPPORT APPLICATIONS
Reset/Toggle Enable register (RTE)
Watchdog Timer (T3)
1997 Apr 08
2
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
This I/O intensive device provides architectural
1
FEATURES
enhancements to function as a controller in the field of
automotive electronics, specifically engine management
and gear box control.
• 80C51 Central Processing Unit
• 8 kbytes ROM, expandable externally to 64 kbytes
• 256 bytes RAM, expandable externally to 64 kbytes
• Two standard 16-bit timer/counters
The P8xC562 contains a non-volatile 8 kbyte read only
program memory, a volatile 256 byte read/write data
memory, six 8-bit I/O ports, two 16-bit timer/event counters
(identical to the timers of the 80C51), an additional 16-bit
timer coupled to capture and compare latches, a
fourteen-source, two-priority-level, nested interrupt
structure, an 8-input ADC, a dual DAC with pulse width
modulated outputs, a serial interface (UART), a
Watchdog Timer and on-chip oscillator and timing circuits.
For systems that require extra capability, the P8xC562 can
be expanded using standard TTL compatible memories
and logic.
• An additional 16-bit timer/counter coupled to four
capture registers and three compare registers
• An 8-bit ADC with 8 multiplexed analog inputs
• Two 8-bit resolution, Pulse Width Modulated outputs
• Five 8-bit I/O ports plus one 8-bit input port shared with
analog inputs
• Full-duplex UART compatible with the standard 80C51
• On-chip Watchdog Timer
• Oscillator frequency: 3.5 to 16 MHz.
The device also functions as an arithmetic processor
having facilities for both binary and BCD arithmetic plus
bit-handling capabilities. The instruction set consists of
over 100 instructions: 49 one-byte, 45 two-byte and
17 three-byte. With a 16 MHz crystal, 58% of the
instructions are executed in 0.75 µs and 40% in 1.5 µs.
Multiply and divide instructions require 3 µs.
2
GENERAL DESCRIPTION
The P80C562/P83C562 (hereafter generally referred to as
P8xC562) single-chip 8-bit microcontroller is
manufactured in an advanced CMOS process and is a
derivative of the 80C51 microcontroller family.
The P8xC562 has the same instruction set as the 80C51.
Two versions of the derivative exist:
• With 8 kbytes mask-programmable ROM
• ROMless version of the P8xC562.
3
ORDERING INFORMATION
PACKAGE
FREQUENCY TEMPERATURE
TYPE NUMBER
NAME
RANGE (MHz)
RANGE (°C)
DESCRIPTION
VERSION
P80CE562EHA(1)
P80C562EBA(1)
PLCC68 plastic leaded chip carrier; 68 leads SOT188-2
3.5 to 16
−40 to +125
0 to +70
P80C562EFA(1)
−40 to +85
−40 to +125
0 to +70
P83C562EHA/nnn(2)
P83C562EBA/nnn(2)
P83C562EFA/nnn(2)
−40 to +85
Notes
1. ROMless type.
2. ROM coded type; nnn denotes the ROM code number.
1997 Apr 08
3
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
4
BLOCK DIAGRAM
BM3H48
a k , f u l l p a g e w i d t h
1997 Apr 08
4
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
5
FUNCTIONAL DIAGRAM
alternative function
XTAL1
XTAL2
0
1
2
3
4
5
6
7
AD0
AD1
AD2
LOW ORDER
ADDRESS
AND
EA
PSEN
ALE
AD3
AD4
AD5
AD6
AD7
PORT 0
PORT 1
PORT 2
PORT 3
DATA BUS
PWM0
PWM1
0
1
2
3
4
5
6
7
CT0I
CT1I
CT2I
CT3I
T2
AV
SS
AV
DD
AV
REF +
REF −
AV
RT2
alternative function
STADC
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
0
1
2
3
0
1
2
3
4
5
6
7
A8
A9
P8xC562
A10
A11
A12
A13
A14
A15
HIGH ORDER
ADDRESS
BUS
PORT 5
4
5
6
7
RXD/DATA
TXD/CLOCK
INT0
CMSR0
CMSR1
CMSR2
CMSR3
CMSR4
CMSR5
CMT0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
INT1
PORT 4
T0
T1
WR
RD
CMT1
V
RST
EW
SS
V
DD
MBH347
Fig.2 Functional diagram.
5
1997 Apr 08
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
6
PINNING INFORMATION
Pinning
6.1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
AV
SS
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
P4.3/CMSR3
AV
P4.4/CMSR4
REF+
REF−
AV
P4.5/CMSR5
P4.6/CMT0
P4.7/CMT1
RST
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
P1.0/CT0I
P1.1/CT1I
P1.2/CT2I
P1.3/CT3I
P1.4/T2
P8xC562
P1.5/RT2
P1.6
ALE
PSEN
P1.7
P3.0/RXD
P3.1/TXD
P3.2/INT0
P2.7/A15
P2.6/A14
P2.5/A13
MBH349
Fig.3 Pinning configuration for PLCC68 (SOT188-2) package.
1997 Apr 08
6
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
6.2
Table 1 PLCC68 (SOT188-2)
To avoid latch-up at Power-on, the voltage at any pin at any time must lie within the range VDD + 0.5 V to VSS − 0.5 V.
Pin description
SYMBOL
VDD
PIN
DESCRIPTION
2
Power supply, digital part (+5 V). Power supply pins during normal operation and
power reduction modes.
STADC
3
Start ADC operation: Input starting analog-to-digital conversion (ADC operation can
also be started by software). This pin must not float.
PWM0
PWM1
EW
4
5
6
Pulse Width Modulation output 0.
Pulse Width Modulation output 1.
Enable Watchdog Timer: enable for Watchdog Timer and disable Power-down mode.
This pin must not float.
P4.0/CMSR0
to
7 to 12 P4.0 to P4.5: 8-bit quasi-bidirectional I/O port lines;
CMSR0 to CMSR5: Compare and Set/Reset outputs for Timer T2.
P4.5/CMSR5
P4.6/CMT0
P4.7/CMT1
RST
13
14
15
P4.6 to P4.7: 8-bit quasi-bidirectional I/O port lines;
CMT0 to CMT1: Compare and toggle outputs for Timer T2.
Reset: Input to reset the P8x562; also generated when the Watchdog Timer overflows.
P1.0/CT0I
to
16 to 19 P1.0 to P1.3: 8-bit quasi-bidirectional I/O port lines;
CT0I to CT3I: Capture timer inputs for Timer 2.
P1.3/CT3I
P1.4/T2
20
21
P1.4: 8-bit quasi-bidirectional I/O port line;
T2: T2 event input (rising edge triggered).
P1.5/RT2
P1.5: 8-bit quasi-bidirectional I/O port line;
RT2: T2 timer reset input (rising edge triggered)
P1.6 to P1.7
P3.0/RXD
22 to 23 P1.6 to P1.7: 8-bit quasi-bidirectional I/O port lines, open-drain.
24
25
26
27
28
29
30
31
P3.0: 8-bit quasi-bidirectional I/O port line;
RXD: Serial input port.
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.1: 8-bit quasi-bidirectional I/O port line;
TXD: Serial output port.
P3.2: 8-bit quasi-bidirectional I/O port line;
INT0: External interrupt input 0.
P3.3: 8-bit quasi-bidirectional I/O port line;
INT1: External interrupt input 1.
P3.4: 8-bit quasi-bidirectional I/O port line;
T0: Timer 0 external input.
P3.5/T1
P3.5: 8-bit quasi-bidirectional I/O port line;
T1: Timer 1 external input.
P3.6/WR
P3.7/RD
P3.6: 8-bit quasi-bidirectional I/O port line;
WR: External Data Memory Write strobe.
P3.7: 8-bit quasi-bidirectional I/O port line;
RD: External Data Memory Read strobe.
n.c.
32, 33
34
Not connected.
XTAL2
Crystal Oscillator Output: output of the inverting amplifier that forms the oscillator.
Left open-circuit when an external oscillator clock is used.
1997 Apr 08
7
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
SYMBOL
XTAL1
PIN
DESCRIPTION
35
Crystal Oscillator Input: input to the inverting amplifier that forms the oscillator, and
input to the internal clock generator. Receives the external oscillator clock signal when
an external oscillator is used.
VSS
n.c.
36, 37
38
Digital ground pins.
Not connected.
P2.0/A08
to
39 to 46 P2.0 to P2.7: 8-bit quasi-bidirectional I/O port lines;
A08 to A15: High-order address byte for external memory.
P2.7/A15
PSEN
47
Program Store Enable: read strobe to the external program memory via Port 0 and 2.
Is activated twice each machine cycle during fetches from external program memory.
When executing out of external program memory two activations of PSEN are skipped
during each access to external data memory. PSEN is not activated (remains HIGH)
during no fetches from external program memory. PSEN can sink/source 8 LSTTL
inputs and can drive CMOS inputs without external pull-ups.
ALE
EA
48
49
Address Latch Enable: latches the low byte of the address during access of external
memory in normal operation. It is activated every six oscillator periods except during an
external data memory access. ALE can sink/source 8 LSTTL inputs and can drive
CMOS inputs without an external pull-up. To prohibit the toggling of the ALE pin (RFI
noise reduction) the RFI bit in the Power Control Register must be set by software.
External Access: if, during RESET, EA is HIGH the CPU executes out of the internal
program memory provided the program Counter is less than 8192. If, during RESET,
EA is LOW the CPU executes out of external program memory via Port 0 and Port 2.
EA is not allowed to float. EA is latched during RESET and don’t care after RESET.
P0.7/AD7
to
50 to 57 P0.7 to P0.0: 8-bit open drain bidirectional I/O port lines;
AD7 to AD0: Multiplexed Low-order address and Data bus for external memory.
P0.0/AD0
AVREF-
AVREF+
AVSS
58
59
60
61
Low-end of ADC (analog-to-digital conversion) reference resistor.
High-end of ADC (analog-to-digital conversion) reference resistor.
Ground, analog part. For ADC receiver and reference voltage.
Power supply, analog part (+5 V). For ADC receiver and reference voltage.
AVDD
P5.7/ADC7
to
62 to 68, P5.7 to P5.0: 8-bit input port lines;
1
ADC7 to ADC0: eight analog ADC inputs
P5.0/ADC0
1997 Apr 08
8
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
The P8xC562 contains 256 bytes of internal data RAM
and 52 Special Function Registers. It provides a
non-paged program memory address space to
accommodate relocatable code. Conditional branches are
performed relative to the Program Counter.
The register-indirect jump permits branching relative to a
16-bit base register with an offset provided by an 8-bit
index register. 16-bit jumps and calls permit branching to
any location in the contiguous 64 kbyte program memory
address space.
7
FUNCTIONAL DESCRIPTION
The P8xC562 is a stand-alone high-performance
microcontroller designed for use in real-time applications
such as instrumentation, industrial control and specific
automotive control applications.
In addition to the 80C51 standard functions, the device
provides a number of dedicated hardware functions for
these applications.
The P8xC562 is a control-oriented CPU with on-chip
program and data memory. It can be extended with
external program memory up to 64 kbytes. It can also
access up to 64 kbytes of external data memory.
For systems requiring extra capability, the P8xC562 can
be expanded using standard memories and peripherals.
8.1
Program Memory
The program memory address space of the P83C562
consists of internal and external memory. The P83C562
has 8 kbytes of program memory on-chip. The program
memory can be externally expanded up to 64 kbytes. If the
EA pin is held HIGH, the P83C562 executes out of the
internal program memory unless the address exceeds
1FFFH then locations 2000H through to 0FFFFH are
fetched from the external program memory. If the EA pin is
held LOW, the P83C562 fetches all instructions from the
external memory. Figure 4 illustrates the program
memory address space.
The P8xC562 has two software selectable modes of
reduced activity for further power reduction − Idle and
Power-down. The Idle mode freezes the CPU while
allowing the RAM, timers, serial ports and interrupt system
to continue functioning. The Power-down mode saves the
RAM contents but freezes the oscillator causing all other
chip functions to be inoperative.
By setting a mask programmable security bit (i.e. user
dependent) the ROM content is protected i.e. it cannot be
read at any time by any test mode or by any instruction in
the external program memory space. The MOVC
instructions are the only ones which have access to
program code in the internal or external program memory.
The EA input is latched during reset and is ‘don’t care’ after
reset. This implementation prevents from reading internal
program code by switching from the external program
memory to internal program memory during MOVC
instruction or an instruction that handles immediate data.
Table 2 lists the access to internal and external program
memory by the MOVC instructions when the security bit
has been set to a logic 1. If the security bit has been set to
a logic 0 there are no restrictions for the MOVC
instructions.
8
MEMORY ORGANIZATION
The Central Processing Unit (CPU) manipulates operands
in three memory spaces; these are the 64 kbyte external
data memory, 256 byte internal data memory and the
64 kbyte internal and external program memory.
The internal data memory is divided into 3 sections: the
lower 128 bytes of RAM, the upper 128 bytes of RAM and
the 128 byte Special Function Register memory
(see Fig.4). Figure 5 shows the Special Function
Registers memory map. Internal RAM locations 0 to 127
are directly and indirectly addressable. Internal RAM
locations 128 to 155 are only indirectly addressable.
The Special Function Register locations 128 to 255 are
only directly addressable.
The internal data RAM contains four register banks (each
with eight registers), 128 addressable bits, a scratch pad
area and the stack. The stack depth is limited by the
available internal data RAM and its location is determined
by the 8-bit Stack Pointer. All registers except the Program
Counter and the four 8-register banks reside in the
Special Function Register address space. These memory
mapped registers include arithmetic registers, pointers,
I/O ports, interrupt system registers, ADC and PWM
registers, timers and serial port registers. There are
120 addressable bit locations in the SFR address space.
Table 2 Memory access by the MOVC instruction
PROGRAM MEMORY ACCESS
MOVC
INSTRUCTION
INTERNAL
EXTERNAL
MOVC in internal
program memory
YES
YES
MOVC in external
program memory
NO
YES
1997 Apr 08
9
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
• 256 bytes of internal data RAM through Direct or
Register-Indirect. Bytes 0 to 127 may be addressed
directly/indirectly. Bytes 128 to 155 share their address
locations with the SFR registers and so may only be
addressed indirectly as data RAM
8.2
Addressing
The P8xC562 has five methods for addressing source
operands:
• Register
• Direct
• Special Function Registers through Direct at address
locations 128 to 255
• Register-Indirect
• External data memory through Register-Indirect
• Immediate
• Program memory look-up tables through Base-Register
• Base-Register plus Index-Register-Indirect.
plus Index-Register-Indirect.
The first three methods can be used for addressing
destination operands. Most instructions have a
'destination/source' field that specifies the data type,
addressing methods and operands involved.
For operations other than MOVs, the destination operand
is also a source operand.
The P8xC562 is classified as an 8-bit device since the
internal ROM, RAM, Special Function Registers,
Arithmetic Logic Unit and external data bus are all 8-bits
wide. It performs operations on bit, nibble, byte and
double-byte data types.
Facilities are available for byte transfer, logic and integer
arithmetic operations. Data transfer, logic and conditional
branch operations can be performed directly on Boolean
variables to provide excellent bit handling.
Access to memory addressing is as follows:
• Registers in one of the four 8-register banks through
Register, Direct or Register-Indirect
64K
EXTERNAL
64K
8192
8191
8191
OVERLAPPED SPACE
SPECIAL
255
127
0
INTERNAL
(EA = 1)
EXTERNAL
(EA = 0)
FUNCTION
REGISTERS
INDIRECT ONLY
DIRECT AND
INDIRECT
0
0
0
EXTERNAL
DATA MEMORY
INTERNAL DATA MEMORY
PROGRAM MEMORY
MBC745
Fig.4 Memory map.
10
1997 Apr 08
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
DIRECT
BYTE
ADDRESS (HEX)
REGISTER
MNEMONIC
BIT ADDRESS
T3
PWMP
PWM1
PWM0
FFH
FEH
FDH
FCH
IP1
FF FE FD FC FB FA F9 F8
F7 F6 F5 F4 F3 F2 F1 F0
F8H
F0H
EFH
EEH
EDH
ECH
EBH
EAH
B
RTE
STE
# TMH2
# TML2
CTCON
TM2CON
IEN1
ACC
EF EE ED EC EB EA E9 E8 E8H
E7 E6 E5 E4 E3 E2 E1 E0 E0H
DBH
SFRs containing
directly addressable
bits
DAH
2
Reserved for I C-bus
D9H
D8H
PSW
# CTH3
# CTH2
# CTH1
# CTH0
CMH2
D7 D6 D5 D4 D3 D2 D1 D0 D0H
CFH
CEH
CDH
CCH
CBH
CAH
C9H
CMH1
CMH0
C8H
TM2IR
CF CE CD CC CB CA C9 C8
# ADCH
ADCON
# P5
C6H
C5H
C4H
P4
C7 C6 C5 C4 C3 C2 C1 C0
C0H
MBH346
# denotes read-only registers
Fig.5 Special Function Register memory map.
11
1997 Apr 08
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
DIRECT
BYTE
ADDRESS (HEX)
REGISTER
MNEMONIC
BIT ADDRESS
IP0
BF BE BD BC BB BA B9 B8 B8H
P3
# CTL3
# CTL2
# CTL1
# CTL0
CML2
B7 B6 B5 B4 B3 B2 B1 B0 B0H
AFH
AEH
ADH
ACH
ABH
CML1
AAH
A9H
CML0
IEN0
AF AE AD AC AB AA A9 A8 A8H
P2
A7 A6 A5 A4 A3 A2 A1 A0 A0H
SFRs containing
directly addressable
bits
S0BUF
S0CON
99H
98H
9F 9E 9D 9C 9B 9A 99 98
P1
97 96 95 94 93 92 91 90 90H
TH1
TH0
8DH
8CH
TL1
8BH
8AH
89H
TL0
TMOD
TCON
PCON
8F 8E 8D 8C 8B 8A 89 88
88H
87H
DPH
DPL
SP
83H
82H
81H
80H
P0
87 86 85 84 83 82 81 80
# denotes read-only registers
MGA151
Fig.6 Special Function Register memory map (continued).
12
1997 Apr 08
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
Port 4 Can be configured to provide signals indicating a
match between timer counter T2 and its compare
registers.
9
I/O FACILITIES
The P8xC562 has six 8-bit ports. Ports 0 to 3 are the same
as in the 80C51, with the exception of the additional
functions of Port 1. The parallel I/O function of Port 4 is
equal to that of Ports 1, 2 and 3. Port 5 has a parallel input
port function, but has no function as an output port.
Port 5 May be used in conjunction with the ADC interface.
Unused analog inputs can be used as digital inputs.
As Port 5 lines may be used as inputs to the ADC,
these digital inputs have an inherent hysteresis to
prevent the input logic from drawing too much
current from the power lines when driven by analog
signals. Channel-to-channel crosstalk should be
taken into consideration when both digital and
analog signals are simultaneously input to Port 5
(see Chapter 20).
Ports 0 to 5 perform the following alternative functions:
Port 0 Provides the multiplexed low-order address and
data bus used for expanding the P8xC562 with
standard memories and peripherals.
Port 1 is used for a number of special functions:
• 4 capture inputs (or external interrupt request inputs if
capture information is not utilized)
All ports are bidirectional with the exception of Port 5 which
is an input port. Alternative function bits which are not used
may be used as normal bidirectional I/O pins.
The generation or use of a Port 1, Port 3 or Port 4 pin as
an alternative function is carried out automatically by the
P8xC562 provided the associated Special Function
Register bit is set HIGH.
• External counter input
• External counter reset input.
Port 2 Provides the high-order address bus when
expanding the P8xC562 with external program
memory and/or external data memory.
In addition to the standard 8-bit ports, the I/O facilities of
the P8xC562 also include a number of special I/O lines.
Port 3 Pins can be configured individually to provide:
• External interrupt request inputs
• Counter inputs
• Serial port receiver input and transmitter output
• Control signals to READ and WRITE external data
memory.
+5 V
strong pull-up
2 oscillator
periods
p2
p3
p1
n
I/O PIN
PORT
Q
from port latch
I1
input data
read port pin
INPUT
BUFFER
MLA513
Fig.7 I/O buffers in the P8xC562 (Ports 2, 3, 4 and P1.0 to P1.5).
1997 Apr 08
13
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
The pulse width ratio is in the range of 0 to 255/255 and
may be programmed in increments of 1/255.
10 PULSE WIDTH MODULATED OUTPUTS
Two pulse width modulated output channels are provided
with the P8xC562. These channels output pulses of
programmable length and interval. The repetition
frequency is defined by an 8-bit prescaler PWMP which
generates the clock for the counter. Both the prescaler and
counter are common to both PWM channels. The 8-bit
counter counts modulo 255 i.e. from 0 to 254 inclusive.
The value of the 8-bit counter is compared to the contents
of two registers: PWM0 and PWM1.
The repetition frequency fPWM, at the PWMn outputs is
fOSC
given by: fPWM
=
------------------------------------------------------------
2 × (1 + PWMP) × 255
When using an oscillator frequency of 16 MHz for
example, the above formula would give a repetition
frequency range of 123 Hz to 31.4 kHz.
By loading the PWM registers with either 00H or FFH, the
PWM outputs can be retained at a constant HIGH or LOW
level respectively. When loading FFH to the PWM
registers, the 8-bit counter will never actually reach this
value. Both PWMn output pins are driven by push-pull
drivers, and are not shared with any other function.
Provided the contents of either of these registers is greater
than the counter value, the output of PWM0 or PWM1 is
set LOW. If the contents of these registers are equal to, or
less than the counter value, the output will be HIGH.
The pulse width ratio is therefore defined by the contents
of the registers PWM0 and PWM1.
PMW0
I
N
T
OUTPUT
BUFFER
8-BIT COMPARATOR
PWM0
E
R
N
A
L
B
U
S
f
osc
8-BIT COUNTER
PRESCALER
PWMP
1/2
8-BIT
COMPARATOR
OUTPUT
BUFFER
PWM1
PWM1
MBC746
Fig.8 Functional diagram of Pulse Width Modulated outputs.
1997 Apr 08
14
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
10.1 Prescaler Frequency Control Register (PWMP)
Table 3 Prescaler Frequency Control Register (SFR address FEH)
7
6
5
4
3
2
1
0
PWMP.7
PWMP.6
PWMP.5
PWMP.4
PWMP.3
PWMP.2
PWMP.1
PWMP.0
Table 4 Description of PWMP bits
BIT
SYMBOL
DESCRIPTION
7
to
0
PWMP.7
to
PWMP.0
Prescaler division factor.
The prescaler division factor = (PWMP) + 1.
10.2 Pulse Width Register 0 (PWM0)
Table 5 Pulse Width Register 0 (SFR address FCH)
7
6
5
4
3
2
1
0
PWM0.7
PWM0.6
PWM0.5
PWM0.4
PWM0.3
PWM0.2
PWM0.1
PWM0.0
Table 6 Description of PWM0 bits
BIT
SYMBOL
DESCRIPTION
7
to
0
PWM0.7
to
PWM0.0
Pulse width ratio.
LOW/HIGH ratio of PWMn signals
(PWMn)
=
-----------------------------------------
255 – (PWMn)
10.3 Pulse Width Register 1 (PWM1)
Table 7 Pulse Width Register 1 (SFR address FDH)
7
6
5
4
3
2
1
0
PWM1.7
PWM1.6
PWM1.5
PWM1.4
PWM1.3
PWM1.2
PWM1.1
PWM1.0
Table 8 Description of PWM1 bits
BIT
SYMBOL
DESCRIPTION
7
to
0
PWM1.7
to
PWM1.0
Pulse width ratio.
LOW/HIGH ratio of PWMn signals
(PWMn)
=
-----------------------------------------
255 – (PWMn)
1997 Apr 08
15
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
11 ANALOG-TO-DIGITAL CONVERTER (ADC)
11.1 Analog input pins
The completion of the 8-bit ADC conversion is flagged by
ADCI in the ADCON register and the result is stored in
Special Function Register ADCH.
The analog input circuitry consists of an 8-input analog
multiplexer and an ADC with 8-bit resolution. The analog
reference voltage and analog power supplies are
connected via separate input pins. The conversion takes
24 machine cycles i.e. 18 µs at an oscillator frequency of
16 MHz.
An ADC conversion in progress is unaffected by an
external or software ADC start. The result of a completed
conversion remains unaffected provided ADCI = 1. While
ADCS = 1 or ADCI = 1, a new ADC start will be blocked
and consequently lost.
The ADC is controlled using the ADC Control Register
(ADCON). Input channels are selected by the analog
multiplexer, using bits AADR.0 to AADR.2 in ADCON.
An ADC conversion already in progress is aborted when
the Idle or Power-down mode is entered. The result of a
completed conversion (ADCI = 1) remains unaffected
when entering the Idle mode.
If ADCI is cleared by software and ADCS is set at the same
time, a new analog-to-digital conversion with the same
channel number, may be started. However, it is
recommended to reset ADCI before ADCS is set.
STADC
ADC0
ADC1
ADC2
analog reference
ADC3
ADC4
ADC5
ADC6
ADC7
ANALOG INPUT
MULTIPLEXER
8-BIT ADC
supply (analog part)
ground (analog part)
ADCON
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
ADCH
INTERNAL BUS
MBH350
Fig.9 Functional diagram of analog input.
1997 Apr 08
16
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
11.2 ADC Control Register (ADCON)
Table 9 ADC Control Register (SFR address C5H)
7
6
5
4
3
2
1
0
−
−
ADEX
ADCI
ADCS
AADR2
AADR1
AADR0
Table 10 Description of ADCON bits
BIT
SYMBOL
DESCRIPTION
7
6
5
−
−
These two bits are reserved.
ADEX
Enable external start: start of conversion by STADC. If ADEX = 0, then conversion
can not be started externally by STADC (only by software by setting ADCS).
If ADEX = 1, then conversion can be started externally by a rising edge on STADC or by
software.
4
3
ADCI
ADC interrupt flag: this flag is set when an analog-to-digital conversion result is ready
to be read. An interrupt is invoked if it is enabled. The flag must be cleared by the
interrupt service routine. While this flag is set, the ADC cannot start a new conversion.
ADCI cannot be set by software.
ADCS
ADC start and status: setting this bit starts an ADC conversion. It may be set by
software or by the external signal STADC. The ADC logic ensures that this signal is
HIGH while the ADC is busy. On completion of the conversion, ADCS is reset
immediately after the interrupt flag has been set. ADCS can not be reset by software nor
can a new conversion be started if either ADCS or ADCI is HIGH.
2
1
0
AADR.2
AADR.1
AADR.0
Analog input select: these three bits are used to select one of the eight analog inputs
of Port 5, for conversion. A selection can only be made when ADCI and ADCS are both
LOW. AADR2 is the most significant bit (e.g. 100 selects the ADC4 analog input
channel).
Table 11 Function of ADCI and ADCS bits
ADCI
ADCS
OPERATION
ADC not busy, a conversion can be started.
0
0
1
1
0
1
0
1
ADC busy, start of a new conversion is blocked.
Conversion completed; start of a new conversion is blocked.
Intermediate status for a maximum of one machine cycle before conversion is
completed.
1997 Apr 08
17
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
12 TIMER/ COUNTERS
12.2 Timer T2 Capture and Compare Logic
The P8xC562 contains:
Timer T2 is a 16-bit timer/counter which has, coupled to it,
capture and compare facilities. The operational diagram is
shown in Fig.10.
• Three 16-bit timer/event counters: Timer 0, Timer 1 and
Timer 2
The 16-bit timer/counter is clocked via a prescaler with a
programmable division factor of 1, 2, 4 or 8. The input of
the prescaler is clocked with 1⁄12 of the oscillator
frequency, or with positive edges on the T2 input, or it is
switched to the off position. The prescaler is cleared if its
division factor or its input source is changed, or if the
timer/counter is reset. T2 is readable on-the-fly, but
possesses no extra read latches; this means that software
precautions have to be taken against misinterpretation on
overflow from least to most significant byte during a read.
T2 is not loadable and is reset by the RST signal or at the
positive edge of the input signal RT2, if enabled. In the Idle
mode the timer/counter and prescaler are reset and
halted.
• One 8-bit Watchdog Timer.
12.1 Timer 0 and Timer 1
Timer 0 and Timer 1 may be programmed to carry out the
following operations:
• Measure time intervals and pulse durations
• Count events
• Generate interrupt requests.
Timer 0 and Timer 1 can also be programmed
independently to operate in three modes:
Mode 0 8-bit timer or 8-bit counter each with
divide-by-32 prescaler
T2 is connected to four 16-bit Capture Registers: CT0,
CT1, CT2 and CT3. These registers are loaded with the
contents of T2 and an interrupt is requested upon receipt
of the input signals CT0I, CT1I, CT2I or CT3I. These input
signals are shared with Port 1. Using the Capture Register
(CTCON), these inputs may invoke capture and interrupt
request on a positive or negative edge or on both edges.
If neither a positive nor a negative edge is selected for a
capture input, no capture or interrupt request can be
generated by this input.
Mode 1 16-bit time-interval or event counter
Mode 2 8-bit time-interval or event counter with automatic
reload upon overflow.
Timer 0 can be programmed to operate in an additional
mode as follows:
Mode 3 one 8-bit time-interval or event counter and one
8-bit time-interval counter.
When Timer 0 is in Mode 3, Timer 1 can be programmed
to operate in Modes 0, 1 or 2 but cannot set an interrupt
request flag or generate an interrupt. However, the
overflow from Timer 1 can be used to pulse the serial port
transmission-rate generator.
The contents of the Compare Registers CM0, CM1 and
CM2 are continually compared with the counter value of
Timer 2. When a match is found an interrupt may be
invoked. Using the match signal of CM0, the controller sets
bits 0 to 5 of Port 4, if the corresponding bits of the Set
Enable Register are logic 1s.
The frequency handling range of these counters with a
16 MHz crystal is as follows:
Considering a match with CM1, if the corresponding bits of
the Reset/toggle Enable Register (RTE) are logic 1, then
the controller will use the match signal to reset bits 0 to 5
of Port 4. Bits 6 and 7 of Port 4 may be toggled by the
signal that indicates a match of Timer T2 and CM2 if the
corresponding bits of RTE are logic 1. CM0, CM1 and CM2
are reset by the RST signal.
• In the timer function, the timer is incremented at a
frequency of 1.33 MHz; a division by 12 of the oscillator
frequency
• 0 Hz to an upper limit of 0.66 MHz when programmed
for external inputs.
Both internal and external inputs can be gated to the
counter by a second external source for directly measuring
pulse durations.
Port 4 can be read and written by software without
affecting the toggle, set and reset signals. At byte overflow
of the least significant byte, or at a 16-bit overflow of the
timer/counter, an interrupt sharing the same interrupt
vector is requested. Either one or both of these overflows
can be programmed to request an interrupt.
The counters are started and stopped under software
control. Each one sets its interrupt request flag when it
overflows from all logic 1s to all logic 0s (or automatic
reload value), with the exception of Mode 3 as previously
described.
All interrupt flags must be reset by software.
1997 Apr 08
18
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
CT0I
INT
CT1I
INT
CT2I
INT
CT3I
INT
CTI0
CTI1
CTI2
CTI3
CT0
CT1
CT2
CT3
off
8-bit overflow interrupt
16-bit overflow interrupt
f
1/12
osc
PRESCALER
T2 COUNTER
T2
RT2
T2ER
external reset
enable
COMP
COMP
COMP
INT
INT
INT
S
S
R
R
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
CM0 (S)
CM2 (T)
CM1 (R)
S
S
S
S
R
R
R
R
T
I/O port 4
MBC755
TG
TG
T
STE
RTE
S
R
T
= set
= reset
= toggle
T2 SFR address: TML2 = lower 8 bits
TMH2 = higher 8 bits
TG = toggle status
Fig.10 Block diagram of Timer T2 configuration.
1997 Apr 08
19
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
12.2.1 T2 CONTROL REGISTER (TM2CON)
Table 12 T2 Control Register (SFR address EAH)
7
6
5
4
3
2
1
0
T2IS1
T2IS0
T2ER
T2B0
T2P1
T2P0
T2MS1
T2MS0
Table 13 Description of TM2CON bits
BIT
SYMBOL
T2IS1
DESCRIPTION
7
6
5
4
3
2
1
0
Timer 2 16-bit overflow interrupt select.
Timer 2 byte overflow interrupt select.
Timer 2 external reset enable.
T2IS0
T2ER
T2B0
Timer 2 byte overflow interrupt flag.
Timer 2 prescaler select (see Table 14).
T2P1
T2P0
T2MS1
T2MS0
Timer 2 mode select (see Table 15).
Table 14 Timer 2 prescaler select
T2P1
T2P0
T2 CLOCK
0
0
1
1
0
1
0
1
Clock source
1⁄2 clock source
1⁄4 clock source
1⁄8 clock source
Table 15 Timer 2 mode select
T2MS1
T2MS0
MODE
0
0
1
1
0
1
0
1
Timer T2 is halted
T2 clock source = 1⁄12 × fOSC
Test mode; do not use
T2 clock source = pin T2
1997 Apr 08
20
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
12.2.2 CAPTURE CONTROL REGISTER (CTCON)
Table 16 Capture Control Register (SFR address EBH)
7
6
5
4
3
2
1
0
CTN3
CTP3
CTN2
CTP2
CTN1
CTP1
CTN0
CTP0
Table 17 Description of CTCON bits
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
CTN3
CTP3
CTN2
CTP2
CTN1
CTP1
CTN0
CTP0
Interrupt triggered on negative edge of CT3I.
Interrupt triggered on positive edge of CT3I.
Interrupt triggered on negative edge of CT2I.
Interrupt triggered on positive edge of CT2I
Interrupt triggered on negative edge of CT1I.
Interrupt triggered on positive edge of CT1I.
Interrupt triggered on negative edge of CT0I.
Interrupt triggered on positive edge of CT0I.
12.2.3 INTERRUPT FLAG REGISTER (TM2IR)
Table 18 Interrupt Flag Register (SFR address C8H)
7
6
5
4
3
2
1
0
T2OV
CMI2
CMI1
CMI0
CTI3
CTI2
CTI1
CTI0
Table 19 Description of TM2IR bits (see notes 1 and 2)
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
T2OV
CMI2
CMI1
CMI0
CTI3
CTI2
CTI1
CTI0
T2: 16-bit overflow interrupt flag.
CM2: interrupt flag.
CM1: interrupt flag.
CM0: interrupt flag.
CT3: interrupt flag.
CT2: interrupt flag.
CT1: interrupt flag.
CT0: interrupt flag.
Notes
1. Interrupt Enable Register 1 (IEN1) is used to enable/disable Timer 2 interrupts.
2. Interrupt Priority Register 1 (IP1) is used to determine the Timer 2 interrupt priority.
1997 Apr 08
21
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
12.2.4 SET ENABLE REGISTER (STE)
Table 20 Set Enable Register (SFR address EEH)
7
6
5
4
3
2
1
0
TG47
TG46
SP45
SP44
SP43
SP42
SP41
SP40
Table 21 Description of STE bits (see notes 1 and 2)
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
TG47
TG46
SP45
SP44
SP43
SP42
SP41
SP40
If HIGH then P4.7 is reset on the next toggle, if LOW P4.7 is set on the next toggle.
If HIGH then P4.6 is reset on the next toggle, if LOW P4.6 is set on the next toggle.
If HIGH the P4.5 is set on a match of CM0 and T2.
If HIGH the P4.4 is set on a match of CM0 and T2.
If HIGH the P4.3 is set on a match of CM0 and T2.
If HIGH the P4.2 is set on a match of CM0 and T2.
If HIGH the P4.1 is set on a match of CM0 and T2.
If HIGH the P4.0 is set on a match of CM0 and T2.
Notes
1. If STE.n is LOW then P4.n is not affected by a match of CM0 and T2 (n = 0 to 5).
2. STE.6 and STE.7 are read only.
12.2.5 RESET/TOGGLE ENABLE REGISTER (RTE)
Table 22 Reset/toggle enable register (SFR address EFH)
7
6
5
4
3
2
1
0
TP47
TP46
RP45
RP44
RP43
RP42
RP41
RP40
Table 23 Description of RTE bits (note 1)
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
TP47
TP46
RP45
RP44
RP43
RP42
RP41
RP40
If HIGH then P4.7 toggles on a match of CM2 and T2.
If HIGH then P4.6 toggles on a match of CM2 and T2.
If HIGH then P4.5 is reset on a match of CM1 and T2.
If HIGH then P4.4 is reset on a match of CM1 and T2.
If HIGH then P4.3 is reset on a match of CM1 and T2.
If HIGH then P4.2 is reset on a match of CM1 and T2.
If HIGH then P4.1 is reset on a match of CM1 and T2.
If HIGH then P4.0 is reset on a match of CM1 and T2.
Note
1. If RTE.n is LOW then P4.n is not affected by a match of CM1 and T2 or CM2 and T2. For more information, refer to
the 8051-based “8-bit Microcontrollers Data Handbook IC20”.
1997 Apr 08
22
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
The Watchdog Timer can only be reloaded if the condition
flag WLE in the Power Control Register has been
previously set by software. At the moment the counter is
loaded the condition flag is automatically cleared.
The timer interval between the timer's reloading and
occurrence of a reset, is dependent upon the reloaded
value. For example, this may range from 2 ms to 0.5 s
when using an oscillator frequency of 12 MHz. In the Idle
state the Watchdog Timer and reset circuitry remain
active.
12.3 Watchdog Timer (T3)
In addition to Timer T2 and the standard timers, a
Watchdog Timer is also available, consisting of an 11-bit
prescaler and a 8-bit timer. The functional diagram of the
Watchdog Timer is shown in Fig.11. The timer is
incremented every t seconds,
12 × 2048
t =
-------------------------
where:
fOSC
When a timer overflow occurs, the microcontroller is reset
and a reset output pulse is generated at the RST pin.
The Watchdog Timer is controlled by the Enable
Watchdog pin (EW). A logic 0 enables the Watchdog
Timer and disables the Power-down mode. A logic 1
disables the Watchdog Timer and enables the
Power-down mode.
To prevent a system reset the timer must be reloaded in
time by the application software. If the processor suffers a
hardware/ software malfunction, the software will fail to
reload the timer. This failure will produce a reset upon
overflow thus preventing the processor running out of
control.
INTERNAL BUS
V
DD
PRESCALER
overflow
f
/12
P
osc
TIMER T3 (8-BIT)
11-BIT
LOAD
LOADEN
CLEAR
RST
internal
reset
CLEAR
R
write
T3
RST
WLE
PD
LOADEN
PCON.4
PCON.1
EW
INTERNAL BUS
MBC753
Fig.11 Functional diagram of Watchdog Timer.
1997 Apr 08
23
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
13 SERIAL I/O
14.1 Interrupt Vectors
The P8xC562 is equipped with a full duplex UART port and
is identical to the serial port of the 80C51 (see‘Single-chip
8-bit Microcontrollers User Manual’ .
Table 24 gives the vector address in Program Memory
where the appropriate interrupt service routine is located.
Table 24 Interrupt vectors
14 INTERRUPT SYSTEM
SOURCE
External 0
SYMBOL
VECTOR
X0
0003H
000BH
0013H
001BH
0023H
0033H
003BH
0043H
004BH
0053H
005BH
0063H
006BH
0073H
External events and the real-time driven on-chip
peripherals require service by the CPU asynchronously to
the execution of any particular section of code. To tie the
asynchronous activities of these functions to normal
program execution a multiple-source, two-priority-level,
nested interrupt system is provided. The interrupt system
is shown in Fig.12. Interrupt response latency is from
2.25 µs to 6 µs when using a 16 MHz crystal.
Timer 0 overflow
External 1
T0
X1
Timer 1 overflow
Serial I/O 0 (UART)
T2 capture 0
T1
S0
CT0
CT1
CT2
CT3
ADC
CM0
CM1
CM2
T2
T2 capture 1
The P8xC562 acknowledges interrupt requests from
14 sources as follows:
T2 capture 2
T2 capture 3
• INT0 and INT1: externally via pins P3.2/INT0 and
P3.3/INT1 respectively
ADC completion
T2 compare 0
T2 compare 1
T2 compare 2
T2 overflow
• Timer 0 and Timer 1: from the two internal counters
• Timer T2 (8 separate interrupts): 4 capture interrupts,
3 compare interrupts and an overflow interrupt. If the
Capture Register remains unused and its contents are
'don't care', then the corresponding input pin CTnI may
be used as a positive and/or negative edge triggered
external interrupt.
14.2 Interrupt priority
Each interrupt source can be either high priority or low
priority. If both priorities are requested simultaneously, the
processor will branch to the high priority vector. If there are
simultaneous requests from sources of the same priority,
then interrupts will be serviced in the following order:
• ADC conversion completed interrupt
• UART serial I/O port interrupt.
Each interrupt vectors to a separate location in program
memory for its service routine. Each source can be
individually enabled or disabled by a corresponding bit in
the IEN0 or IEN1 registers, in addition each interrupt may
be programmed to a high or low priority level using the
corresponding bit in the IP0 or IP1 registers. All enabled
sources can be globally disabled or enabled. Both external
interrupts can be programmed to be level-activated or
transition-activated; an active LOW level allows
X0, ADC, T0, CT0, CM0, X1, CT1, CM1, T1, CT2, CM2,
S0, CT3, T2.
A low priority interrupt routine can only be interrupted by a
high priority interrupt. A high priority interrupt routine can
not be interrupted.
'wire-ORing' of several interrupt sources to the input pin.
1997 Apr 08
24
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
interrupt enable registers
source enable global enable
interrupt
interrupt priority
registers
sources
polling hardware
EXTERNAL
INTERRUPT
REQUEST 0
INT0
a1
a2
b1
b2
c1
c2
d1
d2
e1
e2
f1
a1
b1
c1
d1
e1
f1
ADC
TIMER 0
OVERFLOW
g1
h1
i1
high
CT0I
TIMER 2
CAPTURE 0
priority
interrupt
request
j1
TIMER 2
COMPARE 0
k1
l1
EXTERNAL
INTERRUPT
REQUEST 1
INT1
CT1I
m1
n1
o1
f2
g1
g2
h1
h2
i1
vector
SOURCE
IDENTIFICATION
TIMER 2
CAPTURE 1
TIMER 2
COMPARE 1
a2
b2
c2
d2
e2
f2
TIMER 1
OVERFLOW
i2
CT2I
j1
TIMER 2
CAPTURE 2
j2
k1
k2
l1
TIMER 2
COMPARE 2
g2
h2
i2
low
priority
interrupt
request
UART
SERIAL
PORT
T
j2
R
l2
k2
l2
CT3I
m1
m2
n1
n2
TIMER 2
CAPTURE 3
m2
n2
o2
TIMER T2
OVERFLOW
vector
SOURCE
IDENTIFICATION
MBH345
Fig.12 Interrupt system.
25
1997 Apr 08
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
14.3 Interrupt Enable and Priority Registers
14.3.1 INTERRUPT ENABLE REGISTER 0 (IEN0)
Table 25 Interrupt Enable Register 0 (SFR address A8H)
7
6
5
4
3
2
1
0
EA
EAD
−
ES0
ET1
EX1
ET0
EX0
Table 26 Description of IEN0 bits (note 1)
BIT
SYMBOL
DESCRIPTION
7
EA
General enable/disable control. If EA = 0, then no interrupt is enabled. If EA =1, then
any individually enabled interrupt will be accepted.
6
5
4
3
2
1
0
EAD
−
Enable ADC interrupt.
Reserved.
ES0
ET1
EX1
ET0
EX0
Enable SIO (UART) interrupt.
Enable Timer 1 interrupt.
Enable External interrupt.
Enable Timer 0 interrupt.
Enable External 0 interrupt.
Note
1. Logic 0 = interrupt disabled; Logic 1 = interrupt enabled.
14.3.2 INTERRUPT ENABLE REGISTER 1 (IEN1)
Table 27 Interrupt Enable Register 1 (SFR address E8H)
7
6
5
4
3
2
1
0
ET2
ECM2
ECM1
ECM0
ECT3
ECT2
ECT1
ECT0
Table 28 Description of IEN1 bits (note 1)
BIT
7
SYMBOL
ET2
DESCRIPTION
Enable T2 overflow interrupt(s).
6
ECM2
ECM1
ECM0
ECT3
ECT1
ECT1
ECT0
Enable T2 comparator 2 interrupt.
Enable T2 comparator 1 interrupt.
Enable T2 comparator 0 interrupt.
5
4
3
Enable T2 capture register 3 interrupt.
Enable T2 capture register 2 interrupt.
Enable T2 capture register 1 interrupt.
Enable T2 capture register 0 interrupt.
2
1
0
Note
1. Logic 0 = interrupt disabled; Logic 1 = interrupt enabled.
1997 Apr 08
26
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
14.3.3 INTERRUPT PRIORITY REGISTER 0 (IP0)
Table 29 Interrupt Priority Register 0 (SFR address B8H)
7
6
5
4
3
2
1
0
−
PAD
−
PS0
PT1
PX1
PT0
PX0
Table 30 Description of IP0 bits (note 1)
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
−
Reserved.
PAD
−
ADC interrupt priority level.
Reserved.
PS0
PT1
PX1
PT0
PX0
SIO0 (UART) interrupt priority level.
Timer 1 interrupt priority level.
External interrupt 1 priority level.
Timer 0 interrupt priority level.
External interrupt 0 priority level.
Note
1. A logic 0 = low priority; a logic 1 = high priority.
14.3.4 INTERRUPT PRIORITY REGISTER 1 (IP1)
Table 31 Interrupt Priority Register 1 (SFR address F8H)
7
6
5
4
3
2
1
0
PT2
PCM2
PCM1
PCM0
PCT3
PCT2
PCT1
PCT0
Table 32 Description of IP1 bits (note 1)
BIT
SYMBOL
DESCRIPTION
T2 overflow interrupt(s) priority level.
7
6
5
4
3
2
1
0
PT2
PCM2
PCM1
PCM0
PCT3
PCT2
PCT1
PCT0
T2 comparator 2 interrupt priority interrupt level.
T2 comparator 1 interrupt priority interrupt level.
T2 comparator 0 interrupt priority interrupt level.
T2 capture register 3 priority interrupt level.
T2 capture register 2 priority interrupt level.
T2 capture register 1 priority interrupt level.
T2 capture register 0 priority interrupt level.
Note
1. A logic 0 = low priority; a logic 1 = high priority.
1997 Apr 08
27
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
The interrupt is serviced, and following the return from
interrupt instruction RETI, the next instruction to be
executed will be the one which follows the instruction
that wrote a logic 1 to PCON.0. The flag bits GF0 and
GF1 may be used to determine whether the interrupt
was received during normal execution or during the Idle
mode. For example, the instruction that writes to
PCON.0 can also set or clear one or both flag bits. When
Idle mode is terminated by an interrupt, the service
routine can examine the status of the flag bits.
15 REDUCED POWER MODES
15.1 Idle and Power-down operation
Idle mode operation permits the interrupt, serial ports and
timer blocks to continue to function while the CPU is
halted. The Idle and Power-down clock configuration is
shown in Fig.13. The following functions are switched off
when the processor enters the Idle mode.
• Timer T2 - stopped and reset
• PWM0 and PWM1 - reset, output HIGH
• ADC - aborted if in progress.
• The second way of terminating the Idle mode is with an
external hardware reset, or an internal reset caused by
an overflow of the Watchdog Timer (T3). Since the
oscillator is still running, the hardware reset is required
to be active for two machine cycles (24 oscillator periods
but at least 2 µs) to complete the reset operation.
The following functions remain active during Idle mode.
These functions may generate an interrupt or reset and
thus end the Idle mode.
• Timer 0, Timer 1
• Timer T3
15.1.2 POWER-DOWN MODE
• SIO
The instruction that sets PCON.1 is the last executed prior
to going into the Power-down mode. Once in Power-down
mode, the oscillator is stopped. Only the contents of the
on-chip RAM are preserved. The Special Function
Registers are not saved. A hardware reset is the only way
of exiting the Power-down mode.
• External Interrupt.
The Power-down operation freezes the oscillator.
The Power-down mode can only be activated by setting
the PD bit in the PCON register. The PD bit can only be set
if the EW input is HIGH.
In the Power-down mode, VDD may be reduced to
minimize circuit power consumption. The supply voltage
must not be reduced until the Power-down mode is
entered, and must be restored before the hardware reset
is applied which will free the oscillator. Reset should not be
released until the oscillator has restarted and stabilized.
15.1.1 IDLE MODE
The instruction that sets PCON.0 is the last instruction
executed in the normal operating mode before Idle mode
is activated. Once in the Idle mode, the CPU status is
preserved in its entirety: the Stack Pointer, Program
Counter, Program Status Word, Accumulator, RAM and all
other registers maintain their data during Idle mode.
The status of the external pins during Idle mode is shown
in Table 33.
The status of the external pins during Power-down mode
is shown in Table 33. If the Power-down mode is activated
while in external program memory, the port data that is
held in the Special Function Register P2 is restored to
Port 2. If the data is a logic 1, the port pin is held HIGH
during the Power-down mode by the strong pull-up
transistor p1 (see Fig.7).
There are two ways to terminate the Idle mode:
• Activation of any enabled interrupt will cause PCON.0 to
be cleared by hardware terminating the Idle mode.
Table 33 Status of external pins during Idle and Power-down modes
MODE
MEMORY
ALE
PSEN PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PWM0
Idle
internal
external
internal
external
1
1
0
0
1
1
0
0
port data port data port data port data port data
floating port data port data port data port data
port data port data port data port data port data
floating port data port data port data port data
1
1
1
1
Power-down
1997 Apr 08
28
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
XTAL2
XTAL1
OSCILLATOR
interrupts
serial ports
timer blocks
CLOCK
GENERATOR
CPU
T2
PWM
ADC
PD
IDL
MBC752
Fig.13 Internal Idle and Power-down clock configuration.
15.2 Power Control Register (PCON)
The reduced power modes are activated by software using this register. PCON is not bit addressable.
Table 34 Power Control Register (SFR address 87H)
7
6
5
4
3
2
1
0
SMOD
−
RFI
WLE
GF1
GF0
PD
IDL
Table 35 Description of PCON bits (note 1)
BIT
SYMBOL
DESCRIPTION
7
SMOD
Double Baud rate. When set to logic 1 the baud rate is doubled when the serial port
SIO0 is being used in modes 1, 2 or 3.
6
5
−
Reserved.
RFI
Reduced radio frequency interference. When set to logic 1, the toggling of the ALE
pin is prohibited; this bit is cleared on RESET (see Table 1).
4
WLE
Watchdog Load Enable. This flag must be set by software prior to loading the
Watchdog Timer. It is cleared when the timer is loaded.
3
2
1
GF1
GF0
PD
General-purpose flag bits.
Power-down bit. Setting this bit activates the Power-down mode. It can only be set if
input EW is HIGH.
0
IDL
Idle mode. Setting this bit activates the Idle mode.
Note
1. If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (0X000000).
1997 Apr 08
29
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
16 OSCILLATOR CIRCUITRY
, halfpage
The oscillator circuitry of the P8xC562 is a single-stage
inverting amplifier in a Pierce oscillator configuration.
The circuitry between XTAL1 and XTAL2 is basically an
inverter biased to the transfer point. Either a crystal or
ceramic resonator can be used as the feedback element to
complete the oscillator circuitry. Both are operated in
parallel resonance. XTAL1 (pin 35) is the high gain
amplifier input, and XTAL2 (pin 34) is the output (see
Fig.14). To drive the P8xC562 externally, XTAL1 is driven
from an external source and XTAL2 left open-circuit (see
Fig.15).
C1
XTAL1
35
20 pF
(1)
C2
XTAL2
34
20 pF
MBC751
1) Use fundamental crystals only.
17 RESET CIRCUITRY
Fig.14 P8xC562P8xC562 oscillator circuit.
The reset circuitry for the P8xC562 is connected to the
reset pin RST. A Schmitt trigger is used at the input for
noise rejection. The output of the Schmitt trigger is
sampled by the reset circuitry every machine cycle.
The on-chip Reset circuit is shown in Fig.16.
ook, halfpage
external clock
XTAL1
A reset is accomplished by holding the RST pin HIGH for
at least two machine cycles (24 oscillator periods but at
least 2 µs). The CPU responds by executing an internal
reset. During reset both ALE and PSEN output a HIGH
level. In order to perform a correct reset, this level must not
be affected by external elements.
(not TTL
35
34
compatible)
XTAL2
not connected
Also with the P8xC562, the RST line can be pulled HIGH
internally by a pull-up transistor activated by the Watchdog
Timer (T3). The length of the output pulse from the
Watchdog Timer is 3 machine cycles. A pulse of such
short duration is necessary in order to recover from a
processor or system fault as fast as possible.
MGA169
Fig.15 Driving the P8xC562 from an external source.
It can be seen that the short reset pulse from T3 cannot
discharge the Power-on reset capacitor (see Fig.17).
Consequently, when the Watchdog Timer is also used to
reset external devices this capacitor arrangement should
not be connected to the RST pin, and an extra circuit
should be used to perform the Power-on-reset operation.
It should be remembered that a T3 overflow, if enabled, will
force a reset condition to the P8xC562 by an internal
connection, whether the output RST is tied LOW or not.
V
DD
andbook, halfpage
overflow
timer T3
SCHMITT
TRIGGER
RESET
CIRCUITRY
RST
The internal reset is executed during the second cycle in
which RST is HIGH and is repeated every cycle until RST
goes LOW. The internal RAM is not affected by reset.
When VDD is turned on, the RAM content is indeterminate.
An internal reset leaves the internal registers as shown in
Table 36.
MBC476 - 1
on-chip
resistor
R
RST
Fig.16 On-chip reset configuration.
1997 Apr 08
30
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
Table 36 State of internal registers after an internal reset
17.1 Power-on-reset
X = undefined state.
When VDD is turned on, and provided its rise-time does not
exceed 10 ms, an automatic reset can be obtained by
connecting the RST pin to VDD via a 2.2 µF capacitor.
When the power is switched on, the voltage on the RST
pin, is equal to VDD minus the capacitor voltage, and
decreases from VDD as the capacitor charges through the
internal resistor (RRST) to ground. The larger the capacitor,
the more slowly VRST decreases. VRST must remain above
the lower threshold of the Schmitt trigger long enough to
effect a complete reset. The time required is the oscillator
start-up time, plus 2 machine cycles. The port pins will be
in a random state until the oscillator has started and the
internal reset algorithm has written logic 1s to the port pins.
The Power-on-reset circuitry is shown in Fig.17.
REGISTER
7
0
X
X
0
0
0
0
X
X
0
0
0
0
X
0
0
0
0
0
0
0
0
1
X
0
X
0
0
1
0
0
0
0
0
0
0
0
0
6
0
X
X
0
0
0
0
X
X
0
0
0
0
0
0
0
0
X
0
0
0
0
1
X
0
X
0
0
1
0
0
0
0
0
0
0
0
0
5
0
0
X
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
X
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
X
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
X
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
X
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
X
0
0
0
0
0
0
0
0
0
0
0
0
2
0
0
X
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
X
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
X
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
X
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
X
0
1
0
0
0
0
0
0
0
0
0
0
ACC
ADC0N
ADCH
B
CML0 to CML2
CMH0 to CMH2
CTCON
CTL0 to CTL3
CTH0 to CTH3
DPL
DPH
IEN0
IEN1
IP0
IP1
V
DD
handbook, halfpage
PCH
PCL
V
PCON
PSW
DD
2.2 µF
8xC562
PWM0
PWM1
PWMP
P0 to P4
P5
RST
R
RST
RTE
SBUF
MBH344
SCON
SP
STE
Fig.17 Power-on-reset.
TCON
TH0, TH1
TMH2
TL0, TL1
TML2
TMOD
TM2CON
TM2IR
T3
1997 Apr 08
31
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
18 INSTRUCTION SET
The P8xC562 uses the powerful instruction set of the 80C51. Additional Special Function Registers are incorporated to
control the on-chip peripherals. The instruction set consists of 49 single-byte, 45 two-byte and 17 three-byte instructions.
When using a 16 MHz oscillator, 64 instructions execute in 0.75 µs and 45 instructions execute in 1.5 µs. Multiply and
divide instructions execute in 3 µs.
Tables 37 to 41 describe the Instruction set; Table 42 explains the Data addressing modes and the Hexadecimal
opcodes.
Table 37 Instruction set descriptions: Arithmetic operations
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES CYCLES
Arithmetic operations
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
A,Rr
Add register to A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
2*
A,direct
A,@Ri
A,#data
A,Rr
Add direct byte to A
25
Add indirect RAM to A
26, 27
24
Add immediate data to A
Add register to A with carry flag
Add direct byte to A with carry flag
Add indirect RAM to A with carry flag
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment A
3*
A,direct
A,@Ri
A,#data
A,Rr
35
36, 37
34
9*
A,direct
A,@Ri
A,#data
A
95
96, 97
94
04
INC
Rr
Increment register
0*
INC
direct
@Ri
Increment direct byte
05
INC
Increment indirect RAM
Decrement A
06, 07
14
DEC
DEC
DEC
DEC
INC
A
Rr
Decrement register
1*
direct
@Ri
Decrement direct byte
15
Decrement indirect RAM
Increment data pointer
16, 17
A3
DPTR
AB
MUL
DIV
Multiply A & B
A4
AB
Divide A by B
84
DA
A
Decimal adjust A
D4
1997 Apr 08
32
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
Table 38 Instruction set description: Logic operations
OPCODE
BYTES CYCLES
(HEX)
MNEMONIC
DESCRIPTION
Logic operations
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
A,Rr
AND register to A
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
5*
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A,Rr
AND direct byte to A
55
AND indirect RAM to A
AND immediate data to A
AND A to direct byte
56, 57
54
52
AND immediate data to direct byte
OR register to A
53
4*
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A,Rr
OR direct byte to A
45
OR indirect RAM to A
46, 47
44
OR immediate data to A
OR A to direct byte
42
OR immediate data to direct byte
Exclusive-OR register to A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate data to A
Exclusive-OR A to direct byte
Exclusive-OR immediate data to direct byte
Clear A
43
6*
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A
65
66, 67
64
62
63
E4
F4
A
Complement A
A
Rotate A left
23
RLC
RR
A
Rotate A left through the carry flag
Rotate A right
33
A
03
RRC
SWAP
A
Rotate A right through the carry flag
Swap nibbles within A
13
A
C4
1997 Apr 08
33
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
Table 39 Instruction set description: Data transfer
OPCODE
BYTES CYCLES
(HEX)
MNEMONIC
Data transfer
DESCRIPTION
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVC
MOVC
MOVX
MOVX
MOVX
MOVX
PUSH
POP
A,Rr
Move register to A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
E*
A,direct
A,@Ri
Move direct byte to A
E5
Move indirect RAM to A
E6, E7
74
A,#data
Rr,A
Move immediate data to A
Move A to register
F*
Rr,direct
Rr,#data
direct,A
direct,Rr
direct,direct
direct,@Ri
direct,#data
@RI,A
Move direct byte to register
Move immediate data to register
Move A to direct byte
A*
7*
F5
Move register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate data to direct byte
Move A to indirect RAM
8*
85
86, 87
75
F6, F7
A6, A7
76, 77
90
@Ri,direct
@Ri,#data
Move direct byte to indirect RAM
Move immediate data to indirect RAM
DPTR,#data16 Load data pointer with a 16-bit constant
A,@A+DPTR
A,@A+PC
A,@Ri
Move code byte relative to DPTR to A
Move code byte relative to PC to A
Move external RAM (8-bit address) to A
Move external RAM (16-bit address) to A
Move A to external RAM (8-bit address)
Move A to external RAM (16-bit address)
Push direct byte onto stack
93
83
E2, E3
E0
A,@DPTR
@Ri,A
F2, F3
F0
@DPTR,A
direct
C0
direct
Pop direct byte from stack
D0
XCH
A,Rr
Exchange register with A
C*
XCH
A,direct
A,@Ri
Exchange direct byte with A
C5
XCH
Exchange indirect RAM with A
C6, C7
D6, D7
XCHD
A,@Ri
Exchange LOW-order nibble indirect RAM with A
1997 Apr 08
34
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
Table 40 Instruction set description: Program and machine control
OPCODE
BYTES CYCLES
(HEX)
MNEMONIC
DESCRIPTION
Program and machine control
ACALL
LCALL
RET
addr11
addr16
Absolute subroutine call
2
3
1
1
2
3
2
1
2
2
2
2
3
3
3
3
3
3
3
2
3
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
•1
Long subroutine call
12
22
32
♦ 1
02
80
73
60
70
40
50
20
30
10
B5
B4
B*
Return from subroutine
RETI
AJMP
LJMP
SJMP
JMP
Return from interrupt
addr11
addr16
rel
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to the DPTR
Jump if A is zero
@A+DPTR
rel
JZ
JNZ
rel
Jump if A is not zero
JC
rel
Jump if carry flag is set
JNC
rel
Jump if carry flag is not set
Jump if direct bit is set
JB
bit,rel
JNB
bit,rel
Jump if direct bit is not set
Jump if direct bit is set and clear bit
Compare direct to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to reg. and jump if not equal
JBC
bit,rel
CJNE
CJNE
CJNE
CJNE
DJNZ
DJNZ
NOP
A,direct,rel
A,#data,rel
Rr,#data,rel
@Ri,#data,rel Compare immediate to ind. and jump if not equal
B6, B7
D*
D5
00
Rr,rel
Decrement register and jump if not zero
Decrement direct and jump if not zero
No operation
direct,rel
1997 Apr 08
35
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
Table 41 Instruction set description: Boolean variable manipulation
OPCODE
BYTES CYCLES
(HEX)
MNEMONIC
DESCRIPTION
Boolean variable manipulation
CLR
CLR
SETB
SETB
CPL
CPL
ANL
ANL
ORL
ORL
MOV
MOV
C
Clear carry flag
Clear direct bit
Set carry flag
Set direct bit
1
2
1
2
1
2
2
2
2
2
2
2
1
1
1
1
1
1
2
2
2
2
1
2
C3
C2
D3
D2
B3
B2
82
B0
72
A0
A2
92
bit
C
bit
C
Complement carry flag
bit
Complement direct bit
C,bit
C,/bit
C,bit
C,/bit
C,bit
bit,C
AND direct bit to carry flag
AND complement of direct bit to carry flag
OR direct bit to carry flag
OR complement of direct bit to carry flag
Move direct bit to carry flag
Move carry flag to direct bit
Table 42 Description of the mnemonics in the instruction set
MNEMONIC
DESCRIPTION
Data addressing modes
Rr
Working register R0-R7.
128 internal RAM locations and any special function register (SFR).
direct
@Ri
Indirect internal RAM location addressed by register R0 or R1 of the actual register bank.
8-bit constant included in instruction.
#data
#data 16
bit
16-bit constant included as bytes 2 and 3 of instruction.
direct addressed bit in internal RAM or SFR.
addr16
16-bit destination address. Used by LCALL and LJMP. The branch will be anywhere within the
64 kbytes program memory address space.
addr11
rel
11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes
page of program memory as the first byte of the following instruction.
Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps.
Range is −128 to +127 bytes relative to first byte of the following instruction.
Hexadecimal opcode cross-reference
*
•
8, 9, A, B, C, D, E, F.
1, 3, 5, 7, 9, B, D, F.
0, 2, 4, 6, 8, A, C, E.
♦
1997 Apr 08
36
First hexadecimal character of opcode
← Second hexadecimal character of opcode →
↓
0
1
2
3
4
5
6
0
0
7
1
1
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
1
1
1
1
1
1
1
1
1
1
1
A B C D E F
INC Rr
INC @Ri
DEC @Ri
AJMP
addr11
LJMP
addr16
RR
A
INC
A
INC
direct
0
NOP
2
3
4
5
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
DEC Rr
JBC
bit,rel
ACALL
addr11
LCALL
addr16
RRC
A
DEC
A
DEC
direct
1
2
3
4
5
6
7
8
9
A
B
C
D
E
2
3
4
5
ADD A,@Ri
ADD A,Rr
JB
bit,rel
AJMP
addr11
RL
A
ADD
A,#data
ADD
A,direct
RET
0
1
2 3 4 5
ADDC A,@Ri
ADDC A,Rr
JNB
bit,rel
ACALL
addr11
RLC
A
ADDC
A,#data
ADDC
A,direct
RETI
0
1
2 3 4 5
ORL A,@Ri
ORL A,Rr
JC
rel
AJMP
addr11
ORL
direct,A
ORL
direct,#data
ORL
A,#data
ORL
A,direct
0
1
2 3 4 5
ANL A,@Ri
ANL A,Rr
JNC
rel
ACALL
addr11
ANL
direct,A
ANL
direct,#data
ANL
A,#data
ANL
A,direct
0
1
2 3 4 5
XRL A,@Ri
XRL A,Rr
JZ
rel
AJMP
addr11
XRL
direct,A
XRL
direct,#data
XRL
A,#data
XRL
A,direct
0
1
2 3 4 5
MOV @Ri,#data
MOV Rr,#data
JNZ
rel
ACALL
addr11
ORL
C,bit
JMP
@A+DPTR
MOV
A,#data
MOV
direct,#data
0
1
2 3 4 5
MOV direct,@Ri
MOV direct,Rr
SJMP
rel
AJMP
addr11
ANL
C,bit
MOVC
A,@A+PC
DIV
AB
MOV
direct,direct
0
1
2 3 4 5
SUBB A,@Ri
SUB A,Rr
MOV
DTPR,#data16
ACALL
addr11
MOV
bit,C
MOVC
A,@A+DPTR
SUBB
A,#data
SUBB
A,direct
0
1
2 3 4 5
MOV @Ri,direct
MOV Rr,direct
ORL
C,/bit
AJMP
addr11
MOV
bit,C
INC
DPTR
MUL
AB
0
1
2 3 4 5
CJNE @Ri,#data,rel
CJNE Rr,#data,rel
ANL
C,/bit
ACALL
addr11
CPL
bit
CPL
C
CJNE
A,#data,rel
CJNE
A,direct,rel
0
1
1
1
1
1
1
1
2
3
4
5
6
6
6
6
6
XCH A,@Ri
XCH A,Rr
PUSH
direct
AJMP
addr11
CLR
bit
CLR
C
SWAP
A
XCH
A,direct
0
2 3 4 5
XCHD A,@Ri
DJNZ Rr,rel
POP
direct
ACALL
addr11
SETB
bit
SETB
C
DA
A
DJNZ
direct,rel
0
1
1
2 3 4 5
MOVX A,@Ri
MOV A,@Ri
MOV A,Rr
MOVX
A,@DTPR
AJMP
addr11
CLR
A
MOV
A,direct (1)
0
0
1
0
2 3 4 5
MOVX @Ri,A
MOV @Ri,A
MOV Rr,A
MOVX
@DTPR,A
ACALL
addr11
CPL
A
MOV
direct,A
F
1
0
1
2 3 4 5
Note
1. MOV A, ACC is not a valid instruction.
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
19 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VI
PARAMETER
MIN.
−0.5
MAX.
+6.5
UNIT
input voltage on any pin with respect to ground (VSS
input, output DC current on any single I/O pin
total power dissipation
)
V
II, IO
Ptot
−
5.0
mA
W
−
1.0
Tstg
Tamb
storage temperature range
operating ambient temperature range
P8xC562EBx
−65
+150
°C
0
+70
°C
°C
°C
P8xC562EFx
−40
−40
+85
P8xC562EHx
+125
20 DC CHARACTERISTICS
VDD = 5 V ±10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; fOSC = 16 MHz.
Tamb = −40 to +85 °C for the P8xC562EFx.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Supply (digital part)
VDD
IDD
supply voltage P8xC562Exx
operating supply current
P8xC562Exx
4.5
−
5.5
40
9
V
note 1
note 2
note 3
mA
mA
IDD(ID)
supply current Idle mode
P8xC562Exx
−
IDD(PD)
supply current Power-down mode
P8X562EBx
2 V < VDD(PD) < VDD(max)
2 V < VDD(PD) < VDD(max)
2 V < VDD(PD) < VDD(max)
−
−
−
50
µA
µA
µA
P8X562EFx
50
P8X562EHx
150
Inputs
VIL
LOW level input voltage (except EA)
LOW level input voltage (EA)
−0.5
−0.5
0.2VDD − 0.1
0.2VDD − 0.3
V
V
V
VIL1
VIH
HIGH level input voltage
(except RST, XTAL1)
0.2VDD + 0.9 VDD + 0.5
VIH1
IIL
HIGH level input voltage
(RST and XTAL1)
0.7VDD
VDD + 0.5
V
input current logic 0
VI = 0.45 V
−
−50
µA
Ports 1, 2, 3 and 4;
(except P1.6/SCL, P1.7/SDA)
ITL
ILI1
ILI3
input current HIGH-to-LOW transition VI = 2.0 V
(Ports 1, 2, 3 and 4)
−
−
−
−650
±10
±1
µA
µA
µA
input leakage current
0.45 V < VI < VDD
(Port 0, EA, STADC, EW)
input leakage current (Port 5)
0.45 V < VI < VDD
1997 Apr 08
38
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Outputs
VOL
LOW level output voltage
(Ports 1, 2, 3 and 4)
IOL = 1.6 mA; note 4
IOL = 3.2 mA; note 4
IOH = −60 µA
−
0.45
V
VOL1
VOH
LOW level output voltage
(Port 0, ALE, PSEN, PWM0, PWM1)
−
0.45
V
HIGH level output voltage
Ports 1, 2, 3 and 4
2.4
−
V
IOH = −25 µA
0.75VDD
0.9VDD
2.4
−
V
IOH = −10 µA
IOH = −800 µA
−
V
VOH1
HIGH level output voltage
−
V
Port 0 in external bus mode,
ALE, PSEN, PWM0, PWM1; note 5
I
OH = −300 µA
0.75VDD
0.9VDD
2.4
−
V
IOH = −80 µA
IOH = −400 µA
−
V
VOH2
HIGH level output voltage (RST)
−
V
I
OH = −120 µA
0.8VDD
50
−
V
RRST
CI/O
RST pull-down resistor
capacitance of I/O buffer
150
10
kΩ
pF
test frequency = 1 MHz;
−
Tamb = 25 °C
Supply (analog part)
VDDA
supply voltage
VDDA = VDD ±0.2 V
4.5
5.5
1.2
V
P8X562Exx
IDDA
supply current operating
supply current Idle mode
P8X562EBx
Port 5 = 0 to VDDA
mA
IDDA(ID)
−
−
−
50
µA
µA
µA
P8X562EFx
50
P8X562EHx
100
IDDA(PD)
supply current Power-down mode
P8X562EBx
2 V < VDDA(PD) < VDDA(max)
−
−
−
50
µA
µA
µA
P8X562EFx
50
P8X562EHx
100
1997 Apr 08
39
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Analog inputs
VIN
analog input voltage
AVSS − 0.2
AVDD + 0.2
V
VREF+
VREF−
RREF
CIA
reference voltage (+)
−
AVDD + 0.2
V
reference voltage (−)
AVSS − 0.2
−
V
resistance between VREF+ and VREF−
analog input capacitance
sampling time
5
−
−
−
25
kΩ
pF
µs
µs
15
tADS
tADC
6tCY
24tCY
conversion time
(including sample time)
DLe
ILe
differential non-linearity
integral non-linearity
offset error
notes 7 and 11
−
−
−
−
−
−
±1
LSB
LSB
LSB
%
notes 6 and 8
notes 6 and 10
notes 6 and 9
±1
OSe
Ge
±1
gain error
±0.4
±1
Mctc
Ct
channel-to-channel matching
crosstalk between P5 inputs
LSB
dB
0 to 100 kHz
−60
Notes to the DC characteristics
1. The operating supply current is measured with all output pins disconnected;
XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V; VIH = VDD − 0.5 V; XTAL2 not connected;
EA = RST = Port 0 = EW = VDD; STADC = VSS
.
2. The Idle mode supply current is measured with all output pins disconnected;
XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V; VIH = VDD − 0.5 V; XTAL2 not connected;
EA = Port 0 = EW = VDD; RST = STADC = VSS
3. The Power-down current is measured with all output pins disconnected; XTAL2 not connected;
EA = Port 0 = EW = VDD; RST = STADC = XTAL1 = VSS
.
.
4. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the low level output
voltage of ALE and Ports 1, 3 and 4. The noise is due to external bus capacitance discharging into the Port 0 and
Port 2 pins when these pins make HIGH-to-LOW transitions during bus operations. In the most adverse condition
(capacitive loading > 100 pF), the noise pulse on the ALE line may exceed 0.8 V. In such events it may be required
to qualify ALE with a Schmitt trigger, or use an address latch with a Schmitt trigger strobe input.
5. Capacitive loading on Ports 0 and 2 may cause the high level output voltage on ALE and PSEN to momentarily fall
below to 0.9VDD specification when the address bits are stabilizing.
6. VREF+ = 5.12 V; VREF− = 0 V; VDDA = 5.0 V.
7. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width.
8. The integral non-linearity (ILe) is the peak difference between the centre of the steps of the actual and the ideal
transfer curve after appropriate adjustment of gain and offset error.
9. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve after
removing offset error, and the straight line which fits the ideal transfer curve. Gain error is constant at every point on
the transfer curve.
10. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve after
removing gain error, and a straight line which fits the ideal transfer curve. The offset error is constant at every point
of the actual transfer curve.
11. VREF− = 0 V; VDDA = 5 V; VREF+ = 5.12 V. The ADC is monotonic with no missing codes. Measurement by
continuously increasing VIN from −20 mV to 5.12 V in increments of 2 mV.
1997 Apr 08
40
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
MBC747
50
handbook, halfpage
I
, I
DD ID
(mA)
40
30
20
(1)
(2)
10
0
(3)
(4)
0
4
8
12
16
f (MHz)
(1) IDD(max) operating mode; VDD = 5.5 V.
(2) IDD(max) operating mode; VDD = 4.5 V.
(3) IID(max) Idle mode; VDD = 5.5V.
(4) IID(max) Idle mode; VDD = 4.5 V.
These values are valid within the specified frequency range.
Fig.18 Supply current (IDD, IID) as a function of frequency at XTAL1 (fosc).
1997 Apr 08
41
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
offset error OS
gain error G
e
255
e
254
253
252
251
250
(2)
code
out
7
6
5
4
3
2
1
0
(1)
(5)
(4)
(3)
7
1 LSB (ideal)
1
2
3
4
5
6
250 251 252 253 254 255 256
AV (LSB
)
ideal
IN
offset error
AV
−AV
REF+
REF−
OS
=
e
1 LSB
ideal
MBH351
1024
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential non-linearity (DLe).
(4) Integral non-linearity (ILe).
(5) Centre of a step of the actual transfer curve.
Fig.19 ADC conversion characteristic.
1997 Apr 08
42
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
21 AC CHARACTERISTICS
Parameters are valid over operating temperature range and operating supply voltage range unless otherwise specified.
CL = 100 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless specified. See Figs 23 to 25.
f
OSC = 16 MHz
fOSC = VARIABLE
SYMBOL
PARAMETER
UNIT
MIN. MAX.
MIN.
MAX.
Program memory
tLL
ALE pulse duration
address set-up time to ALE
85
8
−
2tCLK − 40
−
−
−
ns
ns
ns
tAL
−
t
t
CLK − 55
CLK − 35
tLA
address hold time after ALE
28
−
−
tLIV
tLC
tCC
tCIV
tCI
time from ALE to valid instruction input
time from ALE to control pulse PSEN
control pulse duration PSEN
150
−
−
4tCLK − 100 ns
23
143
−
tCLK − 40
−
−
ns
ns
−
3tCLK − 45
time from PSEN to valid instruction input
input instruction hold time after PSEN
input instruction float delay after PSEN
address to valid instruction input
address float delay after PSEN
83
−
−
0
−
−
−
3tCLK − 105 ns
0
−
ns
ns
tCIF
tAIV
tAFC
−
38
208
10
tCLK − 25
−
5tCLK − 105 ns
−
10
ns
External data memory
tRR
RD pulse duration
275
275
8
−
6tCLK − 100
6tCLK − 100
−
−
−
−
ns
ns
ns
ns
tWW
tAL
WR pulse duration
−
address set-up time to ALE
address hold time after ALE
RD to valid data input
−
t
t
CLK − 55
CLK − 35
tLA
28
−
−
tRD
148
−
−
0
−
−
−
5tCLK − 165 ns
tDR
data hold time after RD
0
−
ns
ns
tDFR
tLD
data float delay after RD
−
55
350
398
238
−
2tCLK − 70
time from ALE to valid data input
address to valid data input
time from ALE to RD or WR
time from address to RD or WR
time from RD or WR HIGH to ALE HIGH
data valid to WR transition
data set-up time before WR
data hold time after WR
−
8tCLK − 150 ns
9tCLK − 165 ns
tAD
−
tLW
138
120
23
3
3tCLK − 50 3tCLK + 50 ns
tAW
tWHLH
tDWX
tDW
tWD
tAFR
4tCLK − 130
−
ns
ns
ns
ns
ns
ns
103
−
t
CLK − 40
CLK − 60
tCLK + 40
t
−
−
−
0
288
13
−
−
7tCLK − 150
CLK − 50
−
t
address float delay after RD
0
−
Note
1. tCLK = 1/fosc = one oscillator clock period. If fosc = 16 MHz then tCLK = 62.5 ns.
1997 Apr 08
43
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
V
0.5
DD
0.2 V
0.2 V
0.9
0.1
DD
DD
0.45 V
(a)
V
0.1 V
0.1 V
V
0.1 V
LOAD
OH
timing reference
points
V
LOAD
V
0.1 V
V
OL
LOAD
MLA753
(b)
AC inputs during testing are driven at VDD − 0.5 V for a logic 1, and 0.45 V for a logic 0.
Timing measurements are made at VIH(min) for a logic 1, and VIL(max) for a logic 0. See Fig.25 (a).
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a
100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ±20 mA (for testing purposes only). See Fig.25 (b).
Fig.20 AC inputs test conditions.
1997 Apr 08
44
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
one machine cycle
one machine cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
P1 P2
P1 P2
P1 P2 P1 P2 P1 P2
P1 P2 P1 P2 P1 P2
P1 P2 P1 P2 P1 P2
P1 P2
XTAL1
INPUT
ALE
dotted lines
are valid when
RD or WR are
active
PSEN
only active
during a read
from external
RD
data memory
only active
during a write
WR
to external
data memory
BUS
(PORT 0)
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
external
program
memory
fetch
PORT 2
address A8 - A15
address A8 - A15
address A8 - A15
address A8 - A15
BUS
(PORT 0)
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
address
A0 - A7
data output or data input
read or
write of
external data
memory
address A8 - A15
address A8 - A15 or Port 2 out
address A8 - A15
PORT 2
PORT
OUTPUT
old data
new data
PORT
INPUT
sampling time of I/O port pins during input (including INT0 and INT1)
SERIAL
PORT
CLOCK
MGA180
The Port 5 input buffers have a maximum propagation delay of 300 ns. As a result Port 5 sample time starts 300 ns in advance of state S5 and ends
when S5 has finished.
Fig.21 Instruction cycle timing.
1997 Apr 08
45
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
t
CY
t
t
LHLL
LLIV
ALE
t
LLPL
t
PLPH
PSEN
t
LLAX
t
t
t
PXIZ
AVLL
PLIV
PORT 0
PORT 2
A0 to A7
inst. input
A0 to A7
inst. input
t
t
PXIX
PLAZ
t
AVIV
address A8 to A15
address A8 to A15
MGA176
Fig.22 Read from program memory.
t
CY
ALE
t
t
t
LL
LD
WHLH
PSEN
RD
t
t
RR
LW
t
t
t
t
DFR
AL
LA
t
t
DR
AW
RD
PORT 0
PORT 2
A0 to A7
data input
t
AFR
t
AD
address A8 to A15 or Port 2 out
MBC743
Fig.23 Read from data memory.
46
1997 Apr 08
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
t
CY
n
t
t
LL
WHLH
ALE
PSEN
WR
t
t
LW
WW
t
AW
t
t
t
t
DW
WD
AL
LA
t
DWX
A0 to A7
data output
PORT 0
PORT 2
address A8 to A15 or special function registers (SFR)
MBC744
Fig.24 Write to data memory.
1997 Apr 08
47
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
Table 44 External clock drive XTAL1
Test conditions: operating temperature and supply voltage ranges; load capacitance = 80 pF.
SYMBOL
PARAMETER
MIN.
62.5
MAX.
285.7
UNIT
tCLK
tHIGH
tLOW
tr
clock period
HIGH time
LOW time
ns
ns
ns
ns
ns
µs
20
20
−
−
−
rise time
20
20
3.43
tf
fall time
−
tCY
cycle time (12 tCLK
)
0.75
t
t
t
f
HIGH
r
V
V
V
V
IH1
IH1
IH1
IH1
0.8 V
0.8 V
0.8 V
0.8 V
t
LOW
MBC479
t
CK
Fig.25 External clock drive XTAL.
Table 45 Serial timing - shift register mode using 16 MHz oscillator
16 MHz OSC
MIN. MAX.
VARIABLE OSCILLATOR
MIN. MAX.
12tCLK
SYMBOL
PARAMETER
serial port clock cycle time
UNIT
tXLXL
0.75
492
8.0
0
−
−
−
−
−
µs
ns
ns
ns
ns
tQVXH
tXHQX
tXHDX
tXHDV
output data set-up to clock rising edge
output data hold after clock rising edge
input data hold after clock rising edge
clock rising edge to input data valid
−
10tCLK − 133
−
2tCLK − 117
−
0
−
492
−
10tCLK − 133
1997 Apr 08
48
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
22 PACKAGE OUTLINE
PLCC68: plastic leaded chip carrier; 68 leads
SOT188-2
e
e
D
E
y
X
A
60
44
Z
E
43
61
b
p
b
1
w
M
68
1
H
E
E
pin 1 index
A
e
A
1
A
4
(A )
3
k
L
1
p
9
k
27
β
detail X
10
26
v
M
A
e
Z
D
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
(1)
(1)
A
min.
A
max.
k
1
max.
Z
Z
E
(1)
(1)
1
4
D
UNIT
mm
A
A
b
D
E
e
e
e
H
H
k
L
p
v
w
y
β
b
D
E
D
E
3
p
1
max. max.
4.57
4.19
0.81 24.33 24.33
0.66 24.13 24.13
23.62 23.62 25.27 25.27 1.22
22.61 22.61 25.02 25.02 1.07
1.44
1.02
0.53
0.33
0.51
0.51 0.25 3.30
0.020 0.01 0.13
1.27
0.05
0.18 0.18 0.10 2.16 2.16
o
45
0.180
0.165
0.032 0.958 0.958
0.026 0.950 0.950
0.930 0.930 0.995 0.995 0.048
0.890 0.890 0.985 0.985 0.042
0.057
0.040
0.021
0.013
inches
0.020
0.007 0.007 0.004 0.085 0.085
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-03-11
SOT188-2
112E10
MO-047AC
1997 Apr 08
49
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
23 SOLDERING
23.3 Wave soldering
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
23.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream corners.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
23.2 Reflow soldering
Reflow soldering techniques are suitable for all PLCC
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
23.4 Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1997 Apr 08
50
Philips Semiconductors
Product specification
8-bit microcontroller
P83C562; P80C562
24 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of this specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
25 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Apr 08
51
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
Tel. +61 2 9805 4455, Fax. +61 2 9805 4466
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Belgium: see The Netherlands
Brazil: see South America
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 689 211, Fax. +359 2 689 102
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,
Tel. +65 350 2538, Fax. +65 251 6500
Colombia: see South America
Czech Republic: see Austria
Slovakia: see Austria
Slovenia: see Italy
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
Tel. +45 32 88 2636, Fax. +45 31 57 0044
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. +27 11 470 5911, Fax. +27 11 470 5494
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615800, Fax. +358 9 61580920
South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 829 1849
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,
Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 3 301 6312, Fax. +34 3 301 4107
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 23 53 60, Fax. +49 40 23 536 300
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 632 2000, Fax. +46 8 632 2745
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,
Tel. +30 1 4894 339/239, Fax. +30 1 4814 240
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2686, Fax. +41 1 481 7730
Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.
Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Indonesia: see Singapore
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
457047/1200/01/pp52
Date of release: 1997 Apr 08
Document order number: 9397 750 02133
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