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P87C055 [NXP]

Microcontrollers for TV and video MTV; 微控制器的电视和视频MTV
P87C055
型号： P87C055
厂家： NXP    NXP
描述：

Microcontrollers for TV and video MTV
微控制器的电视和视频MTV

微控制器 电视
文件： 总40页 (文件大小：245K)
中文：  中文翻译
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INTEGRATED CIRCUITS  
DATA SHEET  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video  
(MTV)  
1996 Mar 22  
Product specification  
File under Integrated Circuits, IC20  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
CONTENTS  
14  
PROGRAMMING CONSIDERATIONS  
14.1  
14.2  
14.3  
14.4  
14.5  
EPROM Characteristics  
Programming operation  
Erasure Characteristics  
Reading Signature Bytes  
EPROM Programming and Verification  
1
FEATURES  
2
DESCRIPTION  
3
APPLICATIONS  
4
ORDERING INFORMATION  
BLOCK DIAGRAM  
Part options  
15  
PROGRAMMING THE OSD EPROM  
5
15.1  
15.2  
15.3  
Overview  
5.1  
6
Character description and programming  
OSD EPROM bit map  
PINNING INFORMATION  
6.1  
6.2  
Pinning  
Pin description  
16  
17  
18  
19  
20  
21  
22  
REGISTER MAP  
LIMITING VALUES  
HANDLING  
7
8
9
DESCRIPTION OF STANDARD FUNCTIONS  
INPUT/OUTPUT (I/O)  
DC CHARACTERISTICS  
AC CHARACTERISTICS  
PACKAGE OUTLINES  
SOLDERING  
DESCRIPTION OF DERIVATIVE  
FUNCTIONS  
9.1  
10  
General description  
6-BIT PWM DACS  
22.1  
22.2  
22.3  
Introduction  
Soldering by dip or wave  
Repairing soldered joints  
10.1  
10.2  
PWM DAC operation  
Special Function Register PWMn (n = 0 to 7)  
11  
14-BIT PWM DAC (TDAC)  
23  
24  
DEFINITIONS  
11.1  
11.2  
11.3  
11.4  
14-bit counter  
14-bit DAC operation  
Special Function Register TDACL  
Special Function Register TDACH  
LIFE SUPPORT APPLICATIONS  
12  
SOFTWARE ANALOG-TO-DIGITAL FACILITY  
12.1  
12.2  
Special Function Register SAD  
Software ADC operation  
13  
ON SCREEN DISPLAY (OSD)  
13.1  
13.2  
13.3  
13.4  
13.5  
13.6  
13.7  
13.8  
13.9  
OSD features  
General description of the OSD module  
OSD logic  
Character Generator ROM  
Display RAM organization  
OSD Special Function Registers  
OSD Control Register OSCON  
OSD Control Register OSMOD  
OSD Control Register OSORG  
1996 Mar 22  
2
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
• One 14-bit PWM for high-precision voltage integration  
1
FEATURES  
• Digital-to-analog converter and comparator with 3 inputs  
multiplexer  
• Masked ROM sizes:  
– 8 kbytes (83C845)  
• Nine dedicated I/Os plus 28 port bits (15 port bits with  
alternative uses)  
– 12 kbytes (83C145)  
– 16 kbytes (83C055)  
• 4 high current open-drain port outputs  
• 12 high voltage (+12 V) open-drain outputs  
• Programmable video input and output polarities  
• 80C51 instruction set  
– 16 kbytes OTP (87C055)  
• RAM: 256 bytes  
• On Screen Display (OSD) controller  
• Three digital video outputs  
• Multiplexer/mixer and background intensity controls  
• Flexible formatting with OSD New Line option  
• 128 × 10 bits display RAM  
• No external memory capability  
• Plastic shrink dual in-line package (0.07 inch centre  
pins)  
• High-speed CMOS technology  
• Power supply: 5 V ±10%.  
• Designed for reduced Radio Frequency Interference  
(RFI)  
• Character generator ROM:  
– character format 18 lines × 14 dots  
– 60 visible characters  
2
DESCRIPTION  
The 83C055, Microcontroller for Television and Video  
(MTV) applications, is a derivative of Philips’ industry  
standard 80C51 microcontroller.  
– 4 special characters  
• Eight text shadowing modes  
• Text colour selectable per character  
• Background colour selectable per word  
The 83C055 is intended for use as the central control  
mechanism in a television receiver or tuner.  
3
APPLICATIONS  
• Background colour versus video selectable per  
character  
Providing tuner functions and an OSD facility, it represents  
a next generation replacement for the currently available  
parts.  
• Eight 6-bit Pulse Width Modulators (PWM) for analog  
voltage integration  
4
ORDERING INFORMATION  
PACKAGE  
DESCRIPTION  
TEMP.  
RANGE  
(°C)  
FREQ.  
(MHz)  
TYPE NUMBER  
NAME  
VERSION  
P83C055BBP  
P87C055BBP  
P83C145BBP  
P83C845BBP  
SDIP42 plastic shrink dual in-line package; 42 leads (600 mil) SOT270-1 0 to +70 3.5 to 12  
1996 Mar 22  
3
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
5
BLOCK DIAGRAM  
BF VID1 VCTRL VCLK1  
HSYNC  
VSYNC  
VID0  
INT1 INT0  
VID2  
T0  
VCLK2  
V
DD  
OSD BLOCK  
XTAL1  
(IN)  
CHARACTER  
GENERATOR  
ROM  
8-BIT  
TIMER /  
EVENT  
ROM  
(1)  
RAM  
256 bytes  
DISPLAY  
RAM  
128 × 10  
CPU  
XTAL2  
(OUT)  
60 × 18 × 14  
COUNTER  
8-bit internal bus  
80C51  
core  
RST  
excluding  
ROM / RAM  
SOFTWARE  
CONTROL  
ADC  
PARALLEL  
I / O  
PORTS  
14-BIT  
PWM  
8 x 6-BIT PWM  
V
SS  
8
8
4
8
8
MBE766  
3
P3  
P2  
P1  
P0  
PWM0 to PWM7  
TDAC  
ADI2 to ADI0  
(1) ROM sizes: see Table 1.  
Fig.1 Block diagram.  
5.1  
Part options  
Table 1 Differences between the types  
TYPES  
MEMORY  
83C845  
83C145  
83C055  
87C055  
ROM  
8 kbytes  
12 kbytes  
16 kbytes  
−
EPROM (OTP)  
−
−
−
16 kbytes  
1996 Mar 22  
4
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
6
PINNING INFORMATION  
Pinning  
6.1  
handbook, halfpage  
V
/TDAC/P0.0  
1
2
42 V  
PP  
DD  
handbook, halfpage  
PROG/PWM1/P0.1  
41 P3.7  
3
40  
39  
38  
37  
36  
ASEL/PWM2/P0.2  
PWM3/P0.3  
PWM4/P0.4  
PWM5/P0.5  
PWM6/P0.6  
PWM7/P0.7  
ADI0/P1.0  
P3.6  
4
P3.5  
5
P3.4  
6
P3.3/INT0  
P3.2/T0  
7
8
35 P3.1/INT1  
9
34  
33  
32  
31  
P3.0  
83C145  
83C845  
83C055  
87C055  
10  
11  
12  
ADI1/P1.1  
RST  
ADI2/P1.2  
XTAL2  
XTAL1  
PWM0/P1.3  
P2.7 13  
30 BF  
14  
15  
16  
17  
18  
19  
20  
21  
29  
28  
27  
26  
25  
24  
23  
22  
P2.6  
P2.5  
P2.4  
P2.3  
P2.2  
P2.1  
P2.0  
VCLK2  
VCLK1  
VSYNC  
HSYNC  
VCTRL  
VID2  
VID1  
V
VID0  
SS  
MBE765  
Fig.2 Pin configuration (SOT270-1).  
1996 Mar 22  
5
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
6.2  
Table 2 Pin description SDIP42 (SOT270-1)  
SYMBOL PIN  
Port 0 (notes 1, 2 and 4)  
Pin description  
DESCRIPTION  
P0.0/TDAC/VPP  
1
P0.0: open-drain bidirectional port line;  
TDAC: output for the 14-bit high-precision PWM;  
VPP: 12 V programming supply voltage during EPROM programming.  
P0.1/PWM1/PROG  
P0.2/PWM2/ASEL  
2
3
P0.1: open-drain bidirectional port line;  
PWM1: output for the 6-bit lower-precision PWM;  
PROG: input for EPROM programming pulses.  
P0.2: open-drain bidirectional port line;  
PWM2: output for the 6-bit lower-precision PWM;  
ASEL: input indicating the EPROM address bits that are applied to Port 2.  
P0.3/PWM3  
to  
4 to 8 P0.3 to P0.7: 5 open-drain bidirectional port lines;  
PWM3 to PWM7: 5 outputs for the 6-bit lower-precision PWM.  
P0.7/PWM7  
Port 1 (notes 1, 2 and 5)  
P1.0/ADI0  
to  
9 to 11 P1.0 to P1.2: 3 open-drain bidirectional port lines;  
ADI0 to ADI2: inputs for the software analog-to-digital facility.  
P1.2/ADI2  
P1.3/PWM0  
12  
P1.3: open-drain bidirectional port line; PWM0: output for the 6-bit lower-precision  
PWM. PWM0 can be externally pulled up as high as +12 V ±5%  
Port 2  
P2.7 to P2.0  
13 to 20 Port 2: 8-bit open-drain bidirectional port; P2.3 to P2.0 have high current capability  
(10 mA at 0.5 V) for driving LEDs. Port 2 pins that have logic 1s written to them float,  
and in that state can be used as high-impedance inputs. Any of the Port 2 pins are  
driven LOW if the port register bit is written as a logic 0. The state of the pin can  
always be read from the port register by the program.  
Port 3 (note 1 and 3)  
P3.0  
34  
35  
36  
37  
P3.0: open-drain bidirectional port line.  
P3.1/INT1  
P3.2/T0  
P3.1: open-drain bidirectional port line; INT1: External interrupt 1.  
P3.2: open-drain bidirectional port line; T0: Timer 0 external input.  
P3.3: open-drain bidirectional port line; INT0: External interrupt 0.  
P3.3/INT0  
P3.4 to P3.7  
38 to 41 P3.4 to P3.7: 4 open-drain bidirectional port lines.  
General  
VSS  
21  
Ground: 0 V reference.  
VID2 to VID0  
22 to 24 Digital Video bus: Three totem-pole outputs comprising digital RGB (or other colour  
encoding) from the OSD facility. The polarity of these outputs is controlled by a  
programmable register bit (register OSCON; bit Po).  
VCTRL  
25  
Video Control: A totem-pole output indicating whether the OSD facility is currently  
presenting active video on the VID2 to VID0 outputs. Signal is used to control an  
external multiplexer (mixer) between normal video and the video derived from VID2 to  
VID0. The polarity of this output is controlled by a programmable register bit (register  
OSCON; bit Pc).  
1996 Mar 22  
6
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
SYMBOL  
HSYNC  
PIN  
DESCRIPTION  
26  
Horizontal Sync: A dedicated input for a TTL-level version of the horizontal sync  
pulse. The polarity of this pulse is programmable; its trailing edge is used by the OSD  
facility as the reference for horizontal positioning.  
VSYNC  
27  
Vertical Sync: A dedicated input for a TTL-level version of the vertical sync pulse. The  
polarity of this pulse is programmable, and either edge can serve as the reference for  
vertical timing.  
VCLK1  
VCLK2  
28  
29  
VCLK1: Video Clock 1; input for the horizontal timing reference for the OSD facility.  
VCLK2: Video Clock 2; output from the on-chip video oscillator. VCLK1 and VCLK2  
are intended to be used with an external LC circuit to provide an on-chip oscillator. The  
period of the video clock is determined such that the width of a pixel in the OSD is  
equal to the inter-line separation of the raster.  
BF  
30  
Background/Foreground: A totem-pole output which, when VCTRL is active,  
indicates whether the current video data represents a Foreground (LOW) or  
Background (HIGH) dot in a character. This signal can be used to reduce the intensity  
of the background colour and thus emphasize the text.  
XTAL1  
XTAL2  
31  
32  
XTAL1: Input to the inverting (oscillator) amplifier and clock generator circuit that  
provides the timing reference for all 83C055 logic other than the OSD facility.  
XTAL2: Oscillator output terminal for system clock. XTAL1 and XTAL2 can be used  
with a quartz crystal or ceramic resonator to provide an on-chip oscillator. Alternatively,  
XTAL1 can be connected to an external clock, and XTAL2 left unconnected.  
RST  
33  
42  
Reset: If this pin is HIGH for two machine cycles (24 oscillator periods) while the  
oscillator is running, the MTV is reset. This pin is also used as a serial input to enter a  
test or EPROM programming mode, as on the 87C751.  
VDD  
Power supply: for normal and Power-down operation.  
Notes  
1. Port 0, Port 1 , and Port 3 pins that have logic 1s written to them float, and in that state can be used as  
high-impedance inputs.  
2. The state of the pin can always be read from the port register by the program.  
3. P3.0, P3.4, and P3.7 can be externally pulled up as high as +12 V ±5%; while P3.5 and P3.6 have 10 mA drive  
capability.  
4. For each PWM block, a register bit (register PWMn; bit PWnE; n = 0 to 7) controls whether the corresponding pin is  
controlled by the block or by Port 0; Port 0 controls the pin immediately after a reset. Regardless of how each pin is  
controlled, it can be externally pulled up as high as +12 V ±5%.  
5. Any of the Port 1 pins are driven LOW if the corresponding port register bit is written as a logic 0, or for P1.3 only, if  
the TDAC module presents a logic 0.  
1996 Mar 22  
7
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
• The IP register is not used, and the IE register (address  
7
DESCRIPTION OF STANDARD FUNCTIONS  
A8H) is similar to that on the 80C51;see Table 36.  
For a description of the standard functions please refer to  
the “Data Handbook IC20; Section 2: 80C51 Technical  
Description” .  
• The VSYNC input used by the OSD facility can generate  
an interrupt. The active polarity of the pulse is  
programmable (see Section 13.7); interrupt occurs at  
the leading edge of the pulse.  
8
INPUT/OUTPUT (I/O)  
• Since there is no serial port, there are no interrupts nor  
control bits relating to this interrupt. The interrupts and  
their vector addresses are shown in Table 3.  
The I/O structure of the 83C055 is similar to the standard  
I/O structure in the 80C51, except for the points described  
in Table 5.  
• External Interrupt 1 is modified so that an interrupt is  
generated when the input switches are in either direction  
(on the 80C51, there is a programmable choice between  
interrupt on a negative edge or a LOW level on INT1).  
This facility allows for software pulse-width  
9
DESCRIPTION OF DERIVATIVE FUNCTIONS  
General description  
9.1  
measurement handling of a remote control.  
Although the 83C055 is specifically referred to throughout  
this data sheet, the information applies to all the devices.  
The differences to 80C51 features and the derivative  
functions are described in the following Sections and  
Chapters.  
Table 3 Program Memory address  
EVENT  
Reset  
PROGRAM MEMORY ADDRESS  
000H  
003H  
00BH  
013H  
01BH  
023H  
Figure 1 shows the block diagram of the 83C055.  
External INT0  
Timer 0  
9.1.1  
NOT IMPLEMENTED FUNCTIONS  
External INT1  
Timer 1  
Standard functions to the 80C51 that are not implemented  
in the 83C055:  
VSync Start  
• As Data and Program Memory are not externally  
expandable on the 83C055, the ALE, EA, and  
PSEN signals are not implemented.  
9.1.3  
PCON REGISTER DIFFERENCE  
The PCON register format is shown in Table 4. Bits GF1  
and GF0 are general purpose flag bits.  
• Idle mode.  
• Power-down mode.  
Table 4 PCON Register format (address 87H)  
9.1.2  
INTERRUPT FACILITIES DIFFERENCES  
7
6
5
4
3
2
1
0
The interrupt facilities of the 83C055 differ from those of  
the 80C51 as follows:  
−
−
−
−
GF1 GF0  
−
−
9.1.4  
I/O PORTS DIFFERENCES  
Table 5 I/O ports differences  
I/O  
STANDARD 80C51  
83C055  
Port 0  
external memory expansion  
8-bit open-drain bidirectional port; and includes:  
alternative use for PWM outputs  
Port 1  
Port 2  
Port 3  
8-bit general purpose quasi-bidirectional  
4-bit open-drain port, and includes alternative uses  
for analog inputs and a PWM output  
quasi-bidirectional and can be used for external  
memory expansion  
open-drain and general purpose  
quasi-bidirectional; all eight bits have alternate uses 3 port bits have some of the same alternative uses  
as on the 80C51 but not necessarily on the same  
pins; 5 pins are open-drain and general purpose  
1996 Mar 22  
8
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
When the value matches, the output flip-flop is cleared, so  
that the output pin is driven LOW.  
10 6-BIT PWM DACS  
Figure 3 shows the 6-bit PWM DAC logic circuit, consisting  
of 8 PWMn modules.  
When the value rolls over to zero, the output flip-flop is set,  
so that the output pin is released. Thus the output  
waveform has a fixed period of 64 PWM clock cycles; its  
duty cycle is determined by contents of PWMn.5 to  
PWMn.0 (PVn5 to PVn0).  
The basic MCU clock is divided by 4 to get a waveform that  
clocks a 14-bit counter which is common to all the PWMs  
(including the 14-bit PWM). This divided clock is hereafter  
called the PWM clock.  
Three of the nine total PWM modules (8 PWMn and the  
14-bit PWM DAC) operate as previously described; for  
three others, both the rising and falling edges of the output  
are delayed by one PWM clock; for the remaining three,  
both edges are delayed by two PWM clocks. This feature  
reduces the radio-frequency emission that would  
otherwise occur when the counter rolled over to zero and  
all nine open-drain outputs were released.  
As illustrated in Fig.3, the lower-precision (6-bit) PWMs  
use the least significant part of the 14-bit counter.  
Figure 4 shows the circuit diagram of a 6-bit PWM module.  
Each PWM module has a Special Function Register  
PWMn; n = 0 to 7. The register format is shown in Table 6.  
10.1 PWM DAC operation  
Value field PVn5 to PVn0 of each PWMn register  
(n = 0 to 7) is compared to the 6 LSBs of the common  
counter (14-bit counter).  
10.2 Special Function Register PWMn (n = 0 to 7)  
Table 6 Special Function Register PWMn (n = 0 to 7; addresses D4H to DFH)  
7
6
5
4
3
2
1
0
PWnE  
−
PVn5  
PVn4  
PVn3  
PVn2  
PVn1  
PVn0  
Table 7 Description of PWMn bits  
BIT  
SYMBOL  
DESCRIPTION  
7
PWnE  
PWM module enable bit. If for a particular PWM block (n) the bit:  
PWnE = 1, then the block is active and controls its assigned port pin.  
PWnE = 0, the corresponding port pin is controlled by the port.  
Reserved.  
6
−
5 to 0  
PVn5 to PVn0 Value field for PWMn register.  
1996 Mar 22  
9
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
ZERO  
P1.3  
8
6
1st PWM MODULE (n = 0)  
PWM0/P1.3  
8
8
8
8
P0.1  
6
6
6
2nd PWM MODULE (n = 1)  
PWM1/P0.1  
P0.2 to P0.6  
PWM2/P0.2  
to  
PWM6/P0.6  
3rd to 7th PWM MODULE (n = 2 to 6)  
P0.7  
8th PWM MODULE (n = 7)  
PWM7/P0.7  
6
internal bus  
LS 6-bits  
PWM clock  
4
14-BIT PWM  
f
14-BIT COUNTER  
xtal  
DAC BLOCK  
MBE771 - 1  
Fig.3 6-bit PWM DAC logic circuit.  
I/O port  
PWM module (n)  
PWMn  
I/O pin  
ZERO  
LS 6-bits  
6-bit  
COMPARATOR  
(1)  
(2)  
6-bits (PVn0 to PVn5)  
8
PVn0  
PVn1  
PVn2  
PVn3  
PVn4  
PVn5  
PWnE  
internal bus  
PWM clock  
MBE770  
(1) This flip-flop occurs in 5 of the 8 PWMn modules.  
(2) This flip-flop occurs in 3 of the 8 PWMn modules.  
Fig.4 A 6-bit PWM module.  
10  
1996 Mar 22  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
11 14-BIT PWM DAC (TDAC)  
11.1 14-bit counter  
11.2.2 HIGH PRECISION OPERATION  
For the higher-precision aspect of this feature, the 7 MSBs  
of the counter are used in a logic block with the 7 LSBs of  
the programmed value.  
The 14-bit counter was already mentioned in Section 10.  
The nature of the counter is such that it can achieve a  
stable output value through its MSB, and the value can  
propagate through logic like that shown in Fig.5. The logic  
output can be stable within:  
The 7th LSB (binary value 64) of the programmed value is  
ANDed with the 7th MSB (128) of the counter, the 6th LSB  
of the value is ANDed with the counter’s 6th and 7th MSBs  
being 10, and so on through the LSB of the programmed  
value being ANDed with the counter’s 7 MSBs being  
100000. Then these 7 ANDed terms are ORed. If the  
result is true (logic 1) at the time the 7 LSBs of the counter  
match the MSBs of the programmed value, the output is  
forced high for 1 (additional) PWM clock cycle.  
• one period of the PWM clock (e.g. 250 ns) if  
edge-triggered logic is used to capture the logic output,  
or  
• one phase of the PWM clock (e.g. 125 ns) if a phase of  
the PWM clock is used to capture the logic output.  
The 14-bit (TDAC) counter is a ripple counter (cost and  
die-size reasons).  
The result is that, if the value-64 bit of the 14-bit value is  
programmed to a logic 1, every other cycle of 128 PWM  
counter clocks has its duty cycle stretched by one counter  
clock; if the value-32 bit is programmed to logic 1, every  
4th cycle is stretched, and so on through, if the value-1 bit  
is programmed to logic 1, one cycle out of each 128 is  
stretched.  
The 14-bit PWM DAC is controlled by two special function  
registers TDACL and TDACH.  
11.2 14-bit DAC operation  
When software wishes to change the 14-bit value  
(TD0 to TD13), it should first write to TDACL and then  
write to TDACH. Alternatively, if the required precision of  
the duty cycle is satisfied by 6 bits or less, software can  
simply write to TDACH (TD8 to TD13).  
11.2.3 14-BIT DAC OUTPUT  
Assuming the external integrator can handle all this, the  
net effect is a PWM DAC that has the period of a 7-bit  
design (which makes the integrator easier and more  
feasible to design) with the accuracy of a 14-bit one.  
11.2.1 LOW PRECISION OPERATION  
An obvious prerequisite for such precision is that the load  
on the voltage must be very light, like a single op-amp or  
comparator.  
Figure 5 shows that this block includes an ‘extra’ 14-bit  
latch between TDACL - TDACH and the comparator and  
other logic. The programmed value is clocked into the  
operative latch when the 7 low-order bits of the counter roll  
over to zero, provided that the software is not in the midst  
of loading a new 14-bit value, i.e. it is not between writing  
TDACL and writing TDACH.  
11.2.3.1 Note  
The TDAC feature differs from the corresponding features  
of predecessor parts in several ways:  
In a similar fashion to the lower-precision PWMs, this  
facility has an output flip-flop that is set when the lower  
7 bits of the counter overflow/wrap. The more significant  
7 bits of the operative latch’s programmed value are  
compared for equality against the less significant 7 bits of  
the counter, and the output FF is cleared when they match.  
Thus this output has a fixed period of 128 PWM clock  
cycles, and the duty cycle is determined by the  
programmed value.  
1. The 14-bit value is functionally composed of major and  
minor portions of 7 bits each.  
2. The 14-bit value is programmed as a contiguous  
multi-register value that can be manipulated  
straight-forwardly via arithmetic instructions.  
3. As discussed for the 6-bit DACs, both of the preceding  
parts had a feature whereby the PWM output could be  
inverted, redundantly with complementing the 14-bit  
value. This feature has been eliminated.  
1996 Mar 22  
11  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
11.3 Special Function Register TDACL  
Table 8 Special Function Register TDACL format (address D2H)  
7
6
5
4
3
2
1
0
TD7  
TD0  
TD1  
TD2  
TD3  
TD4  
TD5  
TD6  
Table 9 Description of TDACL bits  
BIT  
SYMBOL  
DESCRIPTION  
7 to 0  
TD7, TD0 to TD6  
8 LSBs of the 14-bit value.  
11.4 Special Function Register TDACH  
Table 10 Special Function Register TDACH format (address D3H)  
7
6
5
4
3
2
1
0
TDE  
−
TD13  
TD12  
TD11  
TD10  
TD9  
TD8  
Table 11 Description of TDACH bits  
BIT  
7
SYMBOL  
DESCRIPTION  
TDE  
Enable bit.  
Reserved.  
6
−
5 to 0  
TD13 to TD8 6 MSBs of the 14-bit value.  
1996 Mar 22  
12  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
INTERNAL BUS  
7
7
TDACL  
TDACH  
8
8
14-BIT LATCH  
7
7 MSB  
7 LSB  
7
7-BIT COMPARATOR  
7
TDACH.7  
TDAC/  
P0.0  
P0.0  
7
7
7 LSB  
7 MSB  
PWM clock  
f
4
14-BIT COUNTER  
xtal  
MBE774  
Fig.5 14-bit PWM logic circuit.  
13  
1996 Mar 22  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
12 SOFTWARE ANALOG-TO-DIGITAL FACILITY  
Figure 6 shows the software analog-to-digital facility block diagram. The block includes Special Function Register SAD.  
12.1 Special Function Register SAD  
Table 12 Special Function Register SAD format (address D8H)  
7
6
5
4
3
2
1
0
VHi  
CH1  
CH0  
St  
SAD3  
SAD2  
SAD1  
SAD0  
Table 13 Description of SAD bits  
BIT  
SYMBOL  
DESCRIPTION  
The comparator output bit; bit addressable.  
7
VHi  
CH1  
CH0  
St  
6
5
The channel field controls which pin, if any, is connected to this facility; see Table 14.  
4
The St bit should be written as a logic 1 in order to initiate a voltage comparison.  
3 to 0  
SAD3 to SAD0 4 LSBs of the SAD register.  
12.2 Software ADC operation  
Table 14 Pin selection: P1.n/ADIn  
Port pins P1.0/ADI0 to P1.2/ADI2 can be alternately  
selected as inputs of a linear voltage comparator. The  
other input of the comparator is connected to a 4-bit DAC.  
CH1  
CH0  
P1.n/ADIn(1)  
none  
0
0
1
1
0
1
0
1
P1.0/ADI0  
P1.1/ADI1  
P1.2/ADI2  
This DAC is controlled by bits SAD3 to SAD0 and  
produces a reference voltage:  
nominally 0.15625 to 4.84375 V in increments of  
0.3125 V.  
Note  
1. Port 1 has open-drain drivers which will not materially  
affect an analog voltage as long as any and all pins  
used for software analog-to-digital measurement have  
corresponding logic 1s in the port register; n = 0, 1, 2.  
The output of the comparator (HIGH or LOW) can be read  
by the program as the MSB of the SAD register i.e. bit VHi.  
After writing St = 1, the program should include intervening  
instructions totalling at least 6 machine cycles (72 clock  
periods or 6 µs at 12 MHz), before the instruction that  
accesses and tests VHi.  
1996 Mar 22  
14  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
I/O PORT  
I/O PORT  
I/O PORT  
VOLTAGE  
COMPARATOR  
P1.0/ADI0  
P1.1/ADI1  
P1.2/ADI2  
ANALOG  
MUX  
4-BIT  
DAC  
SAD.6:5  
SAD.3:0  
internal bus  
MBE772  
Fig.6 Software analog-to-digital facility.  
1996 Mar 22  
15  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
13 ON SCREEN DISPLAY (OSD)  
13.1.3 DUAL-PORTED DISPLAY RAM  
Figure 7 shows the OSD block diagram. It shows the CPU  
writing into the 128 × 10 display RAM, which is dual-ported  
to allow the CPU to write into it at any time, including when  
it is being read out by the OSD logic. The 10-bit wide data  
coming out of the display RAM is used to access the  
appropriate character in the Character Generator memory  
(6-bits) and to specify character and display control  
functions (4-bits).  
The OSD has a true display RAM instead of a character  
line buffer. This display RAM is dual-ported to allow  
updating the display RAM at any time instead of having to  
wait for a vertical retrace.  
Vertical Sync (VSYNC) interrupts are supported if  
flicker-free updates are required.  
13.1.4 PROGRAMMABLE CHARACTER SIZE  
Timing for the OSD is controlled by the HSYNC, VSYNC,  
and dot clock input VCLK1.  
• Normal characters are displayed as 18 × 14 bit maps.  
• In an interlaced display:  
13.1 OSD features  
– 2 fields are displayed so that one actually sees a  
36 × 14 pixel size character.  
The 83C055 features an advanced OSD function with  
some unique features as described in Sections 13.1.1 to  
13.1.10.  
– The part has a double height and width mode which  
displays 36 × 28 pixel size bit maps per field.  
• For use in non-interlaced systems, the part has a double  
height mode so that the displayed characters have the  
same pixel size (36 × 14) as on an interlaced display.  
13.1.1 USER-DEFINABLE DISPLAY FORMAT  
The OSD does not restrict the user to a fixed number of  
lines with a fixed number of characters per line:  
13.1.5 CHARACTER SHADOWING  
• Using a fixed number of lines restricts the generation of  
displays that can be differentiated from others that use  
the same chip and places limits on screen content.  
When characters are displayed overlaid on a background  
of base video, a black border around the characters makes  
them highly legible. This feature is called shadowing. The  
83C055 has 8 shadowing modes to allow the user to select  
various partial shadow modes as well as full surround  
shadow; see Fig.8 and Table 28.  
• Using a fixed number of characters per line wastes  
display RAM if a line has less than the full number of  
displayable characters (it has to be padded with  
non-visible characters).  
The OSD on the 83C055 defines a control character:  
13.1.6 PROGRAMMABLE POLARITIES  
• New Line, that has the same function as a Carriage  
Return and Line Feed.  
Inputs to and outputs from the OSD can be programmed  
to be recognized as active LOW or HIGH. In conjunction  
with the 12 V outputs, this allows direct interfacing to most  
video signal processing circuits.  
When the OSD circuitry fetches this character from display  
RAM it stops displaying further characters, waits for the  
next horizontal scan line, and starts displaying the next  
character in display RAM after the New Line character was  
received.  
13.1.7 CHARACTER GENERATOR MEMORY IN EPROM  
On the 87C055, the Character Generator memory is in  
EPROM. This feature allows quick and inexpensive font  
development and refinement against the alternative of  
creating a masked ROM version to see how the final fonts  
will appear.  
The number of lines is thus up to the user, within the limits  
of the display and memory, as are the number of  
characters per line. This allows far better control of the  
appearance of the OSD.  
13.1.8 HSYNC LOCKED DOT CLOCK OSCILLATOR  
13.1.2 COLOURS SELECTABLE BY CHARACTER  
The 83C055 is designed to use an LC oscillator circuit that  
is started at the trailing edge of HSYNC and stopped at its  
leading edge. In practice, this gives a highly consistent  
delay from HSYNC to oscillator start and is stable from  
scan line to scan line so that no left margin effects are  
seen.  
Characters can be displayed on a background of the base  
video or a programmable background colour.  
The background colour is selectable by word and the  
choice of background (base video/user programmed  
colour) by character.  
1996 Mar 22  
16  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
Figure 7 shows the 3 major elements of the OSD facility:  
• OSD logic  
13.1.9 SHORT ROWS  
This mode only displays 4 horizontal lines and is used for  
generating underlines.  
• Display RAM  
• Character Generator ROM.  
13.1.10 PROGRAMMABLE HORIZONTAL AND VERTICAL  
POSITIONS  
13.3 OSD logic  
Bit pairs HS4 to HS0 and VS2 to VS0 in register OSORG  
(Table 30) define the starting point of the display.  
For a standard NTSC TV signal with an HSYNC frequency  
of 15.750 kHz and a VSYNC frequency of nominally  
60 Hz, there are roughly 50 µs of active horizontal scan  
line available.  
13.2 General description of the OSD module  
This block is the largest of the additions that are specific to  
this product. Its basic function is to superimpose text on  
the television video image, to indicate various parameters  
and settings of the receiver or tuner. External circuitry  
handles the mixing (multiplexing) of the text and the TV  
video. The OSD block has 4 input pins:  
A typical pixel clock frequency is 8 MHz, and therefore  
roughly 400 pixels of resolution can be obtained. At  
14 dots per character, this means 28 character per  
horizontal scan line. If the 12 dot per character display  
mode is used, that means 33 character per horizontal scan  
line. Allowing for edge effects, 26 characters (14 across) or  
31 characters (12 across) can be displayed.  
• Two for a video clock: VCLK1 and VCLK2  
• Horizontal sync signal: HSYNC  
• Vertical sync signal: VSYNC.  
Note that VGA rates and higher can be used. The  
minimum character dot size will be a function of the VGA  
frequency used. For a 640 × 480 display, running at  
33 kHz, the equivalent 83C055 pixel resolution is about  
160 across (because of the 8 MHz clock and allowing for  
overscan). This means that status and diagnostic  
information can be displayed on video monitors.  
The block has 4 outputs:  
• 3 colour video signals  
• a control signal.  
Since this block is the major feature of the part, its main  
inputs and outputs are dedicated pins, without alternate  
port bits. The OSD of the 83C055 differs from that in  
preceding devices in one major way:  
13.3.1 ON-CHIP VIDEO OSCILLATOR  
The video clock pins (VCLK1 and VCLK2) are used to  
connect a LC circuit to an on-chip video oscillator that is  
independent of the normal MCU clock.  
• It does not fix the number and size of displayed rows of  
text.  
The L and C values are chosen so that a video pulse, of a  
duration equal to the VCLK period, will produce a  
more-or-less square dot on the screen, that is, a dot having  
a width approximately equal to the vertical distance  
between consecutive scan lines.  
Several predecessor parts allowed two displayed rows of  
16 characters each. The 83C055 simply has 128 locations  
of Display RAM, each of which can contain:  
• a displayed character, or  
• a New Line character that indicates the end of a row.  
A variant of the New Line character is used to indicate  
the end of displayed data.  
The video oscillator is stopped (with VCLK2 = LOW) while:  
• HSYNC (Horizontal Sync) is maintained, and  
• is released to operate at the trailing edge of HSYNC.  
A number of changes in the OSD architecture have  
reduced the number of other Special Function Registers  
involved in the feature, below the number needed with  
predecessor devices:  
This technique helps provide uniform horizontal  
positioning of characters/dots from one scan line to the  
next.  
1. The elimination of certain options such as 4, 6, or  
8 × character sizes and alternate use of two of the  
video outputs.  
2. The moving of certain other options from central  
registers to Display RAM, such as foreground colour  
codes (Fcolor) and background (B) selection.  
1996 Mar 22  
17  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
13.4 Character Generator ROM  
13.5 Display RAM organization  
Character Generator ROM. Containing 60 displayable bit  
maps, i.e. 64 minus 4, comprising:  
Each Display RAM location includes:  
• 6 data bits, and  
• One for each of new line: New Line, and  
• Three space characters:  
– Space  
• 4 attribute bits.  
The 6 data bits from Display RAM, along with a  
line-within-row count, act as addresses into the Character  
Generator ROM. Except in special test modes that are  
beyond the scope of this data sheet, Display RAM cannot  
be read by the MCU program.  
– BSpace  
– SplitBSpace.  
Each bit map includes 18 scan lines by 14 dots.  
The Character Generator ROM is maskable or  
programmable along with the Program ROM to allow for  
various character sets and languages.  
d
HSYNC  
VCLK2  
VCLK1  
OSD LOGIC  
VSYNC  
7
7
4
VCTRL  
internal  
bus  
OSD RAM  
128 × 10  
ATTRIBUTE  
CONTROL  
VID2  
RGB  
DIGITAL  
6
VIDEO OUT  
VID1  
6
CHARACTER  
GENERATOR  
CHARACTER  
GENERATOR  
ADDRESS LOGIC  
60 × 18 × 14  
VID0  
MBG323  
Fig.7 OSD block diagram.  
1996 Mar 22  
18  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
need not be rewritten for each character, only prior to  
writing OSDT for the first character with those particular  
attributes.  
13.6 OSD Special Function Registers  
The programming interface to Display RAM is provided by  
three Special Function Registers as shown in Tables 15,  
17 and 20.  
The OSAT attribute bits associated with the BSpace,  
SplitBSpace and New Line characters (see Table 19) are  
interpreted differently from those that accompany other  
data characters. With BSpace and SplitBSpace, B is  
interpreted as described above, but the 3 colour bits  
specify the background colour (Bcolor) for subsequent  
characters. For BSpace, a change in B and Bcolor  
becomes effective at the left edge of the character’s bit  
map.  
Writing OSAT simply latches the attribute bits into a  
register, while writing OSDT causes the data bus  
information, plus the contents of the OSAT register, to be  
written into display RAM.  
Thus, for a given Display RAM location, OSAT should be  
written before OSDT. If successive characters are to be  
written into Display RAM with the same attributes, OSAT  
13.6.1 SPECIAL FUNCTION REGISTER OSAD  
Table 15 Special Function Register OSAD (On Screen ADdress; address 9AH)  
7
6
5
4
3
2
1
0
−
OSAD6  
OSAD5  
OSAD4  
OSAD3  
OSAD2  
OSAD1  
OSAD0  
Table 16 Description of OSAD bits  
BIT  
7
SYMBOL  
−
DESCRIPTION  
Reserved.  
6 to 0  
OSAD6 to OSAD0  
These 7-bits hold the Display RAM address into which data will be  
loaded. OSAD is automatically incremented by one each time OSDT and  
Display RAM are written to.  
13.6.2 SPECIAL FUNCTION REGISTER OSDT  
Writing OSDT causes the data bus information, plus the contents of the OSAT register, to be written into display RAM.  
Table 17 Special Function Register OSDT (On Screen DaTa; address 99H)  
7
6
5
4
3
2
1
0
−
−
OSDT5  
OSDT4  
OSDT3  
OSDT2  
OSDT1  
OSDT0  
Table 18 Description of OSDT bits  
BIT  
SYMBOL  
−
DESCRIPTION  
7 to 6  
5 to 0  
Reserved.  
OSDT5 to OSDT0  
Character data; see Table 19. In reality, there is a potential conflict  
between the timing of a write to OSDT and an access to display RAM by  
the OSD logic for data display. This is resolved by the use of a true  
dual-ported RAM for display memory.  
1996 Mar 22  
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Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
Table 19 Special characters related to OSDT register  
SPECIAL CHARACTER  
OSDT5  
OSDT4  
OSDT3  
OSDT2  
OSDT1  
OSDT0  
New Line  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
Space (normal)  
BSpace  
SplitBspace  
13.6.3 SPECIAL FUNCTION REGISTER OSAT  
Table 20 Special Function Register OSAT ( On Screen ATtributes; address 98H)  
WITH OSDT =  
New Line  
7
−
−
−
−
6
−
−
−
−
5
−
−
−
−
4
E
B
B
B
3
−
−
−
−
2
1
0
SR  
D
Sh  
BSpace  
BC2  
BC2  
FC2  
BC1  
BC1  
FC1  
BC0  
BC0  
FC0  
SplitBSpace  
Any other character  
Table 21 Description of OSAT bits  
BIT  
SYMBOL  
DESCRIPTION  
7 to 5, 3  
−
Reserved.  
With OSDT = New Line; note 1  
4
2
E
End; If the E bit is 1, no further rows are displayed on the screen.  
SR  
Short row; If E = 0 and SR = 1, the next row is a ‘short row’, i.e. it is only 4 or 8 scan lines high  
rather than 18 or 36. Short rows can be used for underlined text.  
1
0
D
Double height; If E = 0 and D = 1, all of the characters in the following row are displayed with  
‘double height and width’.  
Sh  
Shadowing; If E = 0 and Sh = 1, all of the characters in the following row are displayed with  
‘shadowing’; see Section 13.8.  
With OSDT = BSpace or SplitBspace; note 2  
4
B
Background; B indicates whether ‘background pixels’ should show the current background  
colour (B = 1), or television video (B = 0).  
2 to 0 BC2 to BC0 Bcolor: Background colour (notes 3 and 4; see Table 22).  
With OSDT = Any other character  
4
B
Background; B indicates whether ‘background pixels’ should show the current background  
colour (B = 1), or television video (B = 0).  
2 to 0 FC2 to FC0 Fcolor: Foreground colour. Fcolor indicates the colour of ‘foreground pixels’ in the ROM bit  
map for this character (see Table 22).  
1996 Mar 22  
20  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
Notes to the description of OSAT bits  
1. The latches in which the E,SR, D, and Sh bits are captured are cleared to zero at the start of each vertical scan. This  
means that if the first text line on the screen is a short row, or if it contains either double size or shadowing, the text  
must be preceded by a New Line character. Like all such characters, this initial New Line advances the vertical  
screen position; the VStart value (see register OSORG; Section 13.9) should take this fact into account.  
2. For SplitBSpace, a change in B and Bcolor occurs halfway through the character horizontally.  
3. The normal Space character has no effect on the Bcolor value.  
4. The Bcolor value is not cleared between vertical scans, so that if a single background colour is all that is needed in  
an application, it can be set via a single BSpace character during program initialization, and never changed  
thereafter. In order for such a BSpace to actually affect the 83C055 internal Bcolor register the Mode field of the  
OSMOD register must be set to ‘01B’ (or higher) so that the OSD hardware is operating (see register OSMOD;  
Section 13.8).  
Table 22 OSD outputs related to character bit map value, Fcolor, Bcolor and B bits  
OSD OUTPUTS (notes 1 and 2)  
CHARACTER BIT MAP VALUE  
VID2  
VID1  
VID0  
VCTRL  
logic 1  
logic 0  
FC2  
BC2  
FC1  
BC1  
FC0  
BC0  
driven active  
B
Notes  
1. Bcolor (BC2,BC1,BC0) values ‘000’ and ‘111’ minimize the occurrence of transient states among the VID2 to VID0  
outputs.  
2. The background colour defined by the most recently encountered BSpace or SplitBSpace character is maintained  
on the VID2 to VID0 pins except at the following times:  
a) During the active time of HSYNC.  
b) During the active time of VSYNC.  
c) During those pixels of an active character that correspond to a logic 1 in the character’s bit map.  
d) During a ‘shadow’ bit.  
1996 Mar 22  
21  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
13.7 OSD Control Register OSCON  
Table 23 OSD Control Register OSCON (address C0H)  
7
6
5
4
3
2
1
0
IV  
Pv  
Lv  
Ph  
Pc  
Po  
DH  
BFe  
Table 24 Description of OSCON bits (see note 1)  
BIT  
SYMBOL  
DESCRIPTION  
7
IV  
Interrupt flag for the OSD feature. Bit IV is set by the leading edge of the VSYNC pulse,  
and is cleared by the hardware when the VSYNC interrupt routine is vectored to. It can  
also be set or cleared by software writing a logic 1 or logic 0 to this bit.  
6
5
Pv  
Lv  
Pv defines the active VSYNC input polarity. If Pv = 0, then VSYNC input is active HIGH;  
if Pv = 1, then VSYNC input is active LOW.  
One effect of bit Pv is that the VID2 to VID0 and VCTRL outputs are blocked (held at  
black/inactive) during the active time of VSYNC. The IV bit is set on the leading edge of  
the VSYNC pulse; thus Pv controls whether the OSD interrupt occurs in response to a  
HIGH-to-LOW or LOW-to-HIGH transition on VSYNC.  
Lv defines the active edge of VSYNC. The active edge (leading or trailing) of VSYNC  
(as defined by Pv), clears the state counter which determines the vertical start of on  
screen data. Time reference for the video field is the leading edge of VSYNC, if Lv = 0,  
or the trailing edge of VSYNC, if Lv = 1.  
4
3
Ph  
Pc  
Ph defines the active HSYNC input polarity. If Ph = 0, then HSYNC input is active HIGH;  
if Ph = 1, then HSYNC input is active LOW.  
Pc defines the active VCTRL output polarity; VCTRL output active means: show the  
colour on VID2 to VID0. If Pc = 0, then VCTRL output is active HIGH; If Pc = 1, then  
VCTRL output is active LOW.  
2
Po  
Po defines the VID2 to VID0 outputs polarity; bit is needed only because the Shadowing  
feature needs to generate black pixels without reference to a register value. Internally,  
the 3-bit code ‘000B’ always designates black.  
If Po = 0, a logic 0 internal to the 83C055 corresponds to a LOW on one of the  
VID2 to VID0 pins.  
If Po = 1, a logic 1 internal to the 83C055 corresponds to a LOW on one of the  
VID2 to VID0 pins.  
1
0
DH  
If DH = 1, character sizes are doubled vertically but not horizontally. This feature allows  
the 83C055 to be used in ‘improved definition’ systems that are not interlaced.  
The vertical doubling imposed by DH does not affect the VStart logic as described in  
Table 30; it operates in HSync units regardless of DH or D.  
BFe  
Background/Foreground enable; output BF. If BFe = 1, then the BF output tracks  
whether each bit in displayed characters is a Foreground bit (LOW), or a Background bit  
(HIGH). If BFe = 0, then the BF pin remains HIGH.  
Note  
1. It is theoretically possible that a VSYNC interrupt could be missed, or an extra one generated, if OSCON is read,  
then modified internally (e.g. in ACC), and the result written back to OSCON. However, none of the other bits in  
OSCON are reasonable candidates for dynamic change. Special provisions are included in the 83C055 logic so that  
IV will not be changed by a single ‘read-modify-write’ instruction such as SETB or CLR, unless the instruction  
specifically changes IV.  
1996 Mar 22  
22  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
13.8 OSD Control Register OSMOD  
Under some conditions writing to OSMOD while the display is active can cause a temporary flicker during that display  
field. This can be avoided by only writing to OSMOD during the vertical sync interval.  
Table 25 OSD Control Register OSMOD (address C1H)  
7
6
5
4
3
2
1
0
Wc  
−
Mode1  
Mode0  
−
SHM2  
SHM1  
SHM0  
Table 26 Description of OSMOD bits (see note )  
BIT  
SYMBOL  
DESCRIPTION  
7
Wc  
If Wc = 1, then each displayed character is horizontally terminated after  
12 bits have been output, as opposed to after 14 bits if Wc = 0. This  
allows text to be ‘packed’ more tightly so that more characters can be  
displayed per line. In effect, the 2 bits out of the display ROM, which  
would otherwise be the rightmost 2 of the 14, are ignored when Wc is 1.  
Clearly, if this feature is to be used, it must be accounted for in the design  
of the bit maps in the display ROM.  
6
−
Mode1  
Reserved.  
5
4
Display mode select bits; see Table 27.  
Mode0  
3
−
Reserved.  
2 to 0  
SHM2 to SHM0  
Shadowing mode (ShMode); determines how characters are shadowed  
in rows for which the row attribute Sh = 1 (register OSAT; see Table 21);  
for the shadowing modes see Fig.8 and Table 28.  
Table 27 Selection of Display Modes  
Mode1 Mode0  
DISPLAY MODE  
0
0
1
0
1
0
Mode 0 The OSD feature is disabled. VCLK oscillator is disabled, VID2 to VID0 are set to black, and  
VCTRL is held inactive.This is the mode to which the 83C055 OSD logic is reset; note 1.  
Mode 1 The VCLK oscillator is enabled and the OSD logic operates normally internally, but  
VID2 to VID0 are set to black and VCTRL is held inactive; note 2.  
Mode 2 Normal OSD operation. Active characters can be shown against TV video (for characters  
with B = 0) or (for characters with B = 1) against a background of the colour defined as an  
attribute of BSpace and SplitBSpace characters.  
1
1
Mode 3 Characters can be displayed but all of the receiver’s normal video is inhibited by holding  
VCTRL asserted throughout the active portion of each scan line; see note 3.  
Notes  
1. A direct transition from this mode to ‘active display’ (Mode1, Mode0 = 1X) would result in undefined operation and  
visual effects for the duration of the current video field (until the next VSYNC).  
2. The OSD feature can be toggled between this state and ‘active display’ as desired to achieve real-time special effects  
such as ‘vertical wiping’.  
3. Since VID2 to VID0 are driven with the current background colour during this time, except during the foreground  
portion of displayed characters, this produces text against a solid background. This mode is useful for extensive  
displays that require user concentration.  
1996 Mar 22  
23  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
Table 28 Shadowing modes determined by bits SHM2 to SHM0 (register OSMOD) and Sh (register OSAT)  
SHM2  
SHM1  
SHM0  
Sh  
SHADOWING MODE(1)  
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
1
1
1
1
1
1
1
1
0
South-west  
West  
North-west  
North  
North-east  
East  
South-east  
Full surround  
No Shadowing  
Note  
1. The mode names are based on the position of an apparent light source, ranging from the lower left (South-west)  
clockwise to the lower right (South-east); see Fig.8.  
13.9 OSD Control Register OSORG  
Table 29 OSD Control Register OSORG (address C2H)  
7
6
5
4
3
2
1
0
HS4  
HS3  
HS2  
HS1  
HS0  
VS2  
VS1  
VS0  
Table 30 Description of OSORG bits (note 1)  
BIT  
SYMBOL  
DESCRIPTION  
7 to 3  
HS4 to HS0 HStart field; defines the horizontal start position of all the on-screen character rows, as  
approximately a multiple of 4 VCLK clock cycles. Active display begins after the trailing  
edge of HSYNC at the position:  
HP = [4 × (HStart) + 1] × VCLK clock cycle + (one single-sized character width)  
Where (HStart) is the decimal value of bits (HS4 to HS0); note 2.  
2 to 0  
VS2 to VS0 VStart field; defines the vertical start position of the first on-screen character row, as  
approximately a multiple of 4 HSYNC pulses. Active display begins after the field’s time  
reference point (a range of 3 to 31)at the position:  
VP = [4 × (VStart) – 1] × HSYNC pulses  
Where (VStart) is the decimal value of bits (VS2 to VS0); note 3.  
Notes  
1. Neither the Hstart nor Vstart parameter is affected by the D line attribute that is used to display double-sized  
characters.  
2. Counting variations in Wc, there may be 17 to 143 VCLK clock cycles from the end of HSYNC to the start of the first  
character of each row.  
3. Subsequent character rows occur directly below the first, such that the last scan line of one row is directly followed  
by the first scan line of the next row. Successive New Line characters (with or without the Short Row designation)  
can be used to vertically separate text rows on the screen.  
1996 Mar 22  
24  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
foreground  
colour pixel  
black pixel  
background  
colour pixel  
apparent light  
source  
ShMode = 010  
ShMode = 001  
ShMode = 000  
ShMode = 011  
No Shadowing  
ShMode = 111  
ShMode = 100  
ShMode = 101  
ShMode = 110  
MBE773  
ShMode = (SHM2, SHM1, SHM0)  
Fig.8 Effect of shadowing on the letter ‘E’.  
25  
1996 Mar 22  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
14 PROGRAMMING CONSIDERATIONS  
14.1 EPROM Characteristics  
The 87C055 is programmed by using a modified Quick-Pulse Programming algorithm similar to that used for devices  
such as the 87C751. It differs from these devices in that a serial data stream is used to place the 87C055 in the  
programming mode.  
Figure 9 shows a block diagram of the programming configuration for the 87C055.  
Table 31 Pin usage for Programming  
PIN  
USAGE  
XTAL1  
RESET  
Oscillator input and receives the master system clock. This clock should be between  
1.2 and 6 MHz.  
Used to accept the serial data stream that places the 87C055 into various programming modes.  
This pattern consists of a 10-bit code with the LSB sent first. Each bit is synchronized to the  
clock input, XTAL1.  
Port 0  
VPP/TDAC/P0.0  
Used as the programming voltage supply input (VPP signal).  
PROG/PWM1/P0.1 Used as the program PROG signal. This pin is used for the 25 programming pulses.  
Port 2  
P2.7 to P2.0  
Address input for the byte to be programmed and accepts both the high- and low-order  
components of the 11-bit address; note 1.  
Port 3  
P3.7 to P3.0  
Used as a bidirectional data bus during programming and verify operations. During programming  
mode, it accepts the byte to be programmed. During verify mode, it provides the contents of the  
EPROM location specified by the address which has been supplied to Port 2.  
Note  
1. Multiplexing of these address components is performed using the ASEL input:  
a) ASEL input is driven HIGH and then drive Port 2 with the high-order bits of the address. ASEL should remain  
HIGH for at least 13 clock cycles.  
b) ASEL may then be driven LOW which latches the high-order bits of the address internally. The high-order address  
should remain on Port 2 for at least 2 clock cycles after ASEL is driven LOW.  
c) Port 2 may then be driven with the low byte of the address. The low-order address will be internally stable 13 clock  
cycles later. The address will remain stable provided that the low byte placed on Port 2 is held stable and ASEL  
is kept LOW.  
d) ASEL needs to be pulsed HIGH only to change the high byte of the address.  
1996 Mar 22  
26  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
14.2 Programming operation  
14.3 Erasure Characteristics  
Figures 10 and 11 show the timing diagrams for the  
Program/Verify cycle. Programming operation:  
Erasure of the EPROM begins to occur when the chip is  
exposed to light with wavelengths shorter than  
approximately 4000 Angstroms. Since sunlight and  
fluorescent lighting have wavelengths in this range,  
exposure to these light sources over an extended time  
(about 1 week in sunlight, or 3 years in room level  
fluorescent lighting) could cause inadvertent erasure.  
1. RST should initially be held HIGH for at least  
2 machine cycles. P0.1 (PROG) and P0.0 (VPP) will be  
at VOH as a result of the RST operation. At this point,  
these pins function as normal quasi-bidirectional I/O  
ports and the programming equipment may pull these  
lines LOW. However, prior to sending the 10-bit code  
on the RST pin, the programming equipment should  
drive these pins HIGH (VIH).  
For this and secondary effects, it is recommended that an  
opaque label be placed over the window. For elevated  
temperature or environments where solvents are being  
used, apply Kapton tape Fluorless (part number 2345-5) or  
equivalent.  
2. The RST pin may now be used as the serial data input  
for the data stream which places the 87C055 in the  
Programming Mode. Data bits are sampled during the  
clock HIGH time and thus should only change during  
the time that the clock is LOW. Following transmission  
of the last data bit, the RST pin should be held LOW.  
The recommended erasure procedure is exposure to  
ultraviolet light (at 2537 Angstroms) to an integrated dose  
of at least 15 Ws/cm2.  
Exposing the EPROM to an ultraviolet lamp of  
12000 µW/cm2 rating for 20 to 39 minutes, at a distance of  
about 1 inch, should be sufficient. Erasure leaves the array  
in an all logic 1s state.  
3. Next the address information for the location to be  
programmed is placed on Port 2 and ASEL is used to  
perform the address multiplexing, as previously  
described (see Table 31; note 1).  
a) At this time, Port 1 functions as an output.  
14.4 Reading Signature Bytes  
b) A high voltage VPP level is then applied to the VPP  
input (P0.0). This sets Port 1 as an input port.  
The Signature Bytes are read by the same procedure as a  
normal verify of locations 30H and 31H (the values are  
shown in Table 32), except that the serial code indicated in  
Table 33 for reading signature bytes should be used.  
c) The data to be programmed into the EPROM array  
is then placed on Port 3. This is followed by a  
series of programming pulses applied to the PROG  
pin (P0.1). These pulses are created by driving  
P0.1 LOW and then HIGH. This pulse is repeated  
until a total of 25 programming pulses have  
occurred. At the conclusion of the last pulse, the  
PROG signal should remain HIGH.  
Table 32 Programming and Verification codes  
ADDRESS CONTENT  
INDICATION  
30H  
31H  
15H  
4BH  
manufactured by Philips  
87C055  
4. The VPP signal may now be driven to the VOH level,  
placing the 87C055 in the Verify Mode; Port 3 is now  
used as an output port. After four machine cycles  
(48 clock periods), the contents of the addressed  
location in the EPROM array will appear on Port 3.  
Table 33 Implementing Program/Verify Modes  
SERIAL  
CODE (PROG)  
P0.1  
P0.0  
OPERATION  
(VPP  
VPP  
VIH  
)
(1)  
5. The next programming cycle may now be initiated by:  
Program user EPROM  
Verify user EPROM  
Read Signature Bytes  
286H  
286H  
280H  
−
a) Placing the address information at the inputs of the  
multiplexed buffers.  
VIH  
VIH  
VIH  
b) Driving the VPP pin to the VPP voltage level.  
Note  
1. Pulsed from VIH to VIL and returned to VIH.  
c) Providing the byte to be programmed to Port 3 and  
issuing the 26 programming pulses on the PROG  
pin.  
d) Bringing VPP back down to the VOH level and  
verifying the byte (see Table 33).  
1996 Mar 22  
27  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
8
V
A0-A15  
ADDRESS STROBE  
P2.0-2.7  
P0.2/ASEL  
P0.1  
5V  
DD  
V
SS  
PROGRAMMING  
PULSES  
87C055  
V
/V VOLTAGE  
PP IH  
P0.0  
8
SOURCE  
P3.0-P3.7  
DATA BUS  
CLK SOURCE  
XTAL1  
RESET  
CONTROL  
LOGIC  
RESET  
MBE767  
Fig.9 Programming Configuration.  
XTAL1  
min 2 machine  
cycles  
10-bit serial code  
RESET  
P0.0  
BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9  
undefined  
P0.1  
undefined  
MBE768  
Fig.10 Entry into Program/Verify Modes.  
28  
1996 Mar 22  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
14.5 EPROM Programming and Verification  
V
DD = 5 V ±10%; VSS = 0 V; Tamb = 21 to 27 °C.  
SYMBOL PARAMETER  
1/tCLCL  
MIN.  
1.2  
MAX.  
UNIT  
MHz  
µs  
Oscillator/clock frequency  
6
(1)  
tAVGL  
Address setup to P0.1 (PROG) LOW  
Address hold after P0.1 (PROG) HIGH  
Data setup to P0.1 (PROG) LOW  
Data hold after P0.1 (PROG) HIGH  
VPP setup to P0.1 (PROG) LOW  
VPP hold after P0.1 (PROG) HIGH  
P0.1 (PROG) width  
10 + 24tCLCL  
48tCLCL  
38tCLCL  
36tCLCL  
10  
−
tGHAX  
tDVGL  
tGHDX  
tSHGL  
tGHSL  
tGLGH  
−
µs  
−
µs  
−
µs  
−
µs  
10  
−
µs  
90  
110  
µs  
(1)  
tAVQV  
VPP (VDD) LOW to data valid  
P0.1 (PROG) HIGH to P0.1 (PROG) LOW  
P0.0 (sync pulse) LOW  
−
48tCLCL  
µs  
tGHGL  
tSYNL  
10  
−
−
−
−
−
−
−
µs  
4tCLCL  
8tCLCL  
13tCLCL  
2tCLCL  
13tCLCL  
13tCLCL  
µs  
tSYNH  
tMASEL  
tHAHLD  
tHASET  
tADSTA  
P0.0 (sync pulse) HIGH  
µs  
ASEL HIGH time  
µs  
Address hold time  
µs  
Address setup to ASEL  
µs  
Low address to address stable  
µs  
Note  
1. Address should be valid at least 24tCLCL before the rising edge of P0.0 (VPP).  
12.75 V  
h
5 V  
5 V  
t
P0.0 [V (p-p)]  
t
SHGL  
GHSL  
25 PULSES  
P0.1 (PROG)  
t
t
GHGL  
GLGH  
t
MASEL  
98µs MIN  
10µs MIN  
P0.2 (ASEL)  
PORT 2  
t
HASET  
t
HAHLD  
LOW ADDRESS  
HIGH ADDRESS  
t
t
DVGL  
GHDX  
t
t
AVQV  
ADSTA  
DATA TO BE  
PROGRAMMED  
PORT 3  
INVALID DATA  
verify mode  
VALID DATA  
INVALID DATA  
VALID DATA  
verify mode  
program mode  
MBE769  
Fig.11 Program/Verify cycle.  
29  
1996 Mar 22  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
Each character is 14 bits wide by 18 lines high.A character  
is split about a vertical axis into two sections UPPER and  
LOWER as illustrated in Table 34:  
15 PROGRAMMING THE OSD EPROM  
15.1 Overview  
The OSD EPROM space starts at location C000H and  
ends at location CFFFH. However, due to the addressing  
scheme of the OSD, not all locations within this space are  
used.The start location of the next character can be  
calculated by adding 40H to the start location of the  
previous character. For example, character 1 starts at  
C000H; then characters 2, 3, and 4 start at C040H,  
C080H, and C0C0H, respectively.  
• Each section contains 7 bits of the character, such that:  
– the LOWER section contains bits 7 to 1, and  
– the UPPER section contains bits 14 to 8.  
• The LOWER section of the character is programmed  
when the LSB of the program address equals a logic 0,  
and the UPPER section when the LSB equals a logic 1.  
During Programming and Verification, each section is  
programmed using bytes of program data. The MSB of the  
program data is not used; however, the MSB location  
physically exists, and so will Program and Verify.  
15.2 Character description and programming  
An example of an OSD character bit map, and the program  
data to obtain that character is shown in Table 34.  
15.3 OSD EPROM bit map  
The mapping for the full OSD EPROM is shown in Table 35. To program the example character into the first character  
location of the OSD EPROM would require the data at the address as shown in Table 34.  
Table 34 Example of an OSD Character Bit Map (note 1)  
CHARACTER BIT MAP  
PROGRAM DATA  
ADDRESS (HEX)  
LINE  
UPPER  
(BIT 14 TO 8)  
LOWER  
(BIT 7 TO 1)  
UPPER  
LOWER  
UPPER  
LOWER  
Line 1  
0000000  
0000000  
0011110  
0011110  
0011110  
0011110  
0011110  
0011110  
0011111  
0011111  
0011111  
0011110  
0011110  
0011110  
0011110  
0011110  
0000000  
0000000  
0000000  
0000000  
0001100  
0001100  
0001100  
0001100  
0001100  
0001100  
1111100  
1111100  
1111100  
0001100  
0001100  
0001100  
0001100  
0001100  
0000000  
0000000  
X0000000  
X0000000  
X0011110  
X0011110  
X0011110  
X0011110  
X0011110  
X0011110  
X0011111  
X0011111  
X0011111  
X0011110  
X0011110  
X0011110  
X0011110  
X0011110  
X0000000  
X0000000  
X0000000  
X0000000  
X0001100  
X0001100  
X0001100  
X0001100  
X0001100  
X0001100  
X1111100  
X1111100  
X1111100  
X0001100  
X0001100  
X0001100  
X0001100  
X0001100  
X0000000  
X0000000  
C001  
C003  
C005  
C007  
C009  
C00B  
C00D  
C00F  
C011  
C013  
C015  
C017  
C019  
C01B  
C01D  
C01F  
C021  
C023  
C000  
C002  
C004  
C006  
C008  
C00A  
C00C  
C00E  
C010  
C012  
C014  
C016  
C018  
C01A  
C01C  
C01E  
C020  
C022  
Line 2  
Line 3  
Line 4  
Line 5  
Line 6  
Line 7  
Line 8  
Line 9  
Line 10  
Line 11  
Line 12  
Line 13  
Line 14  
Line 15  
Line 16  
Line 17  
Line 18  
Note  
1. X can be a logic 0 or logic 1, and will Program and Verify correctly.  
1996 Mar 22  
30  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
Table 35 OSD EPROM Bit Map  
ADDRESS (HEX)  
CHARACTER NO.  
CHARACTER LINE NO.  
LOWER BYTE  
UPPER BYTE  
0
C000  
C002  
C004  
C006  
C008  
C00A  
C00C  
C00E  
C010  
C012  
C014  
C016  
C018  
C01A  
C01C  
C01E  
C020  
C022  
C001  
C003  
C005  
C007  
C009  
C00B  
C00D  
C00F  
C011  
C013  
C015  
C017  
C019  
C01B  
C01D  
C01F  
C021  
C023  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
C024 to C03F  
not used  
1 to 18  
not used  
1 to 18  
not used  
−
1(1)  
2(1)  
C040 to C063  
C064 to C07F  
C080 to C0A3  
C0A4 to C0BF  
−
3 to 59(1)  
60(2)  
CF00 to CF23  
CF24 to CF3F  
CF40 to CF63  
CF64 to CF7F  
CF80 to CFA3  
CFA4 to CFBF  
CFC0 to CFE3  
CFE4 to CFFF  
1 to 18  
not used  
1 to 18  
not used  
1 to 18  
not used  
1 to 18  
not used  
61(2)  
62(2)  
63(2)  
Notes  
1. Characters 1 to 59 are setup in the similar way as character 0; due to space and simplicity this is not fully displayed.  
2. Locations 60, 61, 62 and 63 should be programmed to logic 0s. The character names are: character no. 60 = Normal  
Space; character no. 61 = New Line; character no. 62 = BSpace; character no. 63 = SplitBSpace.  
1996 Mar 22  
31  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
16 REGISTER MAP  
Table 36 Register map  
Values within parenthesis show the bit state after a reset operation; ‘X’ denotes an undefined state.  
ADDR.  
(HEX)  
REGISTER  
7
6
5
4
3
2
1
0
E0  
ACC(1)  
ACC7  
(0)  
ACC6  
(0)  
ACC5  
(0)  
ACC4  
(0)  
ACC3  
(0)  
ACC2  
(0)  
ACC1  
(0)  
ACC0  
(0)  
F0  
83  
82  
A8  
9A  
B(1)  
B7  
(0)  
B6  
(0)  
B5  
(0)  
B4  
(0)  
B3  
(0)  
B2  
(0)  
B1  
(0)  
B0  
(0)  
DPH  
DPL  
IE(1)  
DPH7  
(0)  
DPH6  
(0)  
DPH5  
(0)  
DPH4  
(0)  
DPH3  
(0)  
DPH2  
(0)  
DPH1  
(0)  
DPH0  
(0)  
DPL7  
(0)  
DPL6  
(0)  
DPL5  
(0)  
DPL4  
(0)  
DPL3  
(0)  
DPL2  
(0)  
DPL1  
(0)  
DPL0  
(0)  
EA  
(0)  
−
(X)  
−
(0)  
EVS  
(0)  
ET1  
(0)  
EX1  
(0)  
ET0  
(0)  
EX0  
(0)  
OSAD  
−
(X)  
OSAD6  
(X)  
OSAD5  
(X)  
OSAD4  
(X)  
OSAD3  
(X)  
OSAD2  
(X)  
OSAD1  
(X)  
OSAD0  
(X)  
9F to 98 OSAT(1)(2)  
OSAT(1)(3)  
−
(X)  
−
(X)  
−
(X)  
E
(X)  
−
(X)  
SR  
(X)  
D
(X)  
Sh  
(X)  
−
(X)  
−
(X)  
−
(X)  
B
(X)  
−
(X)  
BC2  
(X)  
BC1  
(X)  
BC0  
(X)  
OSAT(1)(4)  
−
(X)  
−
(X)  
−
(X)  
B
(X)  
−
(X)  
FC2  
(X)  
FC1  
(X)  
FC0  
(X)  
99  
C0  
C1  
C2  
80  
90  
A0  
B0  
87  
D0  
D4  
OSDT  
OSCON(1)  
OSMOD  
OSORG  
P0(1)  
−
(X)  
−
(X)  
OSDT5  
(X)  
OSDT4  
(X)  
OSDT3  
(X)  
OSDT2  
(X)  
OSDT1  
(X)  
OSDT0  
(X)  
IV  
(X)  
Pv  
(X)  
Lv  
(X)  
Ph  
(X)  
Pc  
(X)  
Po  
(X)  
DH  
(X)  
BFe  
(X)  
Wc  
(X)  
−
(X)  
Mode1  
(X)  
Mode0  
(X)  
−
(X)  
SHM2  
(X)  
SHM1  
(X)  
SHM0  
(X)  
HS4  
(X)  
HS3  
(X)  
HS2  
(X)  
HS1  
(X)  
HS0  
(X)  
VS2  
(X)  
VS1  
(X)  
VS0  
(X)  
P07  
(1)  
P06  
(1)  
P05  
(1)  
P04  
(1)  
P03  
(1)  
P02  
(1)  
P01  
(1)  
P00  
(1)  
P1(1)  
P17  
(1)  
P16  
(1)  
P15  
(1)  
P14  
(1)  
P13  
(1)  
P12  
(1)  
P11  
(1)  
P10  
(1)  
P2(1)  
P27  
(1)  
P26  
(1)  
P25  
(1)  
P24  
(1)  
P23  
(1)  
P22  
(1)  
P21  
(1)  
P20  
(1)  
P3(1)  
P37  
(1)  
P36  
(1)  
P35  
(1)  
P34  
(1)  
P33  
(1)  
P32  
(1)  
P31  
(1)  
P30  
(1)  
PCON  
PSW(1)  
PWM0  
−
(0)  
−
(X)  
−
(X)  
−
(X)  
GF1  
(X)  
GF0  
(X)  
−
(X)  
−
(X)  
CY  
(0)  
AC  
(0)  
F0  
(0)  
RS1  
(0)  
RS0  
(0)  
OV  
(0)  
−
(0)  
P
(0)  
PW0E  
(0)  
−
(0)  
PV05  
(0)  
PV04  
(0)  
PV03  
(0)  
PV02  
(0)  
PV01  
(0)  
PV00  
(0)  
1996 Mar 22  
32  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
ADDR.  
(HEX)  
REGISTER  
7
6
5
4
3
2
1
0
D5  
PWM1  
PW1E  
(0)  
−
(0)  
PV15  
(0)  
PV14  
(0)  
PV13  
(0)  
PV12  
(0)  
PV11  
(0)  
PV10  
(0)  
D6  
D7  
DC  
DD  
DE  
DF  
D8  
81  
PWM2  
PWM3  
PWM4  
PWM5  
PWM6  
PWM7  
SAD(1)  
SP  
PW2E  
(0)  
−
(0)  
PV25  
(0)  
PV24  
(0)  
PV23  
(0)  
PV22  
(0)  
PV21  
(0)  
PV20  
(0)  
PW3E  
(0)  
−
(0)  
PV35  
(0)  
PV34  
(0)  
PV33  
(0)  
PV32  
(0)  
PV31  
(0)  
PV30  
(0)  
PW4E  
(0)  
−
(0)  
PV45  
(0)  
PV44  
(0)  
PV43  
(0)  
PV42  
(0)  
PV41  
(0)  
PV40  
(0)  
PW5E  
(0)  
−
(0)  
PV55  
(0)  
PV54  
(0)  
PV53  
(0)  
PV52  
(0)  
PV51  
(0)  
PV50  
(0)  
PW6E  
(0)  
−
(0)  
PV65  
(0)  
PV64  
(0)  
PV63  
(0)  
PV62  
(0)  
PV61  
(0)  
PV60  
(0)  
PW7E  
(0)  
−
(0)  
PV75  
(0)  
PV74  
(0)  
PV73  
(0)  
PV72  
(0)  
PV71  
(0)  
PV70  
(0)  
VHi  
(0)  
CH1  
(0)  
CH0  
(0)  
St  
(0)  
SAD3  
(0)  
SAD2  
(0)  
SAD1  
(0)  
SAD0  
(0)  
SP7  
(0)  
SP6  
(0)  
SP5  
(0)  
SP4  
(0)  
SP3  
(0)  
SP2  
(0)  
SP1  
(0)  
SP0  
(0)  
D3  
D2  
8F  
8C  
8D  
8A  
8B  
89  
TDACH  
TDACL  
TCON(1)  
TH0  
TDE  
(0)  
−
(0)  
TD13  
(0)  
TD12  
(0)  
TD11  
(0)  
TD10  
(0)  
TD9  
(0)  
TD8  
(0)  
TD7  
(0)  
TD0  
(0)  
TD1  
(0)  
TD2  
(0)  
TD3  
(0)  
TD4  
(0)  
TD5  
(0)  
TD6  
(0)  
TF1  
(0)  
TR1  
(0)  
TF0  
(0)  
TR0  
(0)  
IE1  
(0)  
IT1  
(0)  
IE0  
(0)  
IT0  
(0)  
TH07  
(0)  
TH06  
(0)  
TH05  
(0)  
TH04  
(0)  
TH03  
(0)  
TH02  
(0)  
TH01  
(0)  
TH00  
(0)  
TH1  
TH17  
(0)  
TH16  
(0)  
TH15  
(0)  
TH14  
(0)  
TH13  
(0)  
TH12  
(0)  
TH11  
(0)  
TH10  
(0)  
TL0  
TL07  
(0)  
TL06  
(0)  
TL05  
(0)  
TL04  
(0)  
TL03  
(0)  
TL02  
(0)  
TL01  
(0)  
TL00  
(0)  
TL1  
TL17  
(0)  
TL16  
(0)  
TL15  
(0)  
TL14  
(0)  
TL13  
(0)  
TL12  
(0)  
TL11  
(0)  
TL10  
(0)  
TMOD  
GATE  
(0)  
C/T  
(0)  
M1  
(0)  
M0  
(0)  
GATE  
(0)  
C/T  
(0)  
M1  
(0)  
M0  
(0)  
C3  
C4  
RAMCHR  
RAMATT  
for test purposes only  
for test purposes only  
Notes  
1. Bit addressable.  
2. With OSDT = New Line.  
3. With OSDT = BSpace or SplitBSpace.  
4. With OSDT = Any other character.  
1996 Mar 22  
33  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
17 LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 34); see notes 1 and 2.  
SYMBOL  
VDD  
PARAMETER  
MIN.  
4.5  
MAX.  
UNIT  
supply voltage  
5.5  
6.5  
V
V
VI  
input voltage on any pin with respect to ground (VSS  
maximum source current for all port lines  
maximum sink current for all port lines  
total power dissipation  
)
−0.5  
−
IOH  
IOL  
−1.5  
15  
mA  
mA  
W
−
Ptot  
Tamb  
Tstg  
−
1.5  
70  
operating ambient temperature  
0
°C  
storage temperature  
−65  
150  
°C  
Notes  
1. Stresses above those listed under Limiting Values may cause permanent damage to the device.  
2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to  
SS unless otherwise noted.  
V
18 HANDLING  
Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take  
normal precautions appropriate to handling MOS devices (see “Handling MOS devices”).  
1996 Mar 22  
34  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
19 DC CHARACTERISTICS  
VDD = 5 V ±10% Tamb = 0 to +70 °C; all voltages with respect to VSS; unless otherwise specified.  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Supply  
VDD  
IDD  
operating supply voltage  
operating supply current  
LOW level input voltage  
4.5  
5.0 5.5  
V
VDD = 5.5 V; note 1  
−
−
−
−
30  
mA  
VIL  
−0.5  
−0.5  
0.2VDD − 0.1 V  
VIL1  
LOW level input voltage;  
VSYNC and HSYNC  
0.15VDD  
VDD + 0.5  
VDD + 0.5  
12.6  
V
V
V
V
V
V
VIH  
HIGH level input voltage;  
XTAL, VCLK1 and RST  
0.7VDD  
−
−
−
−
−
VIH1  
VIH2  
VIH3  
HIGH level input voltage; P1.2 to P1.0,  
P3.6 to P3.5 and P3.3 to P3.1  
0.2VDD + 0.9  
0.2VDD + 0.9  
0.67VDD  
HIGH level input voltage;  
P1.3, P3.7,P3.4 and P3.0  
HIGH level input voltage; VSYNC and  
HSYNC  
VDD + 0.5  
VDD + 0.5  
V
IH − VDD HIGH level input voltage with respect  
to VDD; Port 0, P1.3, P3.7, P3.4 and  
P3.0  
note 2  
0.7VDD  
VOL1  
VOL2  
VOL3  
VOH  
LOW level output voltage; P2.7 to P2.0 IOL = 10 mA; note 3  
and P3.6 to P3.5  
−
−
−
−
−
0.5  
0.5  
0.45  
−
V
V
V
V
LOW level output voltage;  
TDAC and PWM0 to PWM7  
IOL = 700 µA; note 4  
−
LOW level output voltage; all other  
outputs  
IOL = 1.6 mA  
−
HIGH level output voltage;  
IOH = −60 µA  
2.4  
Port 1, VID2 to VID0, VCTRL and BF  
RRST  
CIO  
Reset (RST) pull-down resistor  
50  
−
−
300  
10  
kΩ  
Pin capacitance; except P0.0 and P0.7 test freq. = 1 MHz;  
−
pF  
Tamb = 25 °C; note 5  
HYS  
Hysteresis; VSYNC and HSYNC  
0.8  
−
−
V
Notes  
1. IDD measured with OSD block initialized and RST remaining LOW.  
2. This maximum applies at all times, including during power switching, and must be accounted for in power supply  
design. During a Power-on process, the +12 V source used for external pull-up resistors should not precede the VDD  
of the 83C055 up their respective voltage ramps by more than this margin, nor, during a Power-down process, should  
VDD precede +12 V down their respective voltage ramps by more than this margin.  
3. No more than 6 (any 6) of these 10 high current outputs may be used at the VOL1 (IOL = 10 mA) specification.  
The other 4 should comply with the VOL3 specification (IOL = 1.6 mA).  
4. The specified current rating applies when any of these pins is used as a Pulse Width Modulated (PWM) output.  
For use as a port output, the rating is as given subsequently.  
5. The capacitance of pins P0.0 and P0.7 for the 87C055 exceeds 10 pF; for P0.0 this is maximum 40 pF, while for P0.7  
it is maximum 20 pF.  
1996 Mar 22  
35  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
20 AC CHARACTERISTICS  
V
DD = 5 V ±10%; Tamb = 0 to +70 °C; all voltages with respect to VSS; unless otherwise specified.  
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT  
1/tCLCL  
tCHCX  
tCLCX  
XTAL frequency  
note 1  
note 2  
6
−
−
−
−
−
−
−
12  
−
MHz  
ns  
XTAL1 clock HIGH time  
XTAL1 clock LOW time  
XTAL1 clock rise time  
XTAL1 clock fall time  
VCLK frequency  
20  
20  
−
−
ns  
tCLCH  
20  
20  
8
ns  
tCHCL  
5
ns  
1/tVCLCL  
5
MHz  
ns  
tVCOH − tVCOL  
tVCOH1 − tVCOH2  
tVCOL1 − tVCOL2  
Rise versus fall time skew on any one of  
VID2 to VID0, VCTRL and BF  
note 3  
−
40  
Rise time skew between any two of  
VID2 to VID0, VCTRL and BF  
−
−
−
−
30  
30  
ns  
ns  
Fall time skew between any two of  
VID2 to VID0, VCTRL and BF  
Notes  
1. The 83C055 is tested at its maximum XTAL frequency, but not at any other (lower) rate.  
2. These parameters apply only when an external clock signal is used.  
3. These parameters assume equal loading at CL = 100 pF, for all the referenced outputs. These parameters are  
specified but not tested.  
1996 Mar 22  
36  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
21 PACKAGE OUTLINES  
SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)  
SOT270-1  
D
M
E
A
2
A
L
A
1
c
e
(e )  
1
w M  
Z
b
1
M
H
b
42  
22  
pin 1 index  
E
1
21  
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
max.  
A
A
2
max.  
(1)  
(1)  
Z
1
w
UNIT  
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.  
max.  
1.3  
0.8  
0.53  
0.40  
0.32  
0.23  
38.9  
38.4  
14.0  
13.7  
3.2  
2.9  
15.80  
15.24  
17.15  
15.90  
mm  
5.08  
0.51  
4.0  
1.778  
15.24  
0.18  
1.73  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
90-02-13  
95-02-04  
SOT270-1  
1996 Mar 22  
37  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
The device may be mounted to the seating plane, but the  
temperature of the plastic body must not exceed the  
specified storage maximum. If the printed-circuit board has  
been pre-heated, forced cooling may be necessary  
immediately after soldering to keep the temperature within  
the permissible limit.  
22 SOLDERING  
22.1 Introduction  
There is no soldering method that is ideal for all IC  
packages. Wave soldering is often preferred when  
through-hole and surface mounted components are mixed  
on one printed-circuit board. However, wave soldering is  
not always suitable for surface mounted ICs, or for  
printed-circuits with high population densities. In these  
cases reflow soldering is often used.  
22.3 Repairing soldered joints  
Apply a low voltage soldering iron (less than 24 V) to the  
lead(s) of the package, below the seating plane or not  
more than 2 mm above it. If the temperature of the  
soldering iron bit is less than 300 °C it may remain in  
contact for up to 10 seconds. If the bit temperature is  
between 300 and 400 °C, contact may be up to 5 seconds.  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “IC Package Databook” (order code 9398 652 90011).  
22.2 Soldering by dip or wave  
The maximum permissible temperature of the solder is  
260 °C; solder at this temperature must not be in contact  
with the joint for more than 5 seconds. The total contact  
time of successive solder waves must not exceed  
5 seconds.  
23 DEFINITIONS  
Data sheet status  
Objective specification  
Preliminary specification  
Product specification  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
Limiting values  
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or  
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation  
of the device at these or at any other conditions above those given in the Characteristics sections of the specification  
is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
24 LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
1996 Mar 22  
38  
Philips Semiconductors  
Product specification  
83C145; 83C845  
83C055; 87C055  
Microcontrollers for TV and video (MTV)  
NOTES  
1996 Mar 22  
39  
Philips Semiconductors – a worldwide company  
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Tel. (03) 645 04 44, Fax. (03) 648 10 07  
Vietnam: see Singapore  
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,  
Tel. (381) 11 825 344, Fax. (359) 211 635 777  
Italy: PHILIPS SEMICONDUCTORS,  
Piazza IV Novembre 3, 20124 MILANO,  
Tel. (0039) 2 6752 2531, Fax. (0039) 2 6752 2557  
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,  
TOKYO 108, Tel. (03) 3740 5130, Fax. (03) 3740 5077  
Korea: Philips House, 260-199 Itaewon-dong,  
Yongsan-ku, SEOUL, Tel. (02) 709-1412, Fax. (02) 709-1415  
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,  
SELANGOR, Tel. (03) 750 5214, Fax. (03) 757 4880  
Mexico: 5900 Gateway East, Suite 200, EL PASO,  
TEXAS 79905, Tel. 9-5(800) 234-7831, Fax. (708) 296-8556  
Middle East: see Italy  
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,  
Tel. (040) 2783749, Fax. (040) 2788399  
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,  
Tel. (09) 849-4160, Fax. (09) 849-7811  
Internet: http://www.semiconductors.philips.com/ps/  
For all other countries apply to: Philips Semiconductors,  
Marketing & Sales Communications, Building BE-p,  
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,  
Fax. +31-40-2724825  
SCDS48  
© Philips Electronics N.V. 1996  
All rights are reserved. Reproduction in whole or in part is prohibited without the  
prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation  
or contract, is believed to be accurate and reliable and may be changed without  
notice. No liability will be accepted by the publisher for any consequence of its  
use. Publication thereof does not convey nor imply any license under patent- or  
other industrial or intellectual property rights.  
Norway: Box 1, Manglerud 0612, OSLO,  
Tel. (022) 74 8000, Fax. (022) 74 8341  
Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc.,  
106 Valero St. Salcedo Village, P.O. Box 2108 MCC,  
MAKATI, Metro MANILA,  
Printed in The Netherlands  
Tel. (63) 2 816 6380, Fax. (63) 2 817 3474  
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,  
Tel. (022) 612 2831, Fax. (022) 612 2327  
457041/1100/01/pp40  
Date of release: 1996 Mar 22  
9397 750 00752  
Document order number:  

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