P87C51MB2BA/02 [NXP]

IC 8-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQCC44, PLASTIC, MS-018, SOT-187-2, LCC-44, Microcontroller;


型号：	P87C51MB2BA/02
厂家：	NXP
描述：	IC 8-BIT, OTPROM, 24 MHz, MICROCONTROLLER, PQCC44, PLASTIC, MS-018, SOT-187-2, LCC-44, Microcontroller 可编程只读存储器时钟 PC 微控制器外围集成电路
文件：	总36页 (文件大小：964K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

P87C51MB2/P87C51MC2

80C51 8-bit microcontroller family with extended memory;

64 kB/96 kB OTP with 2 kB/3 kB RAM

Rev. 03 — 13 November 2003

Product data

1. General description

The P87C51Mx2 represents the ﬁrst microcontroller based on Philips

Semiconductors’ new 51MX core. The P87C51MC2 features 96 kbytes of OTP

program memory and 3 kbytes of data SRAM, while the P87C51MB2 has 64 kbytes

of OTP and 2 kbytes of RAM. In addition, both devices are equipped with a

Programmable Counter Array (PCA), a watchdog timer that can be conﬁgured to

different time ranges through SFR bits, as well as two enhanced UARTs and Serial

Peripheral Interface (SPI).

Philips Semiconductors’ 51MX (Memory eXtension) core is an accelerated 80C51

architecture that executes instructions at twice the rate of standard 80C51 devices.

The linear address range of the 51MX has been expanded to support up to 8 Mbytes

of program memory and 8 Mbytes of data memory. It retains full program code

compatibility to enable design engineers to re-use 80C51 development tools,

eliminating the need to move to a new, unfamiliar architecture. The 51MX core also

retains 80C51 bus compatibility to allow for the continued use of 80C51-interfaced

peripherals and Application Speciﬁc Integrated Circuits (ASICs).

The P87C51Mx2 provides greater functionality, increased performance and overall

lower system cost. By offering an embedded memory solution combined with the

enhancements to manage the memory extension, the P87C51Mx2 eliminates the

need for software work-around. The increased program memory enables design

engineers to develop more complex programs in a high-level language like C, for

example, without struggling to contain the program within the traditional 64 kbytes of

program memory. These enhancements also greatly improve C Language efﬁciency

for code size below 64 kbytes.

The 51MX core is described in more detail in the 51MX Architecture Reference.

2. Features

2.1 Key features

■ Extended features of the 51MX Core:

◆ 23-bit program memory space and 23-bit data memory space

◆ Linear program and data address range expanded to support up to 8 Mbytes

each

◆ Program counter expanded to 23 bits

◆ Stack pointer extended to 16 bits enabling stack space beyond the 80C51

limitation

P87C51MB2/P87C51MC2

Philips Semiconductors

80C51 8-bit microcontroller family

◆ New 23-bit extended data pointer and two 24-bit universal pointers greatly

improve C compiler code efﬁciency in using pointers to access variables in

different spaces

■ 100% binary compatibility with the classic 80C51 so that existing code is

completely reusable

■ Up to 24 MHz CPU clock with 6 clock cycles per machine cycle

■ 96 kbytes (MC2) or 64 kbytes (MB2) of on-chip OTP

■ 3 kbytes (MC2) or 2 kbytes (MB2) of on-chip RAM

■ Programmable Counter Array (PCA)

■ Two full-duplex enhanced UARTs and Serial Peripheral Interface (SPI)

communication modules

2.2 Key beneﬁts

■ Increases program/data address range to 8 Mbytes each

■ Enhances performance and efﬁciency for C programs

■ Fully 80C51-compatible microcontroller

■ Provides seamless and compelling upgrade path from classic 80C51

■ Preserves 80C51 code base, investment/knowledge, and peripherals & ASICs

■ Supported by wide range of 80C51 development systems and programming tools

vendors

■ The P87C51Mx2 makes it possible to develop applications at lower cost and with

a reduced time-to-market

2.3 Complete features

■ Fully static

■ Up to 24 MHz CPU clock with 6 clock cycles per machine cycle

■ 96 kbytes or 64 kbytes of on-chip OTP

■ 3 kbytes or 2 kbytes of on-chip RAM

■ 23-bit program memory space and 23-bit data memory space

■ Four-level interrupt priority

■ 34 I/O lines (5 ports)

■ Three Timers: Timer0, Timer1 and Timer2

■ Two full-duplex enhanced UARTs with baud rate generator

■ Framing error detection

■ Automatic address recognition

■ Supports industry-standard Serial Peripheral Interface (SPI) with a baud rate up to

6 Mbits/s

■ Power control modes

■ Clock can be stopped and resumed

■ Idle mode

■ Power down mode with advanced clock control

■ Second DPTR register

■ Asynchronous port reset

■ Programmable Counter Array (PCA) (compatible with 8xC51Rx+) with ﬁve

Capture/Compare modules

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80C51 8-bit microcontroller family

■ Low EMI (inhibit ALE)

■ Watchdog timer with programmable prescaler for different time ranges

(compatible with 8xC66x with added prescaler)

3. Differences between P87C51MX2/02 part and previous revisions of

P87C51MX2

The P87C51MX2/02 offers several advantages over the previous generation of

P87C51MX2 parts. Right now, SPI module is available, two more general purpose

digital pins on P4 are present and additional power control features are implemented

(advanced peripheral clock control). New memory interface mode and code size

optimization options are available with the use of MXCON register.

No changes are necessary when porting and loading code written for existing

P87C51MX2 to the new P87C51MX2/02.

4. Ordering information

Table 1:

Ordering information

Type number

Memory

Temp

V_DDvoltage Frequency

Package

Range range

(°C)

OTP RAM

V_DD= 2.7 V_DD= 4.5 Name

Description Version

to 5.5 V

P87C51MB2BA/02 64 kB 2048 B 0 to +70 2.7 to 5.5 V 0 to

12 MHz

0 to

24 MHz

PLCC44 plastic leaded SOT187-2

chip carrier;

44 leads

P87C51MC2BA/02 96 kB 3072 B 0 to +70 2.7 to 5.5 V 0 to

12 MHz

0 to

24 MHz

PLCC44 plastic leaded SOT187-2

chip carrier;

44 leads

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Philips Semiconductors

80C51 8-bit microcontroller family

5. Block diagram

HIGH PERFORMANCE

80C51 CPU

(51 MX CORE)

96kB/64kB

CODE EPROM

UART 0

internal bus

BAUD RATE

3kB/2kB

GENERATOR

DATA RAM

UART 1

PORT 4

PORT 3

SPI

TIMER 0

TIMER 1

PORT 2

PORT 1

TIMER 2

PCA (PROGRAMMABLE

COUNTER ARRAY)

PORT 0

CONFIGURABLE I/Os

CRYSTAL OR

RESONATOR

OSCILLATOR

WATCHDOG TIMER

002aaa148

Fig 1. Block diagram.

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Philips Semiconductors

80C51 8-bit microcontroller family

6. Functional diagram

T2EX

ECI

CEX0

CEX1

CEX2

CEX3

CEX4

Address bus 0-7

Data Bus

MOSI

SPICLK

RXD0

TXD0

INT0

INT1

Address Bus 16-22

P87C51Mx2

MISO

RXD1

TXD1

RST

XTAL2

XTAL1

EA/V

PSEN

ALE/PROG

002aaa147

Fig 2. Functional diagram.

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80C51 8-bit microcontroller family

7. Pinning information

7.1 Pinning

P1.5/CEX2/SPICLK

P1.6/CEX3

39 P0.4/AD4

38 P0.5/AD5

37 P0.6/AD6

36 P0.7/AD7

P1.7/CEX4

RST 10

P3.0/RXD0 11

P4.0/RXD1/MIS0 12

P3.1/TXD0 13

P3.2/INT0 14

35 EA/V

P87C51MB2/

P87C51MC2

34 P4.1/TXD1/SS

33 ALE

32 PSEN

P3.3/INT1 15

31 P2.7/A15

30 P2.6/A14/A22

29 P2.5/A13/A21

P3.4/T0 16

P3.5/T1 17

002aaa165

Fig 3. Pinning.

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80C51 8-bit microcontroller family

7.2 Pin description

Table 2:

Pin description

Symbol

Type

Description

P0.0 - P0.7

43 - 36

I/O

Port 0: Port 0 is an open drain, bidirectional I/O port. Port 0 pins that have 1s

written to them ﬂoat and can be used as high-impedance inputs. Port 0 is also

the multiplexed low-order address and data bus during accesses to external

program and data memory. In this application, it uses strong internal pull-ups

when emitting 1s.

P1.0 - P1.7

2 - 9

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups on all pins.

Port 1 pins that have 1s written to them are pulled HIGH by the internal pull-ups

and can be used as inputs. As inputs, port 1 pins that are externally pulled LOW

will source current because of the internal pull-ups.

I/O

• P1.0, T2

– Timer/Counter 2 external count input/Clock out

• P1.1, T2EX

– Timer/Counter 2 Reload/Capture/Direction Control

• P1.2, ECI

– External Clock Input to the PCA

I/O

• P1.3, CEX0

– Capture/Compare External I/O for PCA module 0

• P1.4, CEX1

– Capture/Compare External I/O for PCA module 1 (with pull-up on pin)

• MOSI

– SPI Master Out/Slave In (Selected when SPEN (SPCTL.6) is ‘1’, in which

case the pull-up for this pin is disabled)

I/O

• P1.5, CEX2

– Capture/Compare External I/O for PCA module 2 (with pull-up on pin)

• SPICLK

– SPI Clock (Selected when SPEN (SPCTL.6) is ‘1’, in which case the

pull-up for this pin is disabled)

I/O

• P1.6, CEX3

– Capture/Compare External I/O for PCA module 3

• P1.7, CEX4

– Capture/Compare External I/O for PCA module

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Philips Semiconductors

80C51 8-bit microcontroller family

Table 2:

Pin description…continued

Symbol

Type

Description

P2.0 - P2.7

24 - 31

I/O

Port 2: Port 2 is a 8-bit bidirectional I/O port with internal pull-ups on all pins.

Port 2 pins that have 1s written to them are pulled HIGH by the internal pull-ups

and can be used as inputs. As inputs, port 2 pins that are externally being pulled

LOW will source current because of the internal pull-ups. (See Section 10

“Static characteristics”, I_IL). Port 2 emits the high-order address byte during

fetches from external program memory and during accesses to external data

memory that use 16-bit addresses (MOVX @ DPTR) or 23-bit addresses

(MOVX @EPTR, EMOV). In this application, it uses strong internal pull-ups

when emitting 1s. During accesses to external data memory that use 8-bit

addresses (MOV @ Ri), port 2 emits the contents of the P2 Special Function

Note that when 23-bit address is used, address bits A16-A22 will be outputted

to P2.0-P2.6 when ALE is HIGH, and address bits A8-A14 are outputted to

P2.0-P2.6 when ALE is LOW. Address bit A15 is outputted on P2.7 regardless

of ALE.

P3.0 - P3.7

11,13 -19 I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins

that have 1s written to them are pulled HIGH by the internal pull-ups and can be

used as inputs. As inputs, port 3 pins that are externally pulled LOW will source

current because of the internal pull-ups.

• P3.0, RXD0

– Serial input port 0

• P3.1, TXD0

– Serial output port 0

• P3.2, INT0

– External interrupt 0

• P3.3, INT1

– External interrupt 1

• P3.4, T0

– Timer0 external input

• P3.5, T1

– Timer1 external input

• P3.6, WR

I/O

– External data memory write strobe

• P3.7, RD

– External data memory read strobe

P4.0 - P4.1

12,34

Port 4: Port 4 is an 2-bit bidirectional I/O port with internal pull-ups on all pins.

Port 4 pins that have 1s written to them are pulled HIGH by the internal pull-ups

and can be used as inputs. As inputs, port 4 pins that are externally pulled LOW

will source current because of the internal pull-ups. As inputs, port 4 pins that

are externally pulled LOW will source current because of the internal pull-ups.

(Note: When SPEN, i.e.,SPCTL.6, is ’1’, the pull-ups at these port pins are

disabled.)

• P4.0, RXD1

– Serial input port 1 (with pull-up on pin)

I/O

• MISO

– SPI Master In/Slave Out (Selected when SFR bit SPEN (SPCTL.6) is ‘1’,

in which case the pull-up for this pin is disabled)

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Philips Semiconductors

80C51 8-bit microcontroller family

Table 2:

Symbol

Pin description…continued

Type

Description

• P4.1, TXD1

– Serial output port 1 (with pull-up on pin)

I/O

• SS

– SPI Slave Select (Selected when SPEN (SPCTL.6) is ‘1’, in which case

the pull-up for this pin is disabled)

RST

ALE

Reset: A HIGH on this pin for two machine cycles, while the oscillator is

running, resets the device. An internal diffused resistor to V_SSpermits a

power-on reset using only an external capacitor to V_DD

Address Latch Enable: Output pulse for latching the LOW byte of the address

during an access to external memory. In normal operation, ALE is emitted at a

constant rate of ¹⁄₆the oscillator frequency, and can be used for external timing

or clocking. Note that one ALE pulse is skipped during each access to external

data memory. ALE can be disabled by setting SFR AUXR.0. With this bit is set,

ALE will be active only during a MOVX/EMOV/MOVC instruction.

PSEN

EA/V_PP

XTAL1

Program Store Enable: The read strobe to external program memory. When

executing code from the external program memory, PSEN is activated twice

each machine cycle, except that two PSEN activations are skipped during each

access to external data memory. PSEN is not activated during fetches from

internal program memory.

External Access Enable/Programming Supply Voltage: EA must be

externally held LOW to enable the device to fetch code from external program

memory locations. If EA is held HIGH, the device executes from internal

program memory. The value on the EA pin is latched when RST is released and

any subsequent changes have no effect.

Crystal 1: Input to the inverting oscillator ampliﬁer and input to the internal clock

generator circuits.

XTAL2

V_SS

Crystal 2: Output from the inverting oscillator ampliﬁer.

Ground: 0 V reference.

V_DD

Power Supply: This is the power supply voltage for normal operation as well as

Idle and Power Down modes.

(NC/V_SS

)

No Connect/Ground: This pin is internally connected to V_SSon the

P87C51MB2/MC2. If connected externally, this pin must only be connected to

the same V_SSas at pin 22. (Note: Connecting the second pair of V_SSand V_DD

pins is not required. However, they may be connected in addition to the primary

V_SSand V_DDpins to improve power distribution, reduce noise in output signals,

and improve system-level EMI characteristics.)

(NC/V_DD

)

No Connect/Power Supply: This pin is internally connected to V_DDon the

P87C51MB2/MC2. If connected externally, this pin must only be connected to

the same V_DDas at pin 44. (Note: Connecting the second pair of V_SSand V_DD

pins is not required. However, they may be connected in addition to the primary

V_SSand V_DDpins to improve power distribution, reduce noise in output signals,

and improve system-level EMI characteristics.)

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P87C51MB2/P87C51MC2

Philips Semiconductors

80C51 8-bit microcontroller family

8. Functional description

8.1 Memory arrangement

P87C51MB2 has 64 kbytes of OTP (MX universal map range: 80:0000-80:FFFF),

while P87C51MC2 has 96 kbytes of OTP (MX universal map range:

80:0000-81:7FFF).

The P87C51MB2 and P87C51MC2 have 2 kbytes and 3 kbytes of on-chip RAM

respectively:

Table 3:

Memory arrangement

Data memory

Size (bytes) and MX universal memory

map range

Type

Description

P87C51MB2

P87C51MC2

128

DATA

memory that can be addressed both 128

directly and indirectly; can be used as (7F:0000-7F:007F)

stack

(7F:0000-7F:001F)

IDATA

superset of DATA; memory that can

be addressed indirectly (where direct

address for upper half is for SFR

only); can be used as stack

256

(7F:0000-7F:00FF)

EDATA superset of DATA/IDATA; memory that 512

can be addressed indirectly using

512

(7F:0000-7F:01FF)

Universal Pointers (PR0,1); can be

used as stack

XDATA memory (on-chip ‘External Data’) that 1536

is accessed via the MOVX/EMOV

2560

(00:0000-00:05FF)

(00:0000-00:09FF)

instructions using DPTR/EPTR

For more detailed information, please refer to the P87C51Mx2 User Manual or the

51MX Architecture Speciﬁcation.

8.2 Special Function Registers

Special Function Register (SFR) accesses are restricted in the following ways:

• User must not attempt to access any SFR locations not deﬁned.

• Accesses to any deﬁned SFR locations must be strictly for the functions for the

SFRs.

• SFR bits labeled ‘-’, ‘0’, or ‘1’ can only be written and read as follows:

– ‘-’ MUST be written with ‘0’, but can return any value when read (even if it was

written with ‘0’). It is a reserved bit and may be used in future derivatives.

– ‘0’ MUST be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ MUST be written with ‘1’, and will return a ‘1’ when read.

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Table 4:

Name

Special Function Registers

Description

SFR

Addr.

Bit functions and addresses

MSB

Reset

value

LSB

Bit address E7

ACC^[1]

Accumulator

E0H

00H

AUXR^[2]

AUXR1^[2]

Auxiliary Function Register

Auxiliary Function Register 1

8EH

A2H

EXTRAM AO

00H^[6]

LPEP

GF2

DPS

Bit address F7

B^[1]

B Register

F0H

00H

BRGCON^[2]Baud Rate Generator Control

85H^[3]

S0BRGS BRGEN

00H^[6]

BRGR0^[2][5]Baud Rate Generator Rate LOW 86H^[3]

00H

BRGR1^[2][5]Baud Rate Generator Rate

HIGH

87H^[3]

00H

CCAP0H^[2]Module 0 Capture HIGH

CCAP1H^[2]Module 1 Capture HIGH

CCAP2H^[2]Module 2 Capture HIGH

CCAP3H^[2]Module 3 Capture HIGH

CCAP4H^[2]Module 4 Capture HIGH

FAH

FBH

FCH

FDH

FEH

EAH

EBH

ECH

EDH

EEH

DAH

DBH

DCH

DDH

DEH

XXH

CCAP0L^[2]

CCAP1L^[2]

CCAP2L^[2]

CCAP3L^[2]

CCAP4L^[2]

Module 0 Capture LOW

Module 1 Capture LOW

Module 2 Capture LOW

Module 3 Capture LOW

Module 4 Capture LOW

CCAPM0^[2]Module 0 Mode

CCAPM1^[2]Module 1 Mode

CCAPM2^[2]Module 2 Mode

CCAPM3^[2]Module 3 Mode

CCAPM4^[2]Module 4 Mode

ECOM_0 CAPP_0 CAPN_0 MAT_0

ECOM_1 CAPP_1 CAPN_1 MAT_1

ECOM_2 CAPP_2 CAPN_2 MAT_2

ECOM_3 CAPP_3 CAPN_3 MAT_3

ECOM_4 CAPP_4 CAPN_4 MAT_4

TOG_0

TOG_1

TOG_2

TOG_3

TOG_4

PWM_0

PWM_1

PWM_2

PWM_3

PWM_4

ECCF_0 00H^[6]

ECCF_1 00H^[6]

ECCF_2 00H^[6]

ECCF_3 00H^[6]

ECCF_4 00H^[6]

Bit address DF

CCON^{[1] [2]}

CH^[2]

CL^[2]

PCA Counter Control

D8H

F9H

E9H

D9H

CCF4

CCF3

CCF2

CCF1

CCF0

00H^[6]

PCA Counter HIGH

PCA Counter LOW

PCA Counter Mode

00H

00H^[6]

CMOD^[2]

CIDL

WDTE

CPS1

CPS0

ECF

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Table 4:

Name

Special Function Registers…continued

Description

SFR

Bit functions and addresses

MSB

Reset

value

Addr.

LSB

DPTR

DPH

Data Pointer (2 bytes)

00H

Data Pointer HIGH

83H

82H

DPL

Data Pointer LOW

EPTR

EPL^[2]

EPM^[2]

EPH^[2]

Extended Data Pointer (3 bytes)

Extended Data Pointer LOW

Extended Data Pointer Middle

Extended Data Pointer HIGH

FCH^[3]

FDH^[3]

FEH^[3]

00H

Bit address AF

A8H EA

IEN0^[1]

IEN1^[1]

Interrupt Enable 0

Interrupt Enable 1

Interrupt Priority

ET2

ES0/

ES0R

ET1

EX1

ET0

EX0

00H

Bit address EF

E8H

ESPI

ES1T

ES0T

ES1/

ES1R

00H^[6]

Bit address BF

IP0^[1]

IP0H

B8H

PPC

PT2

PS0/

PS0R

PS0H/

PS0RH

PT1

PX1

PT0

PX0

00H

Interrupt

Priority 0 HIGH

B7H

PPCH

PT2H

PT1H

PX1H

PT0H

PX0H

Bit address FF

IP1^[1]

Interrupt Priority 1

Interrupt Priority 1 HIGH

MX Control Register

Port 0

F8H

PSPI

PS1T

PS0T

PS1/

PS1R

PS1H/

PS1RH

EIFM

00H^[6]

FFH

IP1H

F7H

PSPIH

PS1TH

PS0TH

MXCON^[2]

P0^[1]

FFH^[3]

ECRM

EAM1

EAM0

ESMM

Bit address 87

80H

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

P1^[1]

Port 1

90H

CEX4

CEX3

CEX2/

CEX1/

CEX0

ECI

T2EX

FFH

SPICLK MOSI

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Table 4:

Name

Special Function Registers…continued

Description

SFR

Bit functions and addresses

MSB

Reset

value

Addr.

LSB

Bit address A7

P2^[1]

Port 2

A0H

AD15

AD14/

AD22

ADA13/ AD12/

AD11/

AD19

AD10/

AD18

AD9/

AD17

AD8/

AD16

FFH

AD21

AD20

Bit address B7

P3^[1]

Port 3

B0H

C6^[3]

C5^[3]

C4^[3]

INT1

C3^[3]

INT0

C2^[3]

TxD0

C1^[3]

TxD1/

RxD0

C0^[3]

RxD1/

MISO

IDL

FFH

Bit address C7^[3]

P4^{[1] [2]}

PCON^[2]

PCONA^[2]

PSW^[1]

Port 4

C0H^[3]

87H

Power Control Register

Power Control Register A

Program Status Word

SMOD1

SMOD0

POF

GF1

GF0

00H/

10H^[4]

B5H

PCAPD

SPIPD

BRGPD T2PD

S1PD

S0PD

Bit address D7

D0H

CBH

CAH

RS1

RS0

00H

RCAP2H^[2]Timer2 Capture HIGH

RCAP2L^[2]

S0CON^[1]

S0BUF

Timer2 Capture LOW

Bit address 9F

Serial Port 0 Control

98H

SM0_0/

FE_0

SM1_0

SM2_0

REN_0

TB8_0

RB8_0

TI_0

RI_0

00H

xxH

Serial Port 0 Data Buffer

99H

S0ADDR

S0ADEN

S0STAT^[2]

Serial Port 0 Address Register

Serial Port 0 Address Enable

Serial Port 0 Status

A9H

B9H

00H

8CH^[3]DBMOD_0 INTLO_0 CIDIS_0 DBISEL_ FE_0

BR_0

OE_0

STINT_0 00H^[6]

Bit address 87^[3]

86^[3]

85^[3]

84^[3]

83^[3]

82^[3]

81^[3]

80^[3]

S1CON^{[1] [2]}Serial Port 1 Control

80H^[3]

SM0_1/

FE_1

SM1_1

SM2_1

REN_1

TB8_1

RB8_1

TI_1

RI_1

00H

S1BUF^[2]

Serial Port 1 Data buffer

81H^[3]

XXH

S1ADDR^[2]Serial Port 1 Address Register

S1ADEN^[2]

Serial Port 1 Address Enable

82H^[3]

83H^[3]

00H

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Table 4:

Name

Special Function Registers…continued

Description

SFR

Bit functions and addresses

Reset

value

Addr.

MSB

LSB

S1STAT^[2]

SPCTL^[2]

SPCFG^[2]

SPDAT^[2]

Serial Port 1 Status

SPI Control Register

SPI Conﬁguration Register

SPI Data

84H^[3]

E2H

E1H

E3H

81H

DBMOD_1 INTLO_1 CIDIS_1 DBISEL1 FE_1

BR_1

CPHA

OE_1

PSC1

STINT_1 00H^[6]

SSIG

SPIF

SPEN

DORD

MSTR

CPOL

PSC0

00H^[6]

00H

SPWCOL

Stack Pointer (or Stack Pointer

LOW Byte When EDATA

Supported)

07H

SPE^[2]

Stack Pointer HIGH

FBH^[3]

00H

Bit address 8F

IE1

IT1

TCON^[1]

Timer Control Register

88H

TF1

TR1

EXF2

TF0

TR0

IE0

IT0

TF2

T2CON^[1][2]Timer2 Control Register

T2MOD^[2]

C8H

C9H

8CH

8DH

CDH

8AH

8BH

CCH

89H

RCLK

ENT2

TCLK

TF2DE

EXEN2 TR2

C/T2

CP/RL2

DCEN

00H

00H^[6]

00H

FFH

Timer2 Mode Control

Timer 0 HIGH

T2GATE T2PWME T2OE

TH0

TH1

Timer 1 HIGH

TH2

Timer 2 HIGH

TL0

Timer 0 LOW

TL1

Timer 1 LOW

TL2

Timer 2 LOW

TMOD

Timer 0 and 1 Mode

GATE

C/T

GATE

C/T

WDTRST^[2]Watchdog Timer Reset

WDCON^[2]

Watchdog Timer Control

A6H

8FH^[3]

WDPRE2 WDPRE1 WDPRE0 00H^[6]

[1] SFRs are bit addressable.

[2] SFRs are modiﬁed from or added to the 80C51 SFRs.

[3] Extended SFRs accessed by preceding the instruction with MX escape (opcode A5h).

[4] Power on reset is 10H. Other reset is 00H.

[5] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any of them is written if BRGEN = 1, result is unpredictable.

[6] The unimplemented bits (labeled ‘-’) in the SFRs are X’s (unknown) at all times. ‘1’s should not be written to these bits, as they may be used for other purposes in future

derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.

P87C51MB2/P87C51MC2

Philips Semiconductors

80C51 8-bit microcontroller family

8.3 Security bits

The P87C51Mx2 has security bits to protect users’ ﬁrmware codes. With none of the

security bits programmed, the code in the program memory can be veriﬁed. When

only security bit 1 (see Table 5) is programmed, MOVC instructions executed from

external program memory are disabled from fetching code bytes from the internal

memory. EA is latched on Reset and all further programming of EPROM is disabled.

When security bits 1 and 2 are programmed, in addition to the above, verify mode is

disabled. When all three security bits are programmed, all of the conditions above

apply and all external program memory execution is disabled.

Table 5:

EPROM security bits

Security Bits^[1][2]

Bit 1

Bit 2

Bit 3

Protection description

No program security features enabled. EEPROM is

programmable and veriﬁable.

MOVC instructions executed from external program

memory are disabled from fetching code bytes from

internal memory, EA is sampled and latched on Reset,

and further programming of the EPROM is disabled.

Same as 2, also veriﬁcation is disabled.

Same as 3, external execution is disabled.

[1] P - programmed. U - unprogrammed.

[2] Any other combination of security bits is not deﬁned.

9. Limiting values

Table 6:

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

T_amb

T_stg

Parameter

Conditions

Min

Max

Unit

°C

operating temperature

under bias

+70

storage temperature range

input voltage on EA/V_PPpin to V_SS

input voltage on any other pin to V_SS

maximum I_OLper I/O pin

power dissipation

−65

+150

+13

V_I

−0.5

V_DD+ 0.5 V

I_I, I_O

based on package heat

transfer, not device power

consumption

1.5

[1] The following applies to the Limiting values:

a) Stresses above those listed under Limiting values may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in Section 10 “Static characteristics” and

Section 11 “Dynamic characteristics” of this speciﬁcation is not implied.

b) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

c) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

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10. Static characteristics

Table 7:

Static characteristics

T_amb= 0 °C to +70 °C for commercial, unless otherwise speciﬁed; V_DD= 2.7 V to 5.5 V unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ^[1]Max

0.2V_DD−0.1

Unit

V_IL

V_IH

Input low voltage

−0.5

Input high voltage (ports 0, 1,

2, 3, 4, EA)

0.2V_DD+0.9

V_DD+0.5

0.4

V_IH1

V_OL

Input high voltage, XTAL1,

RST

0.7V_DD

Output low voltage, ports 1, V_DD= 4.5 V, I_OL= 1.6 mA

2, 3, 4^[8]

V_DD= 2.7 V, I_OL= 1.6 mA

V_OL1

Output LOW voltage, port 0, V_DD= 4.5 V, I_OL= 3.2 mA

0.4

ALE, PSEN^[7][8]

V_DD= 2.7 V, I_OL= 3.2 mA

V_OH

Output high voltage, ports 1, V_DD= 4.5 V, I_OH= −30 A

_DD− 0.7

2, 3, 4

V_DD= 2.7 V, I_OH= −10 A

V_OH1

Output high voltage (port 0 in V_DD= 4.5 V,

external bus mode), ALE^[9], I_OH= −3.2 mA

PSEN^[3]

V_DD= 2.7 V,

I_OH= −3.2 mA

I_IL

Logical 0 input current, ports V_IN= 0.4 V

1, 2, 3, 4

−1

−75

µA

[4]

[5]

I_TL

Logical 1-to-0 transition

current, ports 1, 2, 3, 4^[8]

4.5 V < V_DD< 5.5 V,

_IN= 2.0 V

−650

I_L1

Input leakage current, port 0 0.45 < V_IN< V_DD−0.3

µA

I_CC

Power supply current

Active mode^[5]

V_DD= 5.5 V

V_DD= 3.6 V

V_DD= 5.5 V

V_DD= 3.6 V

V_DD= 5.0 V

V_DD= 5.5 V

7 + 2.7 /MHz × f_oscmA

4 + 1.3 /MHz × f_osc

Idle mode^[5]

4 + 1.3 /MHz × f_oscmA

1 + 1.0 /MHz × f_osc

Power-down mode or clock

stopped (see Figure 16 for

conditions)

µA

100

R_RST

C₁₀

Internal reset pull-down

resistor

Pin capacitance^[10]

(except EA)

225

kΩ

[1] Typical ratings are not guaranteed. The values listed are at room temperature (+25 ˚C), 5 V, unless otherwise stated.

[2] Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V_OLof ALE and ports 1, 3 and 4. The noise is

due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus

operations. In the worst cases (capacitive loading >100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be

desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I_OLcan exceed these

conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions.

[3] Capacitive loading on ports 0 and 2 may cause the V_OHon ALE and PSEN to momentarily fall below the V_DD−0.7 V speciﬁcation when

the address bits are stabilizing.

[4] Pins of ports 1, 2, 3 and 4 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V_INis approximately 2 V for 4.5 V < V_DD< 5.5 V.

[5] See Figure 13 through Figure 16 for I_CCtest conditions. f_oscis the oscillator frequency in MHz.

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[6] This value applies to T_amb= 0 °C to +70 °C.

[7] Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.

[8] Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

a) Maximum I_OLper port pin: 15 mA

b) Maximum I_OLper 8-bit port: 26 mA

c) Maximum total I_OLfor all outputs: 71 mA

If I_OLexceeds the test condition, V_OLmay exceed the related speciﬁcation. Pins are not guaranteed to sink current greater than the

listed test conditions.

[9] ALE is tested to V_OH1, except when ALE is off then V_OHis the voltage speciﬁcation.

[10] Pin capacitance is characterized but not tested.

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11. Dynamic characteristics

Table 8:

Dynamic characteristics

T_amb= 0 to +70 °C for commercial unless otherwise speciﬁed. Formulae including t_CLCLassume oscillator signal with 50/50

duty cycle.^[1][2][3]

Symbol Fig

Parameter

2.7 V < V_DD< 5.5 V

Variable clock^[4]

4.5 V < V_DD< 5.5 V

Variable clock^[4]

Unit

f_OSC

12 MHz^[4]

Min Max Min

f_OSC=

24 MHz^[4]

Min Max

Min

Max

f_OSC

Oscillator

frequency

MHz

t_CLCL

t_LHLL

t_AVLL

Clock cycle

41.5

ALE pulse width

t_CLCL−15

4, 5, Address valid to 0.5t_CLCL−15

ALE LOW

4, 5, Address hold

0.5t_CLCL−15 -

t_LLAX

t_LLIV

t_LLPL

t_PLPH

t_PLIV

t_PXIX

t_PXIZ

t_AVIV

0.5t_CLCL−25

0.5t_CLCL−15 -

after ALE LOW

ALE LOW to valid

instruction in

0.5t_CLCL−25

121

2t_CLCL− 30

ALE LOW to

PSEN LOW

0.5t_CLCL−25

0.5t_CLCL−12 -

1.5t_CLCL−20 -

PSEN pulse

width

1.5t_CLCL−25

100

PSEN LOW to

valid instruction in

1.5t_CLCL−45

1.5t_CLCL−35

Input instruction

hold after PSEN

Input instruction

ﬂoat after PSEN

0.5t_CLCL−10

2.5t_CLCL−35

173

0.5t_CLCL−5

Address to valid

instruction in

(non-Extended

Addressing

Mode)

2.5t_CLCL−30 -

t_AVIV1

Address

1.5t_CLCL−44

1.5t_CLCL−34 -

(A16-A22) to

valid instruction in

(Extended

Addressing

Mode)

t_PLAZ

PSEN LOW to

address ﬂoat

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Table 8:

Dynamic characteristics…continued

T_amb= 0 to +70 °C for commercial unless otherwise speciﬁed. Formulae including t_CLCLassume oscillator signal with 50/50

duty cycle.^[1][2][3]

Symbol Fig

Parameter

2.7 V < V_DD< 5.5 V

Variable clock^[4]

4.5 V < V_DD< 5.5 V

Variable clock^[4]

Unit

f_OSC

12 MHz^[4]

Min Max Min

f_OSC=

24 MHz^[4]

Min

Max

Min Max

Data Memory

t_RLRH

t_WLWH

t_RLDV

RD pulse width

WR pulse width

3t_CLCL−25

225

3t_CLCL−20

105

RD LOW to valid

data in

2.5t_CLCL−55

153

2.5t_CLCL−40 -

t_RHDX

t_RHDZ

t_LLDV

t_AVDV

Data hold after

Data ﬂoat after

_CLCL−20

283

335

_CLCL−15

ALE LOW to valid

data in

4t_CLCL−50

4t_CLCL−35

131 ns

157 ns

Address to valid

data in

4.5t_CLCL−40

4.5t_CLCL−30 -

(non-Extended

Addressing

Mode)

t_AVDV1

Address

3.5t_CLCL−45

246

3.5t_CLCL−35 -

110 ns

(A16-A22) to

valid data in

(Extended

Addressing

Mode)

t_LLWL

t_AVWL

5, 6 ALE LOW to RD 1.5t_CLCL−5

1.5t_CLCL+20 120 145 1.5t_CLCL−10 1.5t_CLCL+20 52

or WR LOW

5, 6 Address valid to 2t_CLCL−5

WR or RD LOW

(non-Extended

161

2t_CLCL−5

Addressing

Mode)

t_AVWL1

5, 6 Address

(A16-A22) valid

t_CLCL−10

_CLCL−10

to WR or RD

LOW (Extended

Addressing

Mode)

t_QVWX

t_WHQX

t_QVWH

Data valid to WR 0.5t_CLCL−20

transition

0.5t_CLCL−15 -

0.5t_CLCL−11 -

3.5t_CLCL−10 -

Data hold after

0.5t_CLCL−25

Data valid to WR 3.5t_CLCL−10

281

135

HIGH

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Table 8:

Dynamic characteristics…continued

T_amb= 0 to +70 °C for commercial unless otherwise speciﬁed. Formulae including t_CLCLassume oscillator signal with 50/50

duty cycle.^[1][2][3]

Symbol Fig

Parameter

2.7 V < V_DD< 5.5 V

Variable clock^[4]

4.5 V < V_DD< 5.5 V

Variable clock^[4]

Unit

f_OSC

12 MHz^[4]

Min Max Min

f_OSC=

24 MHz^[4]

Min

Max

Min Max

t_RLAZ

RD LOW to

address ﬂoat

t_WHLH

5, 6 RD or WR HIGH 0.5t_CLCL−20 0.5t_CLCL+10 21

0.5t_CLCL−11 0.5t_CLCL+10 9

to ALE HIGH

External Clock

t_CHCX

t_CLCX

t_CLCH

t_CHCL

HIGH time

LOW time

Rise time

Fall Time

_CLCL−t_CLCX33

_CLCL−t_CHCX33

_CLCL−t_CLCX16

_CLCL−t_CHCX16

Shift Register

t_XLXL

Serial port clock 6t_CLCL

cycle time

500

406

_CLCL−t_CLCX

_CLCL−t_CHCX

250

198

t_QVXH

Output data setup 5t_CLCL−10

to clock rising

edge

t_XHQX

t_XHDX

t_XHDV

Output data hold

after clock rising

edge

_CLCL−10

_CLCL−15

Input data hold

after clock rising

edge

Clock rising edge

to input data valid

5t_CLCL−55

361

5t_CLCL−35

173 ns

SPI Interface

f_SPI

MHz

2.0

3.0

t_SPICYC8, 9, Cycle time

10,

2.0 MHz

(Master)

2.0 MHz

(Slave)

500

3.0 MHz

(Master)

3.0 MHz

(Slave)

333

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Table 8:

Dynamic characteristics…continued

T_amb= 0 to +70 °C for commercial unless otherwise speciﬁed. Formulae including t_CLCLassume oscillator signal with 50/50

duty cycle.^[1][2][3]

Symbol Fig

Parameter

2.7 V < V_DD< 5.5 V

Variable clock^[4]

4.5 V < V_DD< 5.5 V

Variable clock^[4]

Unit

f_OSC

12 MHz^[4]

Min Max Min

f_OSC=

24 MHz^[4]

Min

Max

Min Max

t_SPILEAD10,

Enable lead time

(Slave)

2.0 MHz

3.0 MHz

250

240

250

240

250

240

250

240

t_SPILAG10,

Enable lag time

(Slave)

2.0 MHz

3.0 MHz

250

240

250

240

250

240

250

240

t_SPICLKH8, 9, SPICLK HIGH

10,

time

Master

Slave

t_SPICLKL8, 9, SPICLK LOW

340

190

340

190

340

190

340

190

10,

time

Master

Slave

t_SPIDSU8, 9, Data setup time

340

190

100

340

190

100

340

190

100

340

190

100

10,

(Master or Slave)

t_SPIDH

8, 9, Data hold time

100

10,

(Master or Slave)

t_SPIA

10,

Access time

(Slave)

120

120 ns

t_SPIDIS

10,

Disable time

(Slave)

2.0 MHz

3.0 MHz

240

167

240

167

240

167

240

167

t_SPIDV

8, 9, Enable to output

10,

data valid

2.0 MHz

3.0 MHz

240

167

240

167

240

167

240

167

t_SPIOH

8, 9, Output data hold

10,

time

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Table 8:

Dynamic characteristics…continued

T_amb= 0 to +70 °C for commercial unless otherwise speciﬁed. Formulae including t_CLCLassume oscillator signal with 50/50

duty cycle.^[1][2][3]

Symbol Fig

Parameter

2.7 V < V_DD< 5.5 V

Variable clock^[4]

4.5 V < V_DD< 5.5 V

Variable clock^[4]

Unit

f_OSC

12 MHz^[4]

Min Max Min

f_OSC=

24 MHz^[4]

Min

Max

Min Max

t_SPIR

8, 9, Rise time

10,

SPI outputs

100

(SPICLK,

MOSI, MISO)

SPI outputs

(SPICLK,

MOSI, MISO,

SS)

2000

2000 -

2000

t_SPIF

8, 9, Fall time

10,

SPI outputs

100

(SPICLK,

MOSI, MISO)

SPI outputs

(SPICLK,

MOSI, MISO,

SS)

2000

2000 -

2000

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.

[3] Interfacing the microcontroller to devices with ﬂoat times up to 45 ns is permitted. This limited bus contention will not cause damage to

Port 0 drivers.

[4] Parts are tested down to 2 MHz, but are guaranteed to operate down to 0 Hz.

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11.1 Explanation of AC symbols

Each timing symbol has ﬁve characters. The ﬁrst character is always ‘t’ (= time). The

other characters, depending on their positions, indicate the name of a signal or the

logical status of that signal. The designations are:

A — Address

C — Clock

D — Input data

H — Logic level HIGH

I — Instruction (program memory contents)

L — Logic level LOW, or ALE

P — PSEN

Q — Output data

R — RD signal

t — Time

V — Valid

W — WR signal

X — No longer a valid logic level

Z — Float

Examples:

t_AVLL— Time for address valid to ALE LOW

t_LLPL— Time for ALE LOW to PSEN LOW

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LHLL

ALE

LLPL

PLPH

LLIV

PLIV

PSEN

PLAZ

PXIZ

AVLL

PXIX

LLAX

PORT 0

A0-A7

INSTR IN

A0-A7

AVIV1

AVIV

PORT 2

P2.0-P2.7 OR A8-A15

P2.0-P2.7 OR

A8-A15 OR

A16-A22,P2.7

002aaa150

Fig 4. External program memory read cycle (extended memory cycle).

ALE

WHLH

PSEN

LLDV

LLWL

RLRH

LLAX

RLDV

RLAZ

RHDZ

AVLL

RHDX

PORT 0

INSTR IN

A0-A7

DATA in

A0-A7 FROM PCL

AVWL

AVWL1

AVDV1

AVDV

P2.0-P2.7 OR A8-A15

PORT 2

P2.0-P2.7 OR

A8-A15 OR

A16-A22,P2.7

002aaa151

Fig 5. External data memory read cycle.

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ALE

PSEN

WHLH

WLWH

LLWL

LLAX

QVWX

WHQX

AVLL

QVWH

DATA OUT

AVWL1

PORT 0

PORT 2

INSTR IN

A0-A7

A0-A7 FROM PCL

AVWL

P2.0-P2.7 OR A8-A15

P2.0-P2.7 OR

A8-A15 OR

A16-A22,P2.7

002aaa153

Fig 6. External data memory write cycle.

INSTRUCTION

ALE

XLXL

CLOCK

XHQX

QVXH

OUTPUT DATA

WRITE TO SBUF

XHDX

SET TI

XHDV

INPUT DATA

CLEAR RI

VALID

SET RI

002aaa155

Fig 7. Shift register mode timing.

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CLCL

SPIR

SPIF

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(output)

SPIR

SPIF

SPICLKL

SPICLKH

SPICLK

(CPOL = 1)

(output)

SPIDH

SPIDSU

MISO

(input)

LSB/MSB in

MSB/LSB in

SPIDV

SPIR

SPIOH

SPIDV

SPIF

MOSI

(output)

Master MSB/LSB out

Master LSB/MSB out

002aaa156

Fig 8. SPI master timing (CPHA = 0).

CLCL

SPIF

SPIR

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(output)

SPIR

SPIF

SPICLKL

SPICLKH

SPICLK

(CPOL = 1)

(output)

SPIDH

SPIDSU

MISO

(input)

LSB/MSB in

MSB/LSB in

SPIDV

SPIOH

SPIDV

SPIR

SPIF

MOSI

(output)

Master MSB/LSB out

Master LSB/MSB out

002aaa157

Fig 9. SPI master timing (CPHA = 1).

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SPIR

CLCL

SPIF

SPILEAD

SPIR

SPILAG

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(input)

SPIR

SPIF

SPICLKL

SPICLKH

SPICLK

(CPOL = 1)

(input)

SPIOH

SPIA

SPIDIS

SPIDV

MISO

(output)

Slave MSB/LSB out

Slave LSB/MSB out

Not defined

SPIDH

SPIDSU

SPIDH

SPIDSU

MOSI

(input)

MSB/LSB in

LSB/MSB in

002aaa158

Fig 10. SPI slave timing (CPHA = 0).

SPIR

CLCL

SPIF

SPILEAD

SPIR

SPILAG

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(input)

SPIR

SPIF

SPICLKL

SPICLKH

SPICLK

(CPOL = 1)

(input)

SPIOH

SPIDV

SPIDIS

SPIDV

SPIA

MISO

(output)

Slave LSB/MSB out

Slave MSB/LSB out

Not defined

SPIDH

SPIDSU

SPIDH

SPIDSU

MOSI

(input)

MSB/LSB in

LSB/MSB in

002aaa159

Fig 11. SPI slave timing (CPHA = 1).

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-0.5 V

0.45 V

0.7 V

0.2 V

-0.1 V

CHCX

CLCX

CHCL

CLCH

CLCL

002aaa160

Fig 12. External clock drive.

RST

(NC)

XTAL2

XTAL1

CLOCK SIGNAL

002aaa161

Fig 13. I_CCtest condition, active mode (all other pins are disconnected).

RST

(NC)

XTAL2

XTAL1

CLOCK SIGNAL

002aaa162

Fig 14. I_CCtest condition, idle mode (all other pins are disconnected).

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-0.5 V

0.45 V

0.7 V

0.2 V

-0.1 V

CHCX

CLCX

CHCL

CLCH

CLCL

002aaa163

Fig 15. Clock signal waveform for I_CCtests in active and idle modes (t_CLCH= t_CHCL= 5 ns).

RST

(NC)

XTAL2

XTAL1

002aaa164

Fig 16. I_CCtest condition, power-down mode (all other pins are disconnected, V_DD= 2.0 V to 5.5 V).

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12. Package outline

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

pin 1 index

(A )

detail X

10 mm

scale

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

(1)

UNIT

max.

min.

max. max.

4.57

4.19

0.81 16.66 16.66

0.66 16.51 16.51

16.00 16.00 17.65 17.65 1.22 1.44

14.99 14.99 17.40 17.40 1.07 1.02

0.53

0.33

0.51 0.25 3.05

0.02 0.01 0.12

1.27

0.05

0.18 0.18

0.1

2.16 2.16

0.180

0.165

0.032 0.656 0.656

0.026 0.650 0.650

0.63 0.63 0.695 0.695 0.048 0.057

0.59 0.59 0.685 0.685 0.042 0.040

0.021

0.013

inches

0.007 0.007 0.004 0.085 0.085

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

01-11-14

SOT187-2

112E10

MS-018

EDR-7319

Fig 17. SOT187-2.

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13. Soldering

13.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account

of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all IC packages. Wave soldering can still

be used for certain surface mount ICs, but it is not suitable for ﬁne pitch SMDs. In

these situations reﬂow soldering is recommended. In these situations reﬂow

soldering is recommended.

13.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling

or pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 to 270 °C depending on solder

paste material. The top-surface temperature of the packages should preferably be

kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with

a thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all

times.

13.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging

and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal

results:

• Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

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• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must

incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or

265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in

most applications.

13.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low

voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time

must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320 °C.

13.5 Package related soldering information

Table 9:

Suitability of surface mount IC packages for wave and reﬂow soldering

methods

Package^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, USON, VFBGA

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable^[4]

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^[5][6]

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal

or external package cracks may occur due to vaporization of the moisture in them (the so called

popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

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[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must

on no account be processed through more than one soldering cycle or subjected to infrared reﬂow

soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow

oven. The package body peak temperature must be kept as low as possible.

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom

side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with

the heatsink on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it

is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex

foil by using a hot bar soldering process. The appropriate soldering proﬁle can be provided on

request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

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14. Revision history

Table 10: Revision history

Rev Date

CPCN

Description

03 20031113

Product data (9397 750 12302); ECN 853-2426 01-A14402 dated 6 November 2003

Modiﬁcations:

• Figure 5 “External data memory read cycle.” on page 24; added t_RLDV, removed

‘non-extended memory cycle’ from ﬁgure title.

• Figure 6 “External data memory write cycle.” on page 25; removed ‘non-extended

memory cycle’ from ﬁgure title.

02 20030519

_1 20010406

Product data (9397 750 11517)

Preliminary speciﬁcation (9397 750 08199)

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15. Data sheet status

Level Data sheet status^[1]

Product status^[2][3]

Deﬁnition

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

16. Deﬁnitions

17. Disclaimers

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

35 of 36

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80C51 8-bit microcontroller family

Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key beneﬁts . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Complete features . . . . . . . . . . . . . . . . . . . . . . 2

2.1

2.2

2.3

Differences between P87C51MX2/02 part

and previous revisions of P87C51MX2. . . . . . 3

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

Functional description . . . . . . . . . . . . . . . . . . 10

Memory arrangement . . . . . . . . . . . . . . . . . . . 10

Special Function Registers. . . . . . . . . . . . . . . 10

Security bits . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.1

8.2

8.3

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15

Static characteristics. . . . . . . . . . . . . . . . . . . . 16

Dynamic characteristics . . . . . . . . . . . . . . . . . 18

Explanation of AC symbols. . . . . . . . . . . . . . . 23

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 30

11.1

13.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 31

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 31

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 32

Package related soldering information . . . . . . 32

13.2

13.3

13.4

13.5

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 34

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 35

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Printed in the U.S.A.

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 13 November 2003

Document order number: 9397 750 12302

P87C51MB2BA/02 [NXP]

相关型号：

P87C51MB2BA/02,512

P87C51MB2BA/02,529

P87C51MC2

P87C51MC2BA

P87C51MC2BA/02

P87C51MC2BA/02,529

P87C51MC2BA/02Y

P87C51RA

P87C51RA+4A

P87C51RA+4A-T

P87C51RA+4B

P87C51RA+4B