P87C58IFBB_技术文档

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

DESCRIPTION

PIN CONFIGURATIONS

The 87C54/87C58 Single-Chip 8-Bit Microcontroller is manufactured

in an advanced CMOS process and is a derivative of the 80C51

microcontroller family. The 87C54/87C58 has the same instruction

set as the 80C51.

T2/P1.0

40

39

V

CC

1

2

3

T2EX/P1.1

P0.0/AD0

P1.2

38 P0.1/AD1

37 P0.2/AD2

This device provides architectural enhancements that make it

applicable in a variety of applications for general control systems.

The 87C58 contains 32k × 8 EPROM memory, and the 87C54

contains 16k × 8 EPROM memory, a volatile 256 × 8 read/write data

memory, four 8-bit I/O ports, three 16-bit timer/event counters, a

multi-source, two-priority-level, nested interrupt structure, an

enhanced UART and on-chip oscillator and timing circuits. For

systems that require extra capability, the 87C54/87C58 can be

expanded using standard TTL compatible memories and logic.

P1.3

P1.4

4

5

36

P0.3/AD3

35 P0.4/AD4

34

P1.5

P1.6

P1.7

RST

6

7

8

9

P0.5/AD5

33 P0.6/AD6

32

P0.7/AD7

DUAL

IN-LINE

PACKAGE

31 EA/V

RxD/P3.0 10

TxD/P3.1 11

INT0/P3.2 12

PP

Its added features make it an even more powerful microcontroller for

applications that require pulse width modulation, high-speed I/O and

up/down counting capabilities such as motor control. It also has a

more versatile serial channel that facilitates multiprocessor

communications.

30

ALE/PROG

29 PSEN

28

13

INT1/P3.3

P2.7/A15

27 P2.6/A14

26

T0/P3.4 14

T1/P3.5 15

WR/P3.6 16

RD/P3.7 17

XTAL2 18

See 80C52/54/58 datasheet for ROM device specification.

P2.5/A13

25 P2.4/A12

24 P2.3/A11

FEATURES

• 80C51 central processing unit

23

22

P2.2/A10

P2.1/A9

P2.0/A8

• 16k × 8 EPROM expandable externally to 64k bytes (87C54)

XTAL1 19

• 16k × 8 EPROM (87C54) and

21

V

20

SS

32k × 8 EPROM expandable externally to 64k bytes (87C58)

– Improved Quick Pulse programming algorithm

SU00748

– Two level program security system

– 32 byte encryption array

• 256 × 8 RAM, expandable externally to 64k bytes

• Three 16-bit timer/counters

– T2 is an up/down counter

• Four 8-bit I/O ports

• Full-duplex enhanced UART

– Framing error detection

– Automatic address recognition

• Power control modes

– Idle mode

– Power-down mode

• Once (On Circuit Emulation) Mode

• Five package styles

• OTP package available

• Programmable clock out

• 6 interrupt sources

• 2 level priority

3-215

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

ORDERING INFORMATION

16k × 8

EPROM

32k × 8

EPROM

DRAWING

FREQUENCY

TEMPERATURE RANGE °C AND PACKAGE

1

NUMBER

P87C54EBP N

P87C54EBF FA

P87C54EBA A

P87C54EBL KA

P87C54EBB B

P87C54EFP N

P87C54EFF FA

P87C54EFA A

P87C54EFB B

P87C54IBP N

P87C54IBF FA

P87C54IBA A

P87C54IBL KA

P87C54IBB B

P87C58EBP N

P87C58EBF FA

P87C58EBA A

P87C58EBL KA

P87C58EBB B

P87C58EFP N

P87C58EFF FA

P87C58EFA A

P87C58EFB B

P87C58IBP N

P87C58IBF FA

P87C58IBA A

P87C58IBL KA

P87C58IBB B

OTP

UV

0 to +70, 40-Pin Plastic Dual In-line Package

0 to +70, 40-Pin Ceramic Dual In-line Package w/Window

0 to +70, 44-Pin Plastic Leaded Chip Carrier

16MHz

24MHz

SOT129-1

0590B

OTP

UV

SOT187-2

1472A

0 to +70, 44-Pin Ceramic Leaded Chip Carrier w/Window

0 to +70, 44-Pin Plastic Quad Flat Pack

OTP

UV

SOT307-2

SOT129-1

0590B

–40 to +85, 40-Pin Plastic Dual In-line Package

–40 to +85, 40-Pin Ceramic Dual In-line Package w/Window

–40 to +85, 44-Pin Plastic Leaded Chip Carrier

–40 to +85, 44-Pin Plastic Quad Flat Pack

OTP

UV

SOT187-2

SOT307-2

SOT129-1

0590B

0 to +70, 40-Pin Plastic Dual In-line Package

0 to +70, 40-Pin Ceramic Dual In-line Package w/Window

0 to +70, 44-Pin Plastic Leaded Chip Carrier

OTP

UV

SOT187-2

1472A

0 to +70, 44-Pin Ceramic Leaded Chip Carrier w/Window

0 to +70, 44-Pin Plastic Quad Flat Pack

OTP

UV

SOT307-2

SOT129-1

0590B

P87C54IFP

N

P87C58IFP

N

–40 to +85, 40-Pin Plastic Dual In-line Package

–40 to +85, 40-Pin Ceramic Dual In-line Package w/Window

–40 to +85, 44-Pin Plastic Leaded Chip Carrier

–40 to +85, 44-Pin Plastic Quad Flat Pack

P87C54IFF FA

P87C58IFF FA

P87C54IFA

A

B

P87C58IFA

P87C58IFB

A

B

OTP

SOT187-2

SOT307-2

P87C54IFB

NOTE:

1. OTP = One Time Programmable EPROM. UV = Erasable EPROM.

LOGIC SYMBOL

V

SS

CC

XTAL1

ADDRESS AND

DATA BUS

XTAL2

T2

T2EX

RST

EA

PSEN

ALE

RxD

TxD

INT0

INT1

T0

ADDRESS BUS

T1

WR

RD

SU00732

3-216

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

BLOCK DIAGRAM

P0.0–P0.7

P2.0–P2.7

PORT 0

DRIVERS

PORT 2

DRIVERS

V

CC

V

SS

RAM ADDR

REGISTER

PORT 0

LATCH

PORT 2

LATCH

ROM/EPROM

RAM

B

STACK

POINTER

ACC

REGISTER

PROGRAM

ADDRESS

REGISTER

TMP1

TMP2

BUFFER

ALU

SFRs

PC

INCRE-

MENTER

TIMERS

PSW

PROGRAM

COUNTER

PSEN

ALE/PROG

TIMING

AND

CONTROL

DPTR

EA/V

PP

RST

PORT 1

LATCH

PORT 3

LATCH

PD

OSCILLATOR

PORT 1

DRIVERS

PORT 3

DRIVERS

XTAL1

XTAL2

P1.0–P1.7

P3.0–P3.7

SU00182

3-217

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

Table 1.

87C54/87C58 Special Function Registers

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

RESET

VALUE

SYMBOL

DESCRIPTION

Accumulator

MSB

E7

–

LSB

ACC*

AUXR#

B*

E0H

8EH

F0H

E6

–

E5

–

E4

–

E3

–

E2

–

E1

–

E0

00H

Auxiliary

AO

F0

xxxxxxx0B

00H

B register

F7

F6

F5

F4

F3

F2

F1

DPTR:

DPH

DPL

Data Pointer (2 bytes)

Data Pointer High

Data Pointer Low

83H

82H

00H

AF

EA

BF

–

AE

–

AD

ET2

BD

AC

ES

BC

PS

AB

ET1

BB

AA

EX1

BA

A9

ET0

B9

A8

EX0

B8

IE*

IP*

Interrupt Enable

Interrupt Priority

A8H

B8H

00H

BE

–

PT2

PT1

PX1

PT0

PX0

x0000000B

87

AD7

97

86

AD6

96

85

AD5

95

84

AD4

94

83

AD3

93

82

AD2

92

81

AD1

91

80

AD0

90

P0*

P1*

P2*

Port 0

Port 1

Port 2

80H

90H

A0H

FFH

–

T2EX

A1

T2

A7

A6

A5

A4

A3

A2

A0

AD15

B7

AD14

B6

AD13

B5

AD12

B4

AD11

B3

AD10

B2

AD9

B1

AD8

B0

P3*

Port 3

B0H

87H

RD

WR

T1

T0

INT1

INT0

TxD

RxD

FFH

1

PCON#

Power Control

SMOD1

SMOD0

–

POF

GF1

GF0

PD

IDL

00xxxx00B

D7

CY

D6

AC

D5

F0

D4

D3

D2

D1

–

D0

P

PSW*

Program Status Word

D0H

RS1

RS0

OV

00H

RCAP2H#

RCAP2L#

SADDR#

SADEN#

Timer 2 Capture High

Timer 2 Capture Low

Slave Address

CBH

CAH

A9H

B9H

00H

Slave Address Mask

SBUF

Serial Data Buffer

99H

xxxxxxxxB

9F

9E

9D

9C

9B

9A

99

TI

98

RI

SCON*

SP

Serial Control

Stack Pointer

98H

81H

SM0

SM1

SM2

REN

TB8

RB8

00H

07H

8F

TF1

CF

8E

TR1

CE

8D

TF0

8C

TR0

CC

8B

IE1

8A

IT1

CA

89

IE0

C9

88

IT0

C8

TCON*

Timer Control

88H

00H

CD

CB

T2CON#*

Timer 2 Control

C8H

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2 00H

TH0

TH1

TH2#

TL0

TL1

TL2#

Timer High 0

Timer High 1

Timer High 2

Timer Low 0

Timer Low 1

Timer Low 2

8CH

8DH

CDH

8AH

8BH

CCH

00H

C7

GATE

–

C6

C/T

–

C5

M1

–

C4

M0

–

C3

GATE

–

C2

C/T

–

C1

M1

C0

TMOD

Timer Mode

89H

C9H

M0

00H

T2MOD#*

Timer 2 Mode Control

T2OE

DCEN

xxxxxx00B

*

#

SFRs are bit addressable.

SFRs are modified from or added to the 80C51 SFRs.

1. Reset value depends on reset source.

3-218

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

CERAMIC AND PLASTIC LEADED CHIP CARRIER

PIN FUNCTIONS

PLASTIC QUAD FLAT PACK

PIN FUNCTIONS

44

34

6

1

40

7

39

29

1

33

23

PQFP

LCC

11

17

12

22

18

28

Pin Function

1

2

P1.5

P1.6

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

NC*

31

32

33

34

35

36

37

38

39

40

41

42

43

44

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

SS

1

2

3

NC*

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

T0/P3.4

T1/P3.5

WR/P3.6

RD/P3.7

XTAL2

XTAL1

V

SS

NC*

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

31

P2.7/A15

PSEN

32

33

34

35

36

37

38

39

40

41

42

43

44

T2/P1.0

T2EX/P1.1

P1.2

3

P1.7

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE/PROG

NC*

4

RST

4

5

6

RxD/P3.0

NC*

EA/V

PP

5

P1.3

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

6

P1.4

7

8

9

10

11

12

13

14

15

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

WR/P3.6

RD/P3.7

XTAL2

XTAL1

7

P1.5

V

CC

8

P1.6

NC*

9

P1.7

T2/P1.0

T2EX/P1.1

P1.2

P1.3

P1.4

10

11

12

13

14

15

RST

RxD/P3.0

NC*

TxD/P3.1

INT0/P3.2

INT1/P3.3

ALE/PROG

NC*

EA/V

PP

V

CC

P0.7/AD7

* DO NOT CONNECT

SU00061

SU00062

3-219

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC DIP

LCC

QFP

TYPE NAME AND FUNCTION

V

20

40

22

44

16

38

I

Ground: 0V reference.

SS

Power Supply: This is the power supply voltage for normal, idle, and power-down operation.

CC

P0.0–0.7

39–32 43–36 37–30

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them

float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order

address and data bus during accesses to external program and data memory. In this

application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code

bytes during program verification and receives code bytes during EPROM programming.

External pull-ups are required during program verification.

P1.0–P1.7

1–8

2–9

40–44,

1–3

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7

which are open drain. Port 1 pins that have 1s written to them are pulled high by the internal

pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will

source current because of the internal pull-ups. (See DC Electrical Characteristics: I ).

IL

Port 1 also receives the low-order address byte during program memory verification.

Alternate functions include:

1

2

3

40

41

I

T2 (P1.0): Timer/Counter 2 external count input/Clockout

T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control

P2.0–P2.7

21–28 24–31 18–25

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,

port 2 pins that are externally being pulled low will source current because of the internal

pull-ups. (See DC Electrical Characteristics: I ). Port 2 emits the high-order address byte

IL

during fetches from external program memory and during accesses to external data memory

that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups

when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV

@Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins receive

the high order address bits during EPROM programming and verification.

P3.0–P3.7

10–17

11,

5,

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,

port 3 pins that are externally being pulled low will source current because of the pull-ups.

13–19 7–13

(See DC Electrical Characteristics: I ). Port 3 also serves the special features of the 80C51

IL

family, as listed below:

10

11

12

13

14

15

16

17

11

13

14

15

16

17

18

19

5

7

8

I

O

I

O

RxD (P3.0): Serial input port

TxD (P3.1): Serial output port

INT0 (P3.2): External interrupt

INT1 (P3.3): External interrupt

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

9

10

11

12

13

RST

9

10

4

I

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the

device. An internal diffused resistor to V permits a power-on reset using only an external

SS

capacitor to V

.

CC

ALE/PROG

30

33

27

I/O

Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

address during an access to external memory. In normal operation, ALE is emitted at a

constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.

Note that one ALE pulse is skipped during each access to external data memory. This pin is

also the program pulse input (PROG) during EPROM programming. ALE can be disabled by

setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.

PSEN

29

31

32

35

26

29

O

I

Program Store Enable: The read strobe to external program memory. When the 8XC58 is

executing code from the external program memory, PSEN is activated twice each machine

cycle, except that two PSEN activations are skipped during each access to external data

memory. PSEN is not activated during fetches from internal program memory.

EA/V

External Access Enable/Programming Supply Voltage: EA must be externally held low to

enable the device to fetch code from external program memory locations 0000H and 7FFFH.

If EA is held high, the device executes from internal program memory unless the program

counter contains an address greater than 7FFFH. This pin also receives the 12.75V

PP

programming supply voltage (V ) during EPROM programming. If security bit 1 is

PP

programmed, EA will be internally latched on Reset.

XTAL1

19

18

21

20

15

14

I

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator

circuits.

XTAL2

O

Crystal 2: Output from the inverting oscillator amplifier.

NOTE:

To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than V + 0.5V or V – 0.5V, respectively.

CC

SS

3-220

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

idle mode is activated. The CPU contents, the on-chip RAM, and all

of the special function registers remain intact during this mode. The

idle mode can be terminated either by any enabled interrupt (at

which time the process is picked up at the interrupt service routine

and continued), or by a hardware reset which starts the processor in

the same manner as a power-on reset.

TIMER 2

This is a 16-bit up or down counter, which can be operated as either

a timer or event counter. It can be operated in one of three different

modes (autoreload, capture or as the baud rate generator for the

UART).

In the autoreload mode the Timer can be set to count up or down by

setting or clearing the bit DCEN in the T2CON Special Function

Register. The SFR’s RCAP2H and RCAP2L are used to reload the

Timer upon overflow or a 1-to-0 transition on the T2EX input (P1.1).

Power-Down Mode

To save even more power, a Power Down mode can be invoked by

software. In this mode, the oscillator is stopped and the instruction

that invoked Power Down is the last instruction executed. The

on-chip RAM and Special Function Registers retain their values until

the Power Down mode is terminated.

In the Capture mode Timer 2 can either set TF2 and generate an

interrupt or capture its value. To capture Timer 2 in response to a

1-to-0 transition on the T2EX input, the EXEN2 bit in the T2CON

must be set. Timer 2 is then captured in SFR’s RCAP2H and

RCAP2L.

On the 8XC58 either a hardware reset or external interrupt can use

an exit from Power Down. Reset redefines all the SFRs but does not

change the on-chip RAM. An external interrupt allows both the SFRs

and the on-chip RAM to retain their values.

As the baud rate generator, Timer 2 is selected by setting TCLK

and/or RCLK in T2CON. As the baud rate generator Timer 2 is

To properly terminate Power Down the reset or external interrupt

1

incremented at / the oscillator frequency.

2

should not be executed before V is restored to its normal

CC

operating level and must be held active long enough for the

oscillator to restart and stabilize (normally less than 10ms).

POWER OFF FLAG

The Power Off Flag (POF) is set by on-chip circuitry when the V

CC

With an external interrupt, INT0 and INT1 must be enabled and

configured as level-sensitive. Holding the pin low restarts the

oscillator but bringing the pin back high completes the exit. Once the

interrupt is serviced, the next instruction to be executed after RETI

will be the one following the instruction that put the device into

Power Down.

level on the 8XC58 rises from 0 to 5V. The POF bit can be set or

cleared by software allowing a user to determine if the reset is the

result of a power-on or a warm start after powerdown. The V level

must remain above 3V for the POF to remain unaffected by the V

level.

CC

Design Consideration

OSCILLATOR CHARACTERISTICS

• When the idle mode is terminated by a hardware reset, the device

normally resumes program execution, from where it left off, up to

two machine cycles before the internal rest algorithm takes

control. On-chip hardware inhibits access to internal RAM in this

event, but access to the port pins is not inhibited. To eliminate the

possibility of an unexpected write when Idle is terminated by reset,

the instruction following the one that invokes Idle should not be

one that writes to a port pin or to external memory.

XTAL1 and XTAL2 are the input and output, respectively, of an

inverting amplifier. The pins can be configured for use as an on-chip

oscillator.

To drive the device from an external clock source, XTAL1 should be

driven while XTAL2 is left unconnected. There are no requirements on

the duty cycle of the external clock signal, because the input to the

internal clock circuitry is through a divide-by-two flip-flop. However,

minimum and maximum high and low times specified in the data

sheet must be observed.

• The windowed parts must be covered with an opaque label to

assure proper chip operation.

Reset

ONCE Mode

A reset is accomplished by holding the RST pin high for at least two

machine cycles (24 oscillator periods), while the oscillator is running.

To insure a good power-on reset, the RST pin must be high long

enough to allow the oscillator time to start up (normally a few

milliseconds) plus two machine cycles. At power-on, the voltage on

The ONCE (“On-Circuit Emulation”) Mode facilitates testing and

debugging of systems using the 8XC58 without the 8XC58 having to

be removed from the circuit. The ONCE Mode is invoked by:

1. Pull ALE low while the device is in reset and PSEN is high;

2. Hold ALE low as RST is deactivated.

V

CC

and RST must come up at the same time for a proper start-up.

Ports 1, 2, and 3 will asynchronously be driven to their reset

condition when a voltage above V

is applied to RESET.

IH1

While the device is in ONCE Mode, the Port 0 pins go into a float

state, and the other port pins and ALE and PSEN are weakly pulled

high. The oscillator circuit remains active. While the 8XC58 is in this

mode, an emulator or test CPU can be used to drive the circuit.

Normal operation is restored when a normal reset is applied.

Idle Mode

In the idle mode, the CPU puts itself to sleep while all of the on-chip

peripherals stay active. The instruction to invoke the idle mode is the

last instruction executed in the normal operating mode before the

Table 2. External Pin Status During Idle and Power-Down Mode

PROGRAM

MEMORY

MODE

ALE

PSEN

PORT 0

Data

PORT 1

Data

PORT 2

Data

PORT 3

Data

Idle

Internal

1

0

1

0

External

Internal

Float

Data

Address

Data

Power-down

Data

External

Float

Data

3-221

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

address which the master will use for addressing each of the slaves.

Use of the Given address allows multiple slaves to be recognized

while excluding others. The following examples will help to show the

versatility of this scheme:

Programmable Clock-Out

The 87C54/87C58 has a new feature. A 50% duty cycle clock can

be programmed to come out on P1.0. This pin, besides being a

regular I/O pin, has two alternate functions. It can be programmed

(1) to input the external clock for Timer/Counter 2 or (2) to output a

50% duty cycle clock ranging from 61Hz to 4MHz at a 16MHz

operating frequency.

Slave 0

SADDR

SADEN

Given

=

1100 0000

1111 1101

1100 00X0

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in

T2CON) must be cleared and bit T20E in T2MOD must be set. Bit

TR2 (T2CON.2) also must be set to start the timer.

Slave 1

SADDR

SADEN

Given

=

1100 0000

1111 1110

1100 000X

The Clock-Out frequency depends on the oscillator frequency and

the reload value of Timer 2 capture registers (RCAP2H, RCAP2L)

as shown in this equation:

In the above example SADDR is the same and the SADEN data is

used to differentiate between the two slaves. Slave 0 requires a 0 in

bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is

ignored. A unique address for Slave 0 would be 1100 0010 since

slave 1 requires a 0 in bit 1. A unique address for slave 1 would be

1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be

selected at the same time by an address which has bit 0 = 0 (for

slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed

with 1100 0000.

OscillatorFrequency

4 (65536 * RCAP2H, RCAP2L)

In the Clock-Out mode Timer 2 roll-overs will not generate an

interrupt. This is similar to when it is used as a baud-rate generator.

It is possible to use Timer 2 as a baud-rate generator and a clock

generator simultaneously. Note, however, that the baud-rate and the

Clock-Out frequency will be the same.

In a more complex system the following could be used to select

slaves 1 and 2 while excluding slave 0:

Enhanced UART

Slave 0

Slave 1

Slave 2

SADDR

SADEN

Given

=

1100 0000

1111 1001

1100 0XX0

The UART operates in all of the usual modes that are described in

the first section of this book for the 80C51. In addition the UART can

perform framing error detect by looking for missing stop bits, and

automatic address recognition. The 87C54/87C58 UART also fully

supports multiprocessor communication as does the standard

80C51 UART.

SADDR

SADEN

Given

=

1110 0000

1111 1010

1110 0X0X

When used for framing error detect the UART looks for missing stop

bits in the communication. A missing bit will set the FE bit in the

SCON register. The FE bit shares the SCON.7 bit with SM0 and the

function of SCON.7 is determined by PCON.6 (SMOD0) (see

Figure 1). If SMOD0 is set then SCON.7 functions as FE. SCON.7

functions as SM0 when SMOD0 is cleared. When used as FE

SCON.7 can only be cleared by software. Refer to Figure 2.

SADDR

SADEN

Given

=

1110 0000

1111 1100

1110 00XX

In the above example the differentiation among the 3 slaves is in the

lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be

uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and

it can be uniquely addressed by 1110 and 0101. Slave 2 requires

that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0

and 1 and exclude Slave 2 use address 1110 0100, since it is

necessary t make bit 2 = 1 to exclude slave 2.

Automatic Address Recognition

Automatic Address Recognition is a feature which allows the UART

to recognize certain addresses in the serial bit stream by using

hardware to make the comparisons. This feature saves a great deal

of software overhead by eliminating the need for the software to

examine every serial address which passes by the serial port. This

feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART

modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be

automatically set when the received byte contains either the “Given”

address or the “Broadcast” address. The 9 bit mode requires that

the 9th information bit is a 1 to indicate that the received information

is an address and not data. Automatic address recognition is shown

in Figure 3.

The Broadcast Address for each slave is created by taking the

logical OR of SADDR and SADEN. Zeros in this result are teated as

don’t-cares. In most cases, interpreting the don’t-cares as ones, the

broadcast address will be FF hexadecimal.

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR

address 0B9H) are loaded with 0s. This produces a given address

of all “don’t cares” as well as a Broadcast address of all “don’t

cares”. this effectively disables the Automatic Addressing mode and

allows the microcontroller to use standard 80C51 type UART drivers

which do not make use of this feature.

The 8 bit mode is called Mode 1. In this mode the RI flag will be set

if SM2 is enabled and the information received has a valid stop bit

following the 8 address bits and the information is either a Given or

Broadcast address.

Reduced EMI Mode

The AO bit (AUXR.0) in the AUXR register, when set, disables the

ALE output.

Mode 0 is the Shift Register mode and SM2 is ignored.

Using the Automatic Address Recognition feature allows a master to

selectively communicate with one or more slaves by invoking the

Given slave address or addresses. All of the slaves may be

8XC58 Reduced EMI Mode

AUXR (0X8E)

contacted by using the Broadcast address. Two special Function

Registers are used to define the slave’s address, SADDR, and the

address mask, SADEN. SADEN is used to define which bits in the

SADDR are to b used and which bits are “don’t care”. The SADEN

mask can be logically ANDed with the SADDR to create the “|Given”

7

6

5

4

–

3

–

2

–

1

–

0

–

AO

AO: Turns off ALE output.

3-222

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

equal or higher priority is not already being serviced. If an interrupt

of equal or higher level priority is being serviced, the new interrupt

will wait until it is finished before being serviced. If a lower priority

level interrupt is being serviced, it will be stopped and the new

interrupt serviced. When the new interrupt is finished, the lower

priority level interrupt that was stopped will be completed.

Interrupt Priority Structure

The 87C54/87C58 has a 6-source two-level interrupt structure.

There are 3 SFRs associated with the interrupts. They are the IE

and IP which are identical in function to those on the 80C51.

The priority scheme for servicing the interrupts is the same as that

for the 80C51. An interrupt will be serviced as long as an interrupt of

Table 3.

Interrupt Table

SOURCE

POLLING PRIORITY

REQUEST BITS

HARDWARE CLEAR?

VECTOR ADDRESS

X0

T0

X1

T1

SP

T2

1

2

3

4

5

6

IE0

TP0

N (L) Y (T)

03H

0B

13

Y

IE1

N (L) Y (T)

TF1

Y

N

1B

23

R1, TI

TF2, EXF2

2B

SCON Address = 98H

Bit Addressable

Reset Value = 0000 0000B

SM0/FE

SM1

SM2

REN

TB8

RB8

Tl

Rl

Bit:

7

6

5

4

3

2

1

0

(SMOD0 = 0/1)*

Symbol

FE

Function

Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid

frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.

SM0

SM1

Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)

Serial Port Mode Bit 1

SM0

SM1

Mode

Description

Baud Rate**

f /12

OSC

0

1

0

1

0

1

0

1

2

3

shift register

8-bit UART

9-bit UART

variable

/64 or f

f

/32

OSC

variable

SM2

Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the

received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.

In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a

Given or Broadcast Address. In Mode 0, SM2 should be 0.

REN

TB8

RB8

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.

In Mode 0, RB8 is not used.

Tl

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the

other modes, in any serial transmission. Must be cleared by software.

Rl

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in

the other modes, in any serial reception (except see SM2). Must be cleared by software.

NOTE:

*SMOD0 is located at PCON6.

**f = oscillator frequency

OSC

SU00043

Figure 1. SCON: Serial Port Control Register

3-223

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

D0

D1

D2

D3

D4

D5

D6

D7

D8

START

BIT

DATA BYTE

ONLY IN

MODE 2, 3

STOP

BIT

SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)

SM0 TO UART MODE CONTROL

SCON

(98H)

SM0 / FE

SMOD1

SM1

SM2

OSF

REN

POF

TB8

LVF

RB8

GF0

TI

RI

PCON

(87H)

SMOD0

GF1

IDL

0 : SCON.7 = SM0

1 : SCON.7 = FE

SU00044

Figure 2. UART Framing Error Detection

D0

D1

D2

D3

D4

D5

D6

D7

D8

SCON

(98H)

SM0

SM1

SM2

REN

1

TB8

X

RB8

TI

RI

1

0

1

RECEIVED ADDRESS D0 TO D7

PROGRAMMED ADDRESS

COMPARATOR

IN UART MODE 2 OR MODE 3 AND SM2 = 1:

INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”

– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES

– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.

SU00045

Figure 3. UART Multiprocessor Communication, Automatic Address Recognition

1, 2, 3

ABSOLUTE MAXIMUM RATINGS

PARAMETER

RATING

UNIT

Operating temperature under bias

Storage temperature range

0 to +70 or –40 to +85

–65 to +150

0 to +13.0

–0.5 to +6.5

15

°C

V

Voltage on EA/V pin to V

PP

SS

Voltage on any other pin to V

V

SS

Maximum I per I/O pin

mA

W

OL

Power dissipation

1.5

(based on package heat transfer limitations, not device power consumption)

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section

of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise

SS

noted.

3-224

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

DC ELECTRICAL CHARACTERISTICS

T

amb

= 0°C to +70°C, V = 5V ±10%, V = 0V

CC SS

TEST

LIMITS

1

SYMBOL

PARAMETER

CONDITIONS

MIN

–0.5

0

TYP

MAX

0.2V –0.1

UNIT

V

Input low voltage, except EA

Input low voltage to EA

V

IL

CC

0.2V –0.3

IL1

IH1

CC

Input high voltage, XTAL1, RST

Output low voltage, ports 1, 2, 3

0.7V

V

CC

+0.5

CC

7

2

V

I

= 1.6mA

= 3.2mA

0.45

V

OL

7

2

Output low voltage, port 0, ALE, PSEN

OL1

OH

OL

3

Output high voltage, ports 1, 2, 3

I

= –30µA

V

– 0.7

OH

CC

Output high voltage (port 0 in external bus mode),

I

= –3.2mA

OH1

OH

CC

8

3

ALE , PSEN

I

Logical 0 input current, ports 1, 2, 3

Logical 1-to-0 transition current, ports 1, 2, 3

Input leakage current, port 0

V

= 0.4V

–50

–650

±10

µA

IL

IN

5

See note 4

0.45 V < V – 0.3

TL

LI

IN

CC

Power supply current (See Figure 11):

Active mode @ 16MHz

See note 10

CC

15

3

10

32

5

75

100

mA

µA

Idle mode @ 16MHz

Power-down mode

T

amb

= 0 to +70°C

T

amb

= –40 to +85°C

µA

R

C

Internal reset pull-down resistor

40

225

15

kΩ

RST

IO

9

Pin capacitance (except EA)

pF

NOTES:

1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V s of ALE and ports 1 and 3. The noise is due

OL

to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the

worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify

ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I can exceed these conditions provided that no

OL

single output sinks more than 5mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specification when the

OH

CC

address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its

maximum value when V is approximately 2V.

IN

5. This value applies to T

= 0°C to +70°C. For T = –40°C to 85°C, I = –750µA.

amb TL

amb

6. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

7. Under steady state (non-transient) conditions, I must be externally limited as follows:

OL

Maximum I per port pin:

15mA

26mA

71mA

OL

Maximum I per 8-bit port:

OL

Maximum total I for all outputs:

OL

If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

OL

test conditions.

8. ALE is tested to V

, except when ALE is off then V is the voltage specification.

OH

OH1

9. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF

(except EA it is 25pF).

10.See Figures 12 through 15 for I test condition.

CC

3-225

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

AC ELECTRICAL CHARACTERISTICS

1, 2, 3

T

amb

= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V

CC SS

16MHz CLOCK

VARIABLE CLOCK

MIN MAX

16

SYMBOL

1/t

FIGURE

PARAMETER

Oscillator frequency

MIN

MAX

UNIT

4

3.5

MHz

CLCL

Speed versions

: E

t

4

ALE pulse width

85

22

32

2t

–40

ns

LHLL

CLCL

Address valid to ALE low

Address hold after ALE low

ALE low to valid instruction in

ALE low to PSEN low

PSEN pulse width

t

–40

–30

AVLL

LLAX

LLIV

CLCL

t

150

82

4t

3t

–100

CLCL

32

t

–30

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

142

3t

CLCL

–45

PSEN low to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address to valid instruction in

PSEN low to address float

–105

CLCL

0

37

207

10

t

–25

CLCL

5t

CLCL

–105

10

Data Memory

t

5, 6

6

RD pulse width

275

6t

–100

ns

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

CLCL

WR pulse width

6t

CLCL

RD low to valid data in

Data hold after RD

147

5t

–165

CLCL

0

Data float after RD

65

2t

–60

CLCL

ALE low to valid data in

Address to valid data in

ALE low to RD or WR low

Address valid to WR low or RD low

Data valid to WR transition

Data hold after WR

350

397

239

8t

CLCL

9t

CLCL

–150

–165

AVDV

LLWL

137

122

13

3t

–50

3t

+50

CLCL

4t

t

–130

–50

AVWL

QVWX

WHQX

QVWH

RLAZ

WHLH

CLCL

13

t

–50

Data valid to WR high

RD low to address float

RD or WR high to ALE high

287

7t

–150

5, 6

0

23

103

t

–40

t

+40

CLCL

External Clock

t

8

High time

Low time

Rise time

Fall time

20

t

+t

ns

CHCX

CLCX

CLCH

CHCL

CLCL CLCX

t

+t

CLCL CHCX

20

Shift Register

t

7

Serial port clock cycle time

750

492

8

12t

ns

XLXL

CLCL

Output data setup to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

10t

–133

QVXH

XHQX

XHDX

XHDV

CLCL

2t

CLCL

–117

0

492

10t

–133

CLCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

3. Interfacing the 8XC58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.

3-226

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

AC ELECTRICAL CHARACTERISTICS

1, 2, 3

T

amb

= 0°C to +70°C or –40°C to +85°C, V = 5V ±10%, V = 0V

CC SS

4

24MHz CLOCK

VARIABLE CLOCK

SYMBOL

1/t

FIGURE

PARAMETER

Oscillator frequency

MIN

MAX

MIN

MAX

UNIT

4

CLCL

Speed versions : I

3.5

24

MHz

ns

t

4

ALE pulse width

43

17

2t

–40

LHLL

CLCL

Address valid to ALE low

Address hold after ALE low

ALE low to valid instruction in

ALE low to PSEN low

t

–25

AVLL

LLAX

LLIV

CLCL

–25

102

65

4t

3t

–65

CLCL

17

80

t

–25

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

CLCL

PSEN pulse width

3t

–45

CLCL

PSEN low to valid instruction in

–60

CLCL

Input instruction hold after PSEN

Input instruction float after PSEN

Address to valid instruction in

PSEN low to address float

0

17

128

10

t

–25

CLCL

5t

–80

CLCL

10

Data Memory

t

5, 6

6

RD pulse width

150

6t

–100

ns

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

CLCL

WR pulse width

6t

CLCL

RD low to valid data in

Data hold after RD

118

5t

2t

–90

–28

CLCL

0

Data float after RD

55

CLCL

ALE low to valid data in

Address to valid data in

ALE low to RD or WR low

Address valid to WR low or RD low

Data valid to WR transition

Data hold after WR

183

210

175

8t

–150

–165

CLCL

9t

AVDV

LLWL

75

92

3t

–50

–75

3t

CLCL

+50

CLCL

4t

AVWL

QVWX

WHQX

QVWH

RLAZ

WHLH

CLCL

12

t

–30

CLCL

17

–25

Data valid to WR high

RD low to address float

RD or WR high to ALE high

162

7t

–130

5, 6

0

17

67

t

–25

t

+25

CLCL

External Clock

t

8

High time

Low time

Rise time

Fall time

17

t

–t

ns

CHCX

CLCX

CLCH

CHCL

CLCL CLCX

t

–t

CLCL CHCX

5

Shift Register

t

7

Serial port clock cycle time

505

283

3

12t

ns

XLXL

CLCL

Output data setup to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

10t –133

CLCL

QVXH

XHQX

XHDX

XHDV

2t

CLCL

–80

0

283

10t

–133

CLCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

3. Interfacing the 87C58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.

4. Variable clock is specified for oscillator frequencies greater than 16MHz to 24MHz. For frequencies equal or less than 16MHz, see 16MHz

“AC Electrial Characteristics”, page 3-226.

3-227

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always

‘t’ (= time). The other characters, depending on their positions,

indicate the name of a signal or the logical status of that signal. The

designations are:

P – PSEN

Q – Output data

R – RD signal

t – Time

A – Address

V – Valid

C – Clock

D – Input data

H – Logic level high

W– WR signal

X – No longer a valid logic level

Z – Float

I – Instruction (program memory contents)

L – Logic level low, or ALE

Examples: t

= Time for address valid to ALE low.

=Time for ALE low to PSEN low.

AVLL

t

LLPL

t

LHLL

ALE

t

LLPL

AVLL

t

PLPH

t

LLIV

t

PLIV

PSEN

t

LLAX

t

PXIZ

t

PLAZ

t

PXIX

A0–A7

INSTR IN

A0–A7

PORT 0

PORT 2

t

AVIV

A0–A15

A8–A15

SU00006

Figure 4. External Program Memory Read Cycle

ALE

PSEN

RD

t

WHLH

t

LLDV

t

LLWL

RLRH

t

RHDZ

t

LLAX

t

RLDV

AVLL

t

RLAZ

t

RHDX

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA IN

A0–A7 FROM PCL

INSTR IN

t

AVWL

t

AVDV

P2.0–P2.7 OR A8–A15 FROM DPF

A0–A15 FROM PCH

SU00025

Figure 5. External Data Memory Read Cycle

3-228

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

ALE

t

WHLH

PSEN

t

WLWH

LLWL

WR

t

LLAX

t

WHQX

t

AVLL

QVWX

t

QVWH

A0–A7

FROM RI OR DPL

PORT 0

PORT 2

DATA OUT

A0–A7 FROM PCL

INSTR IN

t

AVWL

P2.0–P2.7 OR A8–A15 FROM DPF

A0–A15 FROM PCH

SU00026

Figure 6. External Data Memory Write Cycle

INSTRUCTION

ALE

0

1

2

3

4

5

6

7

8

t

XLXL

CLOCK

t

XHQX

t

QVXH

OUTPUT DATA

0

1

2

3

4

5

6

7

WRITE TO SBUF

t

XHDX

t

SET TI

VALID

XHDV

INPUT DATA

CLEAR RI

VALID

SET RI

SU00027

Figure 7. Shift Register Mode Timing

V

–0.5

CC

0.7V

CC

0.45V

0.2V

–0.1

t

CHCX

t

CHCL

CLCX

CLCH

t

CLCL

SU00009

Figure 8. External Clock Drive

3-229

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

V

–0.5

CC

V

+0.1V

LOAD

V

–0.1V

TIMING

REFERENCE

POINTS

OH

0.2V

+0.9

–0.1

CC

V

LOAD

CC

–0.1V

LOAD

+0.1V

OL

0.45V

NOTE:

For timing purposes, a port is no longer floating when a 100mV change from

load voltage occurs, and begins to float when a 100mV change from the loaded

AC inputs during testing are driven at V –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.

Timing measurements are made at V min for a logic ‘1’ and V max for a logic ‘0’.

CC

IH

IL

V

/V level occurs. I /I ≥ ±20mA.

OH OL

SU00717

SU00718

Figure 9. AC Testing Input/Output

Figure 10. Float Waveform

45

MAX ACTIVE MODE

I

= 1.50 X FREQ. + 8

CCMAX

40

35

30

25

TYP ACTIVE MODE

0.9 X FREQ. + 2.5

I

mA

CC

20

15

10

5

MAX IDLE MODE

TYP IDLE MODE

4MHz

8MHz

12MHz

16MHz

20MHz

24MHz

FREQ AT XTAL1

SU00046

Figure 11. I vs. Frequency

CC

3-230

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

V

CC

I

CC

V

CC

V

RST

V

CC

P0

EA

P0

EA

RST

(NC)

XTAL2

XTAL1

(NC)

XTAL2

XTAL1

CLOCK SIGNAL

V

SS

SU00719

SU00720

Figure 12. I Test Condition, Active Mode

Figure 13. I Test Condition, Idle Mode

CC

All other pins are disconnected

V

–0.5

CC

0.7V

CC

0.45V

0.2V

–0.1

CC

t

CHCX

t

CHCL

t

CLCX

CLCH

t

CLCL

SU00015

Figure 14. Clock Signal Waveform for I Tests in Active and Idle Modes

CC

t

= t

= 5ns

CHCL

CLCH

V

CC

I

CC

V

CC

V

RST

P0

EA

(NC)

XTAL2

XTAL1

V

SS

SU00016

Figure 15. I Test Condition, Power Down Mode

CC

All other pins are disconnected. V = 2V to 5.5V

CC

3-231

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

shown in Figure 18. The other pins are held at the ‘Verify Code Data’

levels indicated in Table 4. The contents of the address location will

be emitted on port 0. External pull-ups are required on port 0 for this

operation.

EPROM CHARACTERISTICS

The 87C58 is programmed by using a modified Improved

Quick-Pulse Programming algorithm. It differs from older methods

in the value used for V (programming supply voltage) and in the

PP

width and number of the ALE/PROG pulses.

If the 32 byte encryption table has been programmed, the data

presented at port 0 will be the exclusive NOR of the program byte

with one of the encryption bytes. The user will have to know the

encryption table contents in order to correctly decode the verification

data. The encryption table itself cannot be read out.

The 87C58 contains two signature bytes that can be read and used

by an EPROM programming system to identify the device. The

signature bytes identify the device as an 87C58 manufactured by

Philips.

Table 4 shows the logic levels for reading the signature byte, and for

programming the program memory, the encryption table, and the

security bits. The circuit configuration and waveforms for quick-pulse

programming are shown in Figures 16 and 17. Figure 18 shows the

circuit configuration for normal program memory verification.

Program/Verify Algorithms

Any algorithm in agreement with the conditions listed in Table 4, and

which satisfies the timing specifications, is suitable.

Erasure Characteristics

Erasure of the EPROM begins to occur when the chip is exposed to

light with wavelengths shorter than approximately 4,000 angstroms.

Since sunlight and fluorescent lighting have wavelengths in this

range, exposure to these light sources over an extended time (about

1 week in sunlight, or 3 years in room level fluorescent lighting)

could cause inadvertent erasure. For this and secondary effects,

it is recommended that an opaque label be placed over the

window. For elevated temperature or environments where solvents

are being used, apply Kapton tape Fluorglas part number 2345–5, or

equivalent.

Quick-Pulse Programming

The setup for microcontroller quick-pulse programming is shown in

Figure 16. Note that the 87C58 is running with a 4 to 6MHz

oscillator. The reason the oscillator needs to be running is that the

device is executing internal address and program data transfers.

The address of the EPROM location to be programmed is applied to

ports 1 and 2, as shown in Figure 16. The code byte to be

programmed into that location is applied to port 0. RST, PSEN and

pins of ports 2 and 3 specified in Table 4 are held at the ‘Program

Code Data’ levels indicated in Table 4. The ALE/PROG is pulsed

low 5 times as shown in Figure 17.

The recommended erasure procedure is exposure to ultraviolet light

2

(at 2537 angstroms) to an integrated dose of at least 15W-s/cm .

2

Exposing the EPROM to an ultraviolet lamp of 12,000µW/cm rating

To program the encryption table, repeat the 25 pulse programming

sequence for addresses 0 through 1FH, using the ‘Pgm Encryption

Table’ levels. Do not forget that after the encryption table is

programmed, verification cycles will produce only encrypted data.

for 20 to 39 minutes, at a distance of about 1 inch, should be

sufficient.

Erasure leaves the array in an all 1s state.

To program the security bits, repeat the 25 pulse programming

sequence using the ‘Pgm Security Bit’ levels. After one security bit is

programmed, further programming of the code memory and

encryption table is disabled. However, the other security bit can still

be programmed.

Security Bits

With none of the security bits programmed the code in the program

memory can be verified. If the encryption table is programmed, the

code will be encrypted when verified. When only security bit 1 (see

Table 5) is programmed, MOVC instructions executed from external

program memory are disabled from fetching code bytes from the

internal memory, EA is latched on Reset and all further programming

of the EPROM is disabled. When security bits 1 and 2 are

programmed, in addition to the above, verify mode is disabled.

When all three security bits are programmed, all of the conditions

above apply and all external program memory execution is disabled.

Note that the EA/V pin must not be allowed to go above the

PP

maximum specified V level for any amount of time. Even a narrow

PP

glitch above that voltage can cause permanent damage to the

device. The V source should be well regulated and free of glitches

PP

and overshoot.

Program Verification

If security bit 2 has not been programmed, the on-chip program

memory can be read out for program verification. The address of the

program memory locations to be read is applied to ports 1 and 2 as

Encryption Array

32 bytes of encryption array are initially unprogrammed (all 1s).

Trademark phrase of Intel Corporation.

1996 Aug 16

3-232

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

Table 4. EPROM Programming Modes

MODE

Read signature

RST

PSEN

ALE/PROG

EA/V

P2.7

P2.6

P3.7

P3.6

P3.3

PP

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Program code data

Verify code data

0*

1

V

PP

1

Pgm encryption table

Pgm security bit 1

0*

V

PP

V

Pgm security bit 2

NOTES:

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.

2. V = 12.75V ±0.25V.

PP

3. V = 5V±10% during programming and verification.

CC

*

ALE/PROG receives 5 programming pulses (only for user array; 25 pulses for encryption or security bits) while V is held at 12.75V. Each

PP

programming pulse is low for 100µs (±10µs) and high for a minimum of 10µs.

Table 5. Program Security Bits

1, 2

PROGRAM LOCK BITS

SB1

SB2

PROTECTION DESCRIPTION

1

2

U

No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if

programmed.)

P

U

P

MOVC instructions executed from external program memory are disabled from fetching code bytes from

internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled.

3

Same as 2, also verify is disabled.

NOTES:

1. P – programmed. U – unprogrammed.

2. Any other combination of the security bits is not defined.

3-233

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

+5V

V

CC

P0

A0–A7

P1

PGM DATA

+12.75V

1

RST

P3.6

EA/V

PP

5 100µs PULSES TO GROUND

ALE/PROG

PSEN

P3.7

P3.3

0

1

87C54

87C58

XTAL2

P2.7

0

P2.6

P2.0–P2.5

P3.4

4–6MHz

XTAL1

A8–A13

A14

V

SS

SU00183A

Figure 16. Programming Configuration

5 PULSES

1

0

ALE/PROG:

10µs MIN

100µs+10

1

0

SU00179

Figure 17. PROG Waveform

+5V

V

CC

P0

A0–A7

PGM DATA

P1

1

0

RST

P3.6

1

EA/V

PP

ALE/PROG

PSEN

P3.7

P3.3

0

87C54

87C58

XTAL2

P2.7

0

P2.6

P2.0–P2.5

P3.4

4–6MHz

XTAL1

A8–A13

A14

V

SS

SU00185B

Figure 18. Program Verification

3-234

1996 Aug 16

Philips Semiconductors

Preliminary specification

CMOS single-chip 8-bit microcontrollers

87C54/87C58

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

T

amb

= 21°C to +27°C, V = 5V±10%, V = 0V (See Figure 19)

CC SS

SYMBOL

PARAMETER

MIN

MAX

UNIT

V

PP

Programming supply voltage

Programming supply current

Oscillator frequency

12.5

13.0

1

I

PP

50

mA

MHz

1/t

CLCL

4

6

t

Address setup to PROG low

Address hold after PROG

Data setup to PROG low

Data hold after PROG

48t

AVGL

CLCL

48t

GHAX

DVGL

GHDX

EHSH

SHGL

GHSL

GLGH

AVQV

ELQZ

EHQZ

GHGL

P2.7 (ENABLE) high to V

PP

V

PP

V

PP

setup to PROG low

hold after PROG

10

90

µs

PROG width

110

Address to data valid

48t

CLCL

ENABLE low to data valid

Data float after ENABLE

PROG high to PROG low

48t

0

10

µs

NOTE:

1. Not tested.

PROGRAMMING*

VERIFICATION*

ADDRESS

P1.0–P1.7

P2.0–P2.5

P3.4

ADDRESS

(A0 – A14)

t

AVQV

PORT 0

P0.0 – P0.7

(D0 – D7)

DATA IN

DATA OUT

t

DVGL

GHDX

GHAX

t

AVGL

ALE/PROG

t

GLGH

GHGL

t

SHGL

GHSL

LOGIC 1

EA/V

PP

LOGIC 0

t

EHSH

ELQV

EHQZ

P2.7

ENABLE

SU00180

*

FOR PROGRAMMING VERIFICATION SEE FIGURE 16.

FOR VERIFICATION CONDITIONS SEE FIGURE 18.

Figure 19. EPROM Programming and Verification

3-235

1996 Aug 16


型号：	P87C58IFBB
厂家：	NXP
描述：	CMOS single-chip 8-bit microcontrollers CMOS单芯片8位微控制器微控制器
文件：	总21页 (文件大小：162K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

P87C58IFBB [NXP]

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