P87C754EBDDB-T [NXP]
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| 型号： | P87C754EBDDB-T |
| 厂家： | 
NXP |
| 描述： | 暂无描述 比较器 |
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INTEGRATED CIRCUITS
83C754/87C754
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
Preliminary specification
Supersedes data of 1997 Dec 03
IC20 Data Handbook
1998 Apr 23
Philips
Semiconductors
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
DESCRIPTION
PIN CONFIGURATION
The Philips 83C754/87C754 offers many of the advantages of the
80C51 architecture in a small package and at low cost.
RxD/T0/P3.4/D4
TxD/T1/P3.5/D5
ECI/P3.6/D6
INT1/P3.7/D7
RST
1
2
3
4
5
6
7
8
9
28 P3.3/D3
The 8XC754 Microcontroller is fabricated with Philips high-density
CMOS technology. Philips epitaxial substrate minimizes CMOS
latch-up senitivity.
27 P3.2/D2
26 P3.1/D1
25 P3.0/D0
The 8XC754 contains a 4k × 8 ROM (83C754) EPROM (87C754), a
single module PCA, a 256 × 8 RAM, 11 I/O lines, two 16-bit
counter/timers, a two-priority level interrupt structure, a full duplex
serial channel, an on-chip oscillator, and an 8-bit D/A converter.
24 INT0/P1.0/A0/A8
CERAMIC
DUAL
IN-LINE
PACKAGE
AND
PLASTIC
SHRINK
SMALL
X2
23 CEX/P1.1/A1/A9
X1
22
21
V
V
CC
The EPROM version of this device, the 87C754, is available in
plastic one-time programmable (OTP) packages. Once the array
has been programmed, it ifs functionally equivalent to the masked
ROM 83C754. Thus, unless explicitly stated otherwise, all
references made to the 87C754 apply equally to the 83C754.
V
/P1.2
PP
SS
ZIN/A2/A10
20 XYDAC/A7
OUTLINE
PACKAGE
YIN/A3/A11 10
XIN/A4 11
19 ZDAC/ASEL
18 XYSOURCE/A6
17 XYDACBIAS/PGM
16 VREG
The 8XC754 supports two power reduction modes of operation
referred to as the idle mode and the power-down mode.
XYZRAMP/A5 12
AV
SS
AV
CC
13
14
15 DECOUPLE
FEATURES
SU00665D
• Available in erasable quartz lid or One-Time Programmable plastic
packages
• 80C51-based architecture
• Small package sizes – 28-pin SSOP
• Wide oscillator frequency range
• Power control modes:
– Idle mode
– Power-down mode
• 4k × 8 ROM (83C754)
EPROM (87C754)
• 256 × 8 RAM
• Two 16-bit auto reloadable counter/timers
• Single module PCA counter/timer
• Full duplex serial channel
• Boolean processor
• CMOS and TTL compatible
PART NUMBER SELECTION
TEMPERATURE RANGE °C
AND PACKAGE
DRAWING
NUMBER
1
ROM
EPROM
FREQUENCY
3.5 to 16MHz
P83C754EBD DB P87C754EBD DB OTP
0 to +70, 28-pin Shrink Small Outline Package
SOT341-1
NOTE:
1. OTP = One Time Programmable EPROM. UV = UV Erasable EPROM.
2
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
BLOCK DIAGRAM
V
V
CC
SS
RAM ADDR
REGISTER
ROM/
EPROM
RAM
STACK
POINTER
B
ACC
REGISTER
PROGRAM
ADDRESS
REGISTER
AV
AV
SS
CC
DAC
TMP1
TMP2
X
BUFFER
IN
PCON
TCON
ALU
XYZRAMP
DECOUPLE
VREG
XYDACBIAS
XYSOURCE
ZDAC
IE
TH0
TH1
TL0
TL1
ANALOG
PC
INCRE-
MENTER
PSW
INTERRUPT, SERIAL
PORT AND TIMER BLOCKS
XYDAC
PROGRAM
COUNTER
TIMING
AND
RST
DPTR
CONTROL
PORT 1
LATCH
PORT 3
LATCH
PD
OSCILLATOR
PORT 1
DRIVERS
PORT 3
DRIVERS
X1
X2
P1.0–P1.2
P3.0–P3.7
SU00666D
3
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
PIN DESCRIPTION
MNEMONIC
DIP
PIN NO.
TYPE
NAME AND FUNCTION
8
22
I
I
Circuit Ground Potential.
Supply voltage during normal, idle, and power-down operation.
V
SS
V
CC
P1.0–P1.2
21, 23, 24
I/O
Port 1: Port 1 is a 3-bit bidirectional I/O port with internal pull-ups on P1.0 and P1.1. Port 1 pins that
have 1s written to them can be used as inputs. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups (P1.0, P1.1). (See DC Electrical Characteristics: I ).
IL
Port 1 also serves the special function features listed below (Note: P1.0 does not have the strong
pullup that is on for 2 oscillator periods.):
24
23
21
I
O
I
INT0 (P1.0): External interrupt 0.
CEX (P1.1): PCA clock output.
V
PP
(P1.2): Programming voltage input (open drain).
P3.0–P3.7
1–4,
25–28
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to
them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are
externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: I ). Port 3 also functions as the data input for the EPROM memory location to be
IL
programmed (or verified). (Note: P3.5 does not have the strong pullup that is on for 2 oscillator
periods.)
Port 3 also serves the special function as listed below:
3
1
I
I
ECI (P3.6): External PCA clock input.
RxD/T0 (P3.4): Serial port receiver data input.
Timer 0 external clock input.
4
2
I
I
INT1: External interrupt 1.
TxD/T1 (P3.5): Serial port transmitter data.
Timer 1 external clock input.
RST
X1
5
I
Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. After
the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device in the
programming state allowing programming address, data and V to be applied for programming or
PP
verification purposes. The RESET serial sequence must be synchronized with the X1 input. (Note: The
83/87C754 does not have an internal reset resistor.)
7
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1
also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
X2
1
6
O
I
Crystal 2: Output from the inverting oscillator amplifier.
Analog supply voltage and reference input.
Analog supply and reference ground.
ZIN: Input to analog multiplexer.
14
13
9
AV
AV
CC
1
I
SS
ZIN
YIN
XIN
I
10
11
12
15
16
17
I
YIN: Input to analog multiplexer.
I
XIN: Input to analog multiplexer.
XYZRAMP
DECOUPLE
VREG
O
O
O
O
XYZRAMP: Provides a low impedance pulldown to V under S/W control.
SS
Decouple: Output from regulated supply for connection of decoupling capacitors.
VREG: Provides regulated analog supply output.
XYDACBIAS
XYDACBIAS: Provides source voltage for bias of external circuitry.
– Input which specifies verify mode (output enable) or the program mode.
/PGM = 1 output enabled (verify mode).
/PGM = 0 program mode.
XYSOURCE
ZDAC
18
19
O
O
XYSOURCE: Provides source voltage from regulated analog supply.
ZDAC: Switchable outp from the internal DAC.
ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
XYDAC
20
O
XYDAC: Non-switchable output from the internal DAC.
NOTE:
1. AV (reference ground) must be connected to 0V (ground). AV (reference input) cannot differ from V by more than ±0.2V, and must be
SS
CC
CC
in the range 4.5V to 5.5V.
4
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
OSCILLATOR CHARACTERISTICS
X1 and X2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator.
STANDARD SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit and receive
simultaneously. It is also receive-buffered, meaning it can
commence reception of a second byte before a previously received
byte has been read from the register. (However, if the first byte still
has not been read by the time reception of the second byte is
complete, one of the bytes will be lost.) The serial port receive and
transmit registers are both accessed at Special Function Register
SBUF. Writing to SBUF loads the transmit register, and reading
SBUF accesses a physically separate receive register.
To drive the device from an external clock source, X1 should be
driven while X2 is left unconnected. There are no requirements on
the duty cycle of the external clock signal, because the input to the
internal clock circuitry is through a divide-by-two flip-flop. However,
minimum and maximum high and low times specified in the data
sheet must be observed.
The serial port can operate in 4 modes:
IDLE MODE
Mode 0: Serial data enters and exits through RxD. TxD outputs the
shift clock. 8 bits are transmitted/received (LSB first). The
baud rate is fixed at 1/12 the oscillator frequency.
The 8XC754 includes the 80C51 power-down and idle mode
features. In idle mode, the CPU puts itself to sleep while all of the
on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt
service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset. Upon
powering-up the circuit, or exiting from idle mode, sufficient time
must be allowed for stabilization of the internal analog reference
voltages before a D/A conversion is started.
Mode 1: 10 bits are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), and a stop bit
(1). On Receive, the stop bit goes into RB8 in Special
Function Register SCON. The baud rate is variable.
Mode 2: 11 bits are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On Transmit,
the 9th data bit (TB8 in SCON) can be assigned the value
of 0 or 1. Or, for example, the parity bit (P, in the PSW)
could be moved into TB8. On Receive, the 9th data bit
goes into RB8 in Special Function Register SCON, while
the stop bit is ignored. The baud rate is programmable to
either 1/32 or 1/64 the oscillator frequency.
Special Function Registers
The special function registers (directly addressable only) contain all
of the 8XC754 registers except the program counter and the four
register banks. Most of the special function registers are used to
control the on-chip peripheral hardware. Other registers include
arithmetic registers (ACC, B, PSW), stack pointer (SP) and data
pointer registers (DPH, DPL). Twelve of the SFRs are bit
addressable.
Mode 3: 11 its are transmitted (through TxD) or received (through
RxD): a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). In fact,
Mode 3 is the same as Mode 2 in all respects except baud
rate. the baud rate in Mode 3 is variable.
Data Pointer
In all four modes, transmission is initiated by any instruction that
uses SBUF as a destination register. Reception is initiated in Mode 0
by the condition RI = 0 and REN = 1. Reception is initiated in the
other modes by the incoming start bit if REN = 1.
The data pointer (DPTR) consists of a high byte (DPH) and a low
byte (DPL). In the 80C51 this register allows the access of external
data memory using the MOVX instruction. Since the 83C754 does
not support MOVX or external memory accesses, this register is
generally used as a 16-bit offset pointer of the accumulator in a
MOVC instruction. DPTR may also be manipulated as two
independent 8-bit registers.
Multiprocessor Communications
Modes 2 and 2 have a special provision for multiprocessor
communications. In these modes, 9 data bits are received. The 9th
one goes into RB8. Then comes a stop bit. The port can be
programmed such that when the stop bit is received, the serial port
interrupt will be activated only if RB8 = 1. This feature is enabled by
setting bit SM2 in SCON. A way to use this feature in multiprocessor
systems is as follows:
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. The control
bits for the reduced power modes are in the special function register
PCON.
When the master processor wants to transmit a block of data to one
of several slaves, it first sends out an address byte which identifies
the target slave. An address byte differs from a data byte in that the
9th bit is 1 in an address byte and 9 in a data byte. With SM2 = 1,
no slave will be interrupted by a data byte. An address byte,
however, will interrupt all slaves, so that each slave can examine the
received byte and see if it is being addressed. The addressed slave
will clear its SM2 bit and prepare to receive the data bytes that will
be coming. The slaves that were not being addressed leave their
SM2s set, and go on about their business, ignoring the coming data
bytes.
Table 1. External Pin Status During Idle and
Power-Down Modes
MODE
Port 1
Data
Port 3
Data
Idle
Power-down
Data
Data
SM2 has no effect in Mode 0, and in Mode 1 can be used to check
the validity of the stop bit. In a Mode 1 reception, if SM2 = 1, the
receive interrupt will not be activated unless a valid stop bit is
received.
5
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
Serial Port Control Register
Using Timer 1 to Generate Baud Rates
The serial port control and status register is the Special Function
Register SCON, shown in Figure 1. This register contains not only
the mode selection bits, but also the 9th data bit for transmit and
receive (TB8 and RB8), and the serial port interrupt bits (TI and RI).
When Timer 1 is used as the baud rate generator, the baud rates in
Modes 1 and 3 are determined by the Timer 1 overflow rate and the
value of SMOD as follows:
2SMOD
32
Mode 1, 3 Baud Rate +
(Timer 1 Overflow Rate)
Baud Rates
The Timer 1 interrupt should be disabled in this application. The
Timer itself can be configured for either “timer” or “counter”
operation, and in any of its 3 running modes. In the most typical
applications, it is configured for “timer” operation, in the auto-reload
mode (high nibble of TMOD = 0010B). In that case the baud rate is
given by the formula:
The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Oscillator
Frequency / 12. The baud rate in Mode 2 depends on the value of
bit SMOD in Special function Register PCON. If SMOD = 0 (which is
the value on reset), the baud rate is 1/64 the oscillator frequency.
If SMOD = 1, the baud rate is 1/32 the oscillator frequency.
2SMOD
64
2SMOD
32
Oscillator Frequency
12 [256 * (TH1)]
Mode 2 Baud Rate +
(Oscillator Frequency)
Mode 1, 3 Baud Rate +
In the 8XC754, the baud rates in Modes 1 and 3 are determined by
the Timer 1 overflow rate.
One can achieve very low baud rates with Timer 1 by leaving the
Timer 1 interrupt enabled, and configuring the Timer to run as a
16-bit timer (high nibble of TMOD = 0001B), and using the Timer 1
interrupt to do a 16-bit software reload. Figure 2 lists various
commonly used baud rates and how they can be obtained from
Timer 1.
MSB
LSB
SM0 SM1 SM2 REN TB8 RB8
TI
RI
Where SM0, SM1 specify the serial port mode, as follows:
SM0 SM1 Mode Description Baud Rate
/ 12
0
0
1
1
0
1
0
1
0
1
2
3
shift register
8-bit UART
9-bit UART
9-bit UART
f
OSC
variable
/64 or f
f
/32
OSC
OSC
variable
SM2
Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then Rl will not be
activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1 then RI will not be activated if a valid stop bit was not
received. In Mode 0, SM2 should be 0.
REN
TB8
RB8
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In Modes 2 and 3, is the 9th data bit that was received. In Mode 1, it SM2=0, RB8 is the stop bit that was received. In Mode 0,
RB8 is not used.
TI
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other
modes, in any serial transmission. Must be cleared by software.
RI
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other
modes, in any serial reception (except see SM2). Must be cleared by software.
SU00120
Figure 1.
Timer 1
Baud Rate
f
SMOD
OSC
C/T
Mode
Reload Value
Mode 0 Max: 1.67MHz
Mode 2 Max: 625k
Mode 1, 3 Max: 104.2k
20MHz
20MHz
20MHz
11.059MHz
11.059MHz
11.059MHz
11.059MHz
11.059MHz
11.986MHz
6MHz
X
1
1
1
0
0
0
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
X
X
2
2
2
2
2
2
2
2
1
X
X
FFH
FDH
FDH
FAH
F4H
E8H
1DH
72H
FEEBH
19.2k
9.6k
4.8k
2.4k
1.2k
137.5
110
110
12MHz
Figure 2. Timer 1 Generated Commonly Used Baud Rates
6
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
DIFFERENCES BETWEEN THE 8XC754 AND THE
80C51
Analog Section
The analog section of the 8XC754, shown in Figure 3, consists of
four major elements: a bandgap referenced voltage regulator, an
8-bit DAC, an input multiplexer and comparator, and a low
impedance pulldown device.
Program Memory
On the 8XC754, program memory is 4096 bytes long and is not
externally expandable, so the 80C51 instructions MOVX, LJMP, and
LCALL are not implemented. If these instructions are executed, the
appropriate number of instruction cycles will take place along with
external fetches; however, no operation will take place. The LJMP
may not respond to all program address bits. The only fixed
locations in program memory are the addresses at which execution
is taken up in response to reset and interrupts, which are as follows:
Program Memory
The bandgap voltage regulator uses the AV pin as its supply and
CC
produces a regulated output on the VREG pin. The bandgap
reference is enabled/disabled by AC0. The regulator also supplies
the analog supply voltage for the DAC. The regulator may be
switched on/off by means of the AC1 bit in the analog control
register (ACON0). The regulator output may also be supplied to the
XYDACBIAS and XYSOURCE pins by means of bits AC3 and AC4,
respectively. The DECOUPLE pin is provided for decoupling the
regulator output.
Event
Reset
Address
000
External INT0
Timer 0
External INT1
PCA
003
00B
013
01B
The DAC is an 8-bit device and its output appears on the XYDAC
pin. In addition, the DAC output may also be routed to the ZDAC pin
by means of bit AC6 in the ACON0 register. The DAC output is not
buffered, so external load impedances should be taken into
consideration when using either of these outputs.
SIO/TF1
023
A 3-input multiplexer is provided, whose output is connected to the
positive reference of a comparator. The multiplexer output is
controlled by bits MUX2:0 of ACON1. A bandgap reference supplies
the negative reference of the comparator. The output of the
comparator may be used the trigger the capture input of PCA
module.
Memory Organization
The 8XC754 manipulates operands in three memory address
spaces. The first is the program memory space which contains
program instructions as well as constants such as look-up tables.
The program memory space contains 4k bytes in the 8XC754.
The second memory space is the data memory array which has a
logical address space of 256 bytes.
A low impedance pulldown is supplied at the XYZRAMP pin and is
controlled by bit AC5 of ACON0.
The third memory space is the special function register array having
a 128-byte address space (80H to FFH). Only selected locations in
this memory space are used (see Table 2). Note that the
architecture of these memory spaces (internal program memory,
internal data memory, and special function registers) is identical to
the 80C51, and the 8XC754 varies only in the amount of memory
physically implemented.
Interrupt Subsystem—Fixed Priority
The interrupt structure is a seven-source, two-level interrupt system.
Simultaneous interrupt conditions are resolved by a single-level,
fixed priority as follows:
Highest priority:
Pin INT0
Timer flag 0
Pin INT1
PCA
The 8XC754 does not directly address any external data or program
memory spaces. For this reason, the MOVX instructions in the
80C51 instruction set are not implemented in the 83C754, nor are
the alternate I/O pin functions RD and WR.
Serial I/O – TF1
Lowest priority:
The vector addresses are as follows:
I/O Ports
Source
INT0
Vector Address
0003H
The I/O pins provided by the 8XC754 consist of port 1 and port 3.
TF0
INT1
PCA
SIO/TF1
000BH
0013H
001BH
0023H
Port 1
Port 1 is a 3-bit bidirectional I/O port and includes alternate functions
on some pins of this port. P1.1 is provided with internal pullups while
the remaining pins (P1.0 and P1.2) are an open drain output
structure. The alternate functions for port 1 are:
Interrupt Enable Register
INT0 – External interrupt 0.
PCAOUT – PCA clock output
MSB
LSB
EX0
EA
–
–
ES/T1
EC
EX1
ET0
V
PP
– External programming voltage.
Port 3
Position
IE.7
Symbol
EA
Function
Global interrupt disable when EA = 0
Port 3 is an 8-bit bidirectional I/O port structure. P3.5 is open drain.
The alternate functions for port 3 are:
IE.6
–
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
–
RxD – Serial port receiver data input.
T1 – Timer 1 external clock input.
INT1 – External interrupt 1.
TxD – Serial port transmitter data.
T0 – Timer 0 external clock input.
ECI – PCA external clock input.
ES/T1
EC
EX1
ET0
EX0
Serial port/Timer Flag 1
PCA interrupt
External interrupt 1
Timer 0 overflow
External interrupt 0
7
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
AV
CC
BANDGAP REF*
AC1
DECOUPLE
VREG
AC2
AC3
20K
10K
XYDACBIAS
AC4
XYSOURCE
XYDAC
1K
DCON 7:0 (84H)
AC6
ZDAC
ZIN
YIN
XIN
AC7
ANALOG
MUX
TO PCA TRIGGER
BANDGAP REF
EXT
MUX0
MUX1
MUX2
XYZRAMP
AC5
*ENABLED/DISABLED BY AC0
SU00765A
Figure 3. Analog Section
ALTERNATE
OUTPUT
FUNCTION
READ
LATCH
V
DD
INTERNAL*
PULL-UP
INT. BUS
D
Q
Q
PIN
LATCH
WRITE TO
LATCH
CL
READ
PIN
ALTERNATE INPUT
FUNCTION
*PINS LISTED AS OPEN DRAIN WILL NOT HAVE THIS PULLUP
SU00671
Figure 4. Typical Port Bit Latches and I/O Buffers
8
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
Table 2.
8XC754 Special Function Registers
DIRECT
ADDRESS
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB
RESET
VALUE
SYMBOL
DESCRIPTION
LSB
E0
ACC*
Accumulator
E0H
A0H
C0H
F0H
FEH
E7
E6
AC6
–
E5
AC5
–
E4
AC4
–
E3
AC3
TSI
F3
E2
AC2
MUX2
F2
E1
AC1
MUX1
F1
00H
ACON0*
ACON1*
B*
Analog Control 0
Analog Control 1
B register
AC7
–
AC0
MUX0
F0
F7
F6
F5
F4
00H
CCAPH#
PCA Module
Capture High
CCAPL#
CCAPM#
PCA Module
Capture Low
EEH
DEH
PCA Module Mode
–
ECOM CAPP CAPN
MAT
DB
TOG
DA
PWM
D9
ECCF
D8
x0000000B
00x00000B
DF
DE
CR
DD
–
DC
PCA Counter
Control
CCON*#
D8H
CF
CCF4
–
–
–
–
CH#
CL#
PCA Counter High
PCA Counter Low
F9H
E9H
00H
00H
CMOD#
DCON
DPTR:
PCA Counter Mode
DAC Control
D9H
84H
CODL WDTE
–
–
–
CPS1
CPS0
ECF
00xxx000B
Data pointer
(2 bytes)
DPL
DPH
Data pointer low
Data pointer high
82H
83H
00H
00H
AF
EA
AF
–
AE
–
AD
–
AC
ES/T1
AC
AB
EC
AB
PPC
83
AA
EX1
AA
A9
ET0
A9
A8
EX0
A8
IE*#
IP*
Interrupt Enable
Interrupt Priority
A8H
B8H
00H
AE
–
AD
–
PS/T1
84
PX1
82
PT0
81
PX0
80
x0000000B
xxx11111B
–
–
–
XYSOURCE
–
XYZRAMP
–
P1*#
Port 1
90H
B0H
87H
–
–
–
–
–
ZIN
–
P3*#
Port 3
INT1
ECI
TxD
–
RxD
POF
D4
–
SMOD1 SMOD0
PCON
Power control
GF1
D3
RS0
GF0
D2
PD
IDL
00xxxx00B
00H
D7
CY
D6
AC
D5
F0
D1
D0
PSW*
Program status word
D0H
RS1
OV
–
P
SBUF
SP
Serial Data Buffer
Stack pointer
99H
81H
xxxxxxxxB
07H
9F
SM0
8F
9E
SM1
8E
9D
SM2
8D
9C
REN
8C
9B
TB8
8B
9A
RB8
8A
99
TI
98
RI
SCON*
TCON*
Serial Control
Timer Control
98H
88H
00H
00H
89
IE0
88
IT0
TF1
TR1
TF0
TR0
IE1
IT1
TH0
TH1
TL0
TL1
Timer High 0
Timer High 1
Timer Low 0
Timer Low 1
8CH
8DH
8AH
8BH
00H
00H
00H
00H
TMOD
Timer Mode
89H
GATE
C7
C/T
C6
M1
C5
M0
C4
GATE
C3
C/T
C2
M1
C1
M0
C0
00H
*
#
SFRs are bit addressable.
SFRs are modified from or added to the 80C51 SFRs.
9
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
a match between the PCA counter and the module’s
capture/compare register.
COUNTER/TIMER
The 8XC754 counter/timers are designated Timer 0 and 1. They are
identical to the 80C51 counter/timers. (Timer 1 shares its interrupt
with the serial port.)
The next two bits CAPN (CCAPM.4) and CAPP (CCAPM.5)
determine the edge that a capture input will be active on. The CAPN
bit enables the negative edge, and the CAPP bit enables the
positive edge. If both bits are set both edges will be enabled and a
capture will occur for either transition. The last bit in the register
ECOM (CCAPM.6) when set enables the comparator function.
Figure 11 shows the CCAPM settings for the various PCA functions.
Programmable Counter Array (PCA)
The Programmable Counter Array is a special Timer that has one
16-bit capture/compare module associated with it. The module can
be programmed to operate in one of four modes: rising and/or falling
edge capture, software timer, high-speed output, or pulse width
modulator. The basic PCA configuration is shown in Figure 5.
There are two additional registers associated with the PCA module.
They are CCAPH and CCAPL and these are the registers that store
the 16-bit count when a capture occurs or a compare should occur.
When the module is used in the PWM mode these registers are
used to control the duty cycle of the output.
The PCA timer can be programmed to run at: 1/12 the oscillator
frequency, 1/4 the oscillator frequency, the Timer 0 overflow, or the
input on the ECI pin (P3.1). The timer count source is determined
from the CPS1 and CPS0 bits in the CMOD SFR as follows (see
Figure 8):
PCA Capture Mode
To use the PCA module in the capture mode, either one or both of
the CCAPM bits CAPN and CAPP must be set. The external CEX
input for the module is sampled for transition. When a valid transition
occurs, the PCA hardware loads the value of the PCA counter
registers (CH and CL) into the module’s capture registers (CCAPL
and CCAPH). If the CCF bit for the module in the CCON SFR and
the ECCF bit in the CCAPM SFR are set, then an interrupt will be
generated. Refer to Figure 12.
CPS1 CPS0 PCA Timer Count Source
0
0
1
1
0
1
0
1
1/12 oscillator frequency
1/4 oscillator frequency
Timer 0 overflow
External Input at ECI pin
In the CMOD SFR are three additional bits associated with the PCA.
They are CIDL which allows the PCA to stop during idle mode,
WDTE which enables or disables the watchdog function, and ECF
which when set causes an interrupt and the PCA overflow flag, CF
(in the CCON SFR) to be set when the PCA timer overflows. These
functions are shown in Figure 6.
16-bit Software Timer Mode
The PCA modules can be used as software timers by setting both
the ECOM and MAT bits in the module’s CCAPM register. The PCA
timer will be compared to the module’s capture registers and when a
match occurs an interrupt will occur if the CCF (CCON SFR) and the
ECCF (CCAPM SFR) bits for the module are both set (see
Figure 13).
The watchdog timer function is implemented in module 4 as
implemented in other parts that have a PCA that are available on the
market.
The CCON SFR contains the run control bit for the PCA and the
flags for the PCA timer (CF) and module (refer to Figure 9). To run
the PCA the CR bit (CCON.6) must be set by software. The PCA is
shut off by clearing this bit. The CF bit (CCON.7) is set when the
PCA counter overflows and an interrupt will be generated if the ECF
bit in the CMOD register is set, The CF bit can only be cleared by
software. Bit 4 of the CCON register is the flag for the module and is
set by hardware when either a match or a capture occurs. This flag
can only be cleared by software. The PCA interrupt system shown in
Figure 7.
High Speed Output Mode
In this mode the CEX output associated with the PCA module will
toggle each time a match occurs between the PCA counter and the
module’s capture registers. To activate this mode the TOG, MAT,
and ECOM bits in the module’s CCAPM SFR must be set (see
Figure 14).
Pulse Width Modulator Mode
The PCA module can be used as a PWM output. Figure 15 shows
the PWM function. The frequency of the output depends on the
source for the PCA timer. The duty cycle of the module is
independently variable using the module’s capture register CCAPL.
When the value of the PCA CL SFR is less than the value in the
module’s CCAPL SFR, the output will be low, when it is equal to or
greater than the output will be high. When CL overflows from FF to
00, CCAPL is reloaded with the value in CCAPH. This allows
updating the PWM without glitches. The PWM and ECOM bits in the
module’s CCAPM register must be set to enable the PWM mode.
The CCAPM register contains the bits that control the mode in which
the module will operate. The ECCF bit enables the CCF flag in the
CCON SFR to generate an interrupt when a match or compare
occurs in the associated module. PWM (CCAPM.1) enables the
pulse width modulation mode. The TOG bit (CCAPM.2) when set
causes the CEX output associated with the module to toggle when
there is a match between the PCA counter and the module’s
capture/compare register. The match bit MAT (CCAPM.3), when set,
will cause the CCF bit in the CCON register to be set when there is
16 BITS
16 BITS
PCA TIMER/COUNTER
P1.1/CEX
PCA MODULE
TIME BASE FOR PCA MODULES
MODULE FUNCTIONS:
16-BIT CAPTURE
16-BIT TIMER
16-BIT HIGH SPEED OUTPUT
8-BIT PWM
WATCHDOG TIMER
SU00672B
Figure 5. Programmable Counter Array (PCA)
10
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
TO PCA
MODULES
OSC/12
OVERFLOW
OSC/4
INTERRUPT
CH
CL
16–BIT UP COUNTER
TIMER 0
OVERFLOW
EXTERNAL INPUT
(P3.6/ECI)
00
01
10
11
DECODE
IDLE
CMOD
(D9H)
CIDL
CF
WDTE
––
––
––
––
––
CPS1
––
CPS0
ECF
––
CCON
(D8H)
CR
CCF
––
SU00673B
Figure 6. PCA Timer/Counter
CCON
(D8H)
CF
CR
––
CCF
––
––
––
––
PCA TIMER/COUNTER
IE.7
EA
IE.6
EC
TO
INTERRUPT
PRIORITY
DECODER
PCA MODULE
CMOD.0
ECF
CCAPM ECCFn
SU00674A
Figure 7. PCA Interrupt System
11
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
CMOD Address = OD9H
Reset Value = 00XX X000B
Bit Addressable
CIDL
WDTE
–
–
–
CPS1
CPS0
ECF
Bit:
Function
7
6
5
4
3
2
1
0
Symbol
CIDL
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
WDTE
–
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module. WDTE = 1 enables it.
Not implemented, reserved for future use.*
CPS1
CPS0
PCA Count Pulse Select bit 1.
PCA Count Pulse Select bit 0.
CPS1
CPS0
Selected PCA Input**
0
0
1
1
0
1
0
1
0
1
2
3
Internal clock, f
÷ 12
÷ 4
OSC
Internal clock, f
OSC
Timer 0 overflow
External clock at ECI/P3.1 pin (max. rate = f
÷ 8)
OSC
ECF
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
NOTE:
*
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
**
f
= oscillator frequency
OSC
SU00675A
Figure 8. CMOD: PCA Counter Mode Register
CCON Address = OD8H
Reset Value = 00X0 0000B
Bit Addressable
CF
CR
––
CCF
––
––
––
––
Bit:
7
6
5
4
3
2
1
0
Symbol
CF
Function
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
CR
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
–
Not implemented, reserved for future use*.
CCF
PCA Module interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
NOTE:
*
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU00676A
Figure 9. CCON: PCA Counter Control Register
12
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
CCAPMn Address
CCAPM
0DEH
Reset Value = X000 0000B
Not Bit Addressable
––
ECOM
CAPP
CAPN
MAT
TOG
PWM
ECCF
Bit:
7
6
5
4
3
2
1
0
Symbol
Function
–
Not implemented, reserved for future use*.
ECOM
CAPP
CAPN
MAT
Enable Comparator. ECOM = 1 enables the comparator function.
Capture Positive, CAPP = 1 enables positive edge capture.
Capture Negative, CAPN = 1 enables negative edge capture.
Match. When MAT = 1, a match of the PCA counter with this module’s compare/capture register causes the CCF bit in
CCON to be set, flagging an interrupt.
TOG
Toggle. When TOG = 1, a match of the PCA counter with this module’s compare/capture register causes the CEX pin
to toggle.
PWM
Pulse Width Modulation Mode. PWM4 = 1 enables the CEX pin to be used as a pulse width modulated output.
Enable CCF interrupt. Enables compare/capture flag CCF in the CCON register to generate an interrupt.
ECCF
NOTE:
*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new
bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU00677A
Figure 10. CCAPM: PCA Modules Compare/Capture Registers
–
X
X
X
X
X
X
X
X
ECOM
CAPP
CAPN
MAT
TOG
PWM
ECCF
MODULE FUNCTION
0
X
X
X
1
1
1
1
0
1
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
X
0
0
0
0
0
0
1
0
0
X
X
X
X
X
0
No operation
16-bit capture by a positive-edge trigger on CEX
16-bit capture by a negative trigger on CEX
16-bit capture by a transition on CEX
16-bit Software Timer
16-bit High Speed Output
8-bit PWM
X
Watchdog Timer
Figure 11. PCA Module Modes (CCAPM Register)
CF
CR
––
CCF
––
––
––
––
CCON
(D8H)
PCA INTERRUPT
PCA TIMER/COUNTER
(TO CCF)
CH
CL
CEX
CAPTURE
CCAPH
CCAPL
––
ECOM
0
CAPP
CAPN
MAT
0
TOG
0
PWM
0
ECCF
CCAPM
SU00678A
Figure 12. PCA Capture Mode
13
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
CCON
(D8H)
CF
CR
––
CCF
––
––
––
––
WRITE TO
CCAPH
RESET
PCA INTERRUPT
CCAPH
CCAPL
WRITE TO
CCAPL
(TO CCF)
0
1
ENABLE
MATCH
16–BIT COMPARATOR
CH
CL
PCA TIMER/COUNTER
CCAPM
––
ECOM
CAPP
0
CAPN
0
MAT
TOG
0
PWM
0
ECCF
SU00679A
Figure 13. PCA Compare Mode
CCON
(D8H)
CF
CR
––
CCF
––
––
––
––
WRITE TO
CCAPH
RESET
PCA INTERRUPT
CCAPH
CCAPL
WRITE TO
CCAPL
(TO CCF4)
0
1
MATCH
ENABLE
16–BIT COMPARATOR
TOGGLE
CEX
CH
CL
PCA TIMER/COUNTER
––
ECOM
CAPP
0
CAPN
0
MAT
TOG
1
PWM
0
ECCF
CCAPM
SU00680A
Figure 14. PCA High Speed Output Mode
14
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
CCAPH
CCAPL
0
CL < CCAPL
ENABLE
8–BIT
CEX
COMPARATOR
CL >= CCAPL
1
CL
OVERFLOW
PCA TIMER/COUNTER
––
ECOM
CAPP
0
CAPN
MAT
0
TOG
0
PWM
ECCF
0
CCAPM
0
SU00681A
Figure 15. PCA PWM Mode
CMOD
(D9H)
CIDL
WDTE
––
––
––
CPS1
CPS0
ECF
WRITE TO
CCAPH
RESET
CCAPH
CCAPL
WRITE TO
CCAPL
0
1
ENABLE
MATCH
16–BIT COMPARATOR
RESET
CH
CL
PCA TIMER/COUNTER
CCAPM
(DEH)
––
ECOM
CAPP
0
CAPN
0
MAT
1
TOG
X
PWM
ECCF
X
0
SU00682A
Figure 16. PCA Watchdog Timer
15
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
1, 3, 4
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Storage temperature range
Voltage from V to V
RATING
UNIT
°C
V
–65 to +150
–0.5 to +6.5
CC
SS
Voltage from any pin to V (except V
SS
)
–0.5 to V
CC
+ 0.5
V
PP
Power dissipation
1.0
W
Voltage from V pin to V
–0.5 to + 13.0
V
PP
SS
DC ELECTRICAL CHARACTERISTICS
4
T
amb
= 0°C to +70°C, AV = 5V ±5, AV = 0V
CC SS
V
CC
= 5V ± 10%, V = 0V
SS
4
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
1
MIN
TYP
MAX
I
Supply current (see Figure 19)
CC
Inputs
V
Input low voltage, port 1, 3
Input high voltage, port 1, 3
Input high voltage, X1, RST
–0.5
V
V
V
0.2V –0.1
CC
IL
V
V
0.2V +0.9
V
CC
CC
+0.5
+0.5
IH
CC
0.7V
V
IH1
CC
Outputs
2
V
V
V
Output low voltage, port 3
I
I
= 1.6mA
= 3.2mA
0.45
0.45
V
V
OL
OL
2
Output low voltage, port 1.0, 1.1, 1.2
Output high voltage, ports 3, 1.0, 1.1
Input leakage current, port 1, 3, RST
Logical 0 input cirrent, ports 1 and 3
Pin capacitance
OL1
OH
OL
I
= –60µA,
2.4
V
OH
I
LI
I
IL
0.45 < V < V
CC
+10
–50
10
µA
µA
pF
IN
V
= 0.45V
IN
C
Test freq = 1MHz,
IO
T
amb
= 25°C
5
I
Power-down current
V
V
= 2 to 5.5V
= 2 to 6.0V
(83C754)
50
13.0
50
µA
V
PD
CC
CC
V
V
PP
program voltage (87C754 only)
V
CC
= 0V
12.5
PP
SS
V
amb
= 5V±10%
= 21°C to 27°C
T
I
PP
Program current (87C754 only)
V
= 13.0V
mA
PP
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum I per port pin:
10mA
26mA
67mA
OL
Maximum I per 8-bit port:
OL
Maximum total I for all outputs:
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
OL
OL
test conditions.
3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
4. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless otherwise
SS
noted.
5. Power-down I is measured with all output pins disconnected; port 0 = V ; X2, X1 n.c.; RST = V .
CC
CC
SS
6. I is measured with all output pins disconnected; X1 driven with t
, t
= 5ns, V = V + 0.5V, V = V – 0.5V; X2 n.c.;
CC
CLCH CHCL IL SS IH CC
RST = port 0 = V . I will be slightly higher if a crystal oscillator is used.
CC CC
7. Idle I is measured with all output pins disconnected; X1 driven with t
, t
= 5ns, V = V + 0.5V, V = V – 0.5V; X2 n.c.;
CC
CLCH CHCL IL SS IH CC
port 0 = V ; RST = V
.
CC
SS
8. Load capacitance for ports = 80pF.
16
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
ANALOG SECTION ELECTRICAL CHARACTERISTICS
4
T
amb
= 0°C to +70°C, AV = 5V ±5, AV = 0V
CC SS
V
CC
= 5V ± 10%, V = 0V
SS
4
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
1
MIN
TYP
MAX
Analog Inputs (D/A guaranteed only with quartz window covered.)
AV
Analog supply voltage
Sensor resistor
4.5
330
–
–
–
5.5
3K
1.5
10
V
Ω
CC
IAV
AC0 = 0 IC only
AC0 = 1
0.88
–
mA
µA
CC
–
Regulator
VREG
3.6
13
3
3.8
–
4.0
55
–
V
IVREG
mA
µF
Ω
CDECOUPLE
RDSONQ1
ILEAKAGEQ1
ILEAKAGEQ2
PSRR
Stability requirement
10
7
–
–
–
TBD
TBD
–40
–
–
µA
µA
dB
mV
ms
–
–
100Hz
–
–
VREGREJ
TVREG
VREGrejectionof1VoltAV stepchange
–100
–
100
5
CC
VREG turn on time
Q1 off, 330Ω sensor
2
MUX and Comparator
Comparator trip point
1.14
–
1.26
50
1.38
–
V
Comparator delay input
Comparator delay change
MUX impedance
0.04V/µs
ns
ns
kΩ
µA
AV 4.5 to 5.5V
–10
–
2
10
–
CC
1
ILEAKAGEMUX
–
TBD
–
Digital-to-Analog Conversion
ZDAC, XYDAC monotonicity
0
–
–
10
40
1
–
–
bits
kΩ
Ω
ZDAC, XYDAC impedance
DAC selection switch impedance
DAC settling
–
–
–
–
µs
Ω
ZDAC switch impedance
ZDAC switch impedance change
ZDAC switch leakage
–
50
–
–
AV 4.5 to 5.5V
–20
–
20
–
Ω
CC
TBD
µA
Switches
XYZRAMP impedance
–
–25
–
25
–
100
25
Ω
Ω
XYZRAMP impedance change
XYZRAMP leakage
AV 4.5 to 5.5V
CC
TBD
1.5
6
–
µA
µs
ns
ns
Ω
XYZRAMP discharge to 1LSB (1.6mV)
XYZRAMP delay turn on time
XYZRAMP start time change
XYDACBIAS impedance
XYDACBIAS leakage
–
10
–
50
AV 4.5 to 5.5V
–10
–
–
10
CC
7
13
–
TBD
130
150
–
–
µA
ns
Ω
XYDACBIAS switching time
XYSOURCE impedance
–
1000
300
100
–
–
XYSOURCE impedance change
XYSOURCE leakage
AV 4.5 to 5.5V
–100
–
Ω
CC
TBD
30
µA
ns
XYSOURCE switching time
–
500
17
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
AC ELECTRICAL CHARACTERISTICS
4, 8
T
amb
= 0°C to +70°C, V
= 5V ±10%, V = 0V
CC
SS
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
1/t
PARAMETER
MIN
MAX
MIN
MAX
UNIT
Oscillator frequency
3.5
16
MHz
CLCL
External Clock (Figure 17)
t
t
t
t
High time
Low time
Rise time
Fall time
20
20
20
20
ns
ns
ns
ns
CHCX
CLCX
CLCH
CHCL
20
20
20
20
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal.
The designations are:
C – Clock
D – Input data
H – Logic level high
L – Logic level low
Q – Output data
T – Time
V – Valid
X – No longer a valid logic level
Z – Float
t
V
–0.5
CLCX
CC
0.2 V + 0.9
CC
0.2 V – 0.1
CC
t
0.45V
CHCX
t
t
CLCH
CHCL
t
CLCL
SU00297
Figure 17. External Clock Drive
V
–0.5
CC
0.2 V + 0.9
CC
0.2 V – 0.1
CC
0.45V
SU00307
Figure 18. AC Testing Input/Output
18
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
6
MAX ACTIVE I
CC
22
20
18
16
14
6
12
10
8
I
mA
TYP ACTIVE I
CC
CC
6
7
MAX IDLE I
CC
4
2
7
TYP IDLE I
CC
4MHz
8MHz
FREQ
12MHz
16MHz
SU00308
Figure 19. I vs. FREQ
CC
Maximum I values taken at V = 5.5V and worst case temperature.
CC
CC
Typical I values taken at V = 5.0V and 25°C.
CC
CC
Notes 6 and 7 refer to AC Electrical Characteristics.
ROM CODE SUBMISSION
When submitting ROM code for the 83C754, the following must be specified:
1. 4k byte user ROM data
2. 64 byte ROM encryption key
3. ROM security bits.
ADDRESS
CONTENT
DATA
BIT(S)
7:0
COMMENT
0000H to 0FFFH
1000H to 101FH
User ROM Data
KEY
7:0
ROM Encryption Key
FFH = no encryption
1020H
1020H
SEC
SEC
0
1
ROM Security Bit 1
0 = enable security
1 = disable security
ROM Security Bit 2
0 = enable security
1 = disable security
Security Bit 1: When programmed, this bit has two effects on masked ROM parts:
1. External MOVC is disabled, and
2. EA# is latched on Reset.
Security Bit 2: When programmed, this bit inhibits Verify User ROM.
If the ROM Code file does not include the options, the following information must be included with the ROM code.
For each of the following, check the appropriate box, and send to Philips along with the code:
Security Bit #1:
Security Bit #2:
Encryption:
V Enabled
V Enabled
V No
V Disabled
V Disabled
V Yes
If Yes, must send key file.
19
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
repeated until a total of 5 programming pulses have occurred. At the
conclusion of the last pulse, the PGM/ signal should remain high.
PROGRAMMING CONSIDERATIONS
EPROM Characteristics
The V signal may now be driven to the V level, placing the
PP
OH
The 87C754 is programmed by using a modified Quick-Pulse
Programming algorithm similar to that used for devices such as the
87C751 and 87C752.
87C754 in the verify mode. (Port 1 is now used as an output port).
After four machine cycles (48 clock periods), the contents of the
addressed location in the EPROM array will appear on Port 1.
Figure 20 shows a block diagram of the programming configuration
for the 87C754. Port pin P0.2 is used as the programming voltage
The next programming cycle may now be initiated by placing the
address information at the inputs of the multiplexed buffers, driving
supply input (V signal). Port pin P0.1 is used as the program
PP
the V pin to the V voltage level, providing the byte to be
PP
PP
(PGM/) signal. This pin is used for the 5 programming pulses.
programmed to Port1 and issuing the 5 programming pulses on the
PGM/ pin, bringing V back down to the V level and verifying the
Port 3 is used as the address input for the byte to be programmed
and accepts both the high and low components of the eleven bit
address. Multiplexing of these address components is performed
using the ASEL input. The user should drive the ASEL input high
and then drive port 3 with the high order bits of the address. ASEL
should remain high for at least 13 clock cycles. ASEL may then be
driven low which latches the high order bits of the address internally.
The high address should remain on port 3 for at least two clock
cycles after ASEL is driven low. Port 3 may then be driven with the
low byte of the address. The low address will be internally stable 13
clock cycles later. The address will remain stable provided that the
low byte placed on port 3 is held stable and ASEL is kept low.
Note: ASEL needs to be pulsed high only to change the high byte of
the address.
PP
C
byte.
Programming Modes
The 87C754 has four programming features incorporated within its
EPROM array. These include the USER EPROM for storage of the
application’s code, a 64-byte encryption key array and two security
bits. Programming and verification of these four elements are
selected by a combination of the serial data stream applied to the
RESET pin and the voltage levels applied to port pins P0.1 and
P0.2. The various combinations are shown in Table 3.
Encryption Key Table
The 87C754 includes a 64-byte EPROM array that is programmable
by the end user. The contents of this array can then be used to
encrypt the program memory contents during a program memory
verify operation. When a program memory verify operation is
performed, the contents of the program memory location is
XNOR’ed with one of the bytes in the 64-byte encryption table. The
resulting data pattern is then provided to port 1 as the verify data.
The encryption mechanism can be disabled, in essence, by leaving
the bytes in the encryption table in their erased state (FFH) since
the XNOR product of a bit with a logical one will result in the original
bit. The encryption bytes are mapped with the code memory in
64-byte groups. the first byte in code memory will be encrypted with
the first byte in the encryption table; the second byte in code
memory will be encrypted with the second byte in the encryption
table and so forth up to and including the 64th byte. The encryption
repeats in 64-byte groups; the 65th byte in the code memory will be
encrypted with the first byte in the encryption table, and so forth.
Port 1 is used as a bidirectional data bus during programming and
verify operations. During programming mode, it accepts the byte to
be programmed. During verify mode, it provides the contents of the
EPROM location specified by the address which has been supplied
to Port 3.
The XTAL1 pin is the oscillator input and receives the master system
clock. This clock should be between 1.2 and 16MHz.
The RESET pin is used to accept the serial data stream that places
the 87C754 into various programming modes. This pattern consists
of a 10-bit code with the LSB sent first. Each bit is synchronized to
the clock input, X1.
Programming Operation
Figures 21 and 22 show the timing diagrams for the program/verify
cycle. RESET should initially be held high for at least two machine
cycles. P0.1 (PGM/) and P0.2 (V ) will be at V as a result of the
Security Bits
PP
OH
RESET operation. At this point, these pins function as normal
quasi-bidirectional I/O ports and the programming equipment may
pull these lines low. However, prior to sending the 10-bit code on the
RESET pin, the programming equipment should drive these pins
Two security bits, security bit 1 and security bit 2, are provided to
limit access to the USER EPROM and encryption key arrays.
Security bit 1 is the program inhibit bit, and once programmed
performs the following functions:
high (V ). The RESET pin may now be used as the serial data input
IH
1. Additional programming of the USER EPROM is inhibited.
for the data stream which places the 87C754 in the programming
mode. Data bits are sampled during the clock high time and thus
should only change during the time that the clock is low. Following
transmission of the last data bit, the RESET pin should be held low.
2. Additional programming of the encryption key is inhibited.
3. Verification of the encryption key is inhibited.
4. Verification of the USER EPROM and the security bit levels may
still be performed.
Next the address information for the location to be programmed is
placed on port 3 and ASEL is used to perform the address
multiplexing, as previously described. At this time, port 1 functions
as an output.
(If the encryption key array is being used, this security bit should be
programmed by the user to prevent unauthorized parties from
reprogramming the encryption key to all logical zero bits. Such
programming would provide data during a verify cycle that is the
logical complement of the USER EPROM contents).
A high voltage V level is then applied to the V input (P0.2).
PP
PP
(This sets Port 1 as an input port). The data to be programmed into
the EPROM array is then placed on Port 1. This is followed by a
series of programming pulses applied to the PGM/ pin (P0.1). These
pulses are created by driving P0.1 low and then high. This pulse is
Security bit 2, the verify inhibit bit, prevents verification of both the
USER EPROM array and the encryption key arrays. The security bit
levels may still be verified.
20
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
Since sunlight and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about
1 week in sunlight, or 3 years in room level fluorescent lighting)
could cause inadvertent erasure. For this and secondary effects,
it is recommended that an opaque label be placed over the
window. For elevated temperature or environments where solvents
are being used, apply Kapton tape Flourless part number 2345–5 or
equivalent.
Programming and Verifying Security Bits
Security bits are programmed employing the same techniques used
to program the USER EPROM and KEY arrays using serial data
streams and logic levels on port pins indicated in Table 3. When
programming either security bit, it is not necessary to provide
address or data information to the 87C754 on ports 1 and 3.
Verification occurs in a similar manner using the RESET serial
stream shown in Table 3. Port 3 is not required to be driven and the
results of the verify operation will appear on ports 1.6 and 1.7.
The recommended erasure procedure is exposure to ultraviolet light
2
(at 2537 angstroms) to an integrated dose of at least 15W-sec/cm .
Ports 1.7 contains the security bit 1 data and is a logical one if
programmed and a logical zero if erased. Likewise, P1.6 contains
the security bit 2 data and is a logical one if programmed and a
logical zero if erased.
2
Exposing the EPROM to an ultraviolet lamp of 12,000uW/cm rating
for 20 to 39 minutes, at a distance of about 1 inch, should be
sufficient.
Erasure leaves the array in an all 1s state.
Erasure Characteristics
Erasure of the EPROM begins to occur when the chip is exposed to
light with wavelengths shorter than approximately 4,000 angstroms.
Table 3. Implementing Program/Verify Modes
OPERATION
SERIAL CODE
PGM
V
PP
Program user EPROM
Verify user EPROM
Program key EPROM
Verify key EPROM
Program security bit 1
Program security bit 2
Verify security bits
296H
296H
292H
292H
29AH
298H
29AH
–*
V
V
V
PP
PP
V
IH
IH
–*
V
IH
V
IH
PP
PP
–*
–*
V
V
V
IH
V
IH
NOTE:
*
Pulsed from V to V and returned to V .
IH IL IH
21
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
EPROM PROGRAMMING AND VERIFICATION
T
amb
= 21°C to +27°C, V
= 5V ±10%, V = 0V
CC
SS
SYMBOL
PARAMETER
MIN
1.2
MAX
UNIT
1/t
CLCL
Oscillator/clock frequency
Address setup to PGM low
Address hold after PGM high
Data setup to PGM low
16
MHz
1
t
10µs + 24t
AVGL
CLCL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
48t
38t
38t
36t
GHAX
DVGL
DVGL
GHDX
SHGL
GHSL
GLGH
CLCL
CLCL
CLCL
CLCL
Data setup to PGM low
Data hold after PGM high
V
V
setup to PGM low
hold after PGM
10
10
90
µs
µs
µs
PP
PP
PGM width
low (V ) to data valid
110
2
V
PP
48t
CLCL
AVQV
CC
PGM high to PGM low
P0.0 (sync pulse) low
P0.0 (sync pulse) high
ASEL high time
10
µs
GHGL
SYNL
4t
CLCL
8t
CLCL
SYNH
MASEL
MAHLD
HASET
ADSTA
13t
CLCL
CLCL
Address hold time
2t
Address setup to ASEL
Low address to address stable
13t
13t
CLCL
CLCL
NOTES:
1. Address should be valid at least 24t
before the rising edge of V
.
PP
CLCL
2. For a pure verify mode, i.e., no program mode in between, t
is 14t
maximum.
CLCL
AVQV
87C754
A0–A10
A0–A10
+5V
V
CC
ADDRESS STROBE
ZDAC/ASEL
V
SS
PROGRAMMING
PULSES
XYDACBIAS/PGM
V
/V VOLTAGE
P1.2/V
PP
PP IH
P3.0–P3.7
DATA BUS
SOURCE
CLK SOURCE
X1
RESET
CONTROL
LOGIC
RST
SU00667A
Figure 20. Programming Configuration
22
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
XTAL1
MIN 2 MACHINE
CYCLES
TEN BIT SERIAL CODE
RESET
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
UNDEFINED
UNDEFINED
V
PP
PGM
SU00721
Figure 21. Entry into Program/Verify Modes
12.75V
V
PP
5V
5V
t
t
SHGL
GHSL
5 PULSES
PGM
t
t
GLGH
MASEL
t
GHGL
98µs MIN
10µs MIN
ASEL
t
HASET
t
HAHLD
HIGH ADDRESS
LOW ADDRESS
A0–A10
D0–D7
t
t
t
t
ADSTA
DVGL
GHDX
AVQV
INVALID DATA
VERIFY MODE
VALID DATA
DATA TO BE PROGRAMMED
PROGRAM MODE
INVALID DATA
VALID DATA
VERIFY MODE
SU00683A
Figure 22. Program/Verify Cycle
23
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3mm
SOT341-1
24
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
NOTES
25
1998 Apr 23
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
83C754/87C754
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 05-98
Document order number:
9397 750 03892
Philips
Semiconductors
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