P87CE598EFB/01 [NXP]
IC 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80, 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-318-1, QFP-80, Microcontroller;
| 型号： | P87CE598EFB/01 |
| 厂家： | 
NXP |
| 描述： | IC 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80, 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-318-1, QFP-80, Microcontroller 可编程只读存储器 时钟 微控制器 外围集成电路 |
| 文件： | 总112页 (文件大小：707K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
P8xCE598
8-bit microcontroller
with on-chip CAN
1996 Jun 27
Product specification
Supersedes data of 1995 Oct 24
File under Integrated Circuits, IC18
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
CONTENTS
14
INTERRUPT SYSTEM
14.1
14.2
14.3
Interrupt Enable and Priority Registers
Interrupt Vectors
Interrupt Priority
1
2
FEATURES
GENERAL DESCRIPTION
2.1
2.2
Electromagnetic Compatibility (EMC)
Recommendation on ALE
15
POWER REDUCTION MODES
15.1
15.2
15.3
15.4
Power Control Register (PCON)
CAN Sleep Mode
Idle Mode
3
4
5
6
7
ORDERING INFORMATION
BLOCK DIAGRAM
Power-down Mode
PINNING
16
OSCILLATOR CIRCUITRY
RESET CIRCUITRY
Power-on Reset
FUNCTIONAL DESCRIPTION
MEMORY ORGANIZATION
17
17.1
18
7.1
7.2
7.3
Program Memory
Internal Data Memory
External Data Memory
INSTRUCTION SET
18.1
18.2
Addressing Modes
Instruction Set
8
9
I/O PORT STRUCTURE
19
20
21
22
ABSOLUTE MAXIMUM RATINGS
DC CHARACTERISTICS
PULSE WIDTH MODULATED OUTPUTS
(PWM)
9.1
9.2
9.3
Prescaler frequency control register (PWMP)
Pulse Width Register 0 (PWM0)
Pulse Width Register 1 (PWM1)
AC CHARACTERISTICS
CAN APPLICATION INFORMATION
22.1
22.2
Latency time requirements
Connecting a P8xCE598 to a bus line
(physical layer)
10
ANALOG-TO-DIGITAL CONVERTER (ADC)
ADC Control register (ADCON)
TIMERS/COUNTERS
10.1
11
23
24
PACKAGE OUTLINES
SOLDERING
11.1
11.2
11.3
Timer 0 and Timer 1
Timer T2 Capture and Compare Logic
Watchdog Timer (T3)
24.1
24.2
24.3
24.4
Introduction
Reflow soldering
Wave soldering
12
13
SERIAL I/O PORT: SIO0 (UART)
SERIAL I/O PORT: SIO1 (CAN)
Repairing soldered joints
25
26
DEFINITIONS
13.1
13.2
13.3
13.4
13.5
On-chip CAN-controller
CAN Features
Interface between CPU and CAN
Hardware blocks of the CAN-controller
Control Segment and Message Buffer
description
LIFE SUPPORT APPLICATIONS
13.6
CAN 2.0A Protocol description
1996 Jun 27
2
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
The P8xCE598 combines the functions of P8XC552
1
FEATURES
(microcontroller) and the PCA82C200 (Philips
CAN-controller) with the following enhanced features:
• 80C51 central processing unit (CPU)
• 32 kbytes on-chip ROM,
externally expandible to 64 kbytes
• 32 kbytes Program Memory
• 2 × 256 bytes Data Memory
• 2 × 256 bytes on-chip RAM,
externally expandible to 64 kbytes
• DMA between CAN Transmit/Receive Buffer and
internal RAM.
• Two standard 16-bit timers/counters
The main differences to the P8xC552 microcontroller are:
• 32 kbytes programmable ROM (P8xC552 has 8 kbytes)
• Additional 256 bytes RAM
• One additional 16-bit timer/counter coupled to four
capture and three compare registers
• 10-bit ADC with 8 multiplexed analog inputs
• A CAN-controller instead of the I2C-serial interface.
• Two 8-bit resolution Pulse Width Modulated outputs
• 15 interrupt sources with 2 priority levels
(2 to 6 external interrupt sources possible)
2.1
Electromagnetic Compatibility (EMC)
Primary attention is paid to the reduction of
electromagnetic emission of the microcontroller
P8xCE598. The following features reduce the
electromagnetic emission and additionally improve the
electromagnetic susceptibility:
• Five 8-bit I/O ports, plus one 8-bit input port shared with
analog inputs
• CAN-controller (CAN = Controller Area Network)
with DMA data transfer facility to internal RAM
• 1 Mbit/s CAN-controller with bus failure management
facility
• One analog part power supply pin (AVDD) and one
analog part ground pin (AVSS), placed as a pair of pins
on one side of the package (see Fig.3), providing power
supply (+5V) and ground for ADC, CAN receiver and
reference voltage.
•
1⁄2AVDD reference voltage
• Full-duplex UART compatible with the standard 80C51
• On-chip Watchdog Timer (WDT)
• Four digital part supply voltage pins (VDD1 to VDD4) and
four digital part ground pins (VSS1 to VSS4) are provided
on the package. These pins, one VDD and one VSS as a
pair of pins are placed on each of the four sides of the
package to provide:
• 1.2 to 16 MHz clock frequency
• Improved Electromagnetic Compatibility (EMC).
2
GENERAL DESCRIPTION
– VDD1/VSS1 for internal logic (CPU, Timers/counters,
Memory, CAN, UART, ADC)
The P8xCE598 is a single-chip 8-bit high-performance
microcontroller with on-chip CAN-controller, derived from
the 80C51 microcontroller family.
– VDD2/VSS2 for Port 1, Port 3 and Port 4, and PWM0
and PWM1 outputs
It uses the powerful 80C51 instruction set.
Figure 1 shows a block diagram of the P8xCE598.
– VDD3/VSS3 for the on-chip oscillator
The P8xCE598 is manufactured in an advanced CMOS
process, and is designed for use in automotive and
general industrial applications. In addition to the 80C51
standard features, the device provides a number of
dedicated hardware functions for these applications.
– VDD4/VSS4 for the Port 0, Port 2, ALE output and
PSEN output.
• External capacitors should be connected across
associated VDDx and VSSx pins (i.e. VDD1 and VSS1).
Lead length should be as short as possible. Ceramic
chip capacitors are recommended (100 nF).
Two versions of the P8xCE598 will be offered:
• P80CE598 (without ROM)
• One CAN supply voltage pin (CVDD) and one CAN
ground pin (CVSS) as a pair of pins placed on one side
of the package providing (digital part) power supply
(+5V) and ground for the CAN transmitter outputs.
• P83CE598 (with ROM)
Hereafter these versions will be referred to as P8xCE598.
• Internal decoupling capacitance improves the EMC
radiation behaviour and the EMC immunity.
The temperature range includes (max. fCLK = 16 MHz):
• −40 to +85 °C version, for general applications
• −40 to +125 °C version for automotive applications.
1996 Jun 27
3
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
ALE will retain its normal HIGH value during Idle mode and
a LOW value during Power-down mode while in the ‘RFI
reduction mode’.
2.2
Recommendation on ALE
For application that require no external memory or
temporarily no external memory: the ALE output signal
(pulses at a frequency of 1⁄6 fOSC) can be disabled under
software control (bit 5 in PCON SFR: ‘RFI’); if disabled, no
ALE pulse will occur. ALE pin will be pulled down
internally, switching an external address latch to a quiet
state. The MOVX instruction will still toggle ALE as a
normal MOVX.
Additionally during internal access (EA = 1) ALE will toggle
normally when the address exceeds the internal Program
Memory size. During external access (EA = 0) ALE will
always toggle normally, whether the flag ‘RFI’ is set or not.
3
ORDERING INFORMATION
TYPE
PACKAGE
TEMPERATURE
RANGE (°C)
FREQ.
(MHz)
NUMBER
NAME
DESCRIPTION
VERSION
Without ROM
P80CE598FFB
P80CE598FHB
plastic quad flat package; 80 leads (lead
length 1.95 mm); body 14 × 20 × 2.7 mm;
high stand-off height
−40 to +85
QFP80
QFP80
SOT318-1
1.2 to 16
1.2 to 16
−40 to +125
With ROM
P83CE598FFB
P83CE598FHB
plastic quad flat package; 80 leads (lead
length 1.95 mm); body 14 × 20 × 2.7 mm;
high stand-off height
−40 to +85
SOT318-1
−40 to +125
1996 Jun 27
4
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
4
BLOCK DIAGRAM
LM2B8
a n d b o o k , f u l l i d t h
1996 Jun 27
5
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
5
PINNING
alternative function
XTAL1
XTAL2
0
1
2
3
4
5
6
7
AD0
AD1
AD2
LOW ORDER
ADDRESS
AND
EA
PSEN
ALE
AD3
AD4
AD5
AD6
AD7
PORT 0
PORT 1
PORT 2
PORT 3
DATA BUS
PWM0
PWM1
CRX0
0
1
2
3
4
5
6
7
CT0I/INT2
CT1I/INT3
CT2I/INT4
CT3I/INT5
T2
CRX1
REF
AV
SS
AV
DD
AV
RT2
ref+
AV
CTX0
ref –
alternative function
CTX1
STADC
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
0
1
2
3
0
1
2
3
4
5
6
7
A8
A9
P8xCE598
A10
HIGH ORDER
ADDRESS
BUS
A11
A12
A13
A14
A15
PORT 5
4
5
6
7
RXD/DATA
CMSR0
CMSR1
CMSR2
CMSR3
CMSR4
CMSR5
CMT0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
TXD/CLOCK
INT0
INT1
T0
PORT 4
T1
WR
RD
CMT1
CV
CV
V
SS
DD
RST
EW
SS
V
DD
MBD036
Fig.2 Pin functions.
6
1996 Jun 27
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
AV
AV
1
2
3
4
5
6
7
8
9
64 ALE
63
62 P2.7/A15
61
ref
ref
PSEN
AV
SS
DD
AV
P2.6/A14
60 P2.5/A13
59
P5.7/ADC7
P5.6/ADC6
P5.5/ADC5
P2.4/A12
58 P2.3/A11
57 P2.2/A10
56 P2.1/A09
55 P2.0/A08
P5.4/ADC4
P5.3/ADC3
P5.2/ADC2 10
P5.1/ADC1 11
P5.0/ADC0 12
V
54
53
52
51
50
49
SS3
DD3
V
P8xCE598
V
13
14
XTAL1
XTAL2
n.c.
SS1
V
DD1
STADC 15
PWM0 16
PWM1 17
n.c.
48 P3.7/RD
47 P3.6/WR
18
19
EW
P3.5/T1
P3.4/T0
46
45
P4.0/CMSR0
P4.1/CMSR1 20
21
P4.3/CMSR3 22
n.c.
P4.4/CMSR4 24
44 P3.3/INT1
43 P3.2/INT0
P4.2/CMSR2
P3.1/TXD
23
42
41 P3.0/RXD
MLB229
Fig.3 Pin configuration QFP80/SOT318-1.
7
1996 Jun 27
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Table 1 Pin description for single function pins (SOT318-1 and SOT351-1; see note 1)
SYMBOL PIN
DESCRIPTION
VDD1
14 Power supply, digital part: for internal logic (CPU, Timers/counters, Memory, CAN, UART, ADC).
28 Power supply, digital part: for Port 1, Port 3, Port 4, PWM0 and PWM1 outputs.
53 Power supply, digital part: for the on-chip oscillator.
VDD2
VDD3
VDD4
76 Power supply, digital part: for Port 0, Port 2, ALE output and PSEN output.
15 Start ADC operation. Input starting analog-to-digital conversion (note 2). This pin must not float.
16 Pulse width modulation output 0.
STADC
PWM0
PMW1
EW
17 Pulse width modulation output 1.
18 Enable Watchdog Timer (WDT): enable for T3 Watchdog Timer and disable Power-down mode.
This pin must not float.
RST
30 Reset: input to reset the P8xCE598 (note 3).
37 Ground potential for the CAN transmitter outputs.
40 Power supply (+5V) for the CAN transmitter outputs.
CVSS
CVDD
XTAL2
51 Crystal pin 2: output of the inverting amplifier that forms the oscillator.
When an external clock oscillator is used this pin is left open-circuit.
XTAL1
52 Crystal pin 1: input to the inverting amplifier that forms the oscillator, and input to the internal clock
generator. Receives the external clock oscillator signal, when an external oscillator is used.
VSS1
VSS2
VSS3
VSS4
PSEN
13 Ground, digital part: for internal logic (CPU, Timers/Counters, Memory, CAN, UART, ADC).
29 Ground, digital part: for Port 1, Port 3 and Port 4, and PWM0 and PWM1 outputs.
54 Ground, digital part: for the on-chip oscillator.
77 Ground, digital part: for the Port 0, Port 2, ALE output and PSEN output.
63 Program Store Enable: Read strobe to external Program Memory (active LOW).
Drive: 8 × LSTTL inputs.
ALE
64 Address Latch Enable: latches the Low-byte of the address during accesses to external memory
(note 4). Drive: 8 × LSTTL inputs; handles CMOS inputs without an external pull-up.
EA
65 External Access input. See note 5.
REF
78 1⁄2AVDD reference voltage output respectively input (note 6).
CRX1
CRX0
AVREF−
AVREF+
AVSS
AVDD
n.c.
79 Inputs from the CAN-bus line to the differential input comparator of the on-chip CAN-controller
(note 7).
80
1
2
3
4
Low-end of ADC (analog-to-digital conversion) reference resistor.
High-end of ADC (analog-to-digital conversion) reference resistor (note 8).
Ground, analog part. For ADC, CAN receiver and reference voltage.
Power supply, analog part (+5 V). For ADC, CAN receiver and reference voltage.
23, No connection.
49,
50,
66,
67
Notes
1. To avoid a ‘latch up’ effect at power-on: VSS − 0.5 V < ‘voltage on any pin at any time’ < VDD + 0.5 V.
2. Triggered by a rising edge. ADC operation can also be started by software.
3. RST also provides a reset pulse as output when timer T3 overflows or after a CAN wake-up from Power-down.
1996 Jun 27
8
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
4. ALE is activated every six oscillator periods. During an external data memory access one ALE pulse is skipped.
5. See Section 7.1, Table 3 for EA operation. For P83CE598 microcontrollers specified with the option ‘ROM-code
protection’, the EA pin is latched during reset and is ‘don't care’ after reset, regardless of whether the ROM-code
protection is selected or not.
6. Pin 78, REF:
a) Selection of input respectively output dependent of CAN Control Register bit 5 (CR.5; see Section 13.5.3
Table 32).
b) If the internal reference is used, then REF should be connected to AVSS via a capacitor with a value of ≥ 10 nF.
c) After an external reset (RST = HIGH) the internal 1⁄2AVDD source is activated and, REF is a reference output.
d) If the CAN-controller is in the reset state, e.g. after an external reset, then the 1⁄2AVDD source is switched off
during Power-down mode.
7. CAN Bus line:
a) CRX0 level > CRX1 level is interpreted as a logic 1 (recessive).
b) CRX0 level < CRX1 level is interpreted as a logic 0 (dominant).
8. The level of AVREF+ must be higher than that of AVREF−
.
Table 2 Pin description for pins with alternative functions (SOT318-2 and SOT351-1; see note 1)
SYMBOL
PIN
DESCRIPTION
DEFAULT
ALTERNATIVE
Port 4
P4.0 to P4.7
19 to 22, 24 to 27 8-bit quasi-bidirectional I/O port.
CMSR0
19
20
21
22
24
25
26
27
Compare and Set/Reset outputs for Timer T2.
CMSR1
CMSR2
CMSR3
CMSR4
CMSR5
CMT0
Compare and toggle outputs for Timer T2.
CMT1
Port 1
P1.0 to P1.7
31 to 36, 38 to 39 8-bit quasi-bidirectional I/O port.
CT0I/INT2
CT1I/INT3
CT2I/INT4
CT3I/INT5
T2
31
32
33
34
35
36
38
39
Capture timer inputs for Timer T2,
or
External interrupt inputs 2 to 5.
T2 event input (rising edge triggered).
T2 timer reset input (rising edge triggered).
CAN transmitter output 0 (note 2).
CAN transmitter output 1 (note 2).
RT2
CTX0
CTX1
1996 Jun 27
9
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
SYMBOL
PIN
DESCRIPTION
DEFAULT
ALTERNATIVE
Port 3
P3.0 to P3.7
41 to 48
41
8-bit quasi-bidirectional I/O port.
Serial Input Port.
RXD
TXD
INT0
INT1
T0
42
Serial Output Port.
43
External interrupt input 0.
External interrupt input 1.
Timer 0 external input.
44
45
T1
46
Timer 1 external input.
WR
RD
47
External Data Memory Write strobe.
External Data Memory Read strobe.
48
Port 2 (Sink/source: 1 × TTL = 4 × LSTTL inputs)
P2.0 to P2.7 55 to 62
8-bit quasi-bidirectional I/O port.
A08 to A15
Port 0 (Sink/source: 8 × LSTTL inputs)
High-order address byte for external memory.
P0.7 to P0.0
68 to 75
8-bit open drain bidirectional I/O port.
AD7 to AD0
Multiplexed Low-order address and Data bus for
external memory.
Port 5
P5.7 to P5.0
5 to 12
8-bit input port.
ADC7 to ADC0
8 input channels to ADC.
Notes
1. To avoid a ‘latch up’ effect at power-on: VSS − 0.5 V < ‘voltage on any pin at any time’ < VDD + 0.5 V.
2. If the CAN-controller is in the reset state (e.g. after a power-up reset; CAN Control Register bit CR.0; see
Section 13.5.3 Table 32, the CAN transmitter outputs are floating and the pins P1.6 and P1.7 can be used as
open-drain port pins. After a power-up reset the port data is HIGH, leaving the pins P1.6 and P1.7 floating.
1996 Jun 27
10
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
6
FUNCTIONAL DESCRIPTION
7
MEMORY ORGANIZATION
The P8xCE598 functions will be described as shown in the
following overview:
The Central Processing Unit (CPU) manipulates operands
in three memory spaces (see Fig.4) as follows:
• Memory organization
• I/O Port structure
• 32 kbytes internal, resp. 64 kbytes external Program
Memory
• 512 bytes internal Data Memory MAIN- and AUXILIARY
RAM.
• Pulse Width Modulated outputs
• Analog-to-Digital Converter
• Timers/Counters
• Up to 64 kbytes external Data Memory
(with 256 bytes residing in the internal AUXILIARY
RAM).
• Serial I/O Ports
• Interrupt system
• Power reduction modes
• Oscillator circuitry
• Reset circuitry
• Instruction Set
• EMC (see Section 2.1).
64K
64K
EXTERNAL
32768
32767
OVERLAPPED SPACE
256
255
127
0
INTERNAL
(EA = 1)
EXTERNAL
(EA = 0)
SFRs
AUXILIARY
RAM
INDIRECT ONLY
DIRECT AND
INDIRECT
0
MAIN RAM
EXTERNAL
DATA MEMORY
PROGRAM MEMORY
INTERNAL DATA MEMORY
MLB230
Fig.4 Memory map.
1996 Jun 27
11
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
7.1
Program Memory
The Program Memory of the P8xCE598 consists of 32 kbytes ROM on-chip, externally expandible up to 64 kbytes.
Table 3 Instruction fetch controlled by EA
PIN EA (note 1)
ADDRESS
INSTRUCTIONS FETCHED FROM:
DURING RESET
LOCATION
AFTER RESET
LATCHED TO:
H
H
L
−
internal Program Memory (note 2)
external Program Memory
0000H → 7FFFH
8000H → FFFFH
0000H → FFFFH
−
−
−
−
‘don’t care’
−
Notes
1. This implementation prevents reading of the internal program code by switching from external Program Memory
during a MOVC instruction.
2. By setting a security bit the internal Program Memory content is protected, which means it cannot be read out.
If the security bit has been set to LOW there are no restrictions for the MOVC instruction.
7.2
Internal Data Memory
The internal Data Memory is physically built-up and accessible as shown in Table 4 (see Fig.5).
Table 4 Internal Data Memory size and address mode
ADDRESS MODE
INTERNAL
SIZE
LOCATION
POINTERS
DATA MEMORY
DIRECT
INDIRECT
MAIN RAM
(note 1)
256 bytes 0 to 127
128 to 255
X
−
−
X
X
X
Address pointers are R0 and R1 of the
selected register bank.
AUXILIARY RAM 256 bytes 0 to 255
(note 2)
Address pointers are R0 and R1 of the
selected register bank and the DPTR.
SFRs (note 3)
128 bytes 128 to 255
X
−
−
Notes
1. MAIN RAM can be addressed directly and indirectly as in the 80C51.
2. AUXILIARY RAM (0 to 255):
a) Is indirectly addressable in the same way as the external Data Memory with MOVX instructions.
b) Access will not affect the ports P0, P2, P3.6 and P3.7 during internal program execution.
3. SFRs = Special Function Registers.
1996 Jun 27
12
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
7.2.1
MAIN RAM
Four 8-bit register banks occupy the lower RAM area,
• BANK 0: location 0 to 7
127
7FH
(MSB)
(LSB)
• BANK 1: location 8 to 15
• BANK 2: location 16 to 23
2FH 7F 7E 7D 7C 7B 7A 79 78
2EH 77 76 75 74 73 72 71 70
2DH 6F 6E 6D 6C 6B 6A 69 68
2CH 67 66 65 64 63 62 61 60
2BH 5F 5E 5D 5C 5B 5A 59 58
2AH 57 56 55 54 53 52 51 50
29H 4F 4E 4D 4C 4B 4A 49 48
28H 47 46 45 44 43 42 41 40
27H 3F 3E 3D 3C 3B 3A 39 38
26H 37 36 35 34 33 32 31 30
25H 2F 2E 2D 2C 2B 2A 29 28
24H 27 26 25 24 23 22 21 20
23H 1F 1E 1D 1C 1B 1A 19 18
22H 17 16 15 14 13 12 11 10
21H 0F 0E 0D 0C 0B 0A 09 08
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
• BANK 4: location 24 to 31.
Only one of these banks may be enabled at the same time.
The next 16 bytes, locations 32 through 45, contains
128 directly addressable bit locations.
The stack can be located anywhere in the internal Main
RAM address space. The stack depth is only limited by the
internal RAM space available. All registers except the
program counter and the four 8-bit register banks reside in
the SFR address space.
7.3
External Data Memory
20H
1FH
07 06 05 04 03 02 01 00
An access to external Data Memory locations higher than
255 will be performed with the MOVX @DPTR instructions
in the same way as in the 80C51 structure,
i.e.with P0 and P2 as data/address bus and P3.6 and P3.7
as Write and Read strobe signals.
BANK 3
18H
17H
24
23
BANK 2
BANK 1
10H
0FH
16
15
Note that these external Data Memory locations cannot be
accessed with R0 or R1 as address pointer.
08H
07H
8
7
BANK 0
00H
0
MGA152
Fig.5 Internal MAIN RAM bit addresses.
1996 Jun 27
13
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
DIRECT
BYTE
ADDRESS (HEX)
REGISTER
MNEMONIC
BIT ADDRESS
T3
PWMP
PWM1
PWM0
FFH
FEH
FDH
FCH
IP1
FF FE FD FC FB FA F9 F8
F7 F6 F5 F4 F3 F2 F1 F0
F8H
F0H
EFH
EEH
EDH
ECH
EBH
EAH
B
RTE
STE
# TMH2
# TML2
CTCON
TM2CON
IEN1
ACC
EF EE ED EC EB EA E9 E8 E8H
E7 E6 E5 E4 E3 E2 E1 E0 E0H
SFRs containing
directly addressable
bits
CANADR
CANDAT
CANCON
CANSTA
DBH
DAH
D9H
DF DE DD DC DB DA D9 D8
D8H
PSW
# CTH3
# CTH2
# CTH1
# CTH0
CMH2
D7 D6 D5 D4 D3 D2 D1 D0 D0H
CFH
CEH
CDH
CCH
CBH
CAH
C9H
CMH1
CMH0
C8H
TM2IR
CF CE CD CC CB CA C9 C8
# ADCH
ADCON
# P5
C6H
C5H
C4H
P4
C7 C6 C5 C4 C3 C2 C1 C0
C0H
MGA150
# denotes read-only registers
Fig.6 Special Function Register memory map (a).
14
1996 Jun 27
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
DIRECT
BYTE
ADDRESS (HEX)
REGISTER
MNEMONIC
BIT ADDRESS
IP0
BF BE BD BC BB BA B9 B8 B8H
P3
# CTL3
# CTL2
# CTL1
# CTL0
CML2
B7 B6 B5 B4 B3 B2 B1 B0 B0H
AFH
AEH
ADH
ACH
ABH
CML1
AAH
A9H
CML0
IEN0
AF AE AD AC AB AA A9 A8 A8H
P2
A7 A6 A5 A4 A3 A2 A1 A0 A0H
SFRs containing
directly addressable
bits
S0BUF
S0CON
99H
98H
9F 9E 9D 9C 9B 9A 99 98
P1
97 96 95 94 93 92 91 90 90H
TH1
TH0
8DH
8CH
TL1
8BH
8AH
89H
TL0
TMOD
TCON
PCON
8F 8E 8D 8C 8B 8A 89 88
88H
87H
DPH
DPL
SP
83H
82H
81H
80H
P0
87 86 85 84 83 82 81 80
# denotes read-only registers
MGA151
Fig.7 Special Function Register memory map (b).
15
1996 Jun 27
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
8
I/O PORT STRUCTURE
The P8xCE598 has six 8-bit parallel ports: Port 0 to Port 5. In addition to the standard 8-bit parallel ports, the I/O facilities
also include a number of special I/O lines. The use of a Port 1, Port 3 or Port 4 pins as an alternative function is carried
out automatically provided the associated SFR bit is set HIGH.
Table 5 Default Port functions
PORT TYPE
FUNCTION
REMARKS
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
I/O The same as in the 80C51
Except for the additional functions of P1.6 and
P1.7.
I/O
I/O
I/O
I/O Parallel I/O port
Parallel I/O function is identical to Port1, 2 and 3.
I
Parallel input port with an input function only
May be used as normal inputs if the ADC function
is inoperative.
Table 6 Alternative Port functions
PORT TYPE FUNCTION
I/O Multiplexed Low-order address and
REMARKS
Port 0
Provides the multiplexed Low-order address and
data bus used for expanding the P8xCE598 with
standard memories and peripherals.
Data bus for external memory (AD7 to AD0)
Port 1
I/O Capture timer inputs for Timer T2
(CT0I to CT3I), or
External interrupt request inputs, if capture
information is not utilized.
External interrupt request inputs
(INT2 to INT5)
T2 event input (T2)
External counter input.
T2 timer reset input (RT2)
CAN transmitter output 0 (CTX0)
CAN transmitter output 1 (CTX1)
External counter reset input.
CTX0 and CTX1 outputs of the CAN interface
(note 1).
Port 2
Port 3
I/O High-order address byte for external memory
(A08 to A15)
Port 2 provides the High-order address bus when
the P8xCE598 is expanded with external Program
Memory and/or external Data Memory.
I/O Serial Input Port (RXD)
Serial Output Port (TXD)
Receiver input of serial port SIO0 (UART).
Transmitter output of serial port SIO0 (UART).
External interrupt request inputs.
External interrupt (INT0)
External interrupt (INT1)
Timer 0 external input (T0)
Counter inputs.
Timer 1 external input (T1)
External data memory Write strobe (WR)
External data memory Read strobe (RD)
Control signal to write to external Data Memory.
Control signal to read from external Data Memory.
Port 4
Port 5
I/O Compare and Set/Reset outputs
(CMSR0 to CMSR5)
Can be configured to provide signals indicating a
match between Timer counter T2 and its compare
registers.
Compare and toggle outputs (CMT0, CMT1)
I
Input channels to ADC (ADC7 to ADC0)
Port 5 may be used in conjunction with the ADC
interface (note 2).
1996 Jun 27
16
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Notes to the Alternative Port functions
1. Port lines P1.6 and P1.7 may be selected as CTX0 and CTX1 outputs of the serial port SIO1 (CAN).
After reset P1.6 and P1.7 may be used as normal I/O ports, if the CAN interface is not used.
2. Unused analog inputs can be used as digital inputs. As Port 5 lines may be used as inputs to the ADC, these digital
inputs have an inherent hysteresis to prevent the input logic from drawing too much current from the power lines
when driven by analog signals.
Channel-to-channel crosstalk should be taken into consideration when both digital and analog signals are
simultaneously input to Port 5 (see Chapter 20).
strong pull-up
+5 V
2 oscillator
periods
p2
p3
p1
n
I/O PIN
PORT
1, 2, 3 or 4
Q
from port latch
I1
input data
INPUT
BUFFER
MGA153
read port pin
Fig.8 I/O buffers in the P8xCE598 (P1.0 to P1.5, Ports 2, 3, and 4).
The repetition frequency fPWM, at the PWMn outputs is
fCLK
9
PULSE WIDTH MODULATED OUTPUTS (PWM)
Two Pulse Width Modulated (PWM) output channels are
available with the P8xCE598. These channels provide
output pulses of programmable length and interval.
The repetition frequency is defined by an 8-bit prescaler
PWMP which generates the clock for the counter.
Both the prescaler and counter are common to both PWM
channels. The 8-bit counter counts modulo 255 i.e. from
0 to 254 inclusive. The value of the 8-bit counter is
compared to the contents of two registers:
given by: fPWM
=
--------------------------------------------------------------
2 × (PWMP + 1) × 255
When using an oscillator frequency of 16 MHz, for
example, the above formula would give a repetition
frequency range of 123 Hz to 31.4 kHz.
By loading the PWM registers with either 00H or FFH, the
PWM outputs can be retained at a constant HIGH or LOW
level respectively. When loading FFH to the PWM
registers, the 8-bit counter will never actually reach this
(FFH) value.
PWM0 and PWM1.
Provided the contents of either of these registers is greater
than the counter value, the output of PWM0 or PWM1 is
set LOW. If the contents of these register are equal to, or
less than the counter value, the output will be HIGH. The
pulse-width-ratio is therefore defined by the contents of
the register PWM0 and PWM1. The pulse-width-ratio is in
Both output pins PWMn are driven by push-pull drivers,
and are not shared with any other function.
the range of 0 to 255
⁄255 and may be programmed in
increments of 1⁄255
.
1996 Jun 27
17
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
9.1
Prescaler frequency control register (PWMP)
Table 7 Prescaler frequency control register (address FEH)
7
6
5
4
3
2
1
0
PWMP.7
PWMP.6
PWMP.5
PWMP.4
PWMP.3
PWMP.2
PWMP.1
PWMP.0
Table 8 Description of PWMP bits
BIT
SYMBOL
FUNCTION
7 to 0
PWMP.7
to
Prescaler division factor.
The Prescaler division factor = (PWMP) + 1
PWMP.0
9.2
Pulse Width Register 0 (PWM0)
Table 9 Pulse Width Register (address FCH)
7
6
5
4
3
2
1
0
PWM0.7
PWM0.6
PWM0.5
PWM0.4
PWM0.3
PWM0.2
PWM0.1
PWM0.0
Table 10 Description of PWM0 bits
BIT
SYMBOL
FUNCTION
7 to 0
PWM0.7
to
PWM0.0
Pulse width ratio.
LOW/HIGH ratio of PWMn signals
(PWMn)
255 – (PWMn)
=
-----------------------------------------
9.3
Pulse Width Register 1 (PWM1)
Table 11 Pulse width register (address FDH)
7
6
5
4
3
2
1
0
PWM1.7
PWM1.6
PWM1.5
PWM1.4
PWM1.3
PWM1.2
PWM1.1
PWM1.0
Table 12 Description of PWM1 bits
BIT
SYMBOL
FUNCTION
7 to 0
PWM1.7
to
PWM1.0
Pulse width ratio.
LOW/HIGH ratio of PWMn signals
(PWMn)
-----------------------------------------
255 – (PWMn)
=
1996 Jun 27
18
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
PWM0
I
N
OUTPUT
BUFFER
PWM0
8-BIT COMPARATOR
8-BIT COUNTER
T
E
R
N
A
L
f
clk
1/2
PRESCALER
PWMP
B
U
S
OUTPUT
BUFFER
PWM1
8-BIT COMPARATOR
PWM1
MGA154
Fig.9 Functional diagram of Pulse Width Modulated outputs.
The result of a completed conversion (ADCI = HIGH)
remains unaffected during the Idle mode.
10 ANALOG-TO-DIGITAL CONVERTER (ADC)
The analog input circuitry consists of an 8-input analog
multiplexer and an ADC with 10-bit resolution. The analog
reference voltage and analog power supplies are
connected via separate input pins. The conversion takes
50 machine cycles i.e. 37.5 µs at 16 MHz oscillator
The LOW-to-HIGH transition of STADC is recognized at
the end of a machine cycle and the conversion
commences at the beginning of the next cycle. When a
conversion is initiated by software, the conversion starts at
the beginning of the machine cycle following the
instruction that sets ADCS.
frequency. The input voltage swing is from 0 V to AVDD
.
The ADC is controlled using the ADCON control register.
Register bits ADCON.0 to ADCON.2 select the input
channels of the analog multiplexer (see Fig.10).
The completion of the 10-bit analog-to-digital conversion is
flagged by ADCI in the ADCON register and the result is
stored in the SFR ADCH (upper 8-bits) and the 2 lower bits
(ADC.1 and ADC.0) in register ADCON.
The next two machine cycles are used to initiate the
converter. At the end of this first cycle, the ADCS status
flag is set to HIGH while the conversion is in progress.
Sampling of the analog input commences at the end of the
second cycle.
During the next eight machine cycles, the voltage at the
previously selected pin of Port 5 is sampled and this input
voltage should be stable in order to obtain a useful sample.
In any case, the input voltage slew rate must be less than
10 V/ms (5 V conversion range) in order to prevent an
undefined result. The conversion takes four machine
cycles per bit.
An analog-to-digital conversion in progress is unaffected
by an external or software ADC start. The result of a
completed conversion remains unchanged provided
ADCI = HIGH. While ADCI or ADCS are HIGH, a new ADC
START will be blocked and consequently lost. An
analog-to-digital conversion already in progress is aborted
when the Idle or Power-down mode is entered.
1996 Jun 27
19
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
10.1 ADC Control register (ADCON)
Table 13 ADC Control register (address C5H)
7
6
5
4
3
2
1
0
ADC.1
ADC.0
ADEX
ADCI
ADCS
AADR2
AADR1
AADR0
Table 14 Description of the ADCON bits
BIT
SYMBOL
FUNCTION
7
6
5
ADC.1
ADC.0
ADEX
Bit 1 of ADC converted value.
Bit 0 of ADC converted value.
Enable external start of conversion by STADC. If ADEX is:
LOW, then conversion cannot be started externally by STADC (only by software by
setting ADCS)
HIGH, then conversion can be started externally by a rising edge on STADC or
externally.
4
3
ADCI
ADC interrupt flag. This flag is set when an analog-to-digital conversion result is ready
to be read.
If enabled, an interrupt is invoked. The flag must be cleared by software.
It cannot be set by software (see Table 15).
ADCS
ADC start and status. Setting this bit starts an analog-to-digital conversion. It may be
set by software or by the external signal STADC. The ADC logic ensures that this signal
is HIGH while the ADC is busy. On completion of the conversion, ADCS is reset at the
same time the interrupt flag ADCI is set. ADCS can not be reset by software (see
Table 15).
2
1
0
AADR2
AADR1
AADR0
Analog input select. This binary coded address selects one of the eight analog port
pins of P5 to be input to the converter. It can only be changed when ADCI and ADCS
are both LOW. AADR2 is the MSB (e.g. 100B selects the analog input channel ADC4).
Table 15 ADCI and ADCS operating modes
If ADCI is cleared by software while ADCS is set at the same time a new analog-to-digital conversion with the same
channel-number may be started. It is recommended to reset ADCI before ADCS is set.
ADCI
ADCS
OPERATION
0
0
1
0
ADC not busy, a conversion can be started.
ADC busy, start of a new conversion is blocked.
Conversion completed (note 1).
1
X (don’t care)
Note
1. Start of a new conversion requires ADCI = 0.
1996 Jun 27
20
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
STADC
h
ADC0
ADC1
ADC2
analog reference
ADC3
ADC4
ADC5
ADC6
ADC7
ANALOG INPUT
MULTIPLEXER
10-BIT A/D
CONVERTER
supply (analog part)
ground (analog part)
ADCON
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
ADCH
INTERNAL BUS
MGA155
Fig.10 Functional diagram of analog input.
1996 Jun 27
21
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
when it overflows from all HIGHs to all LOWs
11 TIMERS/COUNTERS
(or automatic reload value), with the exception of Mode 3
as previously described.
The P8xCE598 contains:
• Three 16-bit timer/event counters:
Timer 0, Timer 1 and Timer 2
11.2 Timer T2 Capture and Compare Logic
• One 8-bit timer, T3 (Watchdog WDT).
Timer T2 is a 16-bit timer/counter which has capture and
compare facilities (see Fig.11).
11.1 Timer 0 and Timer 1
The 16-bit timer/counter is clocked via a prescaler with a
programmable division factor of 1, 2, 4 or 8. The input of
the prescaler is clocked with 1⁄12 of the oscillator
Timer 0 and Timer 1 may be programmed to carry out the
following functions:
• Measure time intervals and pulse durations
• Count events
frequency, or by an external source connected to the T2
input, or it is switched off. The maximum repetition rate of
the external clock source is 1⁄12fCLK, twice that of Timer 0
and Timer 1. The prescaler is incremented on a rising
edge. It is cleared if its division factor or its input source is
changed, or if the timer/counter is reset.
• Generate interrupt requests.
Timer 0 and Timer 1 can be programmed independently to
operate in 3 modes:
T2 is readable ‘on the fly’, without any extra read latches;
this means that software precautions have to be taken
against misinterpretation at overflow from least to most
significant byte while T2 is being read. T2 is not loadable
and is reset by the RST signal or at the positive edge of the
input signal RT2, if enabled. In the Idle mode the
Mode 0 8-bit timer or 8-bit counter each with divide-by-32
prescaler.
Mode 1 16-bit timer-interval or event counter.
Mode 2 8-bit timer-interval or event counter with
automatic reload upon overflow.
timer/counter and prescaler are reset and halted.
Timer 0 can be programmed to operate in an additional
mode as follows:
T2 is connected to four 16-bit Capture Registers: CT0,
CT1, CT2 and CT3. A rising or falling edge on the inputs
CT0I, CT1I, CT2I or CT3I (alternative function of Port 1)
results in loading the contents of T2 into the respective
Capture Registers and an interrupt request.
Mode 3 one 8-bit time-interval or event counter and one
8-bit timer-interval counter.
When Timer 0 is in Mode 3, Timer 1 can be programmed
to operate in Modes 0, 1 or 2 but cannot set an interrupt
flag or generate an interrupt. However, the overflow from
Timer 1 can be used to pulse the Serial Port baud-rate
generator.
Using the Capture Register CTCON, these inputs may
invoke capture and interrupt request on a positive edge, a
negative edge or on both edges. If neither a positive nor a
negative edge is selected for capture input, no capture or
interrupt request can be generated by this input.
The frequency handling range of these counters with a
16 MHz crystal is as follows:
The contents of the Compare Registers CM0, CM1 and
CM2 are continually compared with the counter value of
Timer T2. When a match occurs, an interrupt may be
invoked. A match of CM0 sets the bits 0 to 5 of Port 4, a
CM1 match resets these bits and a CM2 match toggles bits
6 and 7 of Port 4, provided these functions are enabled by
the STE/RTE registers. A match of CM0 and CM1 at the
same time results in resetting bits 0 to 5 of Port 4. CM0,
CM1 and CM2 are reset by the RST signal.
• In the timer function, the timer is incremented at a
frequency of 1.33 MHz (1⁄12 of the oscillator frequency)
• 0 Hz to an upper limit of 0.66 MHz (1⁄24 of the oscillator
frequency) when programmed for external inputs.
Both internal and external inputs can be gated to the
counter by a second external source for directly measuring
pulse durations. When configured as a counter, the
register is incremented on every falling edge on the
corresponding input pin, T0 or T1.
Port 4 can be read and written by software without
affecting the toggle, set and reset signals. At a byte
overflow of the least significant byte, or at a 16-bit overflow
of the timer/counter, an interrupt sharing the same
interrupt vector is requested. Either one or both of these
overflows can be programmed to request an interrupt.
All interrupt flags must be reset by software.
The earliest moment, when the incremented register value
can be read is during the second machine cycle following
the machine cycle within which the incrementing pulse
occurred.The counters are started and stopped under
software control. Each one sets its interrupt request flag
1996 Jun 27
22
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
CT0I
INT
CT1I
INT
CT2I
INT
CT3I
INT
CTI0
CTI1
CTI2
CTI3
CT0
CT1
CT2
CT3
off
8-bit overflow interrupt
16-bit overflow interrupt
f
1/12
CLK
PRESCALER
T2 COUNTER
T2
RT2
T2ER
external reset
enable
INT
INT
INT
COMP
COMP
COMP
S
S
S
S
S
S
R
R
R
R
R
R
T
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
CM0 (S)
CM1 (R)
CM2 (T)
I/O port 4
MGA156
TG
TG
T
STE
RTE
S
R
T
= set
= reset
= toggle
T2 SFR address: TML2 = lower 8 bits
TMH2 = higher 8 bits
TG = toggle status
Fig.11 Block diagram of Timer T2 configuration.
1996 Jun 27
23
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
11.2.1 COUNTER CONTROL REGISTER (TM2CON)
Table 16 Counter Control register (address EAH)
7
6
5
4
3
2
1
0
T2IS1
T2IS0
T2ER
T2B0
T2P1
T2P0
T2MS1
T2MS0
Table 17 Description of the TM2CON bits
BIT
SYMBOL
T2IS1
FUNCTION
7
6
5
4
3
2
1
0
Timer 2 16-bit overflow interrupt select.
Timer 2 byte overflow interrupt select.
Timer 2 external reset enable.
T2IS0
T2ER
T2B0
Timer 2 byte overflow interrupt flag.
Timer 2 prescaler select (see Table 18).
T2P1
T2P0
T2MS1
T2MS0
Timer 2 mode select (see Table 19).
Table 18 Timer 2 prescaler select
Table 19 Timer 2 mode select
T2P1
T2P0
T2 CLOCK
Clock source
1⁄2 Clock source
1⁄4 Clock source
1⁄8 Clock source
T2MS1
T2MS0
MODE
Timer T2 is halted
T2 clock source = 1⁄12fCLK
Test mode; do not use
T2 clock source = pin T2
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
11.2.2 CAPTURE CONTROL REGISTER (CTCON)
Table 20 Capture Control register (address EBH)
7
6
5
4
3
2
1
0
CTN3
CTP3
CTN2
CTP2
CTN1
CTP1
CTN0
CTP0
Table 21 Description of the CTCON bits
FUNCTION
INTERRUPT ON
BIT
SYMBOL
CTN3
CAPTURE
CT3I
7
6
5
4
3
2
1
0
negative edge
positive edge
negative edge
positive edge
negative edge
positive edge
negative edge
positive edge
CTP3
CTN2
CTP2
CTN1
CTP1
CTN0
CTP0
CT3I
CT2I
CT2I
CT1I
CT1I
CT0I
CT0I
1996 Jun 27
24
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
11.2.3 TIMER INTERRUPT FLAG REGISTER (TM2IR)
Table 22 Timer Interrupt Flag register (address C8H)
7
6
5
4
3
2
1
0
T2OV
CMI2
CMI1
CMI0
CTI3
CTI2
CTI1
CTI0
Table 23 Description of the TM2IR bits (see notes 1 and 2)
BIT
SYMBOL
T2OV
FUNCTION
7
6
5
4
3
2
1
0
T2: 16-bit overflow interrupt flag.
CM2: interrupt flag.
CM1: interrupt flag.
CM0: interrupt flag.
CT3: interrupt flag.
CMI2
CMI1
CMI0
CTI3
CTI2
CTI1
CTI0
CT2: interrupt flag.
CT1: interrupt flag.
CT0: interrupt flag.
Notes
1. Interrupt Enable IEN1 is used to enable/disable Timer 2 interrupts (see Section 14.1.2).
2. Interrupt Priority Register IP1 is used to determine the Timer 2 interrupt priority (see Section 14.1.4).
11.2.4 SET ENABLE REGISTER (STE)
Table 24 Set Enable register (address EEH)
7
6
5
4
3
2
1
0
TG47
TG46
SP45
SP44
SP43
SP42
SP41
SP40
Table 25 Description of the STE bits (see notes 1 and 2)
BIT
SYMBOL
TG47
FUNCTION
7
6
5
4
3
2
1
0
if HIGH then P4.7 is reset on the next toggle, if LOW P4.7 is set on the next toggle.
if HIGH then P4.6 is reset on the next toggle, if LOW P4.6 is set on the next toggle.
if HIGH then P4.5 is set on a match of CM0 and T2.
TG46
SP45
SP44
SP43
SP42
SP41
SP40
if HIGH then P4.4 is set on a match of CM0 and T2.
if HIGH then P4.3 is set on a match of CM0 and T2.
if HIGH then P4.2 is set on a match of CM0 and T2.
if HIGH then P4.1 is set on a match of CM0 and T2.
if HIGH then P4.0 is set on a match of CM0 and T2.
Notes
1. If STE.n is LOW then P4.n is not affected by a match of CM0 and T2 (n = 0, 1, 2, 3, 4, 5).
2. STE.6 and STE.7 are read only.
1996 Jun 27
25
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
11.2.5 RESET/TOGGLE ENABLE REGISTER (RTE)
Table 26 Reset/Toggle Enable register (address EFH)
7
6
5
4
3
2
1
0
TP47
TP46
RP45
RP44
RP43
RP42
RP41
RP40
Table 27 Description of the RTE bits (note 1)
BIT
SYMBOL
TP47
FUNCTION
7
6
5
4
3
2
1
0
if HIGH then P4.7 toggles on a match of CM2 and T2.
if HIGH then P4.6 toggles on a match of CM2 and T2.
if HIGH then P4.5 is reset on a match of CM1 and T2.
if HIGH then P4.4 is reset on a match of CM1 and T2.
if HIGH then P4.3 is reset on a match of CM1 and T2.
if HIGH then P4.2 is reset on a match of CM1 and T2.
if HIGH then P4.1 is reset on a match of CM1 and T2.
if HIGH then P4.0 is reset on a match of CM1 and T2.
TP46
RP45
RP44
RP43
RP42
RP41
RP40
Note
1. If RTE.n is LOW then P4.n is not affected by a match of CM1 and T2 or CM2 and T2.
For more information, refer to the 8051-based “8-bit Microcontrollers Data Handbook IC20”.
1996 Jun 27
26
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
The Watchdog Timer can only be reloaded if the condition
flag WLE = PCON.4 has been previously set by software.
At the moment the counter is loaded the condition flag is
automatically cleared.
11.3 Watchdog Timer (T3)
In addition to Timer T2 and the standard timers (Timer 0
and Timer 1), a Watchdog Timer (WDT) comprising an
11-bit prescaler and an 8-bit timer (T3) is also provided
(see Fig.12).
The timer interval between the timer's reloading and the
occurrence of a reset depends on the reloaded value. For
example, this may range from 1.5 ms to 0.375 s when
using an oscillator frequency of 16 MHz.
The timer T3 is incremented every 1.5 ms, derived from
the oscillator frequency of 16 MHz by the following
fCLK
formula: ftimer
=
-------------------------
In the Idle state the Watchdog Timer and reset circuitry
remain active.
12 × 2048
When a timer T3 overflow occurs, the microcontroller is
reset and a reset-output-pulse is generated at pin RST.
This short output pulse (3 machine cycles) may be
suppressed if the RST pin is connected to a capacitor.
The Watchdog Timer (WDT) is controlled by the Enable
Watchdog pin (EW); see Table 28.
Table 28 EW controlling WDT and Power-down mode
To prevent a system reset (by an overflow of the WDT), the
user program has to reload T3 within periods that are
shorter than the programmed Watchdog time interval.
PIN EW
LOW
WDT
POWER-DOWN MODE
disabled
enabled
disabled
HIGH
enabled
If the processor suffers a hardware/software malfunction,
the software will fail to reload the timer. This failure will
produce a reset upon overflow thus preventing the
processor running out of control.
INTERNAL BUS
V
DD
PRESCALER
11-BIT
1/12 f
overflow
P
CLK
TIMER T3 (8-BIT)
CLEAR
LOAD
LOADEN
RST
internal
reset
CLEAR
R
write
T3
RST
WLE
PD
LOADEN
PCON.4
PCON.1
EW
INTERNAL BUS
MGA157
Fig.12 Functional diagram of T3 Watchdog Timer.
27
1996 Jun 27
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
This feature is enabled by setting bit SM2 in S0CON. This
feature may be used in multiprocessor systems.
12 SERIAL I/O PORT: SIO0 (UART)
The Serial Port SIO0 is a full duplex (UART) serial I/O port
i.e. it can transmit and receive simultaneously. This Serial
Port is also receive-buffered. It can commence reception
of a second byte before the previously received byte has
been read from the receive register. However, if the first
byte has still not been read by the time reception of the
second byte is complete, one of these (first or second)
bytes will be lost. The SIO0 receive and transmit registers
are both accessed via the S0BUF SFR. Writing to S0BUF
loads the transmit register, and reading S0BUF accesses
to a physically separate receive register. SIO0 can operate
in 4 modes:
For more information about how to use the UART in
combination with the registers S0CON, PCON, IE, SBUF
and the Timer register, refer to the 8051-based
“8-bit Microcontrollers Data Handbook IC20”.
13 SERIAL I/O PORT: SIO1 (CAN)
SIO1 (CAN) provides the CAN (Controller Area Network)
serial-bus data communication interface. SIO1 (CAN)
replaces the SIO1 (I2C) serial interface as provided in the
microcontroller derivative P8xC552.
Mode 0 Serial data is transmitted and received through
RXD. TXD outputs the shift clock. 8 data bits are
transmitted/received (LSB first). The baud rate is
fixed at 1⁄12 of the oscillator frequency.
13.1 On-chip CAN-controller
CAN is the definition of a high performance
communication protocol for serial data communication.
The P8xCE598 on-chip CAN-controller is a full
implementation of the CAN 2.0A protocol. With the
P8xCE598 powerful local networks can be built, both for
automotive and general industrial environments. This
results in a much reduced wiring harness and enhanced
diagnostic and supervisory capabilities.
Mode 1 10 bits are transmitted via TXD or received
through RXD: a start bit (0), 8 data bits (LSB first),
and a stop bit (1). On receive, the stop bit is put
into RB8 of the S0CON SFR. The baud rate is
variable.
Mode 2 11 bits are transmitted through TXD or received
through RXD: a start bit (0), 8 data bits (LSB first),
a programmable 9th data bit, and a stop bit (1).
On transmit, the 9th data bit (TB8 in S0CON) can
be assigned the value of 0 or 1. With nominal
software, TB8 can be the parity bit (P in PSW).
During a receive, the 9th data bit is stored in RB8
(S0CON), and the stop bit is ignored. The baud
rate is programmable to either 1⁄32 or 1⁄64 of the
oscillator frequency.
13.2 CAN Features
• Multi-master architecture
• Bus access priority determined by the message
identifier
• 2032 message identifier (211 standard frame CAN 2.0A)
• Guaranteed latency time for high priority messages
• Powerful error handling capability
• Data length from 0 up to 8 bytes
Mode 3 11 bits are transmitted through TXD or received
through RXD: a start bit (0), 8 data bits (LSB first),
a programmable 9th data bit, and a stop bit (1).
Mode 3 is the same as Mode 2 except for the
baud rate which is variable in Mode 3.
• Multicast and broadcast message facility
• Non destructive bit-wise arbitration
• Non-return-to-zero (NRZ) coding/decoding with
bit-stuffing
In all four modes, transmission is initiated by any
instruction that writes to the S0BUF SFR.
Reception is initiated in Mode 0 when RI = 0 and REN = 1.
In the other three modes, reception is initiated by the
incoming start bit provided that REN = 1.
• Programmable transfer rate (up to 1 Mbit/s)
• Programmable output driver configuration
• Suitable for use in a wide range of networks including
the SAE's network classes A, B and C
• DMA providing high-speed on-chip data exchange
• Bus failure management facility
Modes 2 and 3 are provided for multiprocessor
communications. In these modes, 9 data bits are received
with the 9th bit written to RB8 (S0CON). The 9th bit is
followed by the stop bit. The port can be programmed so
that with receiving the stop bit, the Serial Port interrupt will
be activated if, and only if RB8 = 1.
•
1⁄2AVDD reference voltage.
1996 Jun 27
28
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
It controls the communication flow through the area
13.3 Interface between CPU and CAN
network using the CAN-protocol. The CAN-controller
meets the following requirements:
The internal interface between the P8xCE598's CPU and
on-chip CAN-controller is achieved via the following four
SFRs (see Fig.13):
• Short message length
• Bus access priority, determined by the message
identifier
• CANADR, to point to a register of the CAN-controller
• CANDAT, to read or write data
• Powerful error handling capability
• CANCON, to read interrupt flags and to write commands
• Configuration flexibility to allow area network expansion
• Guaranteed latency time for urgent messages;
• CANSTA, to read status information and to write DMA
pointer.
– The latency time defines the period between the
initiation (Transmission Request) and the start of the
transmission on the bus. The latency time strongly
depends on a large variety of bus-related conditions.
In the case of a message being transmitted on the
bus and one distortion, the latency time can be up to
149 bit times (worst case). For more information see
Chapter 22, “CAN application information”.
Additionally, the DMA-logic allows a high-speed data
exchange between the CAN-controller and the CPU's
on-chip Main RAM. For more information, see
Section 13.5.15 “Handling of the CPU-CAN interface”.
13.4 Hardware blocks of the CAN-controller
The P8xCE598 CAN-controller contains all necessary
hardware for high performance serial network
communications (see Fig.14 and Table 29).
internal
bus
4 special function
registers
ADDRESS
DBH
DAH
D9H
D8H
CANADR
DATA
CANDAT
CANCON
CANSTA
CPU
CAN
CONTROLLER
MAIN
RAM
DMA
LOGIC
DMA bus
MGA158
Fig.13 Interface between CPU and CAN-controller.
29
1996 Jun 27
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
CRX0
and
CRX1
2
2
address
INTERFACE
MANAGEMENT
BIT TIMING
LOGIC
data
LOGIC
CTX0
and
CTX1
TRANSMIT
BUFFER
TRANSCEIVER
LOGIC
CAN
CONTROLLER
ON - CHIP
ERROR
MANAGEMENT
LOGIC
RECEIVE
BUFFER 0
RECEIVE
BUFFER 1
BIT STREAM
PROCESSOR
MGA159
Fig.14 Block diagram of the P8xCE598 on-chip CAN-controller.
Table 29 Hardware blocks of the CAN-controller (see Fig.14)
NAME BLOCK
Interface Management Logic IML
DESCRIPTION
Interprets commands from the CPU, allocates the message buffers
(TBF, RBF0 and RBF1) and provides interrupts and status information to the
microcontroller.
Transmit Buffer
TBF
10 bytes memory into which the CPU writes messages which are to be
transmitted over the CAN network.
Receive Buffers (0 and 1)
RBF0
RBF1
RBF0 and RBF1 are each 10 bytes memories which are alternatively used to
store messages received from the CAN network.
The CPU can process one message while another is being received.
Bit Stream Processor
BSP
Is a sequencer, controlling the data stream between the Transmit Buffer,
Receive Buffers (parallel data) and the CAN-bus (serial data).
Bit Timing Logic
BTL
TCL
EML
Synchronizes the CAN-controller to the bitstream on the CAN-bus.
Controls the output driver.
Transceiver Control Logic
Error Management Logic
Performs the error confinement according to the CAN-protocol.
1996 Jun 27
30
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
13.5 Control Segment and Message Buffer
description
After a successful reception the CPU may read the
message from the Receive Buffer and then release it for
further use.
The CAN-Controller appears to the CPU as a
memory-mapped peripheral, guaranteeing the
independent operation of both parts.
13.5.2 CONTROL SEGMENT LAYOUT
The exchange of status, control and command signals
between the CPU and the CAN-controller is performed in
the control segment. The layout of this segment is shown
in Fig.15. After an initial down-load, the contents of the
registers Acceptance Code, Acceptance Mask,
Bus Timing 0, Bus Timing 1 and Output Control should not
be changed. These registers may only be accessed when
the Reset Request bit in the Control Register is set HIGH
(see Tables 30, 31 and 32).
13.5.1 ADDRESS ALLOCATION
The address area of the CAN-controller consists of the
Control Segment and the message buffers. The Control
Segment is programmed during an initialization down-load
in order to configure communication parameters (e.g. bit
timing). The communication over the CAN-bus is also
controlled via this segment by the CPU. A message which
is to be transmitted, must be written to the Transmit Buffer.
ADDRESS
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0
1
2
3
4
5
6
7
8
9
CONTROL
COMMAND
STATUS
INTERRUPT
ACCEPTANCE CODE
ACCEPTANCE MASK
BUS TIMING 0
BUS TIMING 1
OUTPUT CONTROL
TEST
control segment
0AH 10 IDENTIFIER,
descriptor
data field
0BH 11 RTR BIT, DATA LENGTH CODE
0CH 12 BYTE 1
13 BYTE 2
0DH
0EH 14 BYTE 3
transmit buffer
15 BYTE 4
16 BYTE 5
17 BYTE 6
18 BYTE 7
0FH
10H
11H
12H
13H 19 BYTE 8
14H 20 IDENTIFIER,
IDENTIFIER,
descriptor
data field
21 RTR BIT, DATA LENGTH CODE
RTR BIT, DATA LENGTH CODE
15H
16H
17H
22 BYTE 1
23 BYTE 2
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
BYTE 8
18H 24 BYTE 3
receive buffer 0 or 1
25 BYTE 4
26 BYTE 5
19H
1AH
1BH 27 BYTE 6
28 BYTE 7
1CH
1DH 29 BYTE 8
MGA160 - 1
Fig.15 CAN-controller internal address allocation.
31
1996 Jun 27
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Table 30 CPU/CAN Register map
BIT
7
6
5
4
3
2
1
0
Control Segment
ADDRESS 0: CONTROL REGISTER
TM
S
RA
OIE
EIE
TIE
RIE
AT
RR
ADDRESS 1: COMMAND REGISTER
RX0A
RX1A
WUM
TS
SLP
RS
COS
TCS
OI
RRB
TBS
EI
TR
ADDRESS 2: STATUS REGISTER
BS
ES
DO
TI
RBS
RI
ADDRESS 3: INTERRUPT REGISTER
Reserved
Reserved
Reserved
WUI
AC.4
AM.4
ADDRESS 4: ACCEPTANCE CODE REGISTER
AC.7
AC.6
AC.5
AC.3
AM.3
AC.2
AM.2
AC.1
AM.1
AC.0
AM.0
BRP.0
ADDRESS 5: ACCEPTANCE MASK REGISTER
AM.7
AM.6
AM.5
ADDRESS 6: BUS TIMING REGISTER 0
SJW.1
SJW.0
BRP.5
BRP.4
BRP.3
BRP.2
BRP.1
ADDRESS 7: BUS TIMING REGISTER 1
SAM
TSEG2.2
TSEG2.1
TESG2.0
OCTP0
TSEG1.3
OCTN0
TSEG1.2
OCPOL0
TSEG1.1
OCMODE1
Normal
TSEG1.0
ADDRESS 8: OUTPUT CONTROL REGISTER
OCTP1
OCTN1
OCPOL1
OCMODE0
ADDRESS 9: TEST REGISTER (note 1)
Reserved
Reserved
Map Internal Connect RX Connect TX Access
Register
Float Output
Driver
Buffer 0
CPU
Buffer CPU
Internal Bus RAM
Connect
1996 Jun 27
32
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
BIT
7
6
5
4
3
2
1
0
Transmit Buffer
ADDRESS 10: IDENTIFIER
ID.10
ID.9
ID.8
ID.7
RTR
Data
ID.6
ID.5
ID.4
ID.3
ADDRESS 11: RTR, DATA LENGTH CODE
ID.2
ID.1
ID.0
DLC.3
Data
DLC.2
Data
DLC.1
Data
DLC.0
Data
ADDRESS 12 TO 19: BYTES 1 TO 8
Data
Data
Data
Receive Buffer 0 and 1
ADDRESS 20: IDENTIFIER
ID.10
ID.9
ID.8
ID.7
RTR
Data
ID.6
ID.5
ID.4
ID.3
ADDRESS 21: RTR, DATA LENGTH CODE
ID.2
ID.1
ID.0
DLC.3
Data
DLC.2
Data
DLC.1
Data
DLC.0
Data
ADDRESS 22 TO 29: BYTES 1 TO 8
Data
Data
Data
Note
1. The Test Register is used for production testing only.
13.5.3 CONTROL REGISTER (CR)
The contents of the Control Register are used to change the behaviour of the CAN-controller. Control bits may be set or
reset by the CPU which uses the Control Register as a read/write memory.
Table 31 Control Register (address 0)
7
6
5
4
3
2
1
0
TM
S
RA
OIE
EIE
TIE
RIE
RR
Table 32 Description of the CR bits
BIT
SYMBOL
TM
FUNCTION
Test Mode (note 1).If the value of TM is:
7
HIGH (enabled), then the CAN-controller enters Test Mode (normal operations
impossible).
LOW (disabled), then the CAN-controller is in normal operating mode.
6
S
Sync (note 2). If the value of S is:
HIGH (2 edges), then bus-line transitions from recessive-to-dominant and vice-versa
are used for resynchronization (see Sections 13.5.20 and 13.6).
LOW (1 edge), then the only transitions from recessive-to-dominant are used for
resynchronization.
1996 Jun 27
33
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
BIT
SYMBOL
RA
FUNCTION
Reference Active (note 2). If the value of RA is:
HIGH (output), then the pin REF is an 1⁄2AVDD reference output.
LOW (input), then a reference voltage may be input.
Overrun Interrupt Enable. If the value of OIE is:
5
4
OIE
HIGH (enabled) and the Data Overrun bit is set (see Section 13.5.5) then the CPU
receives an Overrun Interrupt signal.
LOW (disabled), then the CPU receives no Overrun Interrupt signal from the
CAN-controller.
3
2
EIE
TIE
Error Interrupt Enable. If the value of EIE is:
HIGH (enabled) and the Error or Bus Status change (see Section 13.5.5) then the CPU
receives an Error Interrupt signal.
LOW (disabled), then the CPU receives no Error Interrupt signal.
Transmit Interrupt Enable. If the value of TIE is:
HIGH (enabled) and when a message has been successfully transmitted or the
Transmit Buffer is accessible again, (e.g. after an Abort Transmission command), then
the CAN-controller transmits a Transmit Interrupt signal to the CPU.
LOW (disabled), then there is no transmission of the Transmit Interrupt signal by the
CAN-controller to the CPU.
1
0
RIE
RR
Receive Interrupt Enable. If the value of RIE is:
HIGH (enabled) and when a message has been received without errors, then the
CAN-controller transmits a Receive Interrupt signal to the CPU.
LOW (disabled), then there is no transmission of the Receive Interrupt signal by the
CAN-controller to the CPU.
Reset Request (note 3). If the value of RR is:
HIGH (present), then detection of a Reset Request results in the CAN-controller
aborting the current transmission/reception of a message entering the reset state
synchronously to the system clock (tSCL, see Section 13.5.9).
LOW (absent), on the HIGH-to-LOW transition of the Reset Request bit, the
CAN-controller returns to its normal operating state.
Notes to the description of the CR bits
1. The test mode is intended for factory testing and not for customer use.
2. A modification of the bits Reference Active and Sync is only possible with Reset Request = HIGH (present). It is
allowed to set these bits while Reset Request is changed from a HIGH level to a LOW level. After an external reset
(pin RST = HIGH) the Reference Active bit is set HIGH (output), the Sync bit is undefined.
3. During an external reset (RST = HIGH) or when the Bus Status bit is set HIGH (Bus-OFF), the IML forces the
Reset Request HIGH (present). After the Reset Request bit is set LOW (absent) the CAN-controller will wait for:
a) One occurrence of the Bus-Free signal (11 recessive bits, see Section 13.6.9.6), if the preceding reset (Reset
Request = HIGH) has been caused by an external reset or a CPU initiated reset.
b) 128 occurrences of Bus-Free, if the preceding reset (Reset Request = HIGH) has been caused by a
CAN-controller initiated Bus-OFF, before re-entering the Bus-On mode, see Section 13.6.9.
c) When Reset Request is set HIGH (present), for whatever reason, the Control, Command, Status and Interrupt
bits are affected, see Table 40. The registers at addresses 4 to 8 are only accessible when the Reset Request is
set HIGH (present).
1996 Jun 27
34
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
RX0 ACTIVE
RX1 ACTIVE
REFERENCE ACTIVE
REF
1/2AV
DD
- VOLTAGE
WAKE-UP MODE
single-ended
wake-up
1
0
WAKE-UP
(bus active signal)
S2
0
RX0
CRX0
differential
wake-up
S0
1
0
RX1
COMP OUT
CRX1
S1
1
P8xCE598
MLB231
Fig.16 Configurable CAN receiver.
1996 Jun 27
35
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
13.5.4 COMMAND REGISTER (CMR)
A command bit initiates an action within the transfer layer of the CAN-controller. The Command Register appears to the
CPU as a read/write memory, except for the bits CMR.0 (TR) to CMR.3 (COS), which return a HIGH if being read.
Table 33 Command Register (address 1)
7
6
5
4
3
2
1
0
RX0A
RX1A
WUM
SLP
COS
RRB
AT
TR
Table 34 Description of the CMR bits
BIT
SYMBOL
RX0A
FUNCTION
7
6
5
RX0 Active. See Table 35; note 1.
RX1 Active. See Table 35; note 1.
RX1A
WUM
Wake-up Mode (note 2). If the value of WUM is:
HIGH (single ended), then the difference of the RX signals to the internal reference
voltage 1⁄2AVDD is used for wake up.
LOW (differential), then the differential signal between RX0 and RX1 is used for wake
up.
4
SLP
Sleep (note 3). If the value of SLP is:
HIGH (sleep), then the CAN-controller enters sleep mode if no CAN interrupt is
pending and there is no bus activity.
LOW (wake up), then the CAN-controller functions normally.
Clear Overrun Status (note 4). If the value of COS is:
HIGH (clear), then the Data Overrun status bit is set to LOW (see Table 37).
LOW (no action), then there is no action.
3
2
1
COS
RRB
AT
Release Receive Buffer (note 5). If the value of RRB is:
HIGH (released), then the Receive Buffer attached to the CPU is released.
LOW (no action), then there is no action.
Abort Transmission (note 6). If the value of AT is:
HIGH (present) and if not already in progress, a pending Transmission Request is
cancelled.
LOW (absent), then there is no action.
0
TR
Transmission Request (note 7). If the value of TR is:
HIGH (present), then a message shall be transmitted.
LOW (absent), then there is no action.
1996 Jun 27
36
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Notes to the description of the CMR bits
1. The RX0/RX1 Active bits, if being read, reflect the status of the respective switches (see Fig.16). It is recommended
to change the switches only during the reset state (Reset Request = HIGH).
2. The Wake-Up Mode bit should be set at the same time as the Sleep bit. The differential wake up mode is useful if
both bus wires are fully functioning; it minimizes the amount of wake ups due to noise. The single ended wake up
mode is recommended if a wake up must be possible even if one bus wire is already or may become disturbed
(see Fig.16).
3. The CAN-controller will enter sleep mode, if the Sleep bit is set HIGH (sleep) there is no bus activity and no interrupt
is pending. The CAN-controller will wake up after the Sleep bit is set LOW (wake up) or when there is bus activity.
On wake up, a Wake-Up Interrupt (see Section 13.5.6) is generated (see also Chapter 15). A CAN-controller which
is sleeping and then awaken by bus activity will not be able to receive this message until it detects a Bus-Free signal
(see Section 13.6.9.6). The Sleep bit, if read, reflects the status of the CAN-controller.
4. This command bit is used to acknowledge the Data Overrun condition signalled by the Data Overrun status bit.
Command is given only after releasing both receive buffers. The stored messages have to be rejected. The
command bit is set simultaneously with setting of the Release Receive Buffer command bit the second time.
5. After reading the contents of the Receive Buffer (RBF0 or RBF1) the CPU must release this buffer by setting Release
Receive Buffer bit HIGH (released). This may result in another message becoming immediately available.
To prevent the RRB command being executed only once, the minimum wait time between two successive RRB
commands is 3 system clock cycles (tSCL, see Section 13.5.9).
6. The Abort Transmission bit is used when the CPU requires the suspension of the previously requested transmission,
e.g. to transmit an urgent message. A transmission already in progress is not stopped. In order to see if the original
message had been either transmitted successfully or aborted, the Transmission Complete Status bit should be
checked. This should be done after the Transmit Buffer Access bit has been set HIGH (released) or a Transmit
Interrupt has been generated (see Section 13.5.6).
7. If the Transmission Request bit was set HIGH in a previous command, it cannot be cancelled by setting the
Transmission Request bit LOW (absent). Cancellation of the requested transmission may be performed by setting
the Abort Transmission bit HIGH (present).
Table 35 Combination of bits RX0A and RX1A (see Fig.16)
CONTROL
RX0
RX1
RX0ACTIVE
RX1ACTIVE
1
1
0
0
1
0
1
0
CRX0
CRX0
1⁄2AVDD
CRX1
1⁄2AVDD
CRX1
No action
1996 Jun 27
37
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
13.5.5 STATUS REGISTER (SR)
The contents of the Status Register reflects the status of the CAN-controller. The Status Register appears to the CPU
as a read only memory.
Table 36 Status Register (address 2)
7
6
5
4
3
2
1
0
BS
ES
TS
RS
TCS
TBS
DO
RBS
Table 37 Description of the SR bits
BIT
SYMBOL
BS
FUNCTION
Bus Status (note 1). If the value of BS is:
7
HIGH (Bus-OFF), then the CAN-controller is not involved in bus activities.
LOW (Bus-ON), then the CAN-controller is involved in bus activities.
Error Status. If the value of ES is:
6
ES
HIGH (error), then at least one of the Error Counters (see Section 13.6.10) has
reached the
CPU Warning limit.
LOW (ok), then both Error Counters have not reached the warning limit.
Transmit Status (note 2). If the value of TS is:
5
4
3
2
TS
HIGH (transmit), then the CAN-controller is transmitting a message.
LOW (idle), then no message is transmitted.
RS
Receive Status (note 2). If the value of RS is:
HIGH (receive), then the CAN-controller is receiving a message.
LOW (idle), then no message is received.
TCS
TBS
Transmission Complete Status (note 3). If the value of TCS is:
HIGH (complete), then last requested transmission has been successfully completed.
LOW (incomplete), then previously requested transmission is not yet completed.
Transmit Buffer Access (note 3). If the value of TBS is:
HIGH (released), then the CPU may write a message into the TBF.
LOW (locked), then the CPU cannot access the Transmit Buffer. A message is either
waiting for transmission or is in the process of being transmitted.
1
0
DO
Data Overrun (note 4). If the value of DO is:
HIGH (overrun), then both Receive Buffers are full and the first byte of another
message should be stored.
LOW (absent), then no data overrun has occurred since the Clear Overrun command
was given.
RBS
Receive Buffer Status (note 5). If the value of RBS is:
HIGH (full), then this bit is set when a new message is available.
LOW (empty), then no message has become available since the last Release Receive
Buffer command bit was set.
1996 Jun 27
38
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Notes to the description of the SR bits
1. When the Bus Status bit is set HIGH (Bus-OFF), the CAN-controller will set the Reset Request bit HIGH (present).
It will stay in this state until the CPU sets the Reset Request bit LOW (absent). Once this is completed the
CAN-controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) before setting
the Bus Status bit LOW (Bus-ON), the Error Status bit LOW (ok) and resetting the Error Counters. During Bus-OFF
the output drivers are switched off (floating); external transceiver circuits should output a recessive level in this case.
2. If both the Receive Status and Transmit Status bits are LOW (idle) the CAN-bus is idle.
3. If the CPU tries to write to the Transmit Buffer when the Transmit Buffer Access bit is LOW (locked), the written bytes
will not be accepted and will be lost without this being signalled. The Transmission Complete Status bit is set LOW
(incomplete) whenever the Transmission Request bit is set HIGH (present). If an Abort Transmission command is
issued, the Transmit Buffer will be released. If the message, which was requested and then aborted, was not
transmitted, the Transmission Complete Status bit will remain LOW.
4. If Data Overrun = HIGH (overrun) is detected, the currently received message is dropped. A transmitted message,
granted acceptance, is also stored in a Receive Buffer. This occurs because it is not known if the CAN-controller will
lose arbitration and so become a receiver of the message. If no Receive Buffer is available, Data Overrun is
signalled. However, this transmitted and accepted message does neither cause a Receive Interrupt nor set the
Receive Buffer Status bit to HIGH (full). Also, a Data Overrun does not cause the transmission of an Overload Frame
(see Sections 13.6.1 and 13.6.5).
5. If the command bit Release Receive Buffer is set HIGH (released) by the CPU, the Receive Buffer Status bit is set
LOW (empty) by IML. When a new message is stored in any of the receive buffers, the Receive Buffer Status bit is
set HIGH (full) again.
1996 Jun 27
39
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
13.5.6 INTERRUPT REGISTER (IR)
The Interrupt Register allows the identification of an interrupt source. When one or more bits of this register are set, a
CAN interrupt (SI01) will be indicated to the CPU. All bits are reset by the CAN-controller after this register is read by the
CPU. This register appears to the CPU as a read only memory.
Table 38 Interrupt Register (address 3)
7
6
5
4
3
2
1
0
−
−
−
WUI
OI
EI
TI
RI
Table 39 Description of the IR bits
BIT
SYMBOL
FUNCTION
7
6
5
4
−
−
−
Reserved.
Reserved.
Reserved.
WUI
Wake-Up Interrupt. The value of WUI is set to:
HIGH (set), when the sleep mode is left. See Section 13.5.4.
LOW (reset), by a read access of the Interrupt Register by the CPU.
3
OI
Overrun Interrupt (note 1). The value of OI is set to:
HIGH (set), if both Receive Buffers contain a message and the first byte of another
message should be stored (passed acceptance), and the Overrun Interrupt Enable is
HIGH (enabled).
LOW (reset), by a read access of the Interrupt Register by the CPU.
2
1
EI
TI
Error Interrupt. The value of EI is set to:
HIGH (set), on a change of either the Error Status or Bus Status bits, if the Error
Interrupt Enable is HIGH (enabled). See Section 13.5.5.
LOW (reset), by a read access of the Interrupt Register by the CPU.
Transmit Interrupt. The value of TI is set to:
HIGH (set), on a change of the Transmit Buffer Access from LOW to HIGH (released)
and
Transmit Interrupt Enable is HIGH (enabled).
LOW (reset), after a read access of the Interrupt Register by the CPU.
0
RI
Receive Interrupt (note 2). The value of RBS is set to:
HIGH (set), when a new message is available in the Receive Buffer and the Receive
Interrupt Enable bit is HIGH (enabled).
LOW (reset) automatically by a read access of Interrupt Register by the CPU.
Notes
1. Overrun Interrupt bit (if enabled) and Data Overrun bit (see Section 13.5.5) are set at the same time.
2. Receive Interrupt bit (if enabled) and Receive Buffer Status bit (see Section 13.5.5) are set at the same time.
1996 Jun 27
40
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Table 40 Effects of setting the Reset Request bit HIGH (present)
TYPE
BIT
CR.7
CR.5
SYMBOL
TM
FUNCTION
EFFECT
Control
Test Mode
LOW (disabled)
RA
Reference Active
RX0 Active
HIGH (output); note 1
HIGH (RX0 = CRX0); note 1
HIGH (RX1 = CRX1); note 1
LOW (wake-up)
HIGH (clear)
Command CMR.7
CMR.6
RX0A
RX1A
SLP
COS
RRB
AT
RX1 Active
CMR.4
Sleep
CMR.3
Clear Overrun Status
Release Receive Buffer
Abort Transmission
Transmission Request
Bus Status
CMR.2
HIGH (released)
LOW (absent)
CMR.1
CMR.0
TR
LOW (absent)
Status
SR.7
SR.6
SR.5
SR.4
SR.3
SR.2
SR.1
SR.0
IR.3
BS
LOW (Bus-On); note 1
LOW (no error); note 1
LOW (idle)
ES
Error Status
TS
Transmit Status
Receive Status
RS
LOW (idle)
TCS
TBS
DO
RBS
OI
Transmission Complete Status
Transmit Buffer Access
Data Overrun
HIGH (complete)
HIGH (released)
LOW (absent)
Receive Buffer Status
Overrun Interrupt
Transmit Interrupt
Receive Interrupt
LOW (empty)
Interrupt
LOW (reset)
IR.1
TI
LOW (reset)
IR.0
RI
LOW (reset)
Note
1. Only after an external reset; see note 5 to Table 37 “Description of the SR bits”.
1996 Jun 27
41
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
When the complete message has been correctly received
the following occurs:
13.5.7 ACCEPTANCE CODE REGISTER (ACR)
The Acceptance Code Register is part of the acceptance
filter of the CAN-controller. This register can be accessed
(read/write), if the Reset Request bit is set HIGH (present).
• The Receive Buffer Status bit is set HIGH (full)
• If the Receive Interrupt Enable bit is set HIGH (enabled),
the Receive Interrupt is set HIGH (set).
When a message is received which passes the
acceptance test and if there is an empty Receive Buffer,
then the respective Descriptor and Data Field
During transmission of a message which passes the
acceptance test, the message is also written to its own
Receive Buffer. If no Receiver Buffer is available, Data
Overrun is signalled because it is not known at the start of
a message whether the CAN-controller will lose arbitration
and so become a receiver of the message.
(see Fig.15) are sequentially stored in this empty buffer.
In the event that there is no empty Receive Buffer, the
Data Overrun bit is set HIGH (overrun); see
Sections 13.5.5 and 13.5.6.
Table 41 Acceptance Code Register (address 4)
7
6
5
4
3
2
1
0
AC.7
AC.6
AC.5
AC.4
AC.3
AC.2
AC.1
AC.0
Table 42 Description of the ACR bits
BIT
SYMBOL
FUNCTION
7 to 0
AC.7 to
AC.0
Acceptance Code. The Acceptance Code bits (AC.7 to AC.0) and the eight most
significant bits of the message's Identifier (ID.10 to ID.3) must be equal to those bit
positions which are marked relevant by the Acceptance Mask bits (AM.7 to AM.0).
The acceptance is given, if the following equation is satisfied:
(ID10 ... ID.3) = [(AC.7 ... AC.0) or (AM.7 ... AM.0)] = 1111 1111 B
The Acceptance Mask Register qualifies which of the
corresponding bits of the acceptance code are ‘relevant’ or
‘don't care’ for acceptance filtering.
13.5.8 ACCEPTANCE MASK REGISTER (AMR)
The Acceptance Mask Register is part of the acceptance
filter of the CAN-controller.
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present).
Table 43 Acceptance Mask Register (address 5)
7
6
5
4
3
2
1
0
AM.7
AM.6
AM.5
AM.4
AM.3
AM.2
AM.1
AM.0
Table 44 Description of the AMR bits
BIT
SYMBOL
FUNCTION
Acceptance Mask. If the Acceptance Mask bit is:
7 to 0
AM.7 to
AM.0
HIGH (don’t care), then this bit position is ‘don’t care’ for the acceptance of a message.
LOW (relevant), then this bit position is ‘relevant’ for acceptance filtering.
1996 Jun 27
42
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present).
For further information on bus timing, see
Sections 13.5.10 and 13.5.18.
13.5.9 BUS TIMING REGISTER 0 (BTR0)
The contents of Bus Timing Register 0 defines the values
of the Baud Rate Prescaler (BRP) and the Synchronization
Jump Width (SJW).
Table 45 Bus Timing Register 0 (address 6)
7
6
5
4
3
2
1
0
SJW.1
SJW.0
BRP.5
BRP.4
BRP.3
BRP.2
BRP.1
BRP.0
Table 46 Description of the BTR0 bits
BIT
SYMBOL
SJW.1
FUNCTION
7
6
Synchronization Jump Width. To compensate for phase shifts between clock
oscillators of different bus controllers, any bus controller must resynchronize on any
relevant signal edge of the current transmission. The synchronization jump width
defines the maximum number of clock cycles a bit period may be shortened or
lengthened by one resynchronization:
SJW.0
tSJW = tSCL (2SJW.1 + SJW.0 + 1)
5
4
3
2
1
0
BRP.5
BRP.4
BRP.3
BRP.2
BRP.1
BRP.0
Baud Rate Prescaler. The period of the system clock tSCL is programmable and
determines the individual bit timing.The system clock is calculated using the following
equation:
tSCL = 2tCLK (32BRP.5 + 16BRP.4 + 8BRP.3 + 4BRP.2 + 2BRP.1 + BRP.0 + 1)
Where tCLK = time period of the P8xCE598 oscillator.
1996 Jun 27
43
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present).For further information
on bus timing, see Sections 13.5.9 and 13.5.18.
13.5.10 BUS TIMING REGISTER 1(BTR1)
The contents of Bus Timing Register 1 defines the length
of the bit period, the location of the sample point and the
number of samples to be taken at each sample point.
Table 47 Bus Timing Register 1 (address 7)
7
6
5
4
3
2
1
0
SAM
TSEG2.2
TSEG2.1
TSEG2.0
TSEG1.3
TSEG1.2
TSEG1.1
TSEG1.0
Table 48 Description of the BTR1 bits
BIT
SYMBOL
SAM
FUNCTION
7
Sampling. If the bit SAM is:
HIGH (3 samples), then three samples are taken. This is recommended for
slow/medium speed buses (SAE class A and B) where filtering of spikes on the
bus-line is beneficial (see Section 13.5.19.6).
LOW (1 sample), the bus is sampled once.
This is recommended for high speed buses (SAE class C).
6
5
4
3
2
1
0
TSEG2.2
TSEG2.1
TSEG2.0
TSEG1.3
TSEG1.2
TSEG1.1
TSEG1.0
Time Segment 1 (TSEG1) and Time Segment 2 (TSEG2).
TSEG1 determines the number of clock cycles per bit period and the location of the
sample point: tTSEG1 = tSCL (8TSEG1.3 + 4TSEG1.2 + 2TSEG1.1 + TSEG1.0 + 1)
TSEG2 determines the number of clock cycles per bit period and the location of the
sample point: tTSEG2 = tSCL (4TSEG2.2 + 2TSEG2.1 + TSEG2.0 + 1)
1996 Jun 27
44
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
is in the reset state (Reset Request = HIGH) the output
drivers are floating.
13.5.11 OUTPUT CONTROL REGISTER (OCR)
The Output Control Register allows, under software
control, the set-up of different output driver configurations.
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present). If the CAN-controller is
in the sleep mode (Sleep = HIGH) a recessive level is
output on the CTX0 and CTX1 pins. If the CAN-controller
Tables 50 and 51, show the relationship between the bits
of the Output Control Register and the two serial output
pins CTX0 and CTX1 of the P8xCE598 CAN-controller,
connected to the serial bus (see Fig.14).
Table 49 Output Control Register (address 8)
7
6
5
4
3
2
1
0
OCTP1
OCTN1
OCPOL1
OCTP0
OCTN0
OCPOL0
OCMODE1
OCMODE0
Table 50 Description of the OCR bits
BIT
7
SYMBOL
OCTP1
FUNCTION
See Tables 51 and 52.
6
OCTN1
5
OCPOL1
OCTP0
4
3
OCTN0
2
OCPOL0
OCMODE1
OCMODE0
1
Output Mode.
These bits select the output mode; see Table 51.
0
Table 51 Description of the Output Mode bits
OCMODE1
OCMODE0
DESCRIPTION
1
0
Normal Output Mode. The bit sequence (TXD) is sent via CTX0, CTX1. TXD is the
data bit to be transmitted. The voltage levels on the output driver pins CTX0 and CTX1
depend on both the driver characteristic programmed by OCTPx, OCTNx (float, pull-up,
pull-down, push-pull) and the output polarity programmed by OCPOLx (see Fig.17).
1
0
1
0
Clock Output Mode. For the CTX0 pin this is the same as in Normal Output Mode
(CTX0: bit sequence). However, the data stream to CTX1 is replaced by the transmit
clock (TXCLK). The rising edge of the transmit clock (non-inverted) marks the beginning
of a bit period. The clock pulse width is tSCL
.
Bi-phase Output Mode. In contrast to Normal Output Mode the bit representation is
time variant and toggled. If the bus controllers are galvanically decoupled from the
bus-line by a transformer, the bit stream is not allowed to contain a DC component. This
is achieved by the following scheme. During recessive bits all outputs are deactivated
(floating). Dominant bits are sent alternately on CTX0 and CTX1, i.e. the first dominant
bit is sent on CTX0, the second is sent on CTX1, and the third one is sent on CTX0
again, etc.
0
1
Test Output Mode. For the CTX0 pin this is the same as in Normal Output Mode
(CTX0: bit sequence). To measure the delay time of the transmitter and receiver this
mode connects the output of the input comparator (COMP OUT) with the input of the
output driver CTX1. This mode is used for production testing only.
1996 Jun 27
45
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Table 52 Output pin set-up
DRIVE
OCTPx
OCTNx
OCPOLx
TXD
0
TPx(1)
OFF
TNx(2)
CTXx(3)
float
Float
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
OFF
OFF
OFF
OFF
ON
1
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
float
0
float
1
float
Pull-down
Pull-up
0
LOW
float
1
OFF
OFF
ON
0
float
1
LOW
float
0
OFF
OFF
OFF
OFF
ON
1
HIGH
HIGH
float
0
ON
1
OFF
OFF
ON
Push/Pull
0
LOW
HIGH
HIGH
LOW
1
OFF
OFF
ON
0
ON
1
OFF
Notes
1. TPx is the on-chip output transistor x, connected to CVDD; x = 0 or 1.
2. TNx is the on-chip output transistor x, connected to CVSS; x = 0 or 1.
3. CTXx is the serial output level on CTX0 or CTX1. It is required that the output level on the CAN-bus is dominant with
TXD = 0 and recessive with TXD = 1, see Section 13.6.1.1 “Bit representation”.
OCTP1
OCTP0
CV
DD
TP0
OCPOL0
OCPOL1
OCMODE0
OCMODE1
TXD
CTX0
TN0
CV
CV
SS
OUTPUT
CONTROL
LOGIC
TXCLK
DD
TP1
CTX1
TN1
CV
SS
OCTN1
OCTN0
MLC904
Fig.17 Configurable CAN Transmitter.
46
1996 Jun 27
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
13.5.12 TEST REGISTER (TR)
The Test Register is used for production testing only.
Table 53 Test Register (address 9)
7
6
5
4
3
2
1
0
Reserved
Reserved
Map Internal Connect RX Connect TX Access
Normal
Float Output
Driver
Register
Buffer 0
CPU
Buffer CPU
Internal Bus RAM
Connect
13.5.13 TRANSMIT BUFFER LAYOUT
The global layout of the Transmit Buffer is shown in Fig.15. This buffer serves to store a message from the CPU to be
transmitted by the CAN-controller. It is subdivided into Descriptor and Data Field. The Transmit Buffer can be written to
and read from by the CPU.
13.5.13.1 Descriptor
Table 54 Descriptor Byte 1 Register (DSCR1, address 10)
7
6
5
4
3
2
1
0
ID.10
ID.9
ID.8
ID.7
ID.6
ID.5
ID.4
ID.3
Table 55 Descriptor Byte 2 Register (DSCR2, address 11)
7
6
5
4
3
2
1
0
ID.2
ID.1
ID.0
RTR
DLC.3
DLC.2
DLC.1
DLC.0
Table 56 Description of the ID.n bits in DSCR1 and DSCR2
BIT
SYMBOL
FUNCTION
DSCR1
7
6
5
4
3
2
1
0
ID.10
Identifier. The Identifier consists of 11 bits (ID.10 to ID.0). ID.10 is the most significant
bit, which is transmitted first on the bus during the arbitration process. The Identifier acts
as the messages' name, used in a receiver for acceptance filtering, and also determines
the bus access priority during the arbitration process. The lower the binary value of the
Identifier the higher the priority. This is due to the larger number of leading dominant bits
during arbitration (see Section 13.6.7).
ID.9
ID.8
ID.7
ID.6
ID.5
ID.4
ID.3
DSCR2
7
6
5
ID.2
ID.1
ID.0
Identifier. See DSCR1.
1996 Jun 27
47
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Table 57 Description of the other DSCR2 bits
BIT
SYMBOL
RTR
FUNCTION
4
Remote Transmission Request. If the RTR bit is:
HIGH (remote), then the Remote Frame will be transmitted by the CAN-controller.
LOW (data), then the Data Frame will be transmitted by the CAN-controller.
3
2
1
0
DLC.3
DLC.2
DLC.1
DLC.0
Data Length Code (DLC). The number of bytes (Data Byte Count) in the Data Field of a
message is coded by the Data Length Code. At the start of a Remote Frame transmission
the Data Length Code is not considered due to the RTR bit being HIGH (remote). This
forces the number of transmitted/received data bytes to be a logic 0. Nevertheless, the
Data Length Code must be specified correctly to avoid bus errors, if two CAN-controllers
start a Remote Frame transmission simultaneously. The range of the Data Byte Count is
0 to 8 bytes and coded as follows:
Data Byte Count = 8DLC.3 + 4DLC.2 + 2DLC.1 + DLC.0
For reasons of compatibility no Data Byte Counts other than 0,1,2,....,8 should be used.
13.5.13.2 Data Field
13.5.15 HANDLING OF THE CPU-CAN INTERFACE
The number of transferred data bytes is determined by the
Data Length Code. The first bit transmitted is the most
significant bit of data byte 1 at address 12.
Via the four special registers CANADR, CANDAT,
CANCON and CANSTA the CPU has access to the
CAN-controller and also to the DMA-logic. Note that
CANCON and CANSTA have different meanings for a
Read and Write access.
13.5.14 RECEIVE BUFFER LAYOUT
The layout of the Receive Buffer and the individual bytes
correspond to the definitions given for the Transmit Buffer
layout, except that the addresses start at 20 instead of 10
(see Fig.15).
Table 58 The SFRs between CPU and CAN
Reserved bits are read as HIGH. R = Read; W = Write; R/W = Read/Write.
BIT
ADDRESS ACCESS
7
6
5
4
3
2
1
0
CANADR
DBH
R/W
R/W
DMA
Reserved AutoInc
CANA4
CAND4
CANA3
CAND3
CANA2
CAND2
CANA1
CAND1
CANA0
CAND0
CANDAT
DAH
CAND7
CAND6
CAND5
CANCON; Do not use a RMW instruction
D9H
R
Reserved Reserved Reserved WUI
RX0A RX1A WUM SLP
OI
EI
TI
RI
W
COS
RRB
AT
TR
CANSTA; The bit addresses of CANSTA (7 to 0) are DFH to D8H; do not use a RMW instruction
DFH to D8H R
W
BS
ES
TS
RS
TCS
TBS
DO
RBS
RAMA7
RAMA6
RAMA5
RAMA4
RAMA3
RAMA2
RAMA1
RAMA0
1996 Jun 27
48
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
13.5.15.1 Special Function Register CANADR
CANADR is implemented as a read/write register.
Table 59 SFR CANADR (address DBH)
7
6
5
4
3
2
1
0
DMA
−
AutoInc
CANA4
CANA3
CANA2
CANA1
CANA0
Table 60 Description of the CANADR bits
BIT
SYMBOL
DMA
FUNCTION
7
6
5
4
3
2
1
0
DMA-logic controlled via bit CANADR.7 (see Section 13.5.17).
Reserved.
−
AutoInc
CANA4
CANA3
CANA2
CANA1
CANA0
Auto Address Increment mode controlled via bit CANADR.5 (see Section 13.5.16).
The five least significant bits CANADR.4 to CANADR.0 define the address of one of the
CAN-controller internal registers to be accessed via CANDAT. For instance, after an
external hardware (e.g. power-on) reset CANADR contains the value 64H, and hence
the CPU accesses (read/write) the Acceptance Code register of the CAN-controller, via
the SFR CANDAT.
13.5.15.2 Special Function Register CANDAT
CANDAT is implemented as a read/write register.
Table 61 SFR CANDAT (address DAH)
7
6
5
4
3
2
1
0
CAND7
CAND6
CAND5
CAND4
CAND3
CAND2
CAND1
CAND0
Table 62 Description of the CANADR bits
BIT
SYMBOL
FUNCTION
7 to 0
CAND7 to
CAND0
The SFR CANDAT appears as a port to the CAN-controller internal register (memory
location) being selected by CANADR. Reading or writing CANDAT is effectively an
access to that CAN-controller internal register, which is selected by CANADR.
1996 Jun 27
49
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
13.5.15.3 Special Function Register CANCON
Table 63 SFR CANCON in Read access (address D9H)
7
6
5
4
3
2
1
0
−
−
−
WUI
OI
EI
TI
RI
Table 64 Description of the CANCON bits in Read access
When reading CANCON the Interrupt Register of the CAN-controller is accessed.
BIT
SYMBOL
FUNCTION
7
6
5
4
3
2
1
0
−
−
−
Reserved; bits are read as HIGH.
WUI
OI
Wake-Up Interrupt (see Table 39).
Overrun Interrupt (see Table 39).
Error Interrupt (see Table 39).
Transmit Interrupt (see Table 39).
Receive Interrupt (see Table 39).
EI
TI
RI
Table 65 SFR CANCON in Write access (address D9H)
7
6
5
4
3
2
1
0
RX0A
RX1A
WUM
SLP
COS
RRB
AT
TR
Table 66 Description of the CANCON bits in Write access
When writing to CANCON then the Command Register of the CAN-controller is accessed.
BIT
SYMBOL
RX0A
FUNCTION
7
6
5
4
3
2
1
0
RX0 Active (see Table 34).
RX1 Active (see Table 34).
Wake-Up Mode (see Table 34).
Sleep (see Table 34).
RX1A
WUM
SLP
COS
RRB
AT
Clear Overrun Status (see Table 34).
Release Receive Buffer (see Table 34).
Abort Transmission (see Table 34).
Transmission Request (see Table 34).
TR
1996 Jun 27
50
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
13.5.15.4 Special Function Register CANSTA
CANSTA is implemented as a bit-addressable read/write register.
The bit addresses of CANSTA (7 to 0) are DFH to D8H.
Table 67 SFR CANCON in Read access (address DFH to D8H)
7
6
5
4
3
2
1
0
BS
ES
TS
RS
TCS
TBS
DO
RBS
Table 68 Description of the CANCON bits in Read access
When reading CANSTA the Status Register of the CAN-controller is accessed.
BIT
7
SYMBOL
BS
FUNCTION
Bus Status (see Table 37).
Error Status (see Table 37).
Transmit Status (see Table 37).
Receive Status (see Table 37).
6
ES
5
TS
4
RS
3
TCS
TBS
DO
RBS
Transmission Complete Status (see Table 37).
Transmit Buffer Access (see Table 37).
Data Overrun (see Table 37).
2
1
0
Receive Buffer Status (see Table 37).
Table 69 SFR CANCON in Write access (address DFH to D8H)
7
6
5
4
3
2
1
0
RAMA7
RAMA6
RAMA5
RAMA4
RAMA3
RAMA2
RAMA1
RAMA0
Table 70 Description of the CANSTA bits in Write access
Writing to CANSTA sets the address of the on-chip MAIN RAM (internal Data Memory) for a subsequent DMA transfer.
BIT
SYMBOL
FUNCTION
7 to 0
RAMA7 to
RAMA0
−
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P8xCE598
CANADR, CANDAT, CANCON or CANSTA is not allowed.
After having set the DMA-bit, every interrupt is disabled
until the end of the transfer. Note, that disadvantageous
programming may lead to an interrupt response time of at
most 10 instruction cycles. The shortest interrupt response
time is achieved by using 2 consecutive 1-cycle
13.5.16 AUTO ADDRESS INCREMENT
With the Auto Address Increment mode a fast stack-like
reading and writing of CAN-controller internal registers is
provided. If the bit CANADR.5 (AutoInc) is HIGH, the
content of CANADR is incremented automatically after any
read or write access to CANDAT. For instance, loading a
message into the Transmit Buffer can be done by writing
2AH into CANADR and then moving byte by byte of the
message to CANDAT. Incrementing CANADR beyond
XX111111B resets the bit CANADR.5 (AutoInc)
instructions directly after setting the DMA-bit.
During the reset state (bit Reset Request is HIGH) a DMA
transfer is not possible.
automatically (CANADR = XX000000B).
13.5.18 BUS TIMING/SYNCHRONIZATION
The Bus Timing Logic (BTL) monitors the serial bus-line
via the on-chip input comparator and performs the
following functions (see Section 13.4
13.5.17 HIGH SPEED DMA
The DMA-logic allows you to transfer a complete message
(up to 10 bytes) between CAN-controller and Main RAM in
2 instruction cycles at maximum; up to 4 bytes are
transferred in 1 instruction cycle. The performance of the
CPU is strongly enhanced because this very fast transfer
is carried out in the background.
“Hardware blocks of the CAN-controller”):
• Monitors the serial bus-line level
• Adjusts the sample point, within a bit period
(programmable)
• Samples the bus-line level using majority logic
(programmable, 1 or 3 samples)
A DMA transfer is achieved by first writing the RAM
address (00H to FFH) into CANSTA and then setting the
TX- or RX-Buffer address in CANDR and the bit
CANADR.7 (DMA) simultaneously; the RAM address
points to the location of the first byte to be transferred.
Setting the DMA bit causes an automatic evaluation of the
Data Length Code and then the transfer; for a TX-DMA
transfer the Data Length Code is expected at the location
‘RAM address + 1’.
• Synchronization to the bit stream:
– hard synchronization at the start of a message
– resynchronization during transfer of a message.
The configuration of the BTL is performed during the
initialization of the CAN-controller. The BTL uses the
following three registers:
• Control Register (Sync)
• Bus Timing Register 0
• Bus Timing Register 1.
In order to program a TX-DMA transfer the value 8AH
(address 10) has to be written into CANADR. Then a
complete message, consisting of the 2-byte Descriptor
and the Data Field (0 to 8 bytes), starting at location
‘RAM address’ is transferred to the TX-Buffer.
13.5.19 BIT TIMING
The RX-DMA transfer is very versatile. By writing a value
in the range of 94H (address 20) up to 9DH (address 29)
into CANADR the whole or a part of the received message,
starting at the specified address, is transferred to the
internal Data Memory. This allows e.g. to transfer the bytes
of the Data Field only.
A bit period is built up from a number of system clock
cycles (tSCL), see Section 13.5.9.
One bit period is the result of the addition of the
programmable segments TSEG1 and TSEG2 and the
general segment SYNCSEG.
13.5.19.1 Synchronization Segment (SYNCSEG)
After a successful DMA transfer the DMA-bit is reset.
The incoming edge of a bit is expected during this state;
this state corresponds to one system clock cycle (1 × tSCL).
During a DMA transfer the CPU can process the next
instruction. However, an access to the Data Memory,
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Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
nominal bit time
SYNC.SEG
PROP.SEG
PHASE SEG1
PHASE SEG2
sample point
(a)
t
(one bit period)
t
SYNCSEG
t
t
TSEG1
TSEG2
transmit point
1 clock cycle (t
sample point
)
SCL
(b)
MGA163
(a) As defined by the CAN-protocol.
(b) As implemented in the P8xCE598's on-chip CAN-controller.
Fig.18 Bit period.
• To avoid sampling at an incorrect position, it is
necessary to include an additional synchronization
buffer on both sides of the sample point. The main
reasons for incorrect sampling are:
13.5.19.2 Time Segment 1 (TSEG1)
This segment determines the location of the sampling
point within a bit period, which is at the end of TSEG1.
TSEG1 is programmable from 1 to 16 system clock cycles
(see Section 13.5.10).
– incorrect synchronization due to spikes on the
bus-line
The correct location of the sample point is essential for the
correct functioning of a transmission. The following points
must be taken into consideration:
– slight variations in the oscillator frequency of each
CAN-controller in the network, which results in a
phase error.
• A Start-Of-Frame (see Section 13.6.2) causes all
CAN-controllers to perform a
• Time Segment 1 consists of the segment for
compensation of propagation delays and the
synchronization buffer segment directly before the
sample point (see Fig.18).
‘hard synchronization’ (see Section 13.5.20) on the first
recessive-to-dominant edge. During arbitration,
however, several CAN-controllers may simultaneously
transmit. Therefore it may require twice the sum of
bus-line, input comparator and the output driver delay
times until the bus is stable. This is the propagation
delay time.
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Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
This type of synchronization occurs only at the beginning
of a message.
13.5.19.3 Time Segment 2 (TSEG2)
This time segment provides:
The CAN-controller synchronizes on the first incoming
recessive-to-dominant edge of a message (being the
leading edge of a message's Start-Of-Frame bit;
see Section 13.6.2.
• additional time at the sample point for calculation of the
subsequent bit levels (e.g. arbitration)
• synchronization buffer segment directly after the sample
point.
Resynchronization occurs during the transmission of a
message's bit stream to compensate for:
TSEG2 is programmable from 1 to 8 system clock cycles
(see Section 13.5.10.
• Variations in individual CAN-controller oscillator
frequencies
13.5.19.4 Synchronisation Jump Width (SJW)
• Changes introduced by switching from one transmitter
to another (e.g. during arbitration).
SJW defines the maximum number of clock cycles (tSCL) a
period may be reduced or increased by one
As a result of resynchronization either tTSEG1 may be
increased by up to a maximum of tSJW or tTSEG2 may be
resynchronization. SJW is programmable from 1 to 4
system clock cycles, see Section 13.5.2.
decreased by up to a maximum of tSJW
:
13.5.19.5 Propagation Delay Time (tprop
)
• tTSEG1 ≤ tSCL [(TSEG1 + 1) + (SJW + 1)]
• tTSEG2 ≥ tSCL [(TSEG2 + 1) − (SJW + 1)].
The Propagation Delay Time is:
tprop = 2 × (physical bus delay
+ input comparator delay
+ output driver delay).
TSEG1, TSEG2 and SJW are the programmed numerical
values.
The phase error (e) of an edge is given by the position of
the edge relative to SYNCSEG, measured in system clock
cycles (tSCL).
tprop is rounded up to the nearest multiple of tSCL
.
13.5.19.6 Bit Timing Restrictions
The value of the phase error is defined as:
• e = 0, if the edge occurs within SYNCSEG
• e > 0, if the edge occurs within TSEG1
• e < 0, if the edge occurs within TSEG2.
Restrictions on the configuration of the bit timing are based
on internal processing. The restrictions are:
• tTSEG2 ≥ 2tSCL
• tTSEG2 ≥ tSJW
• tTSEG1 ≥ tSEG2
The effect of resynchronization is:
• The same as that of a hard synchronization, if the
magnitude of the phase error (e) is less or equal to the
programmed value of tSJW
• tTSEG1 ≥ tSJW + tprop
.
The three sample mode (SAM = HIGH) has the effect of
introducing a delay of one system clock cycle on the
bus-line. This must be taken into account for the correct
calculation of TSEG1 and TSEG2:
• To increase a bit period by the amount of tSJW,if the
phase error is positive and the magnitude of the phase
error is larger than tSJW
• To decrease a bit period by the amount of tSJW if the
• tTSEG1 ≥ tSJW + tprop + 2tSCL
phase error is negative and the magnitude of the phase
• tTSEG2 ≥ 3tSCL
.
error is larger than tSJW
.
13.5.20 SYNCHRONIZATION
Synchronization is performed by a state machine which
compares the incoming edge with its actual bit timing and
adapts the bit timing by hard synchronization or
resynchronization.
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8-bit microcontroller with on-chip CAN
P8xCE598
13.5.20.1 Synchronization Rules
13.6.2 DATA FRAME
The synchronization rules are as follows:
A Data Frame carries data from a transmitting
CAN-controller to one or more receiving ones.
A Data Frame is composed of seven different bit-fields:
• Only one synchronization within one bit time is used.
• An edge is used for synchronization only if the value
detected at the previous sample point differs from the
bus value immediately after the edge.
• Start-Of-Frame
• Arbitration Field
• Hard synchronization is performed whenever there is a
recessive-to-dominant edge during Bus-Idle
(see Section 13.6.6).
• Control Field
• Data Field (may have a length of zero)
• CRC Field
• All other edges (recessive-to-dominant and optionally
dominant-to recessive edges if the Sync bit is set HIGH
(see Section 13.5.3) which are candidates for
resynchronization will be used with the following
exception:
• Acknowledge Field
• End-Of-Frame.
13.6.2.1 Start-Of-Frame bit
– A transmitting CAN-controller will not perform a
resynchronization as a result of a
Signals the start of a Data Frame or Remote Frame.
It consists of a single dominant bit use for hard
synchronization of a CAN-controller in receive mode.
recessive-to-dominant edge with positive phase
error, if only these edges are used for
resynchronization. This ensures that the delay times
of the output driver and input comparator do not
cause a permanent increase in the bit time.
13.6.2.2 Arbitration Field
Consists of the message Identifier and the RTR bit. In the
case of simultaneous message transmissions by two or
more CAN-controllers the bus access conflict is solved by
bit-wise arbitration, which is active during the transmission
of the Arbitration Field.
13.6 CAN 2.0A Protocol description
13.6.1 FRAME TYPES
The P8xCE598's CAN-controller supports the four
different CAN-protocol frame types for communication:
13.6.2.3 Identifier
This 11-bit field is used to provide information about the
message, as well as the bus access priority. It is
transmitted in the order ID.10 to ID.0 (LSB). The situation
that the seven most significant bits (ID.10 to ID.4) are all
recessive must not occur.
• Data Frame, to transfer data
• Remote Frame, request for data
• Error Frame, globally signal a (locally) detected error
condition
• Overload Frame, to extend delay time of subsequent
frames (an Overload Frame is not initiated by the
P8xCE598 CAN-Controller).
An Identifier does not define which particular
CAN-controller will receive the frame because a CAN
based communication network does not differentiate
between a point-to-point, multicast or broadcast
communication.
13.6.1.1 Bit representation
There are two logical bit representations used in the
CAN-protocol:
• A recessive bit on the bus-line appears only if all
connected CAN-controllers send a recessive bit at that
moment.
• Dominant bits always overwrite recessive bits i.e. the
resulting bit level on the bus-line is dominant.
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P8xCE598
13.6.2.4 RTR bit
13.6.2.8 Acknowledge Field (ACK)
A CAN-controller, acting as a receiver for certain
The Acknowledge Field consists of two bits, the
Acknowledge Slot and the Acknowledge Delimiter, which
are transmitted with a recessive level by the transmitter of
the Data Frame. All CAN-controllers having received the
matching CRC Sequence, report this by overwriting the
transmitter's recessive bit in the Acknowledge Slot with a
dominant bit. Thereby a transmitter, still monitoring the bus
level recognizes that at least one receiver within the
network has received a complete and correct message
(i.e. no error was found). The Acknowledge Delimiter
(recessive bit) is the second bit of the Acknowledge Field.
As a result, the Acknowledge Slot is surrounded by two
recessive bits: the CRC Delimiter and the Acknowledge
Delimiter.
information may initiate the transmission of the respective
data by transmitting a Remote Frame to the network,
addressing the data source via the Identifier and setting
the RTR bit HIGH (remote; recessive bus level). If the data
source simultaneously transmits a Data Frame containing
the requested data, it uses the same Identifier. No bus
access conflict occurs due to the RTR bit being set LOW
(data; dominant bus level) in the Data Frame.
13.6.2.5 Control Field
This field consists of six bits. It includes two reserved bits
(for future expansions of the CAN-protocol), transmitted
with a dominant bus level, and is followed by the Data
Length Code (4 bits).
The number of bytes (destuffed; number of data bytes to
be transmitted/received) in the Data Field is indicated by
the Data Length Code. Admissible values of the Data
Length Code, and hence the number of bytes in the
(destuffed) Data Field, are {0, 1, ...., 8}. A logic 0 (logic 1)
in the Data Length Code is transmitted as dominant
(recessive) bus level, respectively.
All nodes within a CAN network may use all the information
coming to the network by all CAN-controllers (shared
memory concept). Therefore, acknowledgement and error
handling are defined to provide all information in a
consistent way throughout this shared memory. Hence,
there is no reason to discriminate different receivers of a
message in the acknowledge field. If a node is
disconnected from the network due to bus failure, this
particular node is no longer part of the shared memory. To
identify a ‘lost node’ additional and application specific
precautions are required.
13.6.2.6 Data Field
The data, stored within the Data Field of the Transmit
Buffer, are transmitted according to the Data Length Code.
Conversely, data of a received Data Frame will be stored
in the Data Field of a Receive Buffer. The Data Field can
contain from 0 up to 8 bytes. The most significant bit of the
first data byte (lowest address) is transmitted/received
first.
13.6.2.9 End-Of-Frame
Each Data Frame or Remote Frame is delimited by the
End-Of-Frame bit sequence which consists of seven
recessive bits (exceeds the bit stuff width by two bits).
Using this method a receiver detects the end of a frame
independent of a previous transmission error because the
receiver expects all bits up to the end of the CRC
Sequence to be coded by the method of bit-stuffing, see
Section 13.6.7.3. The bit-stuffing logic is deactivated
during the End-Of-Frame sequence.
13.6.2.7 Cyclic Redundancy Code Field (CRC)
The CRC Field consists of the CRC Sequence (15 bits)
and the CRC Delimiter (1 recessive bit). The Cyclic
Redundancy Code (CRC) encloses the destuffed bit
stream of the Start-Of-Frame, Arbitration Field, Data Field
and CRC Sequence. The most significant bit of the CRC
Sequence is transmitted/received first. This frame check
sequence, implemented in the CAN-controller is derived
from a cyclic redundancy code best suited for frames with
a total bit count of less than 127 bits, see Section 13.6.8.3.
With Start-Of-Frame (dominant bit) included in the code
word, any rotation of the code word can be detected by the
absence of the CRC Delimiter (recessive bit).
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Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
GM1A64
a n d b o o k , f u l l p a g e w
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Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
from Start-Of-Frame to CRC Delimiter, or destroys the
fixed form of the fields Acknowledge Field or
13.6.3 REMOTE FRAME
A CAN-controller acting as a receiver for certain
information may initiate the transmission of the respective
data by transmitting a Remote Frame to the network,
addressing the data source via the Identifier and setting
the RTR bit HIGH (remote; recessive bus level). The
Remote Frame is similar to the Data Frame with the
following exceptions:
End-Of-Frame (see Fig.20). Consequently, all other
CAN-controllers detect an error condition and start
transmission of an Error Flag. Therefore the sequence of
dominant bits, which can be monitored on the bus, results
from the superimposing of different Error Flags transmitted
by individual CAN-controllers. The total length of this
sequence varies between six (minimum) and twelve
(maximum) bits.
• RTR bit is set HIGH
• Data Length Code is ignored
• no Data Field contained.
An error-passive CAN-controller (see Section 13.6.9)
detecting an error condition tries to signal this by
transmission of a Passive Error Flag. The error-passive
CAN-controller waits for six consecutive bits with identical
polarity, beginning at the start of the Passive Error Flag.
The Passive Error Flag is complete when these six
identical bits have been detected.
Note that the value of the Data Length Code should be the
one of the corresponding Data Frame, although it is
ignored for a Remote Frame.
A Remote Frame is composed of six different bit fields:
• Start-of-Frame
13.6.4.2 Error Delimiter
• Arbitration Field
The Error Delimiter consists of eight recessive bits and has
the same format as the Overload Delimiter. After
• Control Field
• CRC Field
transmission of an Error Flag, each CAN-controller
monitors the bus-line until it detects a transition from a
dominant-to-recessive bit level. At this point in time, every
CAN-controller has finished sending its Error Flag and has
additionally sent the first out of the 8 recessive bits of the
Error Delimiter. Afterwards all CAN-controllers transmit the
remaining recessive bits. After this event and an
• Acknowledge Field
• End-Of-Frame.
See Section 13.6.2 for more detailed explanation of the
Remote Frame bit fields.
13.6.4 ERROR FRAME
Intermission Field all error-active CAN-controllers within
the network can start a transmission simultaneously.
The Error Frame consists of two different fields:
If a detected error is signalled during transmission of a
Data Frame or Remote Frame, the current message is
spoiled and a retransmission of the message is initiated.
• The first field, accomplished by the superimposing of
Error Flags contributed from different CAN-controllers
• The second field is the Error Delimiter.
If a CAN-controller monitors any deviation of the Error
Frame, a new Error Frame will be transmitted. Several
consecutive Error Frames may result in the CAN-controller
becoming error-passive and leaving the network
unblocked.
13.6.4.1 Error Flag
There are two forms of an Error Flag:
• Active Error Flag, consists of six consecutive dominant
bits
In order to terminate an Error Flag correctly, an
error-passive CAN-controller requires the bus to be
Bus-Idle (see Section 13.6.6) for at least three bit periods
(if there is a local error at an error-passive-receiver).
Therefore a CAN-bus should not be 100% permanently
loaded.
• Passive Error Flag, consists of six consecutive
recessive bits unless it is overwritten by dominant bits
from other CAN-controllers.
An error-active CAN-controller (see Section 13.6.9)
detecting an error condition signals this by transmission of
an Active Error Flag. This Error Flag's form violates the
bit-stuffing rule (see Section 13.6.7) applied to all fields,
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Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
INTER-FRAME SPACE
or OVERLOAD FRAME
DATA FRAME
ERROR FRAME
1 ERROR
FLAG
superimposing of
ERROR FLAGs
ERROR DELIMITER
MGA165
Fig.20 Error Frame.
13.6.5 OVERLOAD FRAME
13.6.5.1 Overload Flag
The Overload Frame consists of two fields:
• The Overload Flag
The Overload Flag consists of six dominant bits and has a
similar format to the Error Flag.
There are two conditions in the CAN-protocol which lead
to the transmission of an Overload Flag:
• The Overload Delimiter.
The transmission of an Overload Frame may only start:
• Condition 1; receiver circuitry requires more time to
process the current data before receiving the next frame
(receiver not ready).
• Condition 1; during the first bit period of an expected
Intermission Field.
• Condition 2; one bit period after detecting the dominant
bit during Intermission Field.
• Condition 2; detection of a dominant bit during
Intermission Field (see Section 13.6.6).
The P8xCE598's on-chip CAN-controller will never initiate
transmission of a condition 1 Overload Frame and will only
react on a transmitted condition 2 Overload Frame,
according to the CAN-protocol. No more than two
Overload Frames are generated to delay a Data Frame or
a Remote Frame. Although the overall form of the
Overload Frame corresponds to that of the Error Frame,
an Overload Frame does not initiate or require the
retransmission of the preceding frame.
The Overload Flag's form corrupts the fixed form of the
Intermission Field. All other CAN-controllers detecting the
overload condition also transmit an Overload Flag
(condition 2).
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P8xCE598
During arbitration every transmitting CAN-controller
13.6.5.2 Overload Delimiter
compares its transmitted bit level with the monitored bus
level. Any CAN-controller which transmits a recessive bit
and monitors a dominant bus level immediately becomes
the receiver of the higher-priority message on the bus
without corrupting any information on the bus. Each
message contains an unique Identifier and a RTR bit
describing the type of data within the message. The
Identifier together with the RTR bit implicitly define the
message's bus access priority. During arbitration the most
significant bit of the Identifier is transmitted first and the
RTR bit last. The message with the lowest binary value of
the Identifier and RTR bit has the highest priority. A Data
Frame has higher priority than a Remote Frame due to its
RTR bit having a dominant level.
The Overload Delimiter consists of eight recessive bits and
takes the same form as the Error Delimiter. After
transmission of an Overload Flag, each CAN-controller
monitors the bus-line until it detects a transition from a
dominant-to-recessive bit level. At this point in time, every
CAN-controller has finished sending its Overload Flag and
all CAN-controllers start simultaneously transmitting seven
more recessive bits.
13.6.6 INTER-FRAME SPACE
Data Frames and Remote Frames are separated from
preceding frames (all types) by an Inter-Frame Space,
consisting of an Intermission Field and a Bus-Idle.
Error-passive CAN-controllers also send a Suspend
Transmission (see Section 13.6.9) after transmission of a
message. Overload Frames and Error Frames are not
preceded by an Inter-Frame Space.
For every Data Frame there is an unique transmitter. For
reasons of compatibility with other CAN-bus controllers,
use of the Identifier bit pattern ID = 1111111XXXXB
(X being bits of arbitrary level) is forbidden.
The number of available different Identifiers:
13.6.6.1 Intermission Field
(211 – 24) = 2032.
The Intermission Field consists of three recessive bits.
During an Intermission period, no frame transmissions will
be started by the P8xCE598's on-chip CAN-controller. An
Intermission is required to have a fixed time period to allow
a CAN-controller to execute internal processes prior to the
next receive or transmit task.
13.6.7.3 Coding/Decoding
The following bit fields are coded using the bit-stuffing
technique:
• Start-Of-Frame
• Arbitration Field
• Control Field
• Data Field
13.6.6.2 Bus-Idle
The Bus-Idle time may be of arbitrary length (min. 0 bit).
The bus is recognized to be free and a CAN-controller
having information to transmit may access the bus. The
detection of a dominant bit level during Bus-Idle on the bus
is interpreted as the Start-Of-Frame.
• CRC Sequence.
When a transmitting CAN-controller detects five
consecutive bits of identical polarity to be transmitted, a
complementary (stuff) bit is inserted into the transmitted
bit-stream.
13.6.7 BUS ORGANIZATION
Bus organization is based on five basic rules described in
the following subsections.
When a receiving CAN-controller has monitored five
consecutive bits with identical polarity in the received bit
streams of the above described bit fields, it automatically
deletes the next received (stuff) bit. The level of the
deleted stuff bit has to be the complement of the previous
bits; otherwise a Stuff Error will be detected and signalled
(see Section 13.6.8).
13.6.7.1 Bus Access
CAN-controllers only start transmission during the
Bus-Idle state. All CAN-controllers synchronize on the
leading edge of the Start-Of-Frame
(hard synchronization).
The remaining bit fields or frames are of fixed form and are
not coded or decoded by the method of bit-stuffing.
13.6.7.2 Bus Arbitration
The bit-stream in a message is coded according to the
Non-Return-to-Zero (NRZ) method, i.e. during a bit period,
the bit level is held constant, either recessive or dominant.
If two or more CAN-controllers simultaneously start
transmitting, the bus access conflict is solved by a bit-wise
arbitration process during transmission of the Arbitration
Field.
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P8xCE598
the retransmission of any previous Data Frame or Remote
Frame. If a CAN-controller which transmitted an Overload
Frame monitors any deviation of its fixed form, it transmits
an Error Frame.
13.6.7.4 Error Signalling
A CAN-controller which detects an error condition,
transmits an Error Flag. Whenever a Bit Error, Stuff Error,
Form Error or an Acknowledgement Error is detected,
transmission of an Error Flag is started at the next bit.
Whenever a CRC Error is detected, transmission of an
Error Flag starts at the bit following the Acknowledge
Delimiter, unless an Error Flag for another error condition
has already started. An Error Flag violates the bit-stuffing
law or corrupts the fixed form bit fields. A violation of the
bit-stuffing law affects any CAN-controller which detects
the error condition. These devices will also transmit an
Error Flag.
13.6.8 ERROR DETECTION
The processes described in Sections 13.6.8.1 to 13.6.10.3
are implemented in the P8xCE598's on-chip
CAN-controller for error detection.
13.6.8.1 Bit Error
A transmitting CAN-controller monitors the bus on a
bit-by-bit basis. If the bit level monitored is different from
the transmitted one, a Bit Error is signalled. The
exceptions being:
An error-passive CAN-controller (see Section 13.6.9)
which detects an error condition, transmits a Passive Error
Flag. A Passive Error Flag is not able to interrupt a current
message at different CAN-controllers but this type of Error
Flag may be ignored (overwritten) by other
CAN-controllers. After having detected an error condition,
an error-passive CAN-controller will wait for six
consecutive bits with identical polarity and when
monitoring them, interpret them as an Error Flag.
• During the Arbitration Field, a recessive bit can be
overwritten by a dominant bit. In this case, the
CAN-controller interprets this as a loss of arbitration.
• During the Acknowledge Slot, only the receiving
CAN-controllers are able to recognize a Bit Error.
13.6.8.2 Stuff Error
After transmission of an Error Flag, each CAN-controller
monitors the bus-line until it detects a transition from a
dominant-to-recessive bit level. At this point in time, every
CAN-controller has finished transmitting its Error Flag and
all CAN-controllers start transmitting seven additional
recessive bits (Error Delimiter, see Section 13.6.4).
The following bit fields are coded using the bit-stuffing
technique:
• Start-Of-Frame
• Arbitration Field
• Control Field
• Data Field
The message format of a Data Frame or Remote Frame is
defined in such a way that all detectable errors can be
signalled within the message transmission time and
therefore it is very simple for the CAN-controllers to
associate an Error Frame to the corresponding message
and to initiate retransmission of the corrupted message. If
a CAN-controller monitors any deviation of the fixed form
of an Error Frame, it transmits a new Error Frame.
• CRC Sequence.
There are two possible ways of generating a Stuff Error:
• A disturbance generates more than the allowed five
consecutive bits with identical polarity. These errors are
detected by all CAN-controllers.
• A disturbance falsifies one or more of the five bits
preceding the stuff bit. This error situation is not
recognized as a Stuff Error by the receivers. Therefore,
other error detection processes may detect this error
condition such as:
13.6.7.5 Overload Signalling
Some CAN-controllers (but not the one on-chip of the
P8xCE598) require to delay the transmission of the next
Data Frame or Remote Frame by transmitting one or more
Overload Frames. The transmission of an Overload Frame
must start during the first bit of an expected Intermission
Field. Transmission of Overload Frames which are
reactions on a dominant bit during an expected
– CRC check, format violation at the receiving
CAN-controllers, or
– Bit Error detection by the transmitting CAN-controller.
Intermission Field, start one bit after this event.
Though the format of Overload Frame and Error Frame are
identical, they are treated differently. Transmission of an
Overload Frame during Intermission Field does not initiate
1996 Jun 27
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Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
13.6.8.3 CRC Error
13.6.8.5 Acknowledgement Error
To ensure the validity of a transmitted message all
receivers perform a CRC check. Therefore, in addition to
the (destuffed) information digits (Start-Of-Frame up to
Data Field), every message includes some control digits
(CRC Sequence; generated by the transmitting
CAN-controller of the respective message) used for error
detection.
This is detected by a transmitter whenever it does not
monitor a dominant bit during the Acknowledge Slot.
13.6.8.6 Error detection by an Error Flag from
another CAN-controller
The detection of an error is signalled by transmitting an
Error Flag. An Active Error Flag causes a Stuff Error, a Bit
Error or a Form Error at all other CAN-controllers.
The code used by all CAN-controllers is a (shortened)
BCH code, extended by a parity check and has the
following attributes:
13.6.8.7 Error Detection Capabilities
• 127 bits as maximum length of the code.
Errors which occur at all CAN-controllers (global errors)
are 100% detected. For local errors, i.e. for errors
occurring at some CAN-controllers only, the shortened
BCH code, extended by a parity check, has the following
error detection capabilities:
• 112 bits as maximum number of information digits
(max. 83 bits are used by the CAN-controller).
• Length of the CRC Sequence amounts to 15 bits.
• Hamming distance d = 6.
• Up to five single Bit Errors are 100% detected, even if
they are distributed randomly within the code.
As a result, ‘(d−1)’ random errors are detectable (some
exceptions exist).
• All single Bit Errors are detected if their total number
The CRC Sequence is determined (calculated) by the
following procedure:
(within the code) is odd.
• The residual error probability of the CRC check amounts
to (3 × 10−5). As an error may be detected not only by
CRC check but also by other detection processes
described above the residual error probability is several
magnitudes less than (3 × 10−5).
1. The destuffed bit stream consisting of Start-Of-Frame
up to the Data Field (if present) is interpreted as
polynomial with coefficients 0 or 1.
2. This polynomial is divided (modulo-2) by the following
generator polynomial, which includes a parity check:
13.6.9 ERROR CONFINEMENT DEFINITIONS
13.6.9.1 Bus-OFF
f(x) = (x14 + x9 + x8 + x6 + x5 + x4 + x2 + x + 1)
(x + 1) = 1100010110011001 B.
3. The remainder of this polynomial division is the
CRC sequence.
A CAN-controller which has too many unsuccessful
transmissions, relative to the number of successful
transmissions, will enter the Bus-OFF state. It remains in
this state, neither receiving nor transmitting messages
until the Reset Request bit is set LOW (absent) and both
Error Counters set to 0 (see Section 13.6.10).
Burst errors are detected up to a length of 15
[degree of f(x)]. Multiple errors (number of disturbed bits at
least d = 6) are not detected with a residual error
probability of 2–15 (3 × 10–5) by CRC check only.
13.6.9.2 Acknowledge
13.6.8.4 Form Error
A CAN-controller which has received a valid message
correctly, indicates this to the transmitter by transmitting a
dominant bit level on the bus during the Acknowledge Slot,
independent of accepting or rejecting the message.
Form Errors result from violations of the fixed form of the
following bit fields:
• CRC Delimiter
• Acknowledge Delimiter
• End-Of-Frame
13.6.9.3 Error-Active
An error-active CAN-controller in its normal operating state
is able to receive and to transmit normally and also to
transmit an Active Error Flag (see Section 13.6.10).
• Error Delimiter
• Overload Delimiter.
During the transmission of these bit fields an error
condition is recognized if a dominant bit level instead of a
recessive one is detected.
1996 Jun 27
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Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
13.6.10.2 Detection and localization of hardware
13.6.9.4 Error-Passive
disturbances and defects
An error-passive CAN-controller may transmit or receive
messages normally. In the case of a detected error
condition it transmits a Passive Error Flag instead of an
Active Error Flag. Hence the influence on bus activities by
an error-active CAN-controller (e.g. due to a malfunction)
is reduced.
The rules for error confinement are defined by the
CAN-protocol specification (and implemented in the
P8xCE598's on-chip CAN-controller), in such a way that
the CAN-controller, being nearest to the error-locus, reacts
with a high probability the quickest (i.e. becomes
error-passive or Bus-OFF). Hence errors can be localized
and their influence on normal bus activities is minimized.
13.6.9.5 Suspend Transmission
After an error-passive CAN-controller has transmitted a
message, it sends eight recessive bits after the
13.6.10.3 Error Confinement
All CAN-controllers contain a Transmit Error Counter and
a Receive Error Counter, which registers errors during the
transmission and the reception of messages, respectively.
Intermission Field and then checks for Bus-Idle. If during
Suspend Transmission another CAN-controller starts
transmitting a message the suspended CAN-controller will
become the receiver of this message; otherwise being in
Bus-Idle it may start to transmit a further message.
If a message is transmitted or received correctly, the count
is decreased. In the event of an error, the count is
increased. The Error Counters have an non-proportional
method of counting: an error causes a larger counter
increase than a correctly transmitted/received message
causes the count to decrease. Over a period of time this
may result in an increase in error counts, even if there are
fewer corrupted messages than uncorrupted ones. The
level of the Error Counters reflect the relative frequency of
disturbances. The ratio of increase/decrease depends on
the acceptable ratio of invalid/valid messages on the bus
and is hardware implemented to eight.
13.6.9.6 Start-Up
A CAN-controller which either was switched off or in the
Bus-OFF state, must run a Start-Up routine in order to:
• Synchronize with other available CAN-controllers before
starting to transmit. Synchronization is achieved, when
11 recessive bits, equivalent to Acknowledge Delimiter,
End-Of-Frame and Intermission Field, have been
detected (Bus-Free).
• Wait for other CAN-controllers without passing into the
Bus-OFF state (due to a missing acknowledge), if there
is no other CAN-controller currently available.
If one of the Error Counters exceeds the Warning Limit of
96 error points, indicating a significant accumulation of
error conditions, this is signalled by the CAN-controller
(Error Status, Error Interrupt).
13.6.10 AIMS OF ERROR CONFINEMENT
A CAN-controller operates in the error-active mode until it
exceeds 127 error points on one of its Error Counters. At
this value it will enter the error-passive state. A transmit
error which exceeds 255 error points results in the
CAN-controller entering the Bus-OFF state.
13.6.10.1 Distinction of short and long disturbances
The CPU must be informed when there are long
disturbances and when bus activities have returned to
normal operation. During long disturbances, a
CAN-controller enters the Bus-OFF state and the CPU
may use default values.
Minor disturbances of bus activities will not effect a
CAN-controller. In particular, a CAN-controller does not
enter the Bus-OFF state or inform the CPU of a short bus
disturbance.
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Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
14 INTERRUPT SYSTEM
External events and the real-time-driven on-chip
peripherals require service by the CPU asynchronous to
the execution of any particular section of code. To tie the
asynchronous activities of these functions to normal
program execution a multiple-source, two-priority-level,
nested interrupt system is provided. Interrupt response
latency is from 2.25 µs to 7.5 µs when using a 16 MHz
crystal. The latency time strongly depends on the
sequence of instructions executed directly after an
interrupt request. During a CAN-DMA transfer the interrupt
system is disabled (see Section 13.5.17). The P8xCE598
acknowledges interrupt requests from fifteen sources as
follows:
• INT0 and INT1: externally via pins 43 and 44
respectively
• Timer 0 and Timer 1: from the two internal counters
– If the capture function remains unused and the
Capture Register contents are ‘don't care’ then the
corresponding input pins ‘CTnI’, with ‘n = 0 ... 3’, may
be used as positive and/or negative edge triggered
external interrupts INT2 to INT5. But note that they
can not terminate the Idle mode because the Timer 2
is switched off then.
• Timer T2, 8 separate interrupts:
– 4 capture interrupts
– 3 compare interrupts
– An overflow interrupt.
• ADC end-of-conversion interrupt
• CAN Controller interrupt
• UART serial I/O port interrupt.
Each interrupt vectors to a separate location in Program
Memory for its service program. Each source can be
individually enabled or disabled by a corresponding bit in
the IEN0 or IEN1 register, moreover each interrupt may be
programmed to a HIGH or LOW priority level using a
corresponding bit in the IP0 or IP1 register. Also all
enabled sources can be globally disabled or enabled. Both
external interrupts can be programmed to be
level-activated or transition-activated, and an active LOW
level allows ‘wire-ORing’ of several interrupt sources to the
input pin.
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Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
interrupt enable registers
interrupt
interrupt priority
registers
sources
source enable
global enable
polling hardware
INT0
EXTERNAL
INTERRUPT
REQUEST 0
a1
a2
b1
b2
c1
c2
d1
d2
e1
e2
f1
a1
b1
c1
d1
e1
f1
CAN
SERIAL
PORT 1
ADC
g1
h1
i1
high
TIMER 0
OVERFLOW
priority
interrupt
request
j1
CT0I
TIMER 2
CAPTURE 0
k1
l1
m1
n1
o1
TIMER 2
COMPARE 0
f2
EXTERNAL
INTERRUPT
REQUEST 1
INT1
CT1I
g1
g2
h1
h2
i1
vector
SOURCE
IDENTIFICATION
TIMER 2
CAPTURE 1
a2
b2
c2
d2
e2
f2
TIMER 2
COMPARE 1
i2
j1
TIMER 1
OVERFLOW
j2
CT2I
k1
k2
l1
TIMER 2
CAPTURE 2
g2
h2
i2
low
priority
interrupt
request
TIMER 2
COMPARE 2
j2
l2
k2
l2
UART
SERIAL
PORT 0
T
m1
m2
n1
n2
o1
o2
R
m2
n2
o2
CT3I
TIMER 2
CAPTURE 3
vector
TIMER T2
OVERFLOW
SOURCE
IDENTIFICATION
MGA166
Fig.21 Interrupt system.
65
1996 Jun 27
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
14.1 Interrupt Enable and Priority Registers
14.1.1 INTERRUPT ENABLE REGISTER 0 (IEN0)
Table 71 Interrupt Enable register 0 (address A8H)
7
6
5
4
3
2
1
0
EA
EAD
ES1
ES0
ET1
EX1
ET0
EX0
Table 72 Description of the IEN0 bits
BIT
SYMBOL
EA
FUNCTION
7
General enable/disable control. If bit EA is:
LOW, then no interrupt is enabled.
HIGH, then any individually enabled interrupt will be accepted.
Enable ADC interrupt.
6
5
4
3
2
1
0
EAD
ES1
ES0
ET1
EX1
ET0
EX0
Enable SIO1 (CAN) interrupt.
Enable SIO0 (UART) interrupt.
Enable Timer 1 interrupt.
Enable External 1 interrupt.
Enable Timer 0 interrupt.
Enable External 0 interrupt.
14.1.2 INTERRUPT ENABLE REGISTER 1 (IEN1)
Table 73 Interrupt Enable register 0 (address E8H)
7
6
5
4
3
2
1
0
ET2
ECM2
ECM1
ECM0
ECT3
ECT2
ECT1
ECT0
Table 74 Description of the IEN1 bits
Logic 0 = interrupt disabled; logic 1 = interrupt enabled.
BIT
7
SYMBOL
ET2
FUNCTION
Enable T2 overflow interrupt(s).
6
ECM2
ECM1
ECM0
ECT3
ECT1
ECT1
ECT0
Enable T2 comparator 2 interrupt.
Enable T2 comparator 1 interrupt.
Enable T2 comparator 0 interrupt.
Enable T2 capture register 3 interrupt.
Enable T2 capture register 2 interrupt.
Enable T2 capture register 1 interrupt.
Enable T2 capture register 0 interrupt.
5
4
3
2
1
0
1996 Jun 27
66
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
14.1.3 INTERRUPT PRIORITY REGISTER 0 (IP0)
Table 75 Interrupt Priority register 0 (address B8H)
7
6
5
4
3
2
1
0
−
PAD
PS1
PS0
PT1
PX1
PT0
PX0
Table 76 Description of the IP0 bits
BIT
SYMBOL
FUNCTION
7
6
5
4
3
2
1
0
−
Not used.
PAD
PS1
PS0
PT1
PX1
PT0
PX0
ADC interrupt priority level.
SIO1 (CAN) interrupt priority level.
SIO0 (UART) interrupt priority level.
Timer 1 interrupt priority level.
External interrupt 1 priority level.
Timer 0 interrupt priority level.
External interrupt 0 priority level.
14.1.4 INTERRUPT PRIORITY REGISTER 1 (IP1)
Table 77 Interrupt Priority register 1 (address F8H)
7
6
5
4
3
2
1
0
PT2
PCM2
PCM1
PCM0
PCT3
PCT2
PCT1
PCT0
Table 78 Description of the IP1 bits
Logic 0 = low priority; logic 1 = high priority.
BIT
SYMBOL
PT2
FUNCTION
7
6
5
4
3
2
1
0
T2 overflow interrupt(s) priority level.
PCM2
PCM1
PCM0
PCT3
PCT2
PCT1
PCT0
T2 comparator 2 priority interrupt level.
T2 comparator 1 priority interrupt level.
T2 comparator 0 priority interrupt level.
T2 capture register 3 priority interrupt level.
T2 capture register 2 priority interrupt level.
T2 capture register 1 priority interrupt level.
T2 capture register 0 priority interrupt level.
1996 Jun 27
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Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
14.2 Interrupt Vectors
14.3 Interrupt Priority
The vector indicates the Program Memory location where
the appropriate interrupt service routine starts
(see Table 79).
Each interrupt source can be either high priority or low
priority. If both priorities are requested simultaneously, the
processor will branch to the high priority vector. If there are
simultaneous requests from sources of the same priority,
then interrupts will be serviced in the following order:
Table 79 Interrupt vectors
X0, S1, ADC, T0, CT0, CM0, X1, CT1, CM1, T1, CT2,
CM2, S0, CT3, T2.
SOURCE
External 0
BIT
VECTOR
X0
T0
X1
T1
S0
S1
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
004BH
0053H
005BH
0063H
006BH
0073H
A low priority interrupt routine can only be interrupted by a
high priority interrupt. A high priority interrupt routine can
not be interrupted.
Timer 0 overflow
External 1
Timer 1 overflow
Serial I/O 0 (UART)
Serial I/O 1 (CAN)
T2 capture 0
15 POWER REDUCTION MODES
The P8xCE598 has three software-selectable modes to
reduce power consumption. These are:
CT0
CT1
CT2
CT3
ADC
CM0
CM1
CM2
T2
T2 capture 1
• Sleep mode, affecting the CAN Controller only
• Idle mode, affecting the
T2 capture 2
T2 capture 3
– CPU (halted)
ADC completion
T2 compare 0
T2 compare 1
T2 compare 2
T2 overflow
– Timer 2 (stopped and reset)
– PWM0, PWM1 (reset, output = HIGH)
– ADC (aborted if in progress)
• Power-down mode, affecting the whole P8xCE598
device.
XTAL2
XTAL1
sleep
CAN
interrupts
serial ports
OSCILLATOR
timer blocks
CLOCK
GENERATOR
CPU
T2
PWM
ADC
IDL
PD
MGA167
Fig.22 Internal Sleep, Idle and Power-down clock configuration.
68
1996 Jun 27
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
15.1 Power Control Register (PCON)
Table 80 Power Control Register (address 87H)
7
6
5
4
3
2
1
0
SMOD
−
RFI
WLE
GF1
GF0
PD
IDL
Table 81 Description of the PCON bits
BIT
SYMBOL
SMOD
FUNCTION
7
Double Baud rate bit. When set to logic 1 the baud rate is doubled when the serial port
SIO0 is being used in Modes 1, 2 and 3.
6
5
−
Reserved.
RFI
RFI-Reduction Mode bit. When set to HIGH the toggling of ALE pin is prohibited. This
bit is cleared on RESET; see also ALE/PROG in Sections 2.1 and 2.2.
4
WLE
Watchdog Load Enable. This flag must be set by software prior to loading T3
(watchdog timer). It is cleared when T3 is loaded.
3
2
1
GF1
GF0
PD
General purpose flag bits.
Power-down bit. Setting this bit activates Power-down mode (note 1). It can only be set
if input EW is HIGH.
0
IDL
Idle mode bit. Setting this bit activates the Idle mode (note 1).
Note
1. If PD and IDL are set to HIGH at the same time, PD takes precedence. The reset value of PCON is 0X000000B.
There are three ways to terminate the Idle mode:
15.2 CAN Sleep Mode
• Activation of any enabled interrupt will cause PCON.0 to
be cleared by hardware, provided that the interrupt
source is active during Idle mode. After the interrupt is
serviced, the program continues with the instruction
immediately after the one, at which the interrupt request
was detected.
In order to reduce power consumption of the P8xCE598
the CAN Controller may be switched off (disconnecting the
internal clock) by setting the CAN Command Register bit 4
(Sleep) HIGH. The CAN Controller leaves this Sleep mode
by detecting either activity on the CAN-bus (dominant
bit-level on CRX0/CRX1; see Chapter 5, Table 1) or by
setting the Sleep bit to LOW. As the CPU can not only write
to the Sleep bit, but can also read it, the CAN Controller
status can be determined directly.
• The flag bits GF0 and GF1 may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.0 can also set or clear
one or both flag bits. When Idle mode is terminated by
an interrupt, the service routine can examine the status
of the flag bits.
15.3 Idle Mode
The instruction that sets bit PCON.0 to HIGH is the last
one executed in the normal operating mode before Idle
mode is activated.
• Another way of terminating the Idle mode is an external
hardware reset. Since the oscillator is still running, the
reset signal is required to be active only for two machine
cycles (24 oscillator periods) to complete to reset
operation.
Once in the Idle mode, the CPU status is preserved in its
entirety: the Stack Pointer, Program Counter, Program
Status Word, Accumulator, RAM and all other registers
maintain their data during Idle mode. The status of the
external pins during Idle mode is shown in see Table 82.
• The third way is the internally generated watchdog reset
after an overflow of Timer 3.
1996 Jun 27
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Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
A hardware reset affects the whole P8xCE598, but leaves
the contents of the on-chip RAM unchanged
15.4 Power-down Mode
The instruction that sets bit PCON.1 to HIGH, is the last
one executed before entering the Power-down mode. In
Power-down mode the oscillator of the P8xCE598 is
stopped. If the CAN Controller is in use, it is recommended
to set it into Sleep mode before entering Power-down
mode. However, setting PCON.1 to HIGH also sets the
Sleep bit (CAN Controller Command Register bit 4) to
HIGH.
(CAN Controller-and CPU's SFRs are reset, see
Section 13.5.2, Chapter 17 and Table 40). A CAN
Wake-Up interrupt during Power-down mode causes a
reset output pulse with a width of 6144 machine cycles
(4.6 ms with fCLK = 16 MHz). All hardware except that for
the CAN Controller of the P8xCE598 is reset (i.e. the
contents of all CAN Controller registers are preserved).
A capacitance connected to the RST pin can be used to
lengthen the internally generated reset pulse. If the pulse
exceeds 8192 machine cycles, the CAN Controller part is
reset too.
The P8xCE598 leaves Power-down mode either by a
hardware reset or by a CAN Wake-Up interrupt
(due to activity on the CAN-bus),
if the SIO1 (CAN) interrupt source is enabled
(contents of register IEN0 = 1X1XXXXXB).
Table 82 Status of external pins during Idle and Power-down modes
PWM0/
PWM1
MODE
PROGRAM
ALE
PSEN
PORT0 PORT1(1) PORT2
PORT3
PORT4
Idle
internal
external
1
1
0
0
1
1
0
0
port data port data port data port data port data
floating port data address port data port data
port data port data port data port data port data
floating port data port data port data port data
1
1
1
1
Power-down internal
external
Note
1. If the port pins P1.6 and P1.7 are used as the CAN transmitter outputs (CTX0 and CTX1), then during Sleep and
Power-down mode these pins output a ‘recessive’ level (see Sections 13.5.2 and 13.5.11).
1996 Jun 27
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Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
16 OSCILLATOR CIRCUITRY
handbook, halfpage
C1
XTAL1
The oscillator circuitry of the P8xCE598 is a single-stage
inverting amplifier in a Pierce oscillator configuration. The
circuitry between XTAL1 and XTAL2 is basically an
inverter biased to the transfer point. Either a crystal or
ceramic resonator can be used as the feedback element to
complete the oscillator circuitry. Both are operated in
parallel resonance. XTAL1 (pin 52) is the high gain
amplifier input, and XTAL2 (pin 51) is the output
(see Fig.23). If XTAL1 is driven from an external source,
XTAL2 must be left open (see Fig.24).
52
51
20 pF
C2
XTAL2
20 pF
MLC905
Fig.23 P8xCE598 oscillator circuit.
17 RESET CIRCUITRY
handbook, halfpage
The reset pin RST is connected to a Schmitt trigger for
noise rejection (see Fig.25). A reset is accomplished by
holding the RST pin HIGH for at least two machine cycles
(24 oscillator periods). The CPU responds by executing an
internal reset. During reset ALE and PSEN output a HIGH
level. In order to perform a correct reset, this level must not
be affected by external elements.
XTAL1
XTAL2
external clock
(not TTL compatible)
52
51
not connected
MLC906
Also with the P8xCE598, the RST line can be pulled HIGH
internally by a pull-up transistor activated by the Watchdog
timer T3. The length of the output pulse from T3 is
3 machine cycles. A pulse of such short duration is
necessary in order to recover from a processor or system
fault as fast as possible.
Fig.24 Driving P8xCE598 from an external source.
V
handbook, halfpage
DD
overflow timer T3
wake-up reset
During Power-down a reset could be generated internally
via the CAN Wake-Up interrupt. Then the RST pin is pulled
HIGH for 6144 machine cycles. In this case the CAN
Controller is not reset.
If the Watchdog timer or the CAN Wake-Up interrupt is
used to reset external devices, the usual capacitor
arrangement for Power-on-reset (see Fig.26) should not
be used.
CAN
RST
CPU
R
RST
on-chip
However, the internal reset is forced, independent of the
external level on the RST pin.
MGA170 - 1
The MAIN RAM and AUXILIARY RAM are not affected.
When VDD is turned on, the RAM content is indeterminate.
A reset leaves the internal registers as shown in Table 83).
Fig.25 On-chip reset configuration.
1996 Jun 27
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Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Table 83 Internal registers' contents after a reset
X = undefined state.
REGISTER
CANSTA
7
0
X
X
0
0
1
0
0
0
0
0
0
0
0
0
6
0
X
X
X
0
1
0
0
0
0
0
0
0
0
0
5
0
X
X
1
0
0
0
0
0
0
0
0
0
0
0
4
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
3
1
0
X
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
X
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
X
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
1
0
0
0
0
0
0
0
0
0
0
REGISTER
CPU part
7
6
5
4
3
2
1
0
CANCON
CANDAT
CANADR
SP
ACC
0
X
X
0
0
0
0
X
X
0
0
0
0
X
0
0
0
0
0
0
0
0
1
X
0
X
0
0
X
X
0
0
0
0
X
X
0
0
0
0
0
0
0
0
X
0
0
0
0
1
X
0
X
0
0
0
X
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
X
0
0
0
X
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
X
0
0
0
X
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
X
0
0
0
X
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
X
0
0
0
X
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
X
0
0
0
X
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
X
0
ADC0
ADCH
B
STE
CML0 to CML2
CMH0 to CMH2
CTCON
CTL0 to CTL3
CTH0 to CTH3
DPL
TCON
TH0, TH1
TMH2
TL0, TL1
TML2
TMOD
TM2CON
TM2IR
T3
DPH
IEN0
IEN1
IP0
CAN part
IP1
CR
0
1
X
1
1
X
0
X
0
X
X
1
X
X
1
X
X
0
1
X
0
PCH
CMR
PCL
SR
0
0
0
PCON
PSW
IR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
ACR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PWM0
PCWM1
PCWMP
P0 to P4
P5
AMR
BTR0
BTR1
OCR
TR
RTE
TXB 10 to 19
RXB 20 to 29
S0BUF
S0CON
1996 Jun 27
72
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
17.1 Power-on Reset
18.1 Addressing Modes
If the RST pin is connected to VDD via a 2.2 µF capacitor,
as shown in Fig.26, an automatic reset can be obtained by
switching on VDD (provided its rise time is <10 ms). The
decrease of the RST pin voltage depends on the capacitor
and the internal resistor RRST. That voltage must remain
above the lower threshold for at minimum the oscillator
start-up time plus 2 machine cycles.
Most instructions have a ‘destination/source’ field that
specifies the data type, addressing modes and operands
involved. For all these instructions, except from MOVs, the
destination operand is also a source operand
(e.g. ADD A, R7).
Five types of addressing modes are used:
• Register Addressing,
– R0 to R7 (4 banks)
– A,B,C (bit), AB (2 bytes), DPTR (double byte).
• Direct Addressing,
V
DD
handbook, halfpage
– lower 128 bytes of internal Main RAM
(including the 4 R0 to R7 register banks)
V
DD
– Special Function Registers (SFRs)
2.2 µF
– 128 bits in a subset of the internal Main RAM
(see Fig.5)
P8xCE598
– 128 bits in a subset of the Special Function Registers
(see Figs 6 and 7).
RST
R
• Register-Indirect Addressing,
RST
– internal RAM (@R0, @R1, @SP [PUSH/POP])
– internal Auxiliary RAM (@R0, @R1, @DPTR)
– external Data Memory (@DPTR).
MLB232
• Immediate Addressing,
Fig.26 Power-on-reset.
– Program Memory (in-code 8 bit or 16 bit constant)
• Base-Register-plus Index-Register-Indirect Addressing,
18 INSTRUCTION SET
– Program Memory look-up table
(@DPTR+A, @PC+A).
The P8xCE598 uses the powerful instruction set of the
P80C51. It consists of 49 single-byte, 45 two-byte and 17
three-byte instructions. Using a 16 MHz quartz, 64 of the
instructions are executed in 0.75 µs, 45 in 1.5 µs and the
multiply, divide instructions in 3 µs. A summary of the
instruction set is given in Tables 84, 85, 86, 87 and 88.
The first three addressing modes are usable for
destination operands.
1996 Jun 27
73
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
18.2 Instruction Set
For the description of the Data Addressing Modes and Hexadecimal opcode cross-reference see Table 88.
Table 84 Instruction set description: Arithmetic operations
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES CYCLES
Arithmetic operations
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
A,Rr
Add register to A
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
2*
A,direct
A,@Ri
A,#data
A,Rr
Add direct byte to A
25
Add indirect RAM to A
26, 27
24
Add immediate data to A
Add register to A with carry flag
Add direct byte to A with carry flag
Add indirect RAM to A with carry flag
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment A
3*
A,direct
A,@Ri
A,#data
A,Rr
35
36, 37
34
9*
A,direct
A,@Ri
A,#data
A
95
96, 97
94
04
INC
Rr
Increment register
0*
INC
direct
@Ri
Increment direct byte
05
INC
Increment indirect RAM
Decrement A
06, 07
14
DEC
DEC
DEC
DEC
INC
A
Rr
Decrement register
1*
direct
@Ri
Decrement direct byte
15
Decrement indirect RAM
Increment data pointer
16, 17
A3
DPTR
AB
MUL
DIV
Multiply A and B
A4
AB
Divide A by B
84
DA
A
Decimal adjust A
D4
1996 Jun 27
74
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Table 85 Instruction set description: Logic operations
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES CYCLES
Logic operations
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
A,Rr
AND register to A
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
5*
A,direct
A,@Ri
A,#data
direct,A
AND direct byte to A
AND indirect RAM to A
AND immediate data to A
AND A to direct byte
55
56, 57
54
52
direct,#data AND immediate data to direct byte
53
A,Rr
OR register to A
4*
A,direct
A,@Ri
A,#data
direct,A
OR direct byte to A
OR indirect RAM to A
OR immediate data to A
OR A to direct byte
45
46, 47
44
42
direct,#data OR immediate data to direct byte
43
A,Rr
Exclusive-OR register to A
6*
A,direct
A,@Ri
A,#data
direct,A
Exclusive-OR direct byte to A
Exclusive-OR indirect RAM to A
Exclusive-OR immediate data to A
Exclusive-OR A to direct byte
65
66, 67
64
62
direct,#data Exclusive-OR immediate data to direct byte
63
A
A
A
A
A
A
A
Clear A
E4
F4
Complement A
Rotate A left
23
RLC
RR
Rotate A left through the carry flag
Rotate A right
33
03
RRC
SWAP
Rotate A right through the carry flag
Swap nibbles within A
13
C4
1996 Jun 27
75
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Table 86 Instruction set description: Data transfer
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES CYCLES
Data transfer
A,Rr
A,direct (note 1) Move direct byte to A
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVC
MOVC
MOVX
MOVX
MOVX
MOVX
PUSH
POP
Move register to A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
1
1
1
1
2
1
1
2
2
2
2
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
E*
E5
A,@Ri
Move indirect RAM to A
E6, E7
74
A,#data
Move immediate data to A
Move A to register
Rr,A
F*
Rr,direct
Rr,#data
direct,A
Move direct byte to register
Move immediate data to register
Move A to direct byte
A*
7*
F5
direct,Rr
direct,direct
direct,@Ri
direct,#data
@Ri,A
Move register to direct byte
Move direct byte to direct
8*
85
Move indirect RAM to direct byte
Move immediate data to direct byte
Move A to indirect RAM
86, 87
75
F6, F7
A6, A7
76, 77
90
@Ri,direct
@Ri,#data
Move direct byte to indirect RAM
Move immediate data to indirect RAM
DPTR,#data 16 Load data pointer with a 16-bit constant
A,@A+DPTR
A,@A+PC
A,@Ri
Move code byte relative to DPTR to A
Move code byte relative to PC to A
Move external RAM (8-bit address) to A
Move external RAM (16-bit address) to A
Move A to external RAM (8-bit address)
Move A to external RAM (16-bit address)
Push direct byte onto stack
93
83
E2, E3
E0
A,@DPTR
@Ri,A
F2, F3
F0
@DPTR,A
direct
C0
direct
Pop direct byte from stack
D0
XCH
A,Rr
Exchange register with A
C*
XCH
A,direct
A,@Ri
Exchange direct byte with A
C5
XCH
Exchange indirect RAM with A
C6, C7
D6, D7
XCHD
A,@Ri
Exchange LOW-order digit indirect RAM with A
Note
1. MOV A,ACC is not permitted.
1996 Jun 27
76
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Table 87 Instruction set description: Boolean variable manipulation, Program and machine control
OPCODE
(HEX)
MNEMONIC
DESCRIPTION
BYTES CYCLES
Boolean variable manipulation
CLR
CLR
SETB
SETB
CPL
CPL
ANL
ANL
ORL
ORL
MOV
MOV
C
Clear carry flag
Clear direct bit
Set carry flag
Set direct bit
1
2
1
2
1
2
2
2
2
2
2
2
1
1
1
1
1
1
2
2
2
2
1
2
C3
C2
D3
D2
B3
B2
82
B0
72
A0
A2
92
bit
C
bit
C
Complement carry flag
bit
Complement direct bit
C,bit
C,/bit
C,bit
C,/bit
C,bit
bit,C
AND direct bit to carry flag
AND complement of direct bit to carry flag
OR direct bit to carry flag
OR complement of direct bit to carry flag
Move direct bit to carry flag
Move carry flag to direct bit
Program and machine control
ACALL
LCALL
RET
addr11
addr16
Absolute subroutine call
2
3
1
1
2
3
2
1
2
2
2
2
3
3
3
3
3
3
3
2
3
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
•1
Long subroutine call
12
22
32
♦ 1
02
80
73
60
70
40
50
20
30
10
B5
B4
B*
Return from subroutine
RETI
AJMP
LJMP
SJMP
JMP
Return from interrupt
addr11
addr16
rel
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to the DPTR
Jump if A is zero
@A+DPTR
rel
JZ
JNZ
rel
Jump if A is not zero
JC
rel
Jump if carry flag is set
JNC
rel
Jump if carry flag is not set
Jump if direct bit is set
JB
bit,rel
JNB
bit,rel
Jump if direct bit is not set
Jump if direct bit is set and clear bit
Compare direct to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to register and jump if not equal
JBC
bit,rel
CJNE
CJNE
CJNE
CJNE
DJNZ
DJNZ
NOP
A,direct,rel
A,#data,rel
Rr,#data,rel
@Ri,#data,rel Compare immediate to indirect and jump if not equal
B6, B7
D*
Rr,rel
Decrement register and jump if not zero
Decrement direct and jump if not zero
No operation
direct,rel
D5
00
1996 Jun 27
77
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Table 88 Description of the mnemonics in the Instruction set
MNEMONIC
DESCRIPTION
Data addressing modes
Rr
Working register R0-R7.
128 internal RAM locations and any special function register (SFR).
direct
@Ri
Indirect internal RAM location addressed by register R0 or R1 of the actual register bank.
8-bit constant included in instruction.
#data
#data 16
bit
16-bit constant included as bytes 2 and 3 of instruction.
Direct addressed bit in internal RAM or SFR.
addr16
16-bit destination address. Used by LCALL and LJMP.
The branch will be anywhere within the 64 kbytes Program Memory address space.
addr11
rel
11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2 kbytes
page of Program Memory as the first byte of the following instruction.
Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps.
Range is −128 to +127 bytes relative to first byte of the following instruction.
Hexadecimal opcode cross-reference
*
•
8, 9, A, B, C, D, E, F.
1, 3, 5, 7, 9, B, D, F.
0, 2, 4, 6, 8, A, C, E.
♦
1996 Jun 27
78
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Table 89 Instruction map
1996 Jun 27
79
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
19 ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134); note 1
SYMBOL
VDD
PARAMETER
MIN.
−0.5
MAX.
UNIT
voltage on VDD pins
+6.5
V
V
VI (note 1)
input voltage on any pin
−0.5
VDD + 0.5
(except CTX0, CTX1, CRX0, CRX1 and EA/VPP
)
VI (note 2)
II, IO
input voltage on EA/VPP to VSS
−0.5
+13
V
input/output current on any single I/O pin
(except from CTX0 and CTX1)
−
±10
mA
IOT
sink current of CTX0, CTX1 together
source current of CTX0, CTX1 together
total power dissipation (note 2)
storage temperature range
−
30
mA
mA
W
−
−20
1.0
Ptot
−
Tstg
Tamb
−65
+150
°C
operating ambient temperature range:
P83CE598 FFB/P80CE598 FFB
P83CE598 FHB/P80CE598 FHB
−40
−40
+85
°C
°C
+125
Notes
1. The following applies to the Absolute Maximum Ratings:
a) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any conditions other than those
described in the Chapters “AC characteristics” and “DC characteristics” of this specification is not implied.
b) This product includes circuitry specifically designed for the protection of its internal devices from the damaging
effect of excessive static charge. However, its suggested that conventional precautions be taken to avoid
applying greater than the rated maxima.
c) Parameters are valid over operating temperature range unless otherwise specified.
All voltages are with respect to VSS unless otherwise noted.
2. This value is based on the maximum allowable die temperature and the thermal resistance of the package, not on
device power consumption.
1996 Jun 27
80
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
20 DC CHARACTERISTICS
VDD = 5 V ± 10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified.
Tamb = −40 to +125 °C for the P8xCE598FFB; Tamb = −40 to +85 °C for the P8xCE598FHB.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Supply (digital part)
VDD
supply voltage
4.5
−
5.5
50
15
10
V
IDD
operating supply current
supply current Idle mode
supply current Idle & Sleep mode
supply current Power-down mode:
P8xCE598 FHB
fCLK = 16 MHz; note 1
fCLK = 16 MHz; note 2
fCLK = 16 MHz; note 3
note 4
mA
mA
mA
IDD(ID)
IDD(IS)
IDD(PD)
−
−
−
−
150
50
µA
µA
P8xCE598 FFB
Inputs
VIL
LOW level input voltage
(except EA, CRX0 and CRX1)
−0.5
−0.5
0.2VDD − 0.1 V
0.2VDD − 0.3 V
VIL1
VIH
LOW level input voltage EA
HIGH level input voltage
0.2VDD + 0.9 VDD + 0.5
V
(except RST, XTAL1, CRX0,CRX1)
VIH1
IIL
HIGH level input voltage
(RST and XTAL1)
0.7VDD
VDD + 0.5
−50
V
LOW level input current
Ports 1, 2, 3 and 4
VI = 0.45 V
−
−
µA
µA
ITL
input current HIGH-to-LOW
transition
VI = 2.0 V to 0.45 V
−650
Ports 1, 2, 3 and 4
(except P1.6 and P1.7)
ILI1
input leakage current
Port 0, EA, STADC, EW, P1.6, P1.7
0.45 V < VI < VDD
0.45 V < VI < VDD
−
−
±10
±1
µA
µA
ILI2
input leakage current Port 5
Outputs
VOL
LOW level output voltage
Ports 1, 2, 3 and 4
(except P1.6 and P1.7)
IOL = 1.6 mA; note 5
IOL = 3.2 mA; note 5
−
−
0.45
0.45
V
V
VOL1
LOW level output voltage
Port 0, ALE, PSEN, PWM0, PWM1,
P1.6, P1.7
VOH
HIGH level output voltage
Ports 1, 2, 3 and 4
(except P1.6 and P1.7)
IOH = −60 µA
IOH = −25 µA
IOH = −10 µA
IOH = −400 µA
IOH = −150 µA
2.4
−
−
−
−
−
−
V
V
V
V
V
V
0.75VDD
0.9VDD
2.4
VOH1
HIGH level output voltage
Port 0 in external bus mode,
ALE, PSEN, PWM0, PWM1
0.75VDD
0.9VDD
IOH = −40 µA; note 6
1996 Jun 27
81
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
SYMBOL
PARAMETER
CONDITIONS
IOH = −400 µA
MIN.
MAX.
UNIT
VOH2
HIGH level output voltage RST
2.4
−
V
IOH = −120 µA
0.8VDD
−
V
RRST
CI/O
RST pull-down resistor
I/O pin capacitance
50
150
10
kΩ
pF
test frequency = 1 MHz;
−
Tamb = 25 °C
Supply (analog part)
AVDD
supply voltage
AVDD = VDD ± 0.2 V
Port 5 = AVDD; note 1
note 2
4.5
−
5.5
2.5
2.5
V
AIDD
supply current operating
supply current Idle mode
mA
mA
AIDD(ID)
AIDD(IS)
−
supply current Idle and Sleep mode: note 3
P8xCE598 FHB
−
−
400
350
µA
µA
P8xCE598 xFx
AIDD(PD)
supply current Power-down mode: note 4
P8xCE598 FHB
−
−
400
350
µA
µA
P8xCE598 xFx
Analog inputs
AVIN
analog input voltage
AVSS − 0.2
AVDD + 0.2
V
AVREF−
AVREF+
RREF
reference voltage
AVSS − 0.2
−
V
−
AVDD + 0.2
50
V
resistance between
AVREF+ and AVREF−
10
kΩ
CIA
analog input capacitance
sampling time
−
−
−
15
pF
µs
µs
tADS
tADC
note 7
note 7
8tCY
50tCY
conversion time
(including sample time)
DLe
ILe
differential non-linearity
integral non-linearity
offset error
notes 8, 9 and 10
notes 8 and 11
notes 8 and 12
notes 8 and 13
notes 8 and 14
−
−
−
−
−
−
−
±1
LSB
LSB
LSB
%
±2
OSe
Ge
±2
gain error
±0.4
±3
Ae
absolute voltage error
channel-to-channel matching
crosstalk between P5 inputs
LSB
LSB
dB
Mctc
Ct
±1
0 to 100 kHz
−60
CAN input comparator (CRX0, CRX1)
VDIF
VHYST
II
differential input voltage (note 15)
hysteresis voltage (note 15)
input current
AVDD = 5 V ± 5%;
1.4 V < VI < AVDD − 1.4 V
±32
8
−
mV
mV
nA
30
−
±400
1996 Jun 27
82
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
CAN output driver (VDD = 5 V ± 5%)
VOLT
output voltage LOW
(CTX0 and CTX1)
Io = 1.2 mA; note 15
Io = 10 mA
−
−
V
V
0.1
0.6
−
V
V
V
V
VOHT
output voltage HIGH
(CTX0 and CTX1)
Io = −1.2 mA; note 15
Io = −10 mA; note 16
DD−0.1
DD−0.6
−
Reference (AVDD = 5 V ± 5%)
VREFOUT REF output voltage
−0.1 mA < IL < 0.1 mA;
CL = 10 nF; note 15;
1⁄2AVDD−0.1 1⁄2AVDD+0.1
V
bit Reference Active = HIGH
IREFIN
REF input current
1.5 V < VREFIN < AVDD−1.5 V;
−
±10
µA
bit Reference Active = LOW
Notes to the DC characteristics
1. Conditions for:
a) The digital operating current measurement: all output pins disconnected; XTAL1 is driven with tr = tf = 10 ns;
VIL = VSS + 0.5 V; VIH = VDD − 0.5 V; EA = RST = Port 0 = P1.6 = P1.7 = EW = VDD
;
STADC = VSS; CRX0 = 2.7 V; CRX1 = 2.3 V.
b) The analog operating current measurement: Port 5 = AVDD; CAN: register 6: = 00H;
load current reference voltage source 100 µA.
2. Conditions for:
a) The digital Idle mode supply current measurement: all output pins disconnected;
XTAL1 is driven with tr = tf = 10 ns; VIL = VSS + 0.5 V; VIH = VDD − 0.5 V; Port 0 = P1.6 = P1.7 = EW = VDD
EA = RST = STADC = VSS; CRX0 = 2.7 V; CRX1 = 2.3 V.
;
b) The analog Idle mode current measurement: Port 5 = AVDD; CAN: register 6: = 00H;
load current reference voltage source 100 µA.
3. Conditions for:
a) The digital Idle and Sleep mode supply current measurement: all output pins disconnected;
XTAL1 is driven with tr = tf = 10 ns; VIL = VSS + 0.5 V; VIH = VDD − 0.5 V;
Port 0 = P1.6 = P1.7 = EW = CRX0 = VDD; EA = RST = STADC = CRX1 = VSS
;
CAN: register 6: = 00H, register 7: = 12H, register 8: = 02H, register 0: = 20H, wait 15tCY
register 1: = 10H, wait for bit Sleep = 1.
,
b) The analog Idle and Sleep mode current measurement: Port 5 = AVDD
;
load current reference voltage source 100 µA.
4. Window devices have to be covered. Conditions for:
a) The digital Power-down mode supply current measurement: all output pins and Port 5 disconnected;
Port 0 = P1.6 = P1.7 = EW = CRX0 = VDD
EA = RST = STADC = CRX1 = XTAL1 = AVREF+ = AVREF− = CVSS = VSS
AVDD = VDD, but current into AVDD pin is not comprised in digital Power-down current.
b) The analog Power-down mode supply current measurement: Port 5 = AVDD
5. Capacitive loads on Port 0 and Port 2 may degrade the LOW level output voltage of ALE, Port 1 and Port 3.
;
;
.
During a HIGH-to-LOW transition on the Port 0 and Port 2 pins and a capacitive load > 100 pF, the ALE LOW level
may exceed 0.8 V. In the case that it is necessary to connect ALE to a Schmitt trigger input respectively use an
address latch with a Schmitt trigger STROBE input.
1996 Jun 27
83
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
6. Capacitive loads on Port 0 and Port 2 may cause a HIGH level voltage degradation of ALE and PSEN below 0.9VDD
during the address bits are stabilizing.
7. tCY = 12 tCLK is the machine cycle time.
8. AVREF+ = 5.12 V; AVREF− = 0 V; AVDD = 5.0 V.
9. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width.
10. The ADC is monotonic, there are no missing codes.
11. The integral non-linearity (ILe) is the peak difference between the centre of the steps of the actual and the ideal
transfer curve after appropriate adjustment of gain and offset error.
12. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve after
removing gain error, and a straight line which fits the ideal transfer curve. The offset error is constant at every point
of the actual transfer curve.
13. The gain error (Ge) is relative difference in percent between the straight line fitting the actual transfer curve after
removing offset error and the straight line which fits the ideal transfer curve. The gain error is constant at every point
on the transfer curve.
14. The absolute voltage error (Ae) is the maximum difference between the centre of the steps of the actual transfer curve
of the not calibrated ADC and the ideal transfer curve.
15. Not tested during production.
16. Source current for the CTX0, CTX1 outputs together.
MGA172
50
handbook, halfpage
I
DD
(mA)
40
30
20
(1)
(2)
10
(3)
(4)
0
0
4
8
12
(MHz)
16
f
CLK
(1) Maximum Operating mode (IDD); VDD = 5.5 V.
(2) Maximum Operating mode (IDD); VDD = 4.5 V.
(3) Maximum Idle and Sleep mode (IDD(IS) ); VDD = 5.5 V.
(4) Maximum Idle and Sleep mode (IDD(IS) ); VDD = 4.5 V.
Fig.27 Supply current (IDD) as a function of frequency at XTAL1 (fCLK).
1996 Jun 27
84
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
offset error OS
gain error G
1023
e
e
1022
1021
1020
1019
(2)
1018
code
out
7
6
5
4
3
2
1
0
(1)
(5)
(4)
(3)
1 LSB (ideal)
1
2
3
4
5
6
7
1018 1019 1020 1021 1022 1023 1024
AV (LSB
)
IN
ideal
−AV
offset error
AV
REF+
REF−
OS
1 LSB
=
e
ideal
MGA173
1024
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential non-linearity (DLe).
(4) Integral non-linearity (ILe).
(5) Centre of a step of the actual transfer curve.
Fig.28 ADC conversion characteristic.
85
1996 Jun 27
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
21 AC CHARACTERISTICS
See notes 1 and 2; CL = 100 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless otherwise specified.
VARIABLE CLOCK
fCLK = 16 MHz fCLK = 12 MHz
1.2 to 16 MHz
SYMBOL
PARAMETER
UNIT
MIN. MAX. MIN. MAX.
MIN.
MAX.
External Program Memory
tLHLL
tAVLL
tLLAX
tLLIV
ALE pulse width
85
8
−
127
28
48
−
−
2tCLK − 40
−
−
−
ns
ns
ns
address valid to ALE LOW
address hold after ALE LOW
ALE LOW to valid instruction in
ALE LOW to PSEN LOW
PSEN pulse width
−
−
t
t
CLK − 55
CLK − 35
28
−
−
−
150
−
233
−
−
4tCLK − 100 ns
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
23
143
−
43
205
−
t
CLK − 40
−
−
ns
ns
−
−
3tCLK − 45
PSEN LOW to valid instruction in
input instruction hold after PSEN
input instruction float after PSEN
address to valid instruction in
PSEN LOW to address float
83
−
145
−
−
0
−
−
−
3tCLK − 105 ns
0
0
−
ns
ns
−
38
208
10
−
59
312
10
tCLK − 25
−
−
5tCLK − 105 ns
−
−
10
ns
External data memory
tRLRH
tWLWH
tAVLL
RD pulse width
275
275
8
−
400
400
28
53
−
−
6tCLK − 100
6tCLK − 100
−
−
−
−
ns
ns
ns
ns
WR pulse width
−
−
address valid to ALE LOW
address hold after ALE LOW
RD LOW to valid data in
data hold after RD
−
−
t
t
CLK − 55
CLK − 30
tLLAX
33
−
−
−
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
148
−
252
−
−
5tCLK −165 ns
0
0
0
−
ns
ns
data float after RD
−
55
350
398
238
−
−
97
517
585
300
−
−
2tCLK − 70
ALE LOW to valid data in
address to valid data in
ALE LOW to RD or WR LOW
address valid to RD or WR LOW
RD or WR HIGH to ALE HIGH
data valid to WR transition
data valid time WR HIGH
data hold after WR
−
−
−
8tCLK − 150 ns
9tCLK − 165 ns
3tCLK + 50 ns
−
−
−
138
120
23
3
200
203
43
23
433
33
−
3tCLK − 50
4tCLK − 130
−
ns
ns
ns
ns
ns
ns
103
−
123
−
t
t
CLK − 40
CLK − 60
tCLK + 40
−
−
−
0
288
13
−
−
−
7tCLK − 150
CLK − 50
−
−
t
RD LOW to address float
0
0
−
Notes
1. For the AC Characteristics the following conditions are valid:P8xCE598 FxB:
VDD = 5 V ± 10%; Tamb = −40 to +85 °C (125 °C); fCLK = 1.2 to 16 MHz.
1
fCLK
2. tCLK
=
= one oscillator clock period; tCLK = 62.5 ns at fCLK = 16 MHz.
----------
1996 Jun 27
86
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Table 90 CAN characteristics.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
CAN input comparator/output driver
tsd
sum of input and output delay AVDD = 5 V ± 5%; VDIF = ± 32 mV;
1.4 V < VI < AVDD − 1.4 V
P8xCE598 xFx
−
−
60
70
ns
ns
P8xCE598 FHB
2.4 V
2.0 V
0.8 V
test points
0.45 V
(a)
float
2.4 V
2.4 V
2.0 V
0.8 V
2.0 V
0.8 V
0.45 V
0.45 V
(b)
MGA174
AC testing inputs are driven at 2.4 V for a HIGH and 0.45 V for a LOW.
Timing measurements are taken at 2.0 V for a HIGH and 0.8 V for a LOW, see Fig.29 (a).
The float state is defined as the point at which a Port 0 pin sinks 3.2 mA or sources 400 µA at the voltage test levels, see Fig.29 (b).
Fig.29 AC testing input, output waveform (a) and float waveform (b).
1996 Jun 27
87
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
one machine cycle
one machine cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
P1 P2
P1 P2
P1 P2 P1 P2 P1 P2
P1 P2 P1 P2 P1 P2
P1 P2 P1 P2 P1 P2
P1 P2
XTAL1
INPUT
ALE
PSEN
RD
dotted lines
are valid when
RD or WR are
active
only active
during a read
from external
data memory
only active
during a write
to external
WR
data memory
BUS
(PORT 0)
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
external
program
memory
fetch
PORT 2
address A8 - A15
address A8 - A15
address A8 - A15
address A8 - A15
BUS
(PORT 0)
inst.
in
address
A0 - A7
inst.
in
address
A0 - A7
address
A0 - A7
data output or data input
read or
write of
external data
memory
address A8 - A15
address A8 - A15 or Port 2 out
address A8 - A15
PORT 2
PORT
OUTPUT
old data
new data
PORT
INPUT
sampling time of I/O port pins during input (including INT0 and INT1)
SERIAL
PORT
CLOCK
MGA180
The Port 5 input buffers have a maximum propagation delay of 300 ns.
As a result Port 5 sample time begins 300 ns before state S5 and ends when S5 has finished.
Fig.30 Instruction cycle timing.
1996 Jun 27
88
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
t
CY
a
t
t
LLIV
LHLL
ALE
PSEN
t
LLPL
t
PLPH
t
LLAX
t
t
t
PXIZ
AVLL
PLIV
PORT 0
PORT 2
A0 to A7
inst. input
A0 to A7
inst. input
t
t
PXIX
PLAZ
t
AVIV
address A8 to A15
address A8 to A15
MGA176
Fig.31 Read from external Program Memory.
t
CY
ALE
t
t
t
LHLL
LLDV
WHLH
PSEN
RD
t
t
RLRH
LLWL
t
t
t
RHDZ
AVLL
LLAX
t
t
t
RHDX
AVWL
RLDV
PORT 0
PORT 2
A0 to A7
data input
t
RLAZ
t
AVDV
address A8 to A15 (DPH) or Port 2
MGA177
Fig.32 Read from external Data Memory.
89
1996 Jun 27
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
t
CY
t
t
WHLH
LHLL
ALE
PSEN
t
t
WLWH
LLWL
WR
t
AVWL
t
t
t
t
WHQX
AVLL
LLAX
QVWH
t
QVWX
PORT 0
PORT 2
A0 to A7
data output
address A8 to A15 (DPH) or Port 2
MGA178
Fig.33 Write to external Data Memory.
t
t
t
f
HIGH
r
V
V
V
V
IH1
IH1
0.8 V
IH1
IH1
0.8 V
0.8 V
0.8 V
CLK
t
LOW
t
MGA175
Fig.34 External clock drive XTAL1 (see Table 91).
90
1996 Jun 27
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Table 91 External clock drive XTAL1
VARIABLE CLOCK
(fCLK = 1.2 to 16 MHz)
SYMBOL
PARAMETER
UNIT
MIN. MAX.
833.3
tCLK
tHIGH
tLOW
tr
oscillator clock period (P83CE598)
62.5
20
20
−
ns
ns
ns
ns
ns
µs
HIGH time
LOW time
t
t
CLK − tLOW
CLK − tHIGH
rise time
20
20
10
tf
fall time
−
tCY
cycle time (12 × tCLK
)
0.75
Table 92 UART Timing in Shift Register Mode
fCLK
SYMBOL
PARAMETER
16 MHz
12 MHz
VARIABLE CLOCK
MIN. MAX.
UNIT
MIN. MAX. MIN. MAX.
tXLXL
Serial Port clock cycle timing
0.75
−
1.0
700
50
0
−
12 tCLK
−
−
−
−
ms
ns
ns
ns
tQVXH
tXHQX
tXHDX
tXHDV
output data setup to clock rising edge 492
output data hold after clock rising edge 8.0
−
−
10 tCLK − 133
−
−
2 tCLK − 117
input data hold after clock rising edge
clock rising edge to input data valid
0
−
−
0
−
492
−
700
−
10 tCLK − 133 ns
n
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
t
XLXL
CLOCK
t
XHQX
t
QVXH
OUTPUT DATA
WRITE TO SBUF
INPUT DATA
t
XHDX
SET TI
t
XHDV
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CLEAR RI
SET RI
MGA179
Fig.35 UART waveforms in Shift Register Mode.
1996 Jun 27
91
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
It is measured from the initiation of the transfer up to the
signalling of reception.
22 CAN APPLICATION INFORMATION
22.1 Latency time requirements
For instance, this is the period of time between
programming the CAN Command Register bit 0
(Transmission Request) to HIGH and the time getting an
interrupt at a receiving CAN-device (due to the reception
of the respective message).
Real-time applications require the ability to process and
transfer information in a limited and predetermined period
of time. If knowing this total time and the time required to
process the information, the (maximum allowed) transfer
delay time is given.
22.1.1 MAXIMUM ALLOWED BIT-TIME CALCULATION
The maximum allowed bit-time (tBIT) due to latency time requirements can be calculated as:
tMAX TRANSFER TIME
tBIT
≤
(1)
--------------------------------------------------------------------------------------------
(nBIT, MAX LATENCY + nBIT, MESSAGE
)
Where:
• tMAX TRANSFER TIME
:
the maximum allowed transfer delay time (application-specific).
• nBIT, MAX LATENCY
:
the maximum latency time (in terms of number of bits), which depends on the
actual state of the CAN network (e.g. another message already on the network).
• nBIT, MESSAGE
:
the number of bits of a message; it varies with the number of transferred data bytes
nDATA BYTES (0..8) and Stuffbits like:
44 + 8.nDATA BYTES ≤ nBIT, MESSAGE ≤ 52 + 10.nDATABYTES
(2)
Example:
For the calculation of nBIT, MAX LATENCY the following is assumed (the term ‘our message’ refers to that one the latency
time is calculated for):
• Since at maximum one-bit-time ago another CAN Controller is transmitting
• A single error occurs during the transmission of that message preceding ours, leading to the additional transfer of one
Error Frame
• ‘our message’ has the highest priority,
giving:
n
BIT, MAX LATENCY ≥ 44 + 8.nDATA BYTES, WORST CASE + 18
(3)
(4)
n
BIT, MAX LATENCY ≤ 52 + 10.nDATA BYTES, WORST CASE + 18
Where:
• The additional 18 bits are due to the Error Frame and the Intermission Field preceding ‘our message’.
• nDATA BYTES, WORST CASE denotes the number of data bytes contained by the longest message being used in a given
CAN network.
1996 Jun 27
92
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
22.1.2 CALCULATING THE MAXIMUM BIT-TIME
Table 93 Example for calculating the maximum bit-time
STATEMENT
COMMENTS
tMAX TRANSFER TIME = 10 ms
nDATA BYTES, WORST CASE = 6
nDATA BYTES = 4
assumption.
longest message in that network; assumption.
‘our message’; assumption.
using Equations (3) and (4).
using Equation (2).
n
BIT MAX LATENCY ≤ 130
MESSAGE ≤ 92
n
10 ms
(130 + 92)
tBIT
≤
= 0.045 ms = 45 µs
using Equation (1).
-----------------------------
22.2 Connecting a P8xCE598 to a bus line
(physical layer)
22.2.3 DETECTION AND HANDLING OF BUS WIRING
FAILURES
Using the P8xCE598 a superior wiring failure tolerance
and detection performance can be achieved. This requires
both bus lines to be mutually decoupled as shown in
Fig.40. Each bus wire is based separately to a reference
22.2.1 ON-CHIP TRANSCEIVER
The P8xCE598 features an on-chip differential transceiver
including output driver and input comparator both being
configurable (see Fig.37). Therefore it supports many
types of common transmission media such as:
voltage of 1⁄2AVDD
.
The diodes suppress reverse current in case of a
termination circuit being not properly powered or a bus line
being short i.e. to a voltage higher than 5 V. Applying this
bus termination circuit the following wiring failures on the
bus are detectable and can be handled:
• Single wire bus line
• Two-wire bus line (differential)
• Optical cable bus line.
The P8xCE598 can directly drive a differential bus line.
An example is given in Fig.38 for a bus line having a
characteristic impedance of 120 Ω. Direct interfacing to
the bus line is well suited for applications with limited
requirements concerning electromagnetic susceptibility,
wiring failure tolerance and protection against transients.
• Interruption of one bus wire at any location.
• Short-circuit of one bus wire to ground or battery
voltage.
• Short-circuit between the bus wires.
A bus failure can be detected e.g. by a drop out of a status
message, regularly being transmitted on the bus. If a bus
wire is corrupted the following actions have to be taken:
22.2.2 TRANSCEIVER FOR IN-VEHICLE COMMUNICATION
Fig.39 shows a versatile transceiver implementation
designed for automotive applications. It features a bit rate
of up to 1 Mbit/s and dissipates low power during standby
(1.4 mA). Thus it is suitable also for applications requiring
a Sleep mode function with system activation via the bus
line. The transceiver provides and extended common
mode range for high electromagnetic susceptibility
performance.
• Switch the corresponding comparator input over to a
reference voltage of 1⁄2AVDD
.
• Disable the corresponding output driver stage.
As a consequence communication will continue on that
bus wire not being corrupted. The required reference
voltage and the switches for the comparator inputs are
provided on-chip. An output driver stage can be disabled
by reconfiguration of the on-chip output driver
(reprogramming of the Output Control Register of the
P8xCE598; see Section 13.5.11, Table 51). To find out
which of the bus wires is corrupted a heuristic method is
applied.
Two external driver transistors amplify the output current
to 35 mA typically and provide protection against
overvoltage conditions on the bus line (e.g. due to an
accidental short-circuit between a bus wire and battery
voltage). The serial diodes prevent in combination with the
transistors the bus from being blocked in case of a bus not
powered. More than 32 nodes may be connected to the
bus line.
1996 Jun 27
93
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
handbook, 4 columns
P8xC592/P8xCE598
CAN-CONTROLLER
CTX0 CRX0 CRX1 Px,y
R
ext
5 V
V
TxD
RxD
Rs
V
ref
CC
PCA82C250T
CAN-TRANSCEIVER
100 nF
GND
CANH
CANL
CAN BUS
LINE
124 Ω
124 Ω
MGC125
Fig.36 Application of a CAN-Transceiver (PCA82C250T).
1996 Jun 27
94
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
P8xCE598
OUTPUT CONTROL REGISTER
COMMAND REGISTER
CONTROL REGISTER
TXD
1/2AV
DD
COMP OUT
OUTPUT CONTROL LOGIC
CV
CV
SS
AV
AV
SS
CTX0 CTX1
CRX0 CRX1
REF
DD
DD
MLB235
5 V
5 V
to the CAN bus line
Fig.37 Structure of on-chip CAN-Transceiver.
1996 Jun 27
95
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
OUTPUT CONTROL REGISTER
10101010B (AAH)
P8xCE598
5 V
CTX0
CTX1
CRX0
CRX1
R1
240 Ω
R2
240 Ω
R3
R4
0 to 1.5 kΩ
0 to 1.5 kΩ
5 V
750 Ω
120 Ω
750 Ω
(1)
120 Ω
CAN BUS LINE
MLB236
(1) Characteristic line impedance 120 Ω
Fig.38 Direct interface to a two-wire differential bus.
1996 Jun 27
96
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
OUTPUT CONTROL REGISTER
11111010B (FAH)
or 10101010B (AAH)
P8xCE598
CTX0
CTX1
CRX0
CRX1
R7
R3
3.9 kΩ
R4
3.9 kΩ
R8
3.9 kΩ
3.48 kΩ
R9
R10
3.48 kΩ
3.9 kΩ
T1
T2
BST100
BST72A
5 V
5 V
D1
1N4150
D2
1N4150
R1
10 Ω
R2
10 Ω
R5
4.53 kΩ
R6
4.53 kΩ
BUS NODE
120
Ω
120
Ω
(1)
CAN BUS LINE
MLB237
(1) Characteristic line impedance 120 Ω
Fig.39 In-vehicle Transceiver.
1996 Jun 27
97
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
h
BUS NODE
5 V
5 V
C1
100 nF
C3
100 nF
C5
100 nF
C7
100 nF
D1
D3
D5
D7
1N4150
1N4150
1N4150
1N4150
R1
120 Ω
R3
120 Ω
R5
120 Ω
R7
120 Ω
(1)
CAN BUS LINE
R2
120 Ω
R4
120 Ω
R6
120 Ω
R8
120 Ω
(1) Characteristic line impedance 120 Ω
1N4150
D2
1N4150
D4
1N4150
D6
1N4150
D8
C2
100 nF
C4
100 nF
C6
100 nF
C8
100 nF
MGA188
Fig.40 Bus termination with decoupled wires.
1996 Jun 27
98
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
Thus more optical power is provided to compensate for
losses in the optical connectors and the optical star. The
P8xCE598 features an on-chip 1⁄2AVDD reference voltage
output so only a capacitor is required for the receiver part.
Two optical fibres are used to connect the bus nodes. The
TX-fibre transfers the output signal of the CAN Controller
to the optical star. The optical star transfers the TX-fibre
input signal over to all the RX-fibres. The RX-fibres
transfer the resulting optical signal over to the receivers of
all the bus nodes.
22.2.4 CONNECTION TO AN OPTICAL BUS LINE
Using an optical medium provides the following
advantages:
• Bus nodes are galvanically decoupled.
• Optical cable features very high noise immunity.
• No noise emission by the bus cable.
An example for an interface to an optical connector is
given in Fig.41. In most cases a transistor is required to
amplify the TX-output current.
OUTPUT CONTROL REGISTER
00011110B (1EH)
or 00010110B (16H)
P8xCE598
CTX0
CTX1
CRX0
CRX1
REF
R2
3.9 kΩ
C1
10 nF
T1
BS170
C2
100 nF
R1
56 Ω
5 V
5 V
OPTICAL
CONNECTOR
HBFR - 0501
SERIES
optical
cable
PASSIVE OPTICAL STAR
MLB238
Fig.41 Optical Transceiver.
99
1996 Jun 27
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
22.2.5
P8XCE598 CAN INTERRUPT HANDLER SOFTWARE EXAMPLE (INCLUDING FAST DMA TRANSFER)
MCS-51 MACRO ASSEMBLER CAN interrupt-handler
LOC OBJ
LINE SOURCE
1
$TITLE 8XCE598 (CAN interrupt-handler)
$NOSYMBOLS NOPAGING
00A0
00A1
2
3
4
;********************************************************************************************************
5
;
6
;Very fast receive-routine for the 8XCE598 CAN Interface. It:
• is embedded in the interrupt-handler for the CAN Controller,
• uses the DMA-logic and
7
8
9
• handles up to eight different messages
;(if these have the same leading 8 identifier-bits).
;
00A2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
;To allow for faster receive-routine, it is assumed that all other routines
;accessing the CAN Controller, disable the interrupt of the CAN Controller
;(IEN0.5) during their execution.
00A5
00A7
;
;Version:
;Date:
;Author:
;at:
1.0
12-April-90
Bernhard Reckels
Philips Components Application Lab., Hamburg (PCALH)
00A9
00AB
00AD
;********************************************************************************************************
;********************************************************************************************************
;initial stuff
;********************************************************************************************************
;equatas
;addresses of Special Function Registers
00AE
00AF
CANADR
CANDAT
CANCON
CANSTA
EQU
EQU
EQU
EQU
0DBH
0DAH
0D9H
0D8H
00B0
1996 Jun 27
100
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
LOC OBJ
LINE SOURCE
35
36
37
38
39
40
41
42
43
44
;commands for the CAN Controller / DMA logic
CAN_REF_REL
CAN_RX_DMA
EQU
EQU
00000100B
80H + 22
;Release Receive Buffer
00A0
00A1
;Rx DMA-transfer
; addresses of CAN Controller internal registers
CAN_REF
EQU
20
;1st address of Rx-buffer
; masks
INT_FLAG_MASK EQU
ID2_0_MASK EQU
00011111B
11100000B
;all CAN's interrupt-flags
;only ID.2 ... ID.0 bits
00A2
45
46
47
48
; jump-address for a CAN Controller interrupt
CSEG at 2BH
020080 49
LJMP
CAN_INT_HANDLER
; CAN's interrupt-vector
00A5
00A7
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
; data storage
DSEG at 20H
CAN_INT_IMAGE: DS
1
00A9
00AB
00AD
BSEG at 00H
CAN_INT_RX:
DBIT
DBIT
DBIT
DBIT
DBIT
1
1
1
1
1
; = CAN_INT_IMAGE.0
; = CAN_INT_IMAGE.1
; = CAN_INT_IMAGE.2
; = CAN_INT_IMAGE.3
; = CAN_INT_IMAGE.4
CAN_INT_TX:
CAN_INT_KR:
CAN_INT_OV:
CAN_INT_WK:
;********************************************************************************************************
;CAN Controller interrupt-handler
00AE
00AF
;
;Only the receive-interrupt is coded.
;
00B0
;*******************************************************************************************************
CSEG at 080H
1996 Jun 27
101
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
LOC OBJ
00A0
LINE SOURCE
CAN_INT_HANDLER:
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
00A1
; first save used registers
C0D0
C0E0
PUSH
PUSH
PSW
ACC
; store the CAN Controller's Interrupt Register contents
; (here: at a bit-addressable location).
00A2
; This is necessary because after reading the Interrupt Register
; its contents is cleared, but − on the other hand − several flags
; may be set in coincidence.
E5D9
541F
MOV
ANL
A, CANON
A, #INT_FLAG_MASK
CAN_INT_IMAGE, A
; only interrupt-flags
00A5 F520
00A7
MOV
;dispatcher-----------------------------------------------------------------------------------------------
INT_TEST0:
00A9 100000 90
JBC
CAN_INT_RX,CAN_RX_SERV
;receive-interrupt?
00AB
00AD
91
92
93
94
95
96
97
98
99
INT_TEST1:
; here the dispatcher has to be completed according
; to the application-specific requirements
; ...
; ...
; end of dispatcher------------------------------------------------------------------------------------
;Rx-serve--------------------------------------------------------------------------------------------------
00AE
00AF
100 ; copy message (Data-Field only) from CAN- to CPU memory
101
102 CAN_RX_SERVE
00B0
103
; read 2nd Descriptor-Byte from the Rx-Buffer (address 21)
75DB15 104
MOV
MOV
CANADR, #CAN_REF + 1
A, CANDAT
E5DA
105
106
1996 Jun 27
102
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
LOC OBJ
00A0
00A1
54E0
C4
LINE SOURCE
107
; determine the destination address in data-memory for the
; message's Data-Field
108
109
ANL
SWAP
RR
A, #ID2_0_MASK
; use ID.2 ... ID.0 only
110
A
A
03
111
; A = 4*ID.2 + 2*ID.1 + ID.0
112
; this value is used as an index for an array of 8 bytes
; containing the destination-addresses for the 8 different
; messages. Note, that the #RX_ARRAY_OFFSET is due to the
; program counter-relative access to the array.
113
114
00A2
2415
83
115
116
ADD
A, #RX_ARRAY_START − RX_ARRAY_OFFSET
117
MOVC
A, @A + PC
118
RX_ARRAY_OFFSET:
119
00A5
00A7
120
; if a message passes the acceptance-filter of the CAN
; Controller, but the CPU doesn't need it, the array
; entry's value may be set to zero indicating this.
; The following <jz> instruction cares for this.
121
122
123
6007
00A9
124
JZ
CAN_RX_READY
125
00AB
126
; now copy the Data-Field (only) from CAN- to CPU memory
; with the aid of the DMA-logic. Note, that a TX-DMA is
; performed when writing 8AH (DMA + address 10) into CANADR
; and a RX-DMA is performed when writing 94H (DMA + address 20)
; ... 9DH (DMA + address 29) into CANADR. Here address 22 is
; used to copy just the Data-Field.
00AD
127
128
129
130
131
F5D8
132
MOV
MOV
CANSTA, A
; data-memory address
75DB96 133
CANADR, #CAN_RX_DMA ; starts RX-DMA at address 22
134
135
136
137
138
139
140
141
142
00AE
00AF
; the DMA-transfer is done in at maximum 2 instruction cycles.
; During the transfer, neither the data-memory (RAM) nor one
; of the SFRs CANADR, CANDAT, CANCON and
; CANSTA may be accessed by the CPU.
; For simplicity, two NOPs are used here.
NOP
00B0
00
00
NOP
00A0
1996 Jun 27
103
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
LOC OBJ
LINE SOURCE
00A1
143
144
145
146
; after reading the Rx-Buffer it must be released back to
; the CAN Controller. In coincidence, the Clear Overrun bit
; (CANCON.3) may be set, regardless of an existing or
; non-existing data overrun.
147 CAN_RX_READY:
75D904 148 MOV
CANCON, #CAN_RBF_REL
149
150
151
152
153
154
155
156
157
158
159
160
00A2
; if no other interrupt-flag is set, the interrupt-handler
; for the CAN Controller can be left. Otherwise further
; services are required.
E520
70E4
MOV
JNZ
A, CAN_INT_IMAGE
INT_TEST1
00A5
00A7
; no other service is required, so the interrupt-handler
; is left.
D0E0
D0D0
POP
POP
RETI
ACC
PSW
00A9 32
00AB
161 ; end of Rx-serve-------------------------------------------------------------------------------------
162
00AD
163
164
165
166
; here the array follows containing 8 destination-addresses
; for up to 8 different messages to be received. The values
; are fully application-specific (the values below show an
; example only).
167 RX_ARRAY_START:
E0
00
168
169
170
171
172
173
DB
DB
; ...
DB
0E0H
000H
; Rx-message #0
; this message is not used
00AE
00AF FA
0FAH
; RX-message #7, containing 6 data bytes
00B0
END
REGISTER BANK(S) USED: 0
ASSEMBLY COMPLETE, NO ERRORS FOUND
1996 Jun 27
104
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
23 PACKAGE OUTLINES
QFP80: plastic quad flat package;
80 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SOT318-1
y
X
A
64
65
41
40
Z
E
e
Q
A
2
H
A
E
(A )
3
E
A
1
w M
p
θ
pin 1 index
L
p
b
L
25
80
detail X
1
24
w M
Z
D
v
M
A
b
p
e
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
Q
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.36 2.87
0.10 2.57
0.45 0.25 20.1 14.1
0.30 0.13 19.9 13.9
24.2 18.2
23.6 17.6
1.0 1.43
0.6 1.23
1.0
0.6
1.2
0.8
mm
3.3
0.25
0.8
1.95
0.2
0.2
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-02-04
SOT318-1
1996 Jun 27
105
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
24 SOLDERING
24.1 Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
24.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP
packages.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
24.4 Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
24.3 Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
1996 Jun 27
106
Philips Semiconductors
Product specification
8-bit microcontroller with on-chip CAN
P8xCE598
25 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
26 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Jun 27
107
Philips Semiconductors – a worldwide company
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Tel. +31 40 27 83749, Fax. +31 40 27 88399
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Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
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Brazil: see South America
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Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
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Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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Tel. +7 095 926 5361, Fax. +7 095 564 8323
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Slovakia: see Austria
Slovenia: see Italy
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,
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Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427
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Tel. +49 40 23 52 60, Fax. +49 40 23 536 300
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Tel. +972 3 645 0444, Fax. +972 3 648 1007
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Tel. +90 212 279 2770, Fax. +90 212 282 6707
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557
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Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,
Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 708 296 8556
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +1 800 234 7381, Fax. +1 708 296 8556
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 825 344, Fax.+381 11 635 777
Middle East: see Italy
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Internet: http://www.semiconductors.philips.com/ps/
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1996
SCA50
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
617021/1200/04/pp108
Date of release: 1996 Jun 27
Document order number: 9397 750 00915
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Description
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Automotive
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Systems
Communications
The P8xCE598 is a single-chip 8-bit high-performance microcontroller with on-chip CAN-controller, derived from the 80C51 microcontroller
family.
It uses the powerful 80C51 instruction set. The P8xCE598 is manufactured in an advanced CMOS process, and is designed for use in
automotive and general industrial applications. In addition to the 80C51 standard features, the device provides a number of dedicated
hardware functions for these applications.
PC/PC-peripherals
Cross reference
Models
Two versions of the P8xCE598 will be offered:
Packages
Application notes
Selection guides
Other technical documentation
End of Life information
Datahandbook system
l P80CE598 (without ROM)
l P83CE598 (with ROM)
Hereafter these versions will be referred to as P8xCE598.
The temperature range includes (max. fCLK = 16 MHz):
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l -40 to +85 °C version, for general applications
l -40 to +125 °C version for automotive applications.
The P8xCE598 combines the functions of P8XC552 (microcontroller) and the PCA82C200 (Philips CAN-controller) with the following
enhanced features:
P8xCE598
P8xCE598
l 32 kbytes Program Memory
l 2 x 256 bytes Data Memory
l DMA between CAN Transmit/Receive Buffer and internal RAM. The main differences to the P8xC552 microcontroller are:
l 32 kbytes programmable ROM (P8xC552 has 8 kbytes)
l Additional 256 bytes RAM
l A CAN-controller instead of the I2C-serial interface.
Electromagnetic Compatibility (EMC)
Primary attention is paid to the reduction of electromagnetic emission of the microcontroller P8xCE598. The following features reduce the
electromagnetic emission and additionally improve the electromagnetic susceptibility:
l One analog part power supply pin (AVDD ) and one analog part ground pin (AVSS ), placed as a pair of pins on one side of the
package , providing power supply (+5V) and ground for ADC, CAN receiver and reference voltage.
l Four digital part supply voltage pins (VDD1 to VDD4 ) and four digital part ground pins (VSS1 to VSS4 ) are provided on the package.
These pins, one VDD and one VSS as a pair of pins are placed on each of the four sides of the package to provide:
- VDD1 /VSS1 for internal logic (CPU, Timers/counters, Memory, CAN, UART, ADC)
- VDD2 /VSS2 for Port 1, Port 3 and Port 4, and PWM0 and PWM1 outputs
- VDD3 /VSS3 for the on-chip oscillator
- VDD4 /VSS4 for the Port 0, Port 2, ALE output and PSEN output.
l External capacitors should be connected across associated VDDx and VSSx pins (i.e. VDD1 and VSS1 ). Lead length should be as short
as possible. Ceramic chip capacitors are recommended (100 nF).
l One CAN supply voltage pin (CVDD ) and one CAN ground pin (CVSS ) as a pair of pins placed on one side of the package providing
(digital part) power supply (+5V) and ground for the CAN transmitter outputs.
l Internal decoupling capacitance improves the EMC radiation behaviour and the EMC immunity.
Recommendation on ALE
For application that require no external memory or temporarily no external memory: the ALE output signal (pulses at a frequency of 1 ¤6
fOSC) can be disabled under software control (bit 5 in PCON SFR: ‘RFI’); if disabled, no ALE pulse will occur. ALE pin will be pulled down
internally, switching an external address latch to a quiet state. The MOVX instruction will still toggle ALE as a normal MOVX.
ALE will retain its normal HIGH value during Idle mode and a LOW value during Power-down mode while in the ‘RFI reduction mode’.
Additionally during internal access (EA = 1) ALE will toggle normally when the address exceeds the internal Program Memory size. During
external access (EA = 0) ALE will always toggle normally, whether the flag ‘RFI’ is set or not.
Refer to our CAN page for more information
Features
l 80C51 central processing unit (CPU)
l 32 kbytes on-chip ROM, externally expandible to 64 kbytes
l 2 x 256 bytes on-chip RAM, externally expandible to 64 kbytes
l Two standard 16-bit timers/counters
l One additional 16-bit timer/counter coupled to four capture and three compare registers
l 10-bit ADC with 8 multiplexed analog inputs
l Two 8-bit resolution Pulse Width Modulated outputs
l 15 interrupt sources with 2 priority levels (2 to 6 external interrupt sources possible)
l Five 8-bit I/O ports, plus one 8-bit input port shared with analog inputs
l CAN-controller (CAN = Controller Area Network) with DMA data transfer facility to internal RAM
l 1 Mbit/s CAN-controller with bus failure management facility
l 1/2 AVDD reference voltage
l Full-duplex UART compatible with the standard 80C51
l On-chip Watchdog Timer (WDT)
l 1.2 to 16 MHz clock frequency
l Improved Electromagnetic Compatibility (EMC).
Datasheet
File
size
(kB)
Publication
release date Datasheet status
Page
count
Type nr.
Title
Datasheet
Download
P8xCE598 8-bit microcontroller with on-chip CAN 27-Jun-96
Product
108
661
Specification
Blockdiagram
Blockdiagram of P80CE598FFB
Blockdiagram of P80CE598FFB
Blockdiagram of P80CE598FFB
Products, packages, availability and ordering
North American
Partnumber
Order code
(12nc)
buy
online
Partnumber
marking/packing
package device status
SOT318 Full production
SOT318 Full production
SOT318 Full production
Standard Marking * Tray Dry Pack,
Bakeable, Single
P80CE598FFB/00 P80CE598FBB-S
P80CE598FBB
9351 657 60551
9351 657 60557
9351 675 60557
-
-
-
Standard Marking * Tray Dry Pack,
Bakeable, Multiple
Standard Marking * Tray Dry Pack,
Bakeable, Multiple
P80CE598FHB/00
Standard Marking * Tray Dry Pack,
Bakeable, Single
P87CE598EFB/01
9351 674 40551
9351 674 40557
SOT318 Full production
SOT318 Full production
-
-
Standard Marking * Tray Dry Pack,
Bakeable, Multiple
Find similar products:
P8xCE598 links to the similar products page containing an overview of products that are similar in function or related to the part
number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant selection guides and
products from the same functional category.
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Royal Philips Electronics
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