P89LPC925FDH-S [NXP]

8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converter - ADCs: 4-ch 8-bit ; Clock type: 2-clk ; External interrupt: 3 ; Function: 8-bit 80C51 uController ; I/O pins: 18 ; Memory size: 8K kBits; Memory type: FLASH ; Number of pins: 20 ; Operating frequency: 0~12 MHz; Operating temperature: -40~+85 Cel; Power supply: 2.4~3.6V ; Program security: yes ; PWMs: 2 ch 8-bit res. ; RAM: 256 bytes; Reset active: Low ; Serial interface: UART, I2C ; Series: LPC900 family ; Special features: Byte-eraseable Flash, pin-comp. w/ LPC76x, BOD, POR, In;


型号：	P89LPC925FDH-S
厂家：	NXP
描述：	8-bit microcontrollers with accelerated two-clock 80C51 core 4 kB/8 kB 3 V low-power Flash with 8-bit A/D converter - ADCs: 4-ch 8-bit ; Clock type: 2-clk ; External interrupt: 3 ; Function: 8-bit 80C51 uController ; I/O pins: 18 ; Memory size: 8K kBits; Memory type: FLASH ; Number of pins: 20 ; Operating frequency: 0~12 MHz; Operating temperature: -40~+85 Cel; Power supply: 2.4~3.6V ; Program security: yes ; PWMs: 2 ch 8-bit res. ; RAM: 256 bytes; Reset active: Low ; Serial interface: UART, I2C ; Series: LPC900 family ; Special features: Byte-eraseable Flash, pin-comp. w/ LPC76x, BOD, POR, In 转换器闪存微控制器时钟
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P89LPC924/925

8-bit microcontrollers with accelerated two-clock 80C51 core

4 kB/8 kB 3 V low-power Flash with 8-bit A/D converter

Rev. 03 — 15 December 2004

Product data

1. General description

The P89LPC924/925 are single-chip microcontrollers designed for applications

demanding high-integration, low cost solutions over a wide range of performance

requirements. The P89LPC924/925 is based on a high performance processor

architecture that executes instructions in two to four clocks, six times the rate of

standard 80C51 devices. Many system-level functions have been incorporated into

the P89LPC924/925 in order to reduce component count, board space, and system

cost.

2. Features

2.1 Principal features

■ 4 kB/8 kB Flash code memory with 1 kB erasable sectors, 64-byte erasable page

size, and single byte erase.

■ 256-byte RAM data memory.

■ Two 16-bit counter/timers. Each timer may be conﬁgured to toggle a port output

upon timer overﬂow or to become a PWM output.

■ Real-Time clock that can also be used as a system timer.

■ 4-input 8-bit multiplexed A/D converter/single DAC output. Two analog

comparators with selectable inputs and reference source.

■ Enhanced UART with fractional baud rate generator, break detect, framing error

detection, automatic address detection and versatile interrupt capabilities.

■ 400 kHz byte-wide I²C-bus communication port.

■ Conﬁgurable on-chip oscillator with frequency range and RC oscillator options

(selected by user programmed Flash conﬁguration bits). The RC oscillator (factory

calibrated to ±1 %) option allows operation without external oscillator

components. Oscillator options support frequencies from 20 kHz to the maximum

operating frequency of 18 MHz. The RC oscillator option is selectable and ﬁne

tunable.

■ 2.4 V to 3.6 V V_DDoperating range. I/O pins are 5 V tolerant (may be pulled up or

driven to 5.5 V).

■ 15 I/O pins minimum. Up to 18 I/O pins while using on-chip oscillator and reset

options.

P89LPC924/925

8-bit microcontrollers with accelerated two-clock 80C51 core

Philips Semiconductors

2.2 Additional features

■ 20-pin TSSOP package.

■ A high performance 80C51 CPU provides instruction cycle times of 111 ns to

222 ns for all instructions except multiply and divide when executing at 18 MHz.

This is six times the performance of the standard 80C51 running at the same

clock frequency. A lower clock frequency for the same performance results in

power savings and reduced EMI.

■ In-Application Programming of the Flash code memory. This allows changing the

code in a running application.

■ Serial Flash programming allows simple in-circuit production coding. Flash

security bits prevent reading of sensitive application programs.

■ Watchdog timer with separate on-chip oscillator, requiring no external

components. The watchdog prescaler is selectable from eight values.

■ Low voltage reset (Brownout detect) allows a graceful system shutdown when

power fails. May optionally be conﬁgured as an interrupt.

■ Idle and two different Power-down reduced power modes. Improved wake-up from

Power-down mode (a low interrupt input starts execution). Typical Power-down

current is 1 µA (total Power-down with voltage comparators disabled).

■ Active-LOW reset. On-chip power-on reset allows operation without external reset

components. A reset counter and reset glitch suppression circuitry prevent

spurious and incomplete resets. A software reset function is also available.

■ Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator

allowing it to perform an oscillator fail detect function.

■ Programmable port output conﬁguration options:

◆ quasi-bidirectional,

◆ open drain,

◆ push-pull,

◆ input-only.

■ Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value

of the pins match or do not match a programmable pattern.

■ LED drive capability (20 mA) on all port pins. A maximum limit is speciﬁed for the

entire chip.

■ Controlled slew rate port outputs to reduce EMI. Outputs have approximately

10 ns minimum ramp times.

■ Only power and ground connections are required to operate the P89LPC924/925

when internal reset option is selected.

■ Four interrupt priority levels.

■ Eight keypad interrupt inputs, plus two additional external interrupt inputs.

■ Second data pointer.

■ Schmitt trigger port inputs.

■ Emulation support.

9397 750 14471

Product data

Rev. 03 — 15 December 2004

2 of 49

P89LPC924/925

8-bit microcontrollers with accelerated two-clock 80C51 core

Philips Semiconductors

3. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

P89LPC924FDH

P89LPC925FDH

TSSOP20 plastic thin shrink small outline package;

20 leads; body width 4.4 mm

SOT360-1

TSSOP20 plastic thin shrink small outline package;

20 leads; body width 4.4 mm

SOT360-1

3.1 Ordering options

Table 2:

Part options

Type number

Flash memory

4 kB

Temperature range

−40 °C to +85 °C

Frequency

P89LPC924FDH

P89LPC925FDH

0 MHz to 18 MHz

8 kB

9397 750 14471

Product data

Rev. 03 — 15 December 2004

3 of 49

P89LPC924/925

8-bit microcontrollers with accelerated two-clock 80C51 core

Philips Semiconductors

4. Block diagram

P89LPC924/925

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

2 kB/4 kB/8 kB

CODE FLASH

UART

INTERNAL BUS

256-BYTE

DATA RAM

REAL-TIME CLOCK/

SYSTEM TIMER

PORT 3

CONFIGURABLE I/Os

I C

PORT 1

CONFIGURABLE I/Os

TIMER 0

TIMER 1

PORT 0

CONFIGURABLE I/Os

WATCHDOG TIMER

AND OSCILLATOR

KEYPAD

INTERRUPT

ANALOG

COMPARATORS

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU

CLOCK

ADC1/DAC1

CRYSTAL

RESONATOR

ON-CHIP

OSCILLATOR

CONFIGURABLE

OSCILLATOR

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

002aaa786

Fig 1. Block diagram.

9397 750 14471

Product data

Rev. 03 — 15 December 2004

4 of 49

P89LPC924/925

8-bit microcontrollers with accelerated two-clock 80C51 core

Philips Semiconductors

5. Pinning information

5.1 Pinning

handbook, halfpage

KBI0/CMP2/P0.0

20 P0.1/CIN2B/KBI1/AD10

19 P0.2/CIN2A/KBI2/AD11

18 P0.3/CIN1B/KBI3/AD12

17 P0.4/CIN1A/KBI4/AD13/DAC1

16 P0.5/CMPREF/KBI5

P1.7

P1.6

RST/P1.5

XTAL1/P3.1

CLKOUT/XTAL2/P3.0

INT1/P1.4

15 V

14 P0.6/CMP1/KBI6

13 P0.7/T1/KBI7

12 P1.0/TXD

SDA/INT0/P1.3

SCL/T0/P1.2 10

11 P1.1/RXD

002aaa787

Fig 2. TSSOP20 pin conﬁguration.

9397 750 14471

Product data

Rev. 03 — 15 December 2004

5 of 49

P89LPC924/925

8-bit microcontrollers with accelerated two-clock 80C51 core

Philips Semiconductors

5.2 Pin description

Table 3:

Symbol

Pin description

Pin Type

Description

P0.0 - P0.7 1, 20, 19, I/O

Port 0: Port 0 is an 8-bit I/O port with a user-conﬁgurable output type. During reset

Port 0 latches are conﬁgured in the input only mode with the internal pull-up disabled.

The operation of Port 0 pins as inputs and outputs depends upon the port conﬁguration

selected. Each port pin is conﬁgured independently. Refer to Section 8.13.1 “Port

conﬁgurations” and Table 8 “DC electrical characteristics” for details.

18, 17, 16,

14, 13

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below:

P0.0 — Port 0 bit 0.

I/O

CMP2 — Comparator 2 output.

KBI0 — Keyboard input 0.

I/O

P0.1 — Port 0 bit 1.

CIN2B — Comparator 2 positive input B.

KBI1 — Keyboard input 1.

AD10 — ADC1 channel 0 analog input.

P0.2 — Port 0 bit 2.

I/O

CIN2A — Comparator 2 positive input A.

KBI2 — Keyboard input 2.

AD11 — ADC1 channel 1analog input.

P0.3 — Port 0 bit 3.

I/O

CIN1B — Comparator 1 positive input B.

KBI3 — Keyboard input 3.

AD12 — ADC1 channel 2 analog input.

P0.4 — Port 0 bit 4.

I/O

CIN1A — Comparator 1 positive input A.

KBI4 — Keyboard input 4.

AD13 — ADC1 channel 3 analog input.

DAC1 — Digital-to-analog converter output 1.

P0.5 — Port 0 bit 5.

I/O

CMPREF — Comparator reference (negative) input.

KBI5 — Keyboard input 5.

I/O

P0.6 — Port 0 bit 6.

CMP1 — Comparator 1 output.

KBI6 — Keyboard input 6.

I/O

P0.7 — Port 0 bit 7.

T1 — Timer/counter 1 external count input or overﬂow output.

KBI7 — Keyboard input 7.

9397 750 14471

Product data

Rev. 03 — 15 December 2004

6 of 49

P89LPC924/925

8-bit microcontrollers with accelerated two-clock 80C51 core

Philips Semiconductors

Table 3:

Symbol

Pin description…continued

Pin Type Description

P1.0 - P1.7 12, 11, 10, I/O, I ^[1]Port 1: Port 1 is an 8-bit I/O port with a user-conﬁgurable output type, except for three

9, 8, 4, 3,

pins as noted below. During reset Port 1 latches are conﬁgured in the input only mode

with the internal pull-up disabled. The operation of the conﬁgurable Port 1 pins as inputs

and outputs depends upon the port conﬁguration selected. Each of the conﬁgurable

port pins are programmed independently. Refer to Section 8.13.1 “Port conﬁgurations”

and Table 8 “DC electrical characteristics” for details. P1.2 - P1.3 are open drain when

used as outputs. P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below:

P1.0 — Port 1 bit 0.

I/O

TXD — Transmitter output for the serial port.

P1.1 — Port 1 bit 1.

I/O

RXD — Receiver input for the serial port.

P1.2 — Port 1 bit 2 (open-drain when used as output).

I/O

T0 — Timer/counter 0 external count input or overﬂow output (open-drain when used as

output).

I/O

SCL — I²C serial clock input/output.

P1.3 — Port 1 bit 3 (open-drain when used as output).

INT0 — External interrupt 0 input.

SDA — I²C serial data input/output.

P1.4 — Port 1 bit 4.

I/O

INT1 — External interrupt 1 input.

P1.5 — Port 1 bit 5 (input only).

RST — External Reset input (if selected via FLASH conﬁguration). A LOW on this pin

resets the microcontroller, causing I/O ports and peripherals to take on their default

states, and the processor begins execution at address 0. When using an oscillator

frequency above 12 MHz, the reset input function of P1.5 must be enabled. An

external circuit is required to hold the device in reset at power-up until V_DDhas

reached its speciﬁed level. When system power is removed V_DDwill fall below the

minimum speciﬁed operating voltage. When using an oscillator frequency above

12 MHz, in some applications, an external brownout detect circuit may be

required to hold the device in reset when V_DDfalls below the minimum speciﬁed

operating voltage.

I/O

P1.6 — Port 1 bit 6.

P1.7 — Port 1 bit 7.

9397 750 14471

Product data

Rev. 03 — 15 December 2004

7 of 49

P89LPC924/925

8-bit microcontrollers with accelerated two-clock 80C51 core

Philips Semiconductors

Table 3:

Symbol

Pin description…continued

Type

Description

P3.0 - P3.1 7, 6

I/O

Port 3: Port 3 is an 2-bit I/O port with a user-conﬁgurable output type. During reset

Port 3 latches are conﬁgured in the input only mode with the internal pull-up disabled.

The operation of Port 3 pins as inputs and outputs depends upon the port conﬁguration

selected. Each port pin is conﬁgured independently. Refer to Section 8.13.1 “Port

conﬁgurations” and Table 8 “DC electrical characteristics” for details.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described below:

P3.0 — Port 3 bit 0.

I/O

XTAL2 — Output from the oscillator ampliﬁer (when a crystal oscillator option is

selected via the FLASH conﬁguration.

CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It

can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or

external clock input, except when XTAL1/XTAL2 are used to generate clock source for

the real time clock/system timer.

I/O

P3.1 — Port 3 bit 1.

XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when

selected via the FLASH conﬁguration). It can be a port pin if internal RC oscillator or

watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used

to generate the clock for the real time clock/system timer.

V_SS

V_DD

Ground: 0 V reference.

Power Supply: This is the power supply voltage for normal operation as well as Idle

and Power Down modes.

[1] Input/Output for P1.0-P1.4, P1.6, P1.7. Input for P1.5.

6. Logic symbol

KBI0

KBI1

KBI2

KBI3

KBI4

KBI5

KBI6

KBI7

CMP2

TxD

RxD

INT0

INT1

RST

AD10

AD11

AD12

AD13

CIN2B

CIN2A

CIN1B

CIN1A

CMPREF

CMP1

SCL

SDA

DAC1

CLKOUT

XTAL2

XTAL1

002aaa789

Fig 3. Logic symbol.

9397 750 14471

Product data

Rev. 03 — 15 December 2004

8 of 49

P89LPC924/925

8-bit microcontrollers with accelerated two-clock 80C51 core

Philips Semiconductors

7. Special function registers

Remark: Special Function Registers (SFRs) accesses are restricted in the following

ways:

• User must not attempt to access any SFR locations not deﬁned.

• Accesses to any deﬁned SFR locations must be strictly for the functions for the

SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise speciﬁed, must be written with ‘0’, but can return any value

when read (even if it was written with ‘0’). It is a reserved bit and may be used in

future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

9397 750 14471

Product data

Rev. 03 — 15 December 2004

9 of 49

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Table 4:

Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

E0H

ACC*

Accumulator

00000000

ADCON1 A/D control register 1

97H

ENBI1

ENADCI

TMM1

EDGE1

ADCI1 ENADC1 ADCS11 ADCS10 00

ADINS A/D input select

A3H

C0H

A1H

ADI13

BNDI1

CLK2

ADI12

BURST1

CLK1

ADI11

SCC1

CLK0

ADI10

SCAN1

00^[1]

00000000

000x0000

11111111

00000000

000000x0

ADMODA A/D mode register A

ADMODB A/D mode register B

ENDAC1

BSA1

AD1BH

AD1BL

A/D_1 boundary high register C4H

A/D_1 boundary low register BCH

AD1DAT0 A/D_1 data register 0

AD1DAT1 A/D_1 data register 1

AD1DAT2 A/D_1 data register 2

AD1DAT3 A/D_1 data register 3

D5H

D6H

D7H

F5H

AUXR1

Auxiliary function register

A2H

CLKLP

EBRR

ENT1

ENT0

SRST

DPS

Bit address

F0H

B register

00000000

BRGR0^[2]Baud rate generator rate

LOW

BEH

BRGR1^[2]Baud rate generator rate

HIGH

BFH

00000000

BRGCON Baud rate generator control

BDH

Comparator 1 control register ACH

Comparator 2 control register ADH

SBRGS BRGEN 00

xxxxxx00

xx000000

00000000

CMP1

CMP2

DIVM

CE1

CE2

CP1

CP2

CN1

CN2

OE1

OE2

CO1

CO2

CMF1 00^[1]

CMF2 00^[1]

CPU clock divide-by-M

control

95H

DPTR

DPH

DPL

Data pointer (2 bytes)

Data pointer HIGH

Data pointer LOW

83H

82H

00000000

FMADRH Program Flash address HIGH E7H

FMADRL Program Flash address LOW E6H

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Special function registers…continued

Table 4:

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

FMCON

Program Flash control (Read) E4H

BUSY

HVA

HVE

01110000

Program Flash control (Write) E4H FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD.

FMDATA

I2ADR

Program Flash data

I²C slave address register

E5H

DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0

00000000

Bit address

I2CON*

I2DAT

I²C control register

I²C data register

D8H

DAH

DDH

I2EN

STA

STO

CRSEL 00

x00000x0

I2SCLH

Serial clock generator/SCL

duty cycle register HIGH

00000000

11111000

I2SCLL

I2STAT

Serial clock generator/SCL

duty cycle register LOW

I²C status register

DCH

D9H

STA.4

EAD

STA.3

STA.2

STA.1

STA.0

Bit address

A8H

IEN0*

IEN1*

Interrupt enable 0

Interrupt enable 1

EWDRT

EBO

ES/ESR

ET1

EX1

ET0

EX0

00^[1]

00000000

00x00000

Bit address

E8H

EST

EKBI

EI2C

Bit address

B8H

IP0*

Interrupt priority 0

PWDRT

PBO

PBOH

PS/PSR

PT1

PT1H

PX1

PX1H

PT0

PT0H

PX0

PX0H

00^[1]

x0000000

IP0H

Interrupt priority 0 HIGH

B7H

PWDRT

PSH/

PSRH

Bit address

F8H

PAD

PADH

PST

PSTH

PCH

IP1*

Interrupt priority 1

PKBI

PKBIH

PI2C

PI2CH 00^[1]

00^[1]

00x00000

xxxxxx00

IP1H

Interrupt priority 1 HIGH

Keypad control register

F7H

KBCON

94H

PATN

_SEL

KBIF

00^[1]

KBMASK Keypad interrupt mask

86H

00000000

11111111

KBPATN

Keypad pattern register

93H

Bit address

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Special function registers…continued

Table 4:

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

Hex Binary

addr.

MSB

LSB

[1]

P0*

Port 0

80H

T1/KB7

CMP1 CMPREF CIN1A

CIN1B

/KB3

CIN2A

/KB2

CIN2B

/KB1

CMP2

/KB0

/KB6

/KB5

/KB4

Bit address

P1*

Port 1

90H

RST

INT1

INT0/

SDA

T0/SCL

RXD

TXD

Bit address

P3*

Port 3

B0H

XTAL1

XTAL2

P0M1

P0M2

P1M1

P1M2

P3M1

P3M2

PCON

PCONA

Port 0 output mode 1

Port 0 output mode 2

Port 1 output mode 1

Port 1 output mode 2

Port 3 output mode 1

Port 3 output mode 2

Power control register

Power control register A

84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF

85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00

11111111

00000000

11x1xx11

00x0xx00

xxxxxx11

xxxxxx00

00000000

91H (P1M1.7) (P1M1.6)

92H (P1M2.7) (P1M2.6)

(P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3^[1]

(P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00^[1]

B1H

B2H

(P3M1.1) (P3M1.0) 03^[1]

(P3M2.1) (P3M2.0) 00^[1]

PMOD1 PMOD0 00

87H SMOD1 SMOD0

BOPD

VCPD

BOI

ADPD

GF1

I2PD

GF0

B5H RTCPD

SPD

00^[1]

Bit address

PSW*

Program status word

D0H

F6H

DFH

D1H

D2H

RS1

RS0

00H

00000000

PT0AD

Port 0 digital input disable

PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1

xx00000x

[3]

RSTSRC Reset source register

RTCCON Real-time clock control

BOF

POF

R_BK

R_WD

R_SF

ERTC

R_EX

RTCF

RTCS1

RTCS0

RTCEN 60^[1][6]

00^[6]

RTCH

Real-time clock register

HIGH

00000000

RTCL

Real-time clock register LOW D3H

00^[6]

00000000

xxxxxxxx

SADDR

SADEN

SBUF

Serial port address register

Serial port address enable

A9H

B9H

99H

Serial Port data buffer

Bit address

SCON*

Serial port control

98H SM0/FE

SM1

SM2

REN

TB8

RB8

00000000

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xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

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Special function registers…continued

Table 4:

* indicates SFRs that are bit addressable.

Name

Description

SFR Bit functions and addresses

Reset value

Hex Binary

addr.

MSB

LSB

SSTAT

Serial port extended status

BAH DBMOD

81H

INTLO

CIDIS

DBISEL

STINT 00

00000000

Stack pointer

00000111

xxx0xxx0

TAMOD

Timer 0 and 1 auxiliary mode 8FH

T1M2

T0M2

Bit address

TF0

IE1

IT1

IE0

TCON*

TH0

Timer 0 and 1 control

Timer 0 HIGH

88H

8CH

8DH

8AH

8BH

TF1

TR1

TR0

IT0

00000000

TH1

Timer 1 HIGH

TL0

Timer 0 LOW

TL1

Timer 1 LOW

TMOD

TRIM

WDCON

WDL

Timer 0 and 1 mode

89H T1GATE

T1C/T

ENCLK

PRE1

T1M1

TRIM.5

PRE0

T1M0

TRIM.4

T0GATE

TRIM.3

T0C/T

T0M1

T0M0

00000000

[5] [6]

Internal oscillator trim register 96H

RCCLK

PRE2

TRIM.2

TRIM.1

TRIM.0

[4] [6]

Watchdog control register

Watchdog load

A7H

C1H

C2H

C3H

WDRUN WDTOF WDCLK

11111111

WFEED1 Watchdog feed 1

WFEED2 Watchdog feed 2

[1] All ports are in input only (high impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reﬂects the cause of the P89LPC924/925 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset value is

xx110000.

[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after watchdog reset and is ‘0’ after power-on reset. Other resets will

not affect WDTOF.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

P89LPC924/925

8-bit microcontrollers with accelerated two-clock 80C51 core

Philips Semiconductors

8. Functional description

Remark: Please refer to the P89LPC924/925 User’s Manual for a more detailed

functional description.

8.1 Enhanced CPU

The P89LPC924/925 uses an enhanced 80C51 CPU which runs at 6 times the speed

of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and

most instructions execute in one or two machine cycles.

8.2 Clocks

8.2.1 Clock deﬁnitions

The P89LPC924/925 device has several internal clocks as deﬁned below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four

clock sources (see Figure 4) and can also be optionally divided to a slower frequency

(see Section 8.7 “CPU Clock (CCLK) modiﬁcation: DIVM register”).

Note: f_oscis deﬁned as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per

machine cycle, and most instructions are executed in one to two machine cycles (two

or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.

PCLK — Clock for the various peripheral devices and is CCLK/2

8.2.2 CPU clock (OSCCLK)

The P89LPC924/925 provides several user-selectable oscillator options in generating

the CPU clock. This allows optimization for a range of needs from high precision to

lowest possible cost. These options are conﬁgured when the FLASH is programmed

and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator

using an external crystal, or an external clock source. The crystal oscillator can be

optimized for low, medium, or high frequency crystals covering a range from 20 kHz

to 12 MHz.

8.2.3 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic

resonators are also supported in this conﬁguration.

8.2.4 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic

resonators are also supported in this conﬁguration.

8.2.5 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic

resonators are also supported in this conﬁguration. When using an oscillator

frequency above 12 MHz, the reset input function of P1.5 must be enabled. An

external circuit is required to hold the device in reset at power-up until V_DDhas

reached its speciﬁed level. When system power is removed V_DDwill fall below

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the minimum speciﬁed operating voltage. When using an oscillator frequency

above 12 MHz, in some applications, an external brownout detect circuit may

be required to hold the device in reset when V_DDfalls below the minimum

speciﬁed operating voltage.

8.2.6 Clock output

The P89LPC924/925 supports a user-selectable clock output function on the

XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if

another clock source has been selected (on-chip RC oscillator, watchdog oscillator,

external clock input on X1) and if the Real-Time clock is not using the crystal

oscillator as its clock source. This allows external devices to synchronize to the

P89LPC924/925. This output is enabled by the ENCLK bit in the TRIM register. The

frequency of this clock output is ¹⁄₂that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power.

8.3 On-chip RC oscillator option

The P89LPC924/925 has a 6-bit TRIM register that can be used to tune the

frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory

pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ±1% at room

temperature. End-user applications can write to the Trim register to adjust the on-chip

RC oscillator to other frequencies.

8.4 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This

oscillator can be used to save power when a high clock frequency is not needed.

8.5 External clock input option

In this conﬁguration, the processor clock is derived from an external source driving

the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2/P3.0 pin

may be used as a standard port pin or a clock output. When using an oscillator

frequency above 12 MHz, the reset input function of P1.5 must be enabled. An

external circuit is required to hold the device in reset at power-up until V_DDhas

reached its speciﬁed level. When system power is removed V_DDwill fall below

the minimum speciﬁed operating voltage. When using an oscillator frequency

above 12 MHz, in some applications, an external brownout detect circuit may

be required to hold the device in reset when V_DDfalls below the minimum

speciﬁed operating voltage.

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XTAL1

XTAL2

High freq.

Med. freq.

Low freq.

RTC

ADC1/

DAC1

OSCCLK

CCLK

DIVM

CPU

WDT

OSCILLATOR

÷2

(7.3728 MHz)

WATCHDOG

OSCILLATOR

(400 kHz)

PCLK

TIMER 0 and

TIMER 1

BAUD RATE

GENERATOR

I C

UART

002aaa790

Fig 4. Block diagram of oscillator control.

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8.6 CPU Clock (CCLK) wake-up delay

The P89LPC924/925 has an internal wake-up timer that delays the clock until it

stabilizes depending to the clock source used. If the clock source is any of the three

crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK

cycles plus 60 to 100 µs. If the clock source is either the internal RC oscillator,

watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus

60 to 100 µs.

8.7 CPU Clock (CCLK) modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a

dividing register, DIVM, to generate CCLK. This feature makes it possible to

temporarily run the CPU at a lower rate, reducing power consumption. By dividing the

clock, the CPU can retain the ability to respond to events that would not exit Idle

mode by executing its normal program at a lower rate. This can also allow bypassing

the oscillator start-up time in cases where Power-down mode would otherwise be

used. The value of DIVM may be changed by the program at any time without

interrupting code execution.

8.8 Low power select

The P89LPC924/925 is designed to run at 18 MHz (CCLK) maximum. However, if

CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the

power consumption further. On any reset, CLKLP is ‘0’ allowing highest performance

access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

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8.9 A/D converter

8.9.1 General description

The P89LPC924/925 has an 8-bit, 4-channel multiplexed successive approximation

analog-to-digital converter module. A block diagram of the A/D converter is shown in

Figure 5. The A/D consists of a 4-input multiplexer which feeds a sample-and-hold

circuit providing an input signal to one of two comparator inputs. The control logic in

combination with the successive approximation register (SAR) drives a

digital-to-analog converter which provides the other input to the comparator. The

output of the comparator is fed to the SAR.

COMP

INPUT

MUX

SAR

–

CONTROL

LOGIC

DAC1

CCLK

002aaa791

Fig 5. ADC block diagram.

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8.9.2 Features

• 8-bit, 4-channel multiplexed input, successive approximation A/D converter.

• Four result registers.

• Six operating modes

– Fixed channel, single conversion mode

– Fixed channel, continuous conversion mode

– Auto scan, single conversion mode

– Auto scan, continuous conversion mode

– Dual channel, continuous conversion mode

– Single step mode

• Three conversion start modes

– Timer triggered start

– Start immediately

– Edge triggered

• 8-bit conversion time of ≥ 3.9 µs at an ADC clock of 3.3 MHz

• Interrupt or polled operation

• Boundary limits interrupt

• DAC output to a port pin with high output impedance

• Clock divider

• Power down mode

8.9.3 A/D operating modes

Fixed channel, single conversion mode: A single input channel can be selected for

conversion. A single conversion will be performed and the result placed in the result

be generated after the conversion completes.

Fixed channel, continuous conversion mode: A single input channel can be

selected for continuous conversion. The results of the conversions will be sequentially

placed in the four result registers. An interrupt, if enabled, will be generated after

every four conversions. Additional conversion results will again cycle through the four

result registers, overwriting the previous results. Continuous conversions continue

until terminated by the user.

Auto scan, single conversion mode: Any combination of the four input channels

can be selected for conversion. A single conversion of each selected input will be

performed and the result placed in the result register which corresponds to the

selected input channel. An interrupt, if enabled, will be generated after all selected

channels have been converted. If only a single channel is selected this is equivalent

to single channel, single conversion mode.

Auto scan, continuous conversion mode: Any combination of the four input

channels can be selected for conversion. A conversion of each selected input will be

performed and the result placed in the result register which corresponds to the

selected input channel. An interrupt, if enabled, will be generated after all selected

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channels have been converted. The process will repeat starting with the ﬁrst selected

channel. Additional conversion results will again cycle through the four result

registers, overwriting the previous results. Continous conversions continue until

terminated by the user.

Dual channel, continuous conversion mode: This is a variation of the auto scan

continuous conversion mode where conversion occurs on two user-selectable inputs.

The result of the conversion of the ﬁrst channel is placed in result register, AD1DAT0.

The result of the conversion of the second channel is placed in result register,

AD1DAT1. The ﬁrst channel is again converted and its result stored in AD1DAT2. The

second channel is again converted and its result placed in AD1DAT3. An interrupt is

generated, if enabled, after every set of four conversions (two conversions per

channel).

Single step mode: This special mode allows ‘single-stepping’ in an auto scan

conversion mode. Any combination of the four input channels can be selected for

conversion. After each channel is converted, an interrupt is generated, if enabled,

and the A/D waits for the next start condition. May be used with any of the start

modes.

8.9.4 Conversion start modes

Timer triggered start: An A/D conversion is started by the overﬂow of Timer 0. Once

a conversion has started, additional Timer 0 triggers are ignored until the conversion

has completed. The Timer triggered start mode is available in all A/D operating

modes.

Start immediately: Programming this mode immediately starts a conversion. This

start mode is available in all A/D operating modes.

Edge triggered: An A/D conversion is started by rising or falling edge of P1.4. Once

a conversion has started, additional edge triggers are ignored until the conversion

has completed. The edge triggered start mode is available in all A/D operating

modes.

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8.9.5 Boundary limits interrupt

The A/D converter has both a high and low boundary limit register. After the four

MSBs have been converted, these four bits are compared with the four MSBs of the

boundary high and low registers. If the four MSBs of the conversion are outside the

limit an interrupt will be generated, if enabled. If the conversion result is within the

limits, the boundary limits will again be compared after all 8 bits have been converted.

An interrupt will be generated, if enabled, if the result is outside the boundary limits.

The boundary limit may be disabled by clearing the boundary limit interrupt enable.

8.9.6 DAC output to a port pin with high output impedance

The A/D converter’s DAC block can be output to a port pin. In this mode, the

AD1DAT3 register is used to hold the value fed to the DAC. After a value has been

written to the DAC, the DAC output will appear on the channel 3 pin.

8.9.7 Clock divider

The A/D converter requires that its internal clock source be in the range of 500 kHz to

3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock

from 1 to 8 is provided for this purpose.

8.9.8 Power-down and idle mode

In idle mode the A/D converter, if enabled, will continue to function and can cause the

device to exit idle mode when the conversion is completed if the A/D interrupt is

enabled. In Power-down mode or Total power-down mode, the A/D does not function.

If the A/D is enabled, it will consume power. Power can be reduced by disabling the

A/D.

8.10 Memory organization

The various P89LPC924/925 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect

addressing, using instruction other than MOVX and MOVC. All or part of the Stack

may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via

indirect addressing using instructions other than MOVX and MOVC. All or part of

the Stack may be in this area. This area includes the DATA area and the 128 bytes

immediately above it.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and

status registers, accessible only via direct addressing.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC924/925 has 4 kB/8 kB of on-chip Code memory.

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8.11 Data RAM arrangement

The 256 bytes of on-chip RAM are organized as shown in Table 5.

Table 5:

Type

On-chip data memory usages

Data RAM

Size (bytes)

128

DATA

Memory that can be addressed directly and indirectly

Memory that can be addressed indirectly

IDATA

256

8.12 Interrupts

The P89LPC924/925 uses a four priority level interrupt structure. This allows great

ﬂexibility in controlling the handling of the many interrupt sources. The

P89LPC924/925 supports 13 interrupt sources: A/D converter, external interrupts 0

and 1, timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx,

brownout detect, watchdog/real-time clock, I²C, keyboard, and comparators 1 and 2.

Each interrupt source can be individually enabled or disabled by setting or clearing a

bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a

global disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An

interrupt service routine in progress can be interrupted by a higher priority interrupt,

but not by another interrupt of the same or lower priority. The highest priority interrupt

service cannot be interrupted by any other interrupt source. If two requests of

different priority levels are pending at the start of an instruction, the request of higher

priority level is serviced.

If requests of the same priority level are pending at the start of an instruction, an

internal polling sequence determines which request is serviced. This is called the

arbitration ranking. Note that the arbitration ranking is only used to resolve pending

requests of the same priority level.

8.12.1 External interrupt inputs

The P89LPC924/925 has two external interrupt inputs as well as the Keypad Interrupt

function. The two interrupt inputs are identical to those present on the standard

80C51 microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered

by setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode if successive samples of the INTn pin show a HIGH in one

cycle and a LOW in the next cycle, the interrupt request ﬂag IEn in TCON is set,

causing an interrupt request.

If an external interrupt is enabled when the P89LPC924/925 is put into Power-down

or Idle mode, the interrupt will cause the processor to wake-up and resume operation.

Refer to Section 8.15 “Power reduction modes” for details.

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IE0

EX0

IE1

EX1

BOF

EBO

RTCF

WAKE-UP

(IF IN POWER-DOWN)

KBIF

EKBI

ERTC

(RTCCON.1)

WDOVF

EWDRT

CMF2

CMF1

EA (IE0.7)

TF0

ET0

TF1

ET1

TI & RI/RI

ES/ESR

INTERRUPT

TO CPU

EST

EI2C

ENADCI1

ADCI1

ENBI1

BNDI1

EAD

002aaa792

Fig 6. Interrupt sources, interrupt enables, and power-down wake-up sources.

8.13 I/O ports

The P89LPC924/925 has three I/O ports: Port 0, Port 1, and Port 3. Ports 0 and 1 are

8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depend

upon the clock and reset options chosen, as shown in Table 6.

Table 6:

Number of I/O pins available

Clock source

Reset option

Number of I/O pins

(20-pin package)

On-chip oscillator or

watchdog oscillator

No external reset (except during power-up) 18

External RST pin supported^[1]

No external reset (except during power-up) 17

External RST pin supported^[1]

External clock input

Low/medium/high speed No external reset (except during power-up) 16

oscillator (external

External RST pin supported^[1]

crystal or resonator)

[1] Required for operation above 12 MHz.

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8.13.1 Port conﬁgurations

All but three I/O port pins on the P89LPC924/925 may be conﬁgured by software to

one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51

port outputs), push-pull, open drain, and input-only. Two conﬁguration registers for

each port select the output type for each port pin.

P1.5 (RST) can only be an input and cannot be conﬁgured.

P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be conﬁgured to be either input-only or

open-drain.

8.13.2 Quasi-bidirectional output conﬁguration

Quasi-bidirectional output type can be used as both an input and output without the

need to reconﬁgure the port. This is possible because when the port outputs a logic

HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the

pin is driven LOW, it is driven strongly and able to sink a fairly large current. These

features are somewhat similar to an open-drain output except that there are three

pull-up transistors in the quasi-bidirectional output that serve different purposes.

The P89LPC924/925 is a 3 V device, but the pins are 5 V-tolerant. In

quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current

ﬂowing from the pin to V_DD, causing extra power consumption. Therefore, applying

5 V in quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch

suppression circuit.

8.13.3 Open-drain output conﬁguration

The open-drain output conﬁguration turns off all pull-ups and only drives the

pull-down transistor of the port driver when the port latch contains a logic ‘0’. To be

used as a logic output, a port conﬁgured in this manner must have an external

pull-up, typically a resistor tied to V_DD

An open-drain port pin has a Schmitt-triggered input that also has a glitch

suppression circuit.

8.13.4 Input-only conﬁguration

The input-only port conﬁguration has no output drivers. It is a Schmitt-triggered input

that also has a glitch suppression circuit.

8.13.5 Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes, but provides a continuous

strong pull-up when the port latch contains a logic ‘1’. The push-pull mode may be

used when more source current is needed from a port output. A push-pull port pin

has a Schmitt-triggered input that also has a glitch suppression circuit.

8.13.6 Port 0 analog functions

The P89LPC924/925 incorporates two Analog Comparators. In order to give the best

analog function performance and to minimize power consumption, pins that are being

used for analog functions must have the digital outputs and digital inputs disabled.

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Digital outputs are disabled by putting the port output into the Input-Only (high

impedance) mode as described in Section 8.13.4.

Digital inputs on Port 0 may be disabled through the use of the PT0AD register,

bits 1:5. On any reset, PT0AD1:5 defaults to ‘0’s to enable digital functions.

8.13.7 Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different

from the LPC76x series of devices.

• After power-up, all I/O pins except P1.5, may be conﬁgured by software.

• Pin P1.5 is input only. Pins P1.2 and P1.3 and are conﬁgurable for either input-only

or open-drain.

Every output on the P89LPC924/925 has been designed to sink typical LED drive

current. However, there is a maximum total output current for all ports which must not

be exceeded. Please refer to Table 8 “DC electrical characteristics” for detailed

speciﬁcations.

All ports pins that can function as an output have slew rate controlled outputs to limit

noise generated by quickly switching output signals. The slew rate is factory-set to

approximately 10 ns rise and fall times.

8.14 Power monitoring functions

The P89LPC924/925 incorporates power monitoring functions designed to prevent

incorrect operation during initial power-up and power loss or reduction during

operation. This is accomplished with two hardware functions: Power-on Detect and

Brownout detect.

8.14.1 Brownout detection

The Brownout detect function determines if the power supply voltage drops below a

certain level. The default operation is for a Brownout detection to cause a processor

reset, however it may alternatively be conﬁgured to generate an interrupt.

Brownout detection may be enabled or disabled in software.

If Brownout detection is enabled, the brownout condition occurs when V_DDfalls below

the brownout trip voltage, V_BO(see Table 8 “DC electrical characteristics”), and is

negated when V_DDrises above V_BO. If the P89LPC924/925 device is to operate with

a power supply that can be below 2.7 V, BOE should be left in the unprogrammed

state so that the device can operate at 2.4 V, otherwise continuous brownout reset

may prevent the device from operating.

For correct activation of Brownout detect, the V_DDrise and fall times must be

observed. Please see Table 8 “DC electrical characteristics” for speciﬁcations.

8.14.2 Power-on detection

The Power-on Detect has a function similar to the Brownout detect, but is designed to

work as power comes up initially, before the power supply voltage reaches a level

where Brownout detect can work. The POF ﬂag in the RSTSRC register is set to

indicate an initial power-up condition. The POF ﬂag will remain set until cleared by

software.

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8.15 Power reduction modes

The P89LPC924/925 supports three different power reduction modes. These modes

are Idle mode, Power-down mode, and total Power-down mode.

8.15.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor

when an interrupt is generated. Any enabled interrupt source or reset may terminate

Idle mode.

8.15.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption.

The P89LPC924/925 exits Power-down mode via any reset, or certain interrupts. In

Power-down mode, the power supply voltage may be reduced to the RAM keep-alive

voltage V_RAM. This retains the RAM contents at the point where Power-down mode

was entered. SFR contents are not guaranteed after V_DDhas been lowered to V_RAM

therefore it is highly recommended to wake up the processor via reset in this case.

V_DDmust be raised to within the operating range before the Power-down mode is

exited.

Some chip functions continue to operate and draw power during Power-down mode,

increasing the total power used during Power-down. These include: Brownout detect,

Watchdog Timer, Comparators (note that Comparators can be powered-down

separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is

disabled unless both the RC oscillator has been selected as the system clock AND

the RTC is enabled.

8.15.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry

and the voltage comparators are also disabled to conserve additional power. The

internal RC oscillator is disabled unless both the RC oscillator has been selected as

the system clock and the RTC is enabled. If the internal RC oscillator is used to clock

the RTC during Power-down, there will be high power consumption. Please use an

external low frequency clock to achieve low power with the Real-Time Clock running

during Power-down.

8.16 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital

input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the

external reset input function on P1.5. When cleared, P1.5 may be used as an input

pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin

will always function as a reset input. An external circuit connected to this pin

should not hold this pin LOW during a power-on sequence as this will keep the

device in reset. After power-up this input will function either as an external reset

input or as a digital input as deﬁned by the RPE bit. Only a power-up reset will

temporarily override the selection deﬁned by RPE bit. Other sources of reset will not

override the RPE bit.

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Remark: During a power cycle, V_DDmust fall below V_POR(see Table 8 “DC electrical

characteristics” on page 40) before power is reapplied, in order to ensure a power-on

reset.

Reset can be triggered from the following sources:

• External reset pin (during power-up or if user conﬁgured via UCFG1. This option

must be used for an oscillator frequency above 12 MHz);

• Power-on detect;

• Brownout detect;

• Watchdog Timer;

• Software reset;

• UART break character detect reset.

For every reset source, there is a ﬂag in the Reset Register, RSTSRC. The user can

read this register to determine the most recent reset source. These ﬂag bits can be

cleared in software by writing a ‘0’ to the corresponding bit. More than one ﬂag bit

may be set:

• During a power-on reset, both POF and BOF are set but the other ﬂag bits are

cleared.

• For any other reset, previously set ﬂag bits that have not been cleared will remain

set.

8.16.1 Reset vector

Following reset, the P89LPC924/925 will fetch instructions from either address 0000h

or the Boot address. The Boot address is formed by using the Boot Vector as the high

byte of the address and the low byte of the address = 00h.

The Boot address will be used if a UART break reset occurs, or the non-volatile Boot

Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on

(see P89LPC924/925 User’s Manual). Otherwise, instructions will be fetched from

address 0000H.

8.17 Timers/counters 0 and 1

The P89LPC924/925 has two general purpose counter/timers which are upward

compatible with the standard 80C51 Timer 0 and Timer 1. Both can be conﬁgured to

operate either as timers or event counter. An option to automatically toggle the T0

and/or T1 pins upon timer overﬂow has been added.

In the ‘Timer’ function, the register is incremented every machine cycle.

In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition

at its corresponding external input pin, T0 or T1. In this function, the external input is

sampled once during every machine cycle.

Timer 0 and Timer 1 have ﬁve operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1,

2 and 6 are the same for both Timers/Counters. Mode 3 is different.

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8.17.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit

Counter with a divide-by-32 prescaler. In this mode, the Timer register is conﬁgured

as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

8.17.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

8.17.3 Mode 2

Mode 2 conﬁgures the Timer register as an 8-bit Counter with automatic reload.

Mode 2 operation is the same for Timer 0 and Timer 1.

8.17.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit

counters and is provided for applications that require an extra 8-bit timer. When

Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.

8.17.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of

256 timer clocks.

8.17.6 Timer overﬂow toggle output

Timers 0 and 1 can be conﬁgured to automatically toggle a port output whenever a

timer overﬂow occurs. The same device pins that are used for the T0 and T1 count

inputs are also used for the timer toggle outputs. The port outputs will be a logic 1

prior to the ﬁrst timer overﬂow when this mode is turned on.

8.18 Real-Time clock/system timer

The P89LPC924/925 has a simple Real-Time clock that allows a user to continue

running an accurate timer while the rest of the device is powered-down. The

Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a

23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down

counter. When it reaches all ‘0’s, the counter will be reloaded again and the RTCF

ﬂag will be set. The clock source for this counter can be either the CPU clock (CCLK)

or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU

clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as

its clock source. Only power-on reset will reset the Real-Time clock and its

associated SFRs to the default state.

8.19 UART

The P89LPC924/925 has an enhanced UART that is compatible with the

conventional 80C51 UART except that Timer 2 overﬂow cannot be used as a baud

rate source. The P89LPC924/925 does include an independent Baud Rate

Generator. The baud rate can be selected from the oscillator (divided by a constant),

Timer 1 overﬂow, or the independent Baud Rate Generator. In addition to the baud

rate generation, enhancements over the standard 80C51 UART include Framing

Error detection, automatic address recognition, selectable double buffering and

several interrupt options. The UART can be operated in 4 modes: shift register, 8-bit

UART, 9-bit UART, and CPU clock/32 or CPU clock/16.

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8.19.1 Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are

transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at ¹⁄₁₆of the CPU clock

frequency.

8.19.2 Mode 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit

(logical ‘0’), 8 data bits (LSB ﬁrst), and a stop bit (logical ‘1’). When data is received,

the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is

variable and is determined by the Timer 1 overﬂow rate or the Baud Rate Generator

(described in Section 8.19.5 “Baud rate generator and selection”).

8.19.3 Mode 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logical ‘0’),

8 data bits (LSB ﬁrst), a programmable 9^thdata bit, and a stop bit (logical ‘1’). When

data is transmitted, the 9^thdata bit (TB8 in SCON) can be assigned the value of ‘0’ or

‘1’. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When

data is received, the 9^thdata bit goes into RB8 in Special Function Register SCON,

while the stop bit is not saved. The baud rate is programmable to either ¹⁄₁₆or ¹⁄₃₂of

the CPU clock frequency, as determined by the SMOD1 bit in PCON.

8.19.4 Mode 3

11 bits are transmitted (through TxD) or received (through RxD): a start bit

(logical ‘0’), 8 data bits (LSB ﬁrst), a programmable 9^thdata bit, and a stop bit

(logical ‘1’). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate.

The baud rate in Mode 3 is variable and is determined by the Timer 1 overﬂow rate or

the Baud Rate Generator (described in Section 8.19.5 “Baud rate generator and

selection”).

8.19.5 Baud rate generator and selection

The P89LPC924/925 enhanced UART has an independent Baud Rate Generator.

The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and

BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a

similar manner as Timer 1 but is much more accurate. If the baud rate generator is

used, Timer 1 can be used for other timing functions.

The UART can use either Timer 1 or the baud rate generator output (see Figure 7).

Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is set. The

independent Baud Rate Generator uses OSCCLK.

SMOD1 = 1

SBRGS = 0

SBRGS = 1

Timer 1 Overflow

(PCLK-based)

Baud Rate Modes 1 and 3

SMOD1 = 0

Baud Rate Generator

(CCLK-based)

002aaa419

Fig 7. Baud rate sources for UART (Modes 1, 3).

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8.19.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0

(PCON.6) is ‘1’, framing errors can be made available in SCON.7 respectively. If

SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)

are set up when SMOD0 is ‘0’.

8.19.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the

device and force the device into ISP mode.

8.19.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to

be written to SBUF while the ﬁrst character is being transmitted. Double buffering

allows transmission of a string of characters with only one stop bit between any two

characters, as long as the next character is written between the start bit and the stop

bit of the previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = ‘0’), the UART

is compatible with the conventional 80C51 UART. If enabled, the UART allows writing

to SnBUF while the previous data is being shifted out. Double buffering is only

allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be

disabled (DBMOD = ‘0’).

8.19.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated

when the double buffer is ready to receive new data.

8.19.10 The 9^thbit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as

long as TB8 is updated some time before that bit is shifted out. TB8 must not be

changed until the bit is shifted out, as indicated by the Tx interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8

will be double-buffered together with SBUF data.

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8.20 I²C-bus serial interface

I²C-bus uses two wires (SDA and SCL) to transfer information between devices

connected to the bus, and it has the following features:

• Bidirectional data transfer between masters and slaves

• Multimaster bus (no central master)

• Arbitration between simultaneously transmitting masters without corruption of

serial data on the bus

• Serial clock synchronization allows devices with different bit rates to communicate

via one serial bus

• Serial clock synchronization can be used as a handshake mechanism to suspend

and resume serial transfer

• The I²C-bus may be used for test and diagnostic purposes.

A typical I²C-bus conﬁguration is shown in Figure 8. The P89LPC924/925 device

provides a byte-oriented I²C-bus interface that supports data transfers up to 400 kHz.

SDA

SCL

I C-BUS

P1.3/SDA

P1.2/SCL

OTHER DEVICE

WITH I C-BUS

INTERFACE

OTHER DEVICE

WITH I C-BUS

INTERFACE

P89LPC920/921/922

002aaa420

Fig 8. I²C-bus conﬁguration.

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I2ADR

ADDRESS REGISTER

COMPARATOR

P1.3

INPUT

FILTER

P1.3/SDA

SHIFT REGISTER

ACK

I2DAT

OUTPUT

STAGE

BIT COUNTER /

ARBITRATION &

SYNC LOGIC

CCLK

INPUT

FILTER

TIMING

CONTROL

LOGIC

P1.2/SCL

SERIAL CLOCK

GENERATOR

OUTPUT

STAGE

INTERRUPT

TIMER 1

OVERFLOW

I2CON

I2SCLH

I2SCLL

P1.2

CONTROL REGISTERS &

SCL DUTY CYCLE REGISTERS

STATUS

DECODER

STATUS BUS

I2STAT

STATUS REGISTER

002aaa421

Fig 9. I²C-bus serial interface block diagram.

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8.21 Analog comparators

Two analog comparators are provided on the P89LPC924/925. Input and output

options allow use of the comparators in a number of different conﬁgurations.

Comparator operation is such that the output is a logical one (which may be read in a

greater than the negative input (selectable from a pin or an internal reference

voltage). Otherwise the output is a zero. Each comparator may be conﬁgured to

cause an interrupt when the output value changes.

The overall connections to both comparators are shown in Figure 10. The

comparators function to V_DD= 2.4 V.

When each comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are

not guaranteed to be stable for 10 microseconds. The corresponding comparator

interrupt should not be enabled during that time, and the comparator interrupt ﬂag

must be cleared before the interrupt is enabled in order to prevent an immediate

interrupt service.

When a comparator is disabled the comparator’s output, COx, goes HIGH. If the

comparator output was LOW and then is disabled, the resulting transition of the

comparator output from a LOW to HIGH state will set the comparator ﬂag, CMFx.

This will cause an interrupt if the comparator interrupt is enabled. The user should

therefore disable the comparator interrupt prior to disabling the comparator.

Additionally, the user should clear the comparator ﬂag, CMFx, after disabling the

comparator.

CP1

Comparator 1

OE1

(P0.4) CIN1A

(P0.3) CIN1B

CO1

CMP1 (P0.6)

(P0.5) CMPREF

Change Detect

REF

CMF1

CN1

Interrupt

Change Detect

CP2

Comparator 2

CMF2

(P0.2) CIN2A

(P0.1) CIN2B

CMP2 (P0.0)

CO2

OE2

002aaa422

CN2

Fig 10. Comparator input and output connections.

8.21.1 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single

comparator input pin is used. The value of the internal reference voltage, referred to

as V_REF, is 1.23 V ±10%.

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8.21.2 Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag

is set whenever the comparator output changes state. The ﬂag may be polled by

software or may be used to generate an interrupt. The two comparators use one

common interrupt vector. If both comparators enable interrupts, after entering the

interrupt service routine, the user needs to read the ﬂags to determine which

comparator caused the interrupt.

8.21.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is

activated, but both comparators are disabled automatically in Total Power-down

mode. If a comparator interrupt is enabled (except in Total Power-down mode), a

change of the comparator output state will generate an interrupt and wake up the

processor. If the comparator output to a pin is enabled, the pin should be conﬁgured

in the push-pull mode in order to obtain fast switching times while in Power-down

mode. The reason is that with the oscillator stopped, the temporary strong pull-up that

normally occurs during switching on a quasi-bidirectional port pin does not take

place.

Comparators consume power in Power-down and Idle modes, as well as in the

normal operating mode. This fact should be taken into account when system power

consumption is an issue. To minimize power consumption, the user can disable the

comparators via PCONA.5, or put the device in Total Power-down mode.

8.22 Keypad interrupt (KBI)

The Keypad Interrupt function is intended primarily to allow a single interrupt to be

generated when Port 0 is equal to or not equal to a certain pattern. This function can

be used for bus address recognition or keypad recognition. The user can conﬁgure

the port via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to deﬁne which input pins

connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN)

is used to deﬁne a pattern that is compared to the value of Port 0. The Keypad

Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when

the condition is matched while the Keypad Interrupt function is active. An interrupt will

be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register

(KBCON) is used to deﬁne equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x

series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then

any key connected to Port 0 which is enabled by the KBMASK register will cause the

hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt

may be used to wake up the CPU from Idle or Power-down modes. This feature is

particularly useful in handheld, battery-powered systems that need to carefully

manage power consumption yet also need to be convenient to use.

In order to set the ﬂag and cause an interrupt, the pattern on Port 0 must be held

longer than 6 CCLKs.

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8.23 Watchdog timer

The watchdog timer causes a system reset when it underﬂows as a result of a failure

to feed the timer prior to the timer reaching its terminal count. It consists of a

programmable 12-bit prescaler, and an 8-bit down counter. The down counter is

decremented by a tap taken from the prescaler. The clock source for the prescaler is

either the PCLK or the nominal 400 kHz Watchdog oscillator. The watchdog timer can

only be reset by a power-on reset. When the watchdog feature is disabled, it can be

used as an interval timer and may generate an interrupt. Figure 11 shows the

watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte

sequence. If PCLK is selected as the watchdog clock and the CPU is powered-down,

the watchdog is disabled. The watchdog timer has a time-out period that ranges from

a few µs to a few seconds. Please refer to the P89LPC924/925 User’s Manual for

more details.

WDL (C1H)

MOV WFEED1, #0A5H

MOV WFEED2, #05AH

Watchdog

oscillator

8-BIT DOWN

COUNTER

PRESCALER

÷32

RESET

see note (1)

PCLK

SHADOW

FOR WDCON

CONTROL REGISTER

PRE2

PRE1

PRE0

–

WDRUN WDTOF WDCLK

WDCON (A7H)

002aaa423

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a

feed sequence.

Fig 11. Watchdog timer in Watchdog mode (WDTE = ‘1’).

8.24 Additional features

8.24.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor

completely, as if an external reset or watchdog reset had occurred. Care should be

taken when writing to AUXR1 to avoid accidental software resets.

8.24.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the

address used with certain instructions. The DPS bit in the AUXR1 register selects

one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic ‘0’ so

that the DPS bit may be toggled (thereby switching Data Pointers) simply by

incrementing the AUXR1 register, without the possibility of inadvertently altering other

bits in the register.

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8.25 Flash program memory

8.25.1 General description

The P89LPC924/925 Flash memory provides in-circuit electrical erasure and

programming. The Flash can be read, erased, or written as bytes. The Sector and

Page Erase functions can erase any Flash sector (1 kB) or page (64 bytes). The Chip

Erase operation will erase the entire program memory. In-System Programming and

standard parallel programming are both available. On-chip erase and write timing

generation contribute to a user-friendly programming interface. The P89LPC924/925

Flash reliably stores memory contents even after 100,000 erase and program cycles.

The cell is designed to optimize the erase and programming mechanisms. The

P89LPC924/925 uses V_DDas the supply voltage to perform the Program/Erase

algorithms.

8.25.2 Features

• Parallel programming with industry-standard commercial programmers.

• In-Circuit serial Programming (ICP) with industry-standard commercial

programmers.

• IAP-Lite allows individual and multiple bytes of code memory to be used for data

storage and programmed under control of the end application.

• Internal ﬁxed boot ROM, containing low-level In-Application Programming (IAP)

routines that can be called from the end application (in addition to IAP-Lite).

• Default serial loader providing In-System Programming (ISP) via the serial port,

located in upper end of user program memory.

• Boot vector allows user-provided Flash loader code to reside anywhere in the

Flash memory space, providing ﬂexibility to the user.

• Programming and erase over the full operating voltage range.

• Read/Programming/Erase using ISP/IAP/IAP-Lite.

• Any ﬂash program operation in 2 ms.

• Any ﬂash erase operation in 4 ms.

• Programmable security for the code in the Flash for each sector.

• >100,000 typical erase/program cycles for each byte.

• 10 year minimum data retention.

8.25.3 ISP and IAP capabilities of the P89LPC924/925

Flash organization: The P89LPC924/925 program memory consists of four/eight

1 kB sectors. Each sector can be further divided into 64-byte pages. In addition to

sector erase, page erase, and byte erase, a 64-byte page register is included which

allows from 1 to 64 bytes of a given page to be programmed at the same time,

substantially reducing overall programming time. An In-Application Programming

(IAP) interface is provided to allow the end user’s application to erase and reprogram

the user code memory. In addition, erasing and reprogramming of

user-programmable bytes including UCFG1, the Boot Status Byte and the Boot

Vector are supported. As shipped from the factory, the upper 512 bytes of user code

space contains a serial In-System Programming (ISP) routine allowing for the device

to be programmed in circuit through the serial port.

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Flash programming and erasing: There are four methods of erasing or

programming of the Flash memory that may be used. First, the Flash may be

programmed or erased in the end-user application by calling low-level routines

through a common entry point. Second, the on-chip ISP boot loader may be invoked.

This ISP boot loader will, in turn, call low-level routines through the same common

entry point that can be used by the end-user application. Third, the Flash may be

programmed or erased using the parallel method by using a commercially available

EPROM programmer which supports this device. Fourth, the Flash may be

programmed or erased using a commercially available EPROM programmer which

supports the ICP protocol. This device does not provide for direct veriﬁcation of code

memory contents. Instead this device provides a 32-bit CRC result on either a sector

or the entire 4 kB/8 kB of user code space.

Boot ROM: When the microcontroller programs its own Flash memory, all of the

low-level details are handled by code that is contained in a Boot ROM that is separate

from the Flash memory. A user program simply calls the common entry point in the

Boot ROM with appropriate parameters to accomplish the desired operation. The

Boot ROM include operations such as erase sector, erase page, program page, CRC,

program security bit, etc. The Boot ROM occupies the program memory space at the

top of the address space from FF00 to FFFF hex, thereby not conﬂicting with the user

program memory space.

Power-on reset code execution: The P89LPC924/925 contains two special Flash

elements: the Boot Vector and the Boot Status Bit. Following reset, the

P89LPC924/925 examines the contents of the Boot Status Bit. If the Boot Status Bit

is set to zero, power-up execution starts at location 0000H, which is the normal start

address of the user’s application code. When the Boot Status Bit is set to a one, the

contents of the Boot Vector is used as the high byte of the execution address and the

low byte is set to 00H. The factory default setting is 1FH for the P89LPC925 and

corresponds to the address 1F00H for the default ISP boot loader. The factory default

setting is 0FH for the P89LPC924 and corresponds to the address 0F00H for the

default ISP boot loader. This boot loader is pre-programmed at the factory into this

address space and can be erased by the user. Users who wish to use this loader

should take precautions to avoid erasing the 1 kB sector from 1C00H to 1FFFH

in the P89LPC925 or the 1 kB sector from 0C00H to 0FFFH in the P89LPC924.

Instead, the page erase function can be used to erase the eight 64-byte pages

which comprise the lower 512 bytes of the sector. A custom boot loader can be

written with the Boot Vector set to the custom boot loader, if desired.

Hardware activation of the boot loader: The boot loader can also be executed by

forcing the device into ISP mode during a power-on sequence (see the

P89LPC924/925 User’s Manual for speciﬁc information). This has the same effect as

having a non-zero Boot Status Bit. This allows an application to be built that will

normally execute user code but can be manually forced into ISP operation. If the

factory default setting for the Boot Vector is changed, it will no longer point to the

factory pre-programmed ISP boot loader code. If this happens, the only way it is

possible to change the contents of the Boot Vector is through the parallel or ICP

programming methods, provided that the end user application does not contain a

customized loader that provides for erasing and reprogramming of the Boot Vector

and Boot Status Bit. After programming the Flash, the Boot Status Bit should be

programmed to zero in order to allow execution of the user’s application code

beginning at address 0000H.

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In-System Programming (ISP): In-System Programming is performed without

removing the microcontroller from the system. The In-System Programming facility

consists of a series of internal hardware resources coupled with internal ﬁrmware to

facilitate remote programming of the P89LPC924/925 through the serial port. This

ﬁrmware is provided by Philips and embedded within each P89LPC924/925 device.

The Philips In-System Programming facility has made in-system programming in an

embedded application possible with a minimum of additional expense in components

and circuit board area. The ISP function uses ﬁve pins (V_DD, V_SS, TXD, RXD, and

RST). Only a small connector needs to be available to interface your application to an

external circuit in order to use this feature. Please see the P89LPC924/925 User’s

Manual for additional details.

In-Application Programming (IAP): Several In-Application Programming (IAP) calls

are available for use by an application program to permit selective erasing and

programming of Flash sectors, pages, security bits, conﬁguration bytes, and device

identiﬁcation. All calls are made through a common interface, PGM_MTP. The

programming functions are selected by setting up the microcontroller’s registers

before making a call to PGM_MTP at FF03H. Please see the P89LPC924/925 User’s

Manual for additional details.

In-Circuit Programming (ICP): In-Circuit Programming is a method intended to

allow commercial programmers to program and erase these devices without

removing the microcontroller from the system. The In-Circuit Programming facility

consists of a series of internal hardware resources to facilitate remote programming

of the P89LPC924/925 through a two-wire serial interface. Philips has made in-circuit

programming in an embedded application possible with a minimum of additional

expense in components and circuit board area. The ICP function uses ﬁve pins (V_DD

V_SS, P0.5, P0.4, and RST). Only a small connector needs to be available to interface

your application to an external programmer in order to use this feature.

8.26 User conﬁguration bytes

A number of user-conﬁgurable features of the P89LPC924/925 must be deﬁned at

power-up and therefore cannot be set by the program after start of execution. These

features are conﬁgured through the use of the Flash byte UCFG1. Please see the

P89LPC924/925 User’s Manual for additional details.

8.27 User sector security bytes

There are four or eight User Sector Security Bytes, depending on the device, each

corresponding to one sector. Please see the P89LPC924/925 User’s Manual for

additional details.

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9. Limiting values

Table 7:

In accordance with the Absolute Maximum Rating System (IEC 60134).

Limiting values^[1]

Symbol

T_amb(bias)

T_stg

Parameter

Conditions

Min

Max

+125

+150

V_DD+ 0.5

+5.5

Unit

°C

operating bias ambient temperature

storage temperature range

−55

−65

V_xtal

voltage on XTAL1, XTAL2 pin to V_SS

voltage on any other pin to V_SS

HIGH-level output current per I/O pin

LOW-level output current per I/O pin

V_n

−0.5

I_OH(I/O)

I_OL(I/O)

I_{I/O(tot)(max)}maximum total I/O current

P_tot(pack)

total power dissipation per package

based on package heat

transfer, not device power

consumption

1.5

[1] The following applies to Limiting values:

a) Stresses above those listed under Table 7 may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any conditions other than those described in Table 8 “DC electrical characteristics”, Table 9 “AC

characteristics” and Table 10 “AC characteristics” of this speciﬁcation are not implied.

b) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

c) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

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8-bit microcontrollers with accelerated two-clock 80C51 core

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10. Static characteristics

Table 8:

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.

DC electrical characteristics

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

µA

[2]

I_DD(oper)

power supply current, operating

3.6 V; 12 MHz

3.6 V; 18 MHz

3.6 V; 12 MHz

3.6 V; 18 MHz

I_DD(idle)

power supply current, Idle mode

3.25

I_DD(PD)

power supply current, Power-down 3.6 V

mode, voltage comparators

powered-down

[2]

I_DD(TPD)

power supply current, Total

Power-down mode

3.6 V

µA

(dV_DD/dt)_r

(dV_DD/dt)_f

V_POR

V_RAM

V_th(HL)

V_IL

V_DDrise rate

mV/µs

V_DDfall rate

mV/µs

Power-on reset detect voltage

RAM keep-alive voltage

negative-going threshold voltage

LOW-level input voltage

positive-going threshold voltage

HIGH-level input voltage

hysteresis voltage

0.2

1.5

except SCL, SDA

SCL, SDA only

except SCL, SDA

SCL, SDA only

Port 1

0.22V_DD

0.4V_DD

−0.5

0.3V_DD

V_th(LH)

V_IH

0.6V_DD

0.7V_DD

5.5

V_hys

0.2V_DD

0.6

[3]

V_OL

LOW-level output voltage; all ports, I_OL= 20 mA

all modes except Hi-Z

1.0

0.3

I_OL= 3.2 mA

0.2

V_OH

HIGH-level output voltage, all ports I_OH= −3.2 mA;

_DD− 0.7

_DD− 0.3

_DD− 0.4

push-pull mode

I_OH= −20 µA;

_DD− 0.2

quasi-bidirectional

mode

[4]

C_ig

I_IL

input/output pin capacitance

logical 0 input current, all ports

input leakage current, all ports

µA

[5]

V_IN= 0.4 V

−80

± 10

−450

[6]

I_LI

V_IN= V_ILor V_IH

[7], [8]

I_TL

logical 1-to-0 transition current,

all ports

V_IN= 2.0 V at

V_DD= 3.6 V

−30

R_RST

internal reset pull-up resistor

kΩ

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Table 8:

DC electrical characteristics…continued

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

V_BO

brownout trip voltage with

BOV = ‘0’, BOPD = ‘1’

2.4 V < V_DD< 3.6 V

2.40

2.70

V_REF

bandgap reference voltage

1.11

1.23

1.34

TC_(VREF)

bandgap temperature coefﬁcient

ppm/°C

[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.

[2] The I_DD(oper), I_DD(idle), and I_DD(PD)speciﬁcations are measured using an external clock with the following functions disabled: comparators,

brownout detect, and watchdog timer.

[3] See Table 7 “Limiting values^[1]” on page 39 for steady state (non-transient) limits on I_OLor I_OH. If I_OL/I_OHexceeds the test condition,

V_OL/V_OHmay exceed the related speciﬁcation.

[4] Pin capacitance is characterized but not tested.

[5] Measured with port in quasi-bidirectional mode.

[6] Measured with port in high-impedance mode.

[7] Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups). Does not apply to open-drain pins.

[8] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from ‘1’ to ‘0’. This current is highest

when V_INis approximately 2 V.

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11. Dynamic characteristics

Table 9:

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.^[1]

AC characteristics

Symbol Parameter

Conditions

Variable clock

f_osc= 12 MHz

Min Max

7.189 7.557 MHz

Unit

Min

Max

f_RCOSC

f_WDOSC

internal RC oscillator frequency

(nominal f = 7.3728 MHz)

trimmed to ±1%

at T_amb= 25 °C

7.189

7.557

internal Watchdog oscillator

320

520

320

520

kHz

frequency (nominal f = 400 kHz)

f_osc

oscillator frequency

clock cycle

MHz

t_CLCL

see Figure 13

f_CLKP

CLKLP active frequency

MHz

Glitch ﬁlter

glitch rejection, P1.5/RST pin

signal acceptance, P1.5/RST pin

125

glitch rejection, any pin except

P1.5/RST

signal acceptance, any pin except

P1.5/RST

External clock

t_CHCX

t_CLCX

t_CLCH

t_CHCL

HIGH time

see Figure 13

_CLCL− t_CLCX

LOW time

rise time

fall time

_CLCL− t_CHCX33

Shift register (UART mode 0)

t_XLXL

serial port clock cycle time

16 t_CLCL

13 t_CLCL

1333

1083

t_QVXH

output data set-up to clock rising

edge

t_XHQX

output data hold after clock rising

edge

t_CLCL+ 20

103

t_XHDX

t_DVXH

input data hold after clock rising edge

input data valid to clock rising edge

150

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed. Parts are tested to 2 MHz, but are guaranteed to

operate down to 0 Hz.

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Table 10: AC characteristics

V_DD= 3.0 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.^[1]

Symbol

Parameter

Conditions

Variable clock

f_osc= 18 MHz

Min Max

7.189 7.557 MHz

Unit

Min

Max

f_RCOSC

f_WDOSC

internal RC oscillator frequency

(nominal f = 7.3728 MHz)

trimmed to ±1%

at T_amb= 25 °C

7.189

7.557

internal Watchdog oscillator

320

520

320

520

kHz

frequency (nominal f = 400 kHz)

[2]

f_osc

oscillator frequency

clock cycle

MHz

t_CLCL

see Figure 13

f_CLKP

CLKLP active frequency

MHz

Glitch ﬁlter

glitch rejection, P1.5/RST pin

signal acceptance, P1.5/RST pin

125

glitch rejection, any pin except

P1.5/RST

signal acceptance, any pin except

P1.5/RST

External clock

t_CHCX

t_CLCX

t_CLCH

t_CHCL

HIGH time

see Figure 13

_CLCL− t_CLCX

LOW time

rise time

fall time

t_CLCL− t_CHCX22

Shift register (UART mode 0)

t_XLXL

serial port clock cycle time

16 t_CLCL

13 t_CLCL

888

722

t_QVXH

output data set-up to clock rising

edge

t_XHQX

t_XHDX

t_DVXH

output data hold after clock rising

edge

t_CLCL+ 20

input data hold after clock rising

edge

input data valid to clock rising edge

150

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed. Parts are tested to 2 MHz, but are guaranteed to

operate down to 0 Hz.

[2] When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to

hold the device in reset at power-up until V_DDhas reached its speciﬁed level. When system power is removed V_DDwill fall below the

minimum speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout

detect circuit may be required to hold the device in reset when V_DDfalls below the minimum speciﬁed operating voltage.

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XLXL

Clock

XHQX

QVXH

Output Data

Write to SBUF

XHDX

Set TI

Valid

XHDV

Input Data

Clear RI

Valid

Set RI

002aaa425

Fig 12. Shift register mode timing.

- 0.5 V

0.45 V

0.2 V

+ 0.9

0.2 V

- 0.1 V

CHCX

CHCL

CLCX

CLCH

002aaa416

Fig 13. External clock timing.

Table 11: AC characteristics, ISP entry mode

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.

Symbol

t_VR

Parameter

Conditions

Min

Typ

Max

Unit

µs

RST delay from V_DDactive

RST HIGH time

RST LOW time

t_RH

µs

t_RL

µs

RST

002aaa426

Fig 14. ISP entry waveform.

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12. Comparator electrical characteristics

Table 12: Comparator electrical characteristics

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.

Symbol

V_IO

Parameter

Conditions

Min

Typ

Max

Unit

offset voltage comparator inputs

common mode range comparator inputs

common mode rejection ratio

response time

±20

V_CR

V_DD− 0.3

[1]

CMRR

−50

500

250

comparator enable to output valid

input leakage current, comparator

µs

I_IL

0 < V_IN< V_DD

±10

µA

[1] This parameter is characterized, but not tested in production.

13. A/D converter electrical characteristics

Table 13: A/D converter electrical characteristics

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

T_amb= −40 °C to +85 °C for industrial, unless otherwise speciﬁed.

All limits valid for an external source impedance of less than 10 kΩ.

Symbol

AV_IN

C_IA

Parameter

Conditions

Min

Typ

Max

V_SS+ 0.2

Unit

analog input voltage

analog input capacitance

differential non-linearity

integral non-linearity

offset error

_SS− 0.2 -

D_NL

±1

LSB

I_NL

±1

OS_e

G_e

±2

gain error

±1

T_ue

total unadjusted error

channel-to-channel matching

crosstalk between port inputs

input slew rate

±2

LSB

M_CTC

α_ct(port)

SR_in

t_ADC

±1

0 to 100 kHz

A/D enabled

−60

100

V/ms

conversion time

ADC

clocks

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14. Package outline

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT360-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

(2)

(1)

UNIT

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

6.6

6.4

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

1.1

0.65

0.25

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT360-1

MO-153

Fig 15. TSSOP20 (SOT360-1).

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15. Revision history

Table 14: Revision history

Rev Date

CPCN

Description

03 20041215

Product data (9397 750 14471)

Modiﬁcation:

• Added 18 MHz information.

Product data (9397 750 13459)

Objective data (9397 750 12879)

02 20040615

01 20040309

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8-bit microcontrollers with accelerated two-clock 80C51 core

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16. Data sheet status

Level Data sheet status^[1]

Product status^[2][3]

Deﬁnition

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

17. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

19. Licenses

Purchase of Philips I²C components

18. Disclaimers

Purchase of Philips I²C components conveys a license

under the Philips’ I²C patent to use the components in the

I²C system provided the system conforms to the I²C

speciﬁcation deﬁned by Philips. This speciﬁcation can be

ordered using the code 9398 393 40011.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

48 of 49

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8-bit microcontrollers with accelerated two-clock 80C51 core

Philips Semiconductors

Contents

General description. . . . . . . . . . . . . . . . . . . . . . . . . . . 1

8.15.2

8.15.3

8.16

8.16.1

8.17

8.17.1

8.17.2

8.17.3

8.17.4

8.17.5

8.17.6

8.18

Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Total Power-down mode . . . . . . . . . . . . . . . . . . . . . . 26

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Timers/counters 0 and 1. . . . . . . . . . . . . . . . . . . . . . 27

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Timer overﬂow toggle output. . . . . . . . . . . . . . . . . . . 28

Real-Time clock/system timer. . . . . . . . . . . . . . . . . . 28

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Baud rate generator and selection . . . . . . . . . . . . . . 29

Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Transmit interrupts with double buffering

enabled (Modes 1, 2 and 3). . . . . . . . . . . . . . . . . . . 30

The 9^thbit (bit 8) in double buffering (Modes 1, 2 and

3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

I²C-bus serial interface . . . . . . . . . . . . . . . . . . . . . . . 31

Analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . 33

Internal reference voltage . . . . . . . . . . . . . . . . . . . . . 33

Comparator interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 34

Comparators and power reduction modes . . . . . . . . 34

Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . . . . . . 34

Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Dual data pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Flash program memory. . . . . . . . . . . . . . . . . . . . . . . 36

General description. . . . . . . . . . . . . . . . . . . . . . . . . . 36

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

ISP and IAP capabilities of the P89LPC924/925 . . . 36

User conﬁguration bytes . . . . . . . . . . . . . . . . . . . . . . 38

User sector security bytes . . . . . . . . . . . . . . . . . . . . 38

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Principal features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1

2.2

Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.1

Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5.1

5.2

Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Special function registers. . . . . . . . . . . . . . . . . . . . . . 9

8.19

8.19.1

8.19.2

8.19.3

8.19.4

8.19.5

8.19.6

8.19.7

8.19.8

8.19.9

Functional description . . . . . . . . . . . . . . . . . . . . . . . 14

Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Clock deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CPU clock (OSCCLK) . . . . . . . . . . . . . . . . . . . . . . . 14

Low speed oscillator option . . . . . . . . . . . . . . . . . . . 14

Medium speed oscillator option . . . . . . . . . . . . . . . . 14

High speed oscillator option. . . . . . . . . . . . . . . . . . . 14

Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

On-chip RC oscillator option . . . . . . . . . . . . . . . . . . 15

Watchdog oscillator option. . . . . . . . . . . . . . . . . . . . 15

External clock input option . . . . . . . . . . . . . . . . . . . . 15

CPU Clock (CCLK) wake-up delay. . . . . . . . . . . . . . 17

CPU Clock (CCLK) modiﬁcation: DIVM register . . . 17

Low power select . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

General description . . . . . . . . . . . . . . . . . . . . . . . . . 18

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

A/D operating modes . . . . . . . . . . . . . . . . . . . . . . . . 19

Conversion start modes . . . . . . . . . . . . . . . . . . . . . . 20

Boundary limits interrupt . . . . . . . . . . . . . . . . . . . . . 21

DAC output to a port pin with high output impedance 21

Clock divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power-down and idle mode . . . . . . . . . . . . . . . . . . . 21

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . 21

Data RAM arrangement . . . . . . . . . . . . . . . . . . . . . . 22

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

External interrupt inputs. . . . . . . . . . . . . . . . . . . . . . 22

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Port conﬁgurations . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Quasi-bidirectional output conﬁguration. . . . . . . . . . 24

Open-drain output conﬁguration. . . . . . . . . . . . . . . . 24

Input-only conﬁguration . . . . . . . . . . . . . . . . . . . . . . 24

Push-pull output conﬁguration . . . . . . . . . . . . . . . . . 24

Port 0 analog functions . . . . . . . . . . . . . . . . . . . . . . 24

Additional port features . . . . . . . . . . . . . . . . . . . . . . 25

Power monitoring functions . . . . . . . . . . . . . . . . . . . 25

Brownout detection . . . . . . . . . . . . . . . . . . . . . . . . . 25

Power-on detection . . . . . . . . . . . . . . . . . . . . . . . . . 25

Power reduction modes . . . . . . . . . . . . . . . . . . . . . . 26

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.1

8.2

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.3

8.4

8.5

8.6

8.7

8.19.10

8.20

8.21

8.21.1

8.21.2

8.21.3

8.22

8.8

8.9

8.9.1

8.9.2

8.9.3

8.9.4

8.9.5

8.9.6

8.9.7

8.9.8

8.10

8.11

8.12

8.12.1

8.13

8.13.1

8.13.2

8.13.3

8.13.4

8.13.5

8.13.6

8.13.7

8.14

8.14.1

8.14.2

8.15

8.15.1

8.23

8.24

8.24.1

8.24.2

8.25

8.25.1

8.25.2

8.25.3

8.26

8.27

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 40

Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 42

Comparator electrical characteristics . . . . . . . . . . . 45

A/D converter electrical characteristics. . . . . . . . . . 45

Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Printed in the U.S.A.

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 15 December 2004

Document order number: 9397 750 14471

P89LPC925FDH-S [NXP]

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