P89LPC9401FBD [NXP]
8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 32 segment x 4 LCD driver; 8位微控制器,带有加速双时钟80C51核心8 KB的3伏字节可擦除闪存与32段×4的LCD驱动器型号: | P89LPC9401FBD |
厂家: | NXP |
描述: | 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 32 segment x 4 LCD driver |
文件: | 总59页 (文件大小:284K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
P89LPC9401
8-bit microcontroller with accelerated two-clock 80C51 core
8 kB 3 V byte-erasable flash with 32 segment × 4 LCD driver
Rev. 01 — 5 September 2005
Preliminary data sheet
1. General description
The P89LPC9401 is a multi-chip module consisting of a P89LPC931 single-chip
microcontroller combined with a PCF8576D universal LCD driver in a low-cost 64-pin
package. The LCD driver provides 32 segments and supports from 1 to 4 backplanes.
Display overhead is minimized by an on-chip display RAM with auto-increment
addressing.
2. Features
2.1 Principal features
■ 8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages.
Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
■ 256-byte RAM data memory.
■ 32 segment × 4 backplane LCD controller supports from 1 to 4 backplanes.
■ Two analog comparators with selectable inputs and reference source.
■ Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output) and a 23-bit system timer that can also be used
as a Real-Time Clock (RTC).
■ Enhanced UART with fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port and SPI communication port.
■ High-accuracy internal RC oscillator option allows operation without external oscillator
components. The RC oscillator option is selectable and fine tunable.
■ 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
■ 64-pin LQFP package with 20 microcontroller I/O pins minimum and up to 23
microcontroller I/O pins while using on-chip oscillator and reset options.
■ Serial flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs.
2.2 Additional features
■ A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequency for the same performance results in power savings and reduced
EMI.
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
■ Serial flash In-System Programming (ISP) allows coding while the device is mounted
in the end application.
■ In-Application Programming (IAP) of the flash code memory. This allows changing the
code in a running application.
■ Watchdog timer with separate on-chip oscillator, requiring no external components.
The watchdog prescaler is selectable from eight values.
■ Low voltage detect (brownout) allows a graceful system shutdown when power fails.
May optionally be configured as an interrupt.
■ Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 9 µA typical (total power-down with voltage comparators disabled).
■ Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent spurious
and incomplete resets. A software reset function is also available.
■ Configurable on-chip oscillator with frequency range options selected by user
programmed flash configuration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 18 MHz.
■ Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
■ Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.
■ Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
■ LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip.
■ Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
■ Only power and ground connections are required to operate the P89LPC9401 when
internal reset option is selected.
■ Four interrupt priority levels.
■ Eight keypad interrupt inputs, plus two additional external interrupt inputs.
■ Schmitt trigger port inputs.
■ Second data pointer.
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
2 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
3. Ordering information
Table 1:
Ordering information
Type number
Package
Name
Description
Version
P89LPC9401FBD
LQFP64
plastic low profile quad flat package; 64 leads;
SOT791-1
body 14 × 14 × 1.4 mm
3.1 Ordering options
Table 2:
Part options
Type number
Flash memory
Temperature range
Frequency
P89LPC9401FBD
8 kB
−40 °C to +85 °C
0 MHz to 18 MHz
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
3 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
4. Block diagram
P3[1:0]
P2.5, P2[3:0]
P1[7:0]
S[31:0]
BP[3:0]
PCF8576D
P89LPC931
LCD
MCU
CONTROLLER
V
LCD
P0[7:0]
002aab460
Fig 1. Block diagram
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
4 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
P89LPC931
ACCELERATED 2-CLOCK 80C51 CPU
TXD
RXD
8 kB CODE FLASH
UART
internal bus
SCL
SDA
256-BYTE
DATA RAM
2
I C-BUS
SPI
SPICLK
MOSI
MISO
PORT 3
CONFIGURABLE I/Os
P3[1:0]
P2.5, P2[3:0]
P1[7:0]
PORT 2
CONFIGURABLE I/Os
REAL-TIME CLOCK/
SYSTEM TIMER
PORT 1
CONFIGURABLE I/Os
T0
T1
TIMER 0
TIMER 1
PORT 0
CONFIGURABLE I/Os
CMP2
CIN2B
CIN2A
CMP1
CIN1A
CIN1B
P0[7:0]
ANALOG
COMPARATORS
KEYPAD
INTERRUPT
WATCHDOG TIMER
AND OSCILLATOR
PROGRAMMABLE
OSCILLATOR DIVIDER
CPU
clock
X1
CRYSTAL
ON-CHIP
RC
OSCILLATOR
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
CONFIGURABLE
OSCILLATOR
OR
RESONATOR
X2
002aab461
Fig 2. Microcontroller section block diagram
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
5 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
BP0 BP1 BP2 BP3
S0 TO S39
V
DD
BACKPLANE
OUTPUTS
DISPLAY SEGMENT OUTPUTS
LCD
VOLTAGE
SELECTOR
DISPLAY LATCH
SHIFT REGISTER
LCD BIAS
GENERATOR
V
LCD
CLK
TIMING
BLINKER
INPUT
BANK
SELECTOR
DISPLAY
RAM
40 × 4 BITS
OUTPUT
BANK
SELECTOR
SYNC
DISPLAY
CONTROLLER
POWER-
ON
RESET
OSCILLATOR
OSC
DATA
POINTER
COMMAND
DECODER
V
SS
SCL
SDA
SUB-
ADDRESS
COUNTER
2
INPUT
FILTERS
I C-BUS
CONTROLLER
SA0
A0 A1 A2
002aab470
Fig 3. LCD display controller block diagram
5. Functional diagram
V
V
SS
DD
TXD
RXD
T0
INT0
INT1
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
KBI6
KBI7
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
CMP1
T1
SCL
SDA
PORT 0
PORT 3
PORT 1
PORT 2
RST
P89LPC9401
CLKOUT
XTAL2
XTAL1
MOSI
MISO
SPICLK
SCL
SDA
BP[0:3]
S[0:31]
002aab462
Fig 4. P89LPC9401 functional diagram
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
6 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
6. Pinning information
6.1 Pinning
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P0.5/CMPREF/KBI5
S17
S16
S15
S14
S13
S12
S11
S10
S9
P0.4/CIN1A/KBI4
P0.3/CIN1B/KBI3
P0.2/CIN2A/KBI2
P0.1/CIN2B/KBI1
P2.0
3
4
5
6
7
P2.1
8
P0.0/CMP2/KBI0
P1.7
P89LPC9401
9
10
11
12
13
14
15
16
P1.6
S8
P1.5/RST
S7
V
SS
S6
P3.1/XTAL1
P3.0/XTAL2/CLKOUT
P1.4/INT1
S5
S4
S3
P1.3/INT0/SDA
S2
002aab469
Fig 5. Pin configuration
6.2 Pin description
Table 3:
Pin description
Symbol
Pin
Type Description
P0.0 to P0.7
I/O
Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset
Port 0 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 0 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 7.13.1 “Port
configurations” and Table 11 “Static electrical characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt trigger inputs.
Port 0 also provides various special functions as described below:
P0.0 — Port 0 bit 0.
P0.0/CMP2/
KBI0
8
I/O
O
I
CMP2 — Comparator 2 output.
KBI0 — Keyboard input 0.
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
7 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
Table 3:
Symbol
Pin description …continued
Pin
Type Description
P0.1/CIN2B/
KBI1
5
I/O
P0.1 — Port 0 bit 1.
I
CIN2B — Comparator 2 positive input B.
KBI1 — Keyboard input 1.
I
P0.2/CIN2A/
KBI2
4
I/O
P0.2 — Port 0 bit 2.
I
CIN2A — Comparator 2 positive input A.
KBI2 — Keyboard input 2.
I
P0.3/CIN1B/
KBI3
3
I/O
P0.3 — Port 0 bit 3.
I
CIN1B — Comparator 1 positive input B.
KBI3 — Keyboard input 3.
I
P0.4/ CIN1A/
KBI4
2
I/O
P0.4 — Port 0 bit 4.
I
CIN1A — Comparator 1 positive input A.
KBI4 — Keyboard input 4.
I
P0.5/
CMPREF/
KBI5
1
I/O
I
P0.5 — Port 0 bit 5.
CMPREF — Comparator reference (negative) input.
KBI5 — Keyboard input 5.
I
P0.6/CMP1/
KBI6
24
I/O
O
I
P0.6 — Port 0 bit 6.
CMP1 — Comparator 1 output.
KBI6 — Keyboard input 6.
P0.7/T1/KBI7 23
P1.0 to P1.7
I/O
I/O
I
P0.7 — Port 0 bit 7.
T1 — Timer/counter 1 external count input or overflow output.
KBI7 — Keyboard input 7.
I/O, I Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three
[1]
pins as noted below. During reset Port 1 latches are configured in the input only mode
with the internal pull-up disabled. The operation of the configurable Port 1 pins as
inputs and outputs depends upon the port configuration selected. Each of the
configurable port pins are programmed independently. Refer to Section 7.13.1 “Port
configurations” and Table 11 “Static electrical characteristics” for details. P1.2 and P1.3
are open drain when used as outputs. P1.5 is input only.
All pins have Schmitt trigger inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD
22
21
17
I/O
O
P1.0 — Port 1 bit 0.
TXD — Transmitter output for the serial port.
P1.1 — Port 1 bit 1.
P1.1/RXD
P1.2/T0/SCL
I/O
I
RXD — Receiver input for the serial port.
P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O
I/O
T0 — Timer/counter 0 external count input or overflow output (open-drain when used
as output).
I/O
SCL — I2C-bus serial clock input/output.
P1.3 — Port 1 bit 3 (open-drain when used as output).
INT0 — External interrupt 0 input.
SDA — I2C-bus serial data input/output.
P1.4 — Port 1 bit 4.
P1.3/INTO/
SDA
16
15
I/O
I
I/O
P1.4/INT1
I
I
INT1 — External interrupt 1 input.
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
8 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
Table 3:
Symbol
P1.5/RST
Pin description …continued
Pin
Type Description
11
I
I
P1.5 — Port 1 bit 5 (input only).
RST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force ISP mode.
When using an oscillator frequency above 12 MHz, the reset input function of
P1.5 must be enabled. An external circuit is required to hold the device in reset at
power-up until VDD has reached its specified level. When system power is
removed VDD will fall below the minimum specified operating voltage. When
using an oscillator frequency above 12 MHz, in some applications, an external
brownout detect circuit may be required to hold the device in reset when VDD falls
below the minimum specified operating range.
P1.6
P1.7
10
9
I/O
I/O
I/O
P1.6 — Port 1 bit 6.
P1.7 — Port 1 bit 7.
P2.0 to P2.3,
P2.5
Port 2: Port 2 is an 5-bit I/O port with a user-configurable output type. During reset
Port 2 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 2 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 7.13.1 “Port
configurations” and Table 11 “Static electrical characteristics” for details.
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0 — Port 2 bit 0.
P2.0
6
I/O
I/O
I/O
I/O
P2.1
7
P2.1 — Port 2 bit 1.
P2.2/MOSI
18
P2.2 — Port 2 bit 2.
MOSI — SPI master out slave in. When configured as master, this pin is output; when
configured as slave, this pin is input.
P2.3/MISO
19
I/O
I/O
P2.3 — Port 2 bit 3.
MISO — When configured as master, this pin is input, when configured as slave, this
pin is output.
P2.5/SPICLK 20
P3.0 to P3.1
I/O
I/O
P2.5 — Port 2 bit 5.
SPICLK — SPI clock. When configured as master, this pin is output; when configured
as slave, this pin is input.
I/O
Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset
Port 3 latches are configured in the input only mode with the internal pull-up disabled.
The operation of Port 3 pins as inputs and outputs depends upon the port configuration
selected. Each port pin is configured independently. Refer to Section 7.13.1 “Port
configurations” and Table 11 “Static electrical characteristics” for details.
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described below:
P3.0 — Port 3 bit 0.
P3.0/XTAL2/
CLKOUT
14
I/O
O
XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is
selected via the flash configuration.
O
CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It
can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source for
the RTC/system timer.
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
9 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
Table 3:
Pin description …continued
Symbol
Pin
Type Description
P3.1/XTAL1
13
I/O
I
P3.1 — Port 3 bit 1.
XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when
selected via the flash configuration). It can be a port pin if internal RC oscillator or
watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used
to generate the clock for the RTC/system timer.
SDA_LCD
SCL_LCD
BP0 to BP3
S0 to S31
VSS
63
I/O
I/O
O
O
I
SDA LCD — I2C-bus data signal for the LCD controller.
SCL LCD — I2C-bus clock signal for the LCD controller.
BP0 to BP3: LCD backplane outputs.
S0 to S31: LCD segment outputs.
64
27 to 30
31 to 62
12
Ground: 0 V reference.
VDD
25
I
Power supply: This is the power supply voltage for normal operation as well as Idle
and Power-down modes.
VLCD
26
I
LCD power supply: LCD supply voltage.
[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
10 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
7. Functional description
Remark: Please refer to the P89LPC9401 User manual for a more detailed functional
description.
7.1 Special function registers
Remark: Special Function Registers (SFRs) accesses are restricted in the following
ways:
• User must not attempt to access any SFR locations not defined.
• Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
• SFR bits labeled ‘-’, logic 0 or logic 1 can only be written and read as follows:
– ‘-’ Unless otherwise specified, must be written with logic 0, but can return any
value when read (even if it was written with logic 0). It is a reserved bit and may be
used in future derivatives.
– Logic 0 must be written with logic 0, and will return a logic 0 when read.
– Logic 1 must be written with logic 1, and will return a logic 1 when read.
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
11 of 59
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Table 4:
Special function registers
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
Reset value
addr.
MSB
LSB
E0
Hex
Binary
Bit address
E7
E6
E5
E4
E3
E2
E1
ACC*
Accumulator
E0H
00
00
0000 0000
0000 00x0
AUXR1
Auxiliary function register
A2H
CLKLP
EBRR
ENT1
ENT0
SRST
0
-
DPS
Bit address
F7
F6
F5
F4
F3
F2
F1
F0
B*
B register
F0H
00
00
00
0000 0000
0000 0000
0000 0000
BRGR0[1] Baud rate generator rate low BEH
BRGR1[1] Baud rate generator rate
high
BFH
BRGCON Baud rate generator control BDH
-
-
-
-
-
-
-
-
SBRGS BRGEN 00[1]
xxxx xx00
xx00 0000
CMP1
CMP2
DIVM
Comparator 1 control
register
ACH
ADH
95H
CE1
CP1
CN1
OE1
CO1
CMF1 00[2]
CMF2 00[2]
00
Comparator 2 control
register
-
-
CE2
CP2
CN2
OE2
CO2
xx00 0000
0000 0000
CPU clock divide-by-M
control
DPTR
DPH
DPL
Data pointer (2 bytes)
Data pointer high
Data pointer low
83H
82H
00
00
00
00
0000 0000
0000 0000
0000 0000
0000 0000
0111 0000
FMADRH Program flash address high E7H
FMADRL Program flash address low
E6H
E4H
FMCON
Program flash control
(Read)
BUSY
-
-
-
HVA
HVE
SV
OI
70
Program flash control
(Write)
E4H FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. FMCMD.
7
6
5
4
3
2
1
0
FMDATA
I2ADR
Program flash data
I2C-bus slave address
register
E5H
DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0
00
00
0000 0000
0000 0000
GC
Bit address
D8H
DF
DE
DD
DC
DB
DA
D9
D8
I2CON*
I2DAT
I2C-bus control register
I2C-bus data register
-
I2EN
STA
STO
SI
AA
-
CRSEL 00
x000 00x0
DAH
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Special function registers …continued
Table 4:
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
Reset value
addr.
MSB
LSB
Hex
Binary
I2SCLH
I2SCLL
I2STAT
Serial clock generator/SCL
duty cycle register high
DDH
DCH
00
0000 0000
0000 0000
1111 1000
Serial clock generator/SCL
duty cycle register low
I2C-bus status register
00
F8
D9H
STA.4
STA.3
AE
STA.2
AD
STA.1
AC
STA.0
AB
0
AA
0
0
Bit address
A8H
AF
EA
EF
-
A9
A8
IEN0*
IEN1*
Interrupt enable 0
Interrupt enable 1
EWDRT
EE
EBO
ED
ES/ESR
EC
ET1
EB
EX1
EA
ET0
E9
EX0
E8
00
0000 0000
00x0 0000
Bit address
E8H
EST
-
-
ESPI
BB
EC
EKBI
B9
EI2C
B8
00 [2]
Bit address
B8H
BF
-
BE
BD
BC
BA
IP0*
Interrupt priority 0
PWDRT
PBO
PBOH
PS/PSR
PT1
PT1H
PX1
PX1H
PT0
PT0H
PX0
PX0H
00[2]
00[2]
x000 0000
x000 0000
IP0H
Interrupt priority 0 high
B7H
-
PWDRT
H
PSH/
PSRH
Bit address
F8H
FF
FE
PST
PSTH
-
FD
FC
FB
PSPI
PSPIH
-
FA
PC
PCH
-
F9
F8
IP1*
Interrupt priority 1
-
-
-
-
-
-
-
-
-
PKBI
PKBIH
PI2C
PI2CH 00[2]
00[2]
00x0 0000
00x0 0000
xxxx xx00
IP1H
Interrupt priority 1 high
Keypad control register
F7H
KBCON
94H
PATN
_SEL
KBIF
00[2]
KBMASK Keypad interrupt mask
register
86H
00
0000 0000
1111 1111
[2]
KBPATN
Keypad pattern register
93H
Bit address
80H
FF
87
86
85
84
83
82
81
80
P0*
Port 0
T1/KB7
CMP1 CMPREF CIN1A
CIN1B
/KB3
CIN2A
/KB2
CIN2B
/KB1
CMP2
/KB0
/KB6
96
-
/KB5
/KB4
Bit address
97
95
94
93
92
91
90
[2]
P1*
Port 1
90H
-
RST
INT1
INT0/
SDA
T0/SCL
RXD
TXD
Bit address
A0H
97
-
96
-
95
SPICLK
B5
94
SS
B4
-
93
MISO
B3
92
MOSI
B2
91
-
90
-
[2]
[2]
P2*
P3*
Port 2
Port 3
Bit address
B0H
B7
-
B6
-
B1
B0
-
-
-
XTAL1
XTAL2
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Special function registers …continued
Table 4:
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
Reset value
Hex Binary
addr.
MSB
LSB
P0M1
P0M2
P1M1
P1M2
P2M1
P2M2
P3M1
P3M2
PCON
PCONA
Port 0 output mode 1
Port 0 output mode 2
Port 1 output mode 1
Port 1 output mode 2
Port 2 output mode 1
Port 2 output mode 2
Port 3 output mode 1
Port 3 output mode 2
Power control register
Power control register A
84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF[2]
85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00[2]
1111 1111
0000 0000
11x1 xx11
00x0 xx00
1111 1111
0000 0000
xxxx xx11
xxxx xx00
0000 0000
0000 0000
91H (P1M1.7) (P1M1.6)
92H (P1M2.7) (P1M2.6)
-
-
(P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3 [2]
(P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00 [2]
A4H (P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF [2]
A5H (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00 [2]
B1H
B2H
-
-
-
-
-
-
-
-
-
-
-
(P3M1.1) (P3M1.0) 03[2]
(P3M2.1) (P3M2.0) 00[2]
PMOD1 PMOD0 00
-
87H SMOD1 SMOD0
BOPD
VCPD
D5
BOI
-
GF1
I2PD
D3
GF0
SPPD
D2
B5H RTCPD
-
SPD
D1
-
D0
P
00[2]
Bit address
D7
D6
D4
RS1
PSW*
Program status word
D0H
F6H
DFH
D1H
CY
AC
F0
RS0
OV
F1
00
00
0000 0000
PT0AD
Port 0 digital input disable
-
-
-
PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1
-
xx00 000x
[3]
RSTSRC Reset source register
RTCCON Real-time clock control
-
BOF
POF
-
R_BK
-
R_WD
-
R_SF
ERTC
R_EX
RTCF
RTCS1
RTCS0
RTCEN 60 [2] [4] 011x xx00
RTCH
RTCL
Real-time clock register high D2H
Real-time clock register low D3H
Serial port address register A9H
00[4]
00[4]
00
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
SADDR
SADEN
SBUF
Serial port address enable
B9H
99H
00
Serial Port data buffer
register
xx
Bit address
9F
9E
9D
9C
9B
TB8
FE
9A
RB8
BR
99
TI
98
SCON*
SSTAT
Serial port control
98H SM0/FE
BAH DBMOD
SM1
SM2
CIDIS
REN
RI
00
0000 0000
0000 0000
Serial port extended status
register
INTLO
DBISEL
OE
STINT 00
SP
Stack pointer
81H
07
0000 0111
0000 0100
00xx xxxx
0000 0000
SPCTL
SPSTAT
SPDAT
SPI control register
SPI status register
SPI data register
E2H
E1H
E3H
SSIG
SPIF
SPEN
DORD
-
MSTR
-
CPOL
-
CPHA
-
SPR1
-
SPR0
-
04
00
00
WCOL
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Special function registers …continued
Table 4:
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
Reset value
addr.
MSB
LSB
Hex
Binary
TAMOD
Timer 0 and 1 auxiliary
mode
8FH
-
-
-
T1M2
-
-
-
T0M2
00
xxx0 xxx0
Bit address
88H
8F
8E
8D
8C
8B
8A
89
88
TCON*
TH0
Timer 0 and 1 control
Timer 0 high
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00
00
00
00
00
00
00
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
8CH
TH1
Timer 1 high
8DH
TL0
Timer 0 low
8AH
TL1
Timer 1 low
8BH
TL2
CCU timer low
Timer 0 and 1 mode
CCH
TMOD
TRIM
89H T1GATE
T1C/T
T1M1
T1M0
T0GATE
TRIM.3
T0C/T
T0M1
T0M0
0000 0000
[5] [4]
Internal oscillator trim
register
96H
-
ENCLK
TRIM.5
TRIM.4
TRIM.2
TRIM.1
TRIM.0
[6] [4]
WDCON
WDL
Watchdog control register
Watchdog load
A7H
C1H
C2H
C3H
PRE2
PRE1
PRE0
-
-
WDRUN WDTOF WDCLK
FF
1111 1111
WFEED1 Watchdog feed 1
WFEED2 Watchdog feed 2
[1] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[2] All ports are in input only (high-impedance) state after power-up.
[3] The RSTSRC register reflects the cause of the P89LPC9401 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is
xx11 0000.
[4] The only reset source that affects these SFRs is power-on reset.
[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
7.2 Enhanced CPU
The P89LPC9401 uses an enhanced 80C51 CPU which runs at six times the speed of
standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most
instructions execute in one or two machine cycles.
7.3 Clocks
7.3.1 Clock definitions
The P89LPC9401 device has several internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock
sources (see Figure 6) and can also be optionally divided to a slower frequency (see
Section 7.8 “CCLK modification: DIVM register”).
Note: fosc is defined as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine
cycle, and most instructions are executed in one to two machine cycles (two or four CCLK
cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK⁄2.
7.3.2 CPU clock (OSCCLK)
The P89LPC9401 provides several user-selectable oscillator options in generating the
CPU clock. This allows optimization for a range of needs from high precision to lowest
possible cost. These options are configured when the flash is programmed and include an
on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external
crystal, or an external clock source. The crystal oscillator can be optimized for low,
medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.
7.3.3 Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.
7.3.4 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.
7.3.5 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this configuration. When using an oscillator frequency
above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit
is required to hold the device in reset at power-up until VDD has reached its
specified level. When system power is removed VDD will fall below the minimum
specified operating voltage. When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specified operating range.
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
7.3.6 Clock output
The P89LPC9401 supports a user-selectable clock output function on the
XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if
another clock source has been selected (on-chip RC oscillator, watchdog oscillator,
external clock input on X1) and if the RTC is not using the crystal oscillator as its clock
source. This allows external devices to synchronize to the P89LPC9401. This output is
enabled by the ENCLK bit in the TRIM register.
The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed
in Idle mode, it may be turned off prior to entering idle, saving additional power.
7.4 On-chip RC oscillator option
The P89LPC9401 has a 6-bit TRIM register that can be used to tune the frequency of the
RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value
to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature. End-user
applications can write to the TRIM register to adjust the on-chip RC oscillator to other
frequencies.
7.5 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator
can be used to save power when a high clock frequency is not needed.
7.6 External clock input option
In this configuration, the processor clock is derived from an external source driving the
XTAL1/P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2/P3.0 pin may be
used as a standard port pin or a clock output. When using an oscillator frequency
above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit
is required to hold the device in reset at power-up until VDD has reached its
specified level. When system power is removed VDD will fall below the minimum
specified operating voltage. When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit may be required to hold the
device in reset when VDD falls below the minimum specified operating voltage.
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P89LPC9401
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
HIGH FREQUENCY
MEDIUM FREQUENCY
LOW FREQUENCY
XTAL1
XTAL2
RTC
OSCCLK
CCLK
DIVM
CPU
WDT
RCCLK
RC
OSCILLATOR
÷2
PCLK
(7.3728 MHz ± 1 %)
WATCHDOG
OSCILLATOR
PCLK
(400 kHz +30 % −20 %)
TIMER 0 AND
TIMER 1
2
I C-BUS
SPI
UART
002aab463
Fig 6. Block diagram of oscillator control - P89LPC931
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
7.7 CPU Clock (CCLK) wake-up delay
The P89LPC9401 has an internal wake-up timer that delays the clock until it stabilizes
depending on the clock source used. If the clock source is any of the three crystal
selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus
60 µs to 100 µs. If the clock source is either the internal RC oscillator, watchdog oscillator,
or external clock, the delay is 224 OSCCLK cycles plus 60 µs to 100 µs.
7.8 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
7.9 Low power select
The P89LPC9401 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is
8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power
consumption further. On any reset, CLKLP is logic 0 allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
7.10 Memory organization
The various P89LPC9401 memory spaces are as follows:
• DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area.
• IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area. This area includes the DATA area and the 128 bytes
immediately above it.
• SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing.
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
• CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC9401 has 8 kB of on-chip Code memory.
7.11 Data RAM arrangement
The 768 bytes of on-chip RAM are organized as shown in Table 5.
Table 5:
Type
On-chip data memory usages
Data RAM
Size (bytes)
128
DATA
Memory that can be addressed directly and indirectly
Memory that can be addressed indirectly
IDATA
256
7.12 Interrupts
The P89LPC9401 uses a four priority level interrupt structure. This allows great flexibility
in controlling the handling of the many interrupt sources. The P89LPC9401 supports
13 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port TX, serial port
RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I2C-bus, keyboard,
comparators 1 and 2, and SPI.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global
disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt, but
not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. If two requests of different priority
levels are pending at the start of an instruction, the request of higher priority level is
serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking. Note that the arbitration ranking is only used to resolve pending requests of the
same priority level.
7.12.1 External interrupt inputs
The P89LPC9401 has two external interrupt inputs as well as the Keypad Interrupt
function. The two interrupt inputs are identical to those present on the standard 80C51
microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered by
setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC9401 is put into Power-down or Idle
mode, the interrupt will cause the processor to wake-up and resume operation. Refer to
Section 7.15 “Power reduction modes” for details.
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P89LPC9401
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
IE0
EX0
IE1
EX1
BOF
EBO
wake-up
(if in power-down)
RTCF
KBIF
EKBI
ERTC
(RTCCON.1)
WDOVF
EWDRT
CMF2
CMF1
EC
EA (IE0.7)
TF0
ET0
TF1
ET1
TI and RI/RI
ES/ESR
TI
EST
interrupt
to CPU
SI
EI2C
SPIF
ESPI
002aab464
Fig 7. Interrupt sources, interrupt enables, and power-down wake-up sources
7.13 I/O ports
The P89LPC9401 has four I/O ports: Port 0 and Port 1 are 8-bit ports. Port 2 is a 5-bit
port. Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the clock
and reset options chosen, as shown in Table 6.
Table 6:
Number of I/O pins available
Clock source
Reset option
Number of I/O pins
(not including LCD
pins)
On-chip oscillator or watchdog oscillator
External clock input
No external reset (except during power-up)
External RST pin supported
23
22
22
21
21
20
No external reset (except during power-up)
External RST pin supported[1]
Low/medium/high speed oscillator
(external crystal or resonator)
No external reset (except during power-up)
External RST pin supported[1]
[1] Required for operation above 12 MHz.
7.13.1 Port configurations
All but three I/O port pins on the P89LPC9401 may be configured by software to one of
four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port
outputs), push-pull, open drain, and input-only. Two configuration registers for each port
select the output type for each port pin.
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
1. P1.5 (RST) can only be an input and cannot be configured.
2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or
open-drain.
7.13.1.1 Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the need
to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open-drain output except that there are three pull-up transistors in
the quasi-bidirectional output that serve different purposes.
The P89LPC9401 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional
mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to VDD
,
causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is
discouraged.
A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
7.13.1.2 Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resistor
tied to VDD
.
An open-drain port pin has a Schmitt trigger input that also has a glitch suppression
circuit.
7.13.1.3 Input-only configuration
The input-only port configuration has no output drivers. It is a Schmitt trigger input that
also has a glitch suppression circuit.
7.13.1.4 Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous strong
pull-up when the port latch contains a logic 1. The push-pull mode may be used when
more source current is needed from a port output. A push-pull port pin has a Schmitt
trigger input that also has a glitch suppression circuit.
7.13.2 Port 0 analog functions
The P89LPC9401 incorporates two analog comparators. In order to give the best analog
function performance and to minimize power consumption, pins that are being used for
analog functions must have the digital outputs and digital inputs disabled.
Digital outputs are disabled by putting the port output into the Input-Only
(high-impedance) mode.
Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5.
On any reset, PT0AD[1:5] defaults to logic 0s to enable digital functions.
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
7.13.3 Additional port features
After power-up, all pins are in Input-Only mode. Please note that this is different from
the LPC76x series of devices.
• After power-up, all I/O pins except P1.5, may be configured by software.
• Pin P1.5 is input only. Pins P1.2 and P1.3 and are configurable for either input-only or
open-drain.
Every output on the P89LPC9401 has been designed to sink typical LED drive current.
However, there is a maximum total output current for all ports which must not be
exceeded. Please refer to Table 11 “Static electrical characteristics” for detailed
specifications.
All ports pins that can function as an output have slew rate controlled outputs to limit noise
generated by quickly switching output signals. The slew rate is factory-set to
approximately 10 ns rise and fall times.
7.14 Power monitoring functions
The P89LPC9401 incorporates power monitoring functions designed to prevent incorrect
operation during initial power-up and power loss or reduction during operation. This is
accomplished with two hardware functions: Power-on detect and Brownout detect.
7.14.1 Brownout detection
The Brownout detect function determines if the power supply voltage drops below a
certain level. The default operation is for a Brownout detection to cause a processor reset,
however it may alternatively be configured to generate an interrupt.
Brownout detection may be enabled or disabled in software.
If Brownout detection is enabled the brownout condition occurs when VDD falls below the
brownout trip voltage, Vbo (see Table 11 “Static electrical characteristics”), and is negated
when VDD rises above Vbo. If the P89LPC9401 device is to operate with a power supply
that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device
can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from
operating.
For correct activation of Brownout detect, the VDD rise and fall times must be observed.
Please see Table 11 “Static electrical characteristics” for specifications.
7.14.2 Power-on detection
The Power-on detect has a function similar to the Brownout detect, but is designed to work
as power comes up initially, before the power supply voltage reaches a level where
Brownout detect can work. The POF flag in the RSTSRC register is set to indicate an
initial power-up condition. The POF flag will remain set until cleared by software.
7.15 Power reduction modes
The P89LPC9401 supports three different power reduction modes. These modes are Idle
mode, Power-down mode, and total Power-down mode.
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7.15.1 Idle mode
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle
mode.
7.15.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption. The
P89LPC9401 exits Power-down mode via any reset, or certain interrupts. In Power-down
mode, the power supply voltage may be reduced to the data retention voltage VDDR. This
retains the RAM contents at the point where Power-down mode was entered. SFR
contents are not guaranteed after VDD has been lowered to VDDR, therefore it is highly
recommended to wake-up the processor via reset in this case. VDD must be raised to
within the operating range before the Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during power-down. These include: Brownout detect,
watchdog timer, Comparators (note that Comparators can be powered-down separately),
and RTC/System Timer. The internal RC oscillator is disabled unless both the RC
oscillator has been selected as the system clock and the RTC is enabled.
7.15.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry and
the voltage comparators are also disabled to conserve additional power. The internal RC
oscillator is disabled unless both the RC oscillator has been selected as the system clock
and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during
power-down, there will be high power consumption. Please use an external low frequency
clock to achieve low power with the RTC running during power-down.
7.16 Reset
The P1.5/RST pin can function as either an active-LOW reset input or as a digital input,
P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to logic 1, enables the external
reset input function on P1.5. When cleared, P1.5 may be used as an input pin.
Remark: During a power-up sequence, The RPE selection is overridden and this pin will
always functions as a reset input. An external circuit connected to this pin should not
hold this pin LOW during a power-on sequence as this will keep the device in reset.
After power-up this input will function either as an external reset input or as a digital input
as defined by the RPE bit. Only a power-up reset will temporarily override the selection
defined by RPE bit. Other sources of reset will not override the RPE bit.
Reset can be triggered from the following sources:
• External reset pin (during power-up or if user configured via UCFG1).
• Power-on detect.
• Brownout detect.
• Watchdog timer.
• Software reset.
• UART break character detect reset.
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For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read
this register to determine the most recent reset source. These flag bits can be cleared in
software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:
• During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
• For any other reset, previously set flag bits that have not been cleared will remain set.
7.16.1 Reset vector
Following reset, the P89LPC9401 will fetch instructions from either address 0000H or the
Boot address. The Boot address is formed by using the Boot Vector as the high byte of the
address and the low byte of the address = 00H.
The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see
P89LPC9401 User manual). Otherwise, instructions will be fetched from address 0000H.
7.17 Timers/counters 0 and 1
The P89LPC9401 has two general purpose counter/timers which are upward compatible
with the standard 80C51 Timer 0 and Timer 1. Both can be configured to operate either as
timers or event counter. An option to automatically toggle the T0 and/or T1 pins upon timer
overflow has been added.
In the ‘Timer’ function, the register is incremented every machine cycle.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once during every machine cycle.
Timer 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1, 2
and 6 are the same for both Timers/Counters. Mode 3 is different.
7.17.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a
13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
7.17.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
7.17.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2
operation is the same for Timer 0 and Timer 1.
7.17.4 Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is
in Mode 3 it can still be used by the serial port as a baud rate generator.
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7.17.5 Mode 6
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.
7.17.6 Timer overflow toggle output
Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer
overflow occurs. The same device pins that are used for the T0 and T1 count inputs are
also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first
timer overflow when this mode is turned on.
7.18 RTC/system timer
The P89LPC9401 has a simple RTC that allows a user to continue running an accurate
timer while the rest of the device is powered-down. The RTC can be a wake-up or an
interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a
16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded
again and the RTCF flag will be set. The clock source for this counter can be either the
CCLK or the XTAL oscillator, provided that the XTAL oscillator is not being used as the
CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as
its clock source. Only power-on reset will reset the RTC and its associated SFRs to the
default state.
7.19 UART
The P89LPC9401 has an enhanced UART that is compatible with the conventional 80C51
UART except that Timer 2 overflow cannot be used as a baud rate source. The
P89LPC9401 does include an independent Baud Rate Generator. The baud rate can be
selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent
Baud Rate Generator. In addition to the baud rate generation, enhancements over the
standard 80C51 UART include Framing Error detection, automatic address recognition,
selectable double buffering and several interrupt options. The UART can be operated in
four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.
7.19.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at 1⁄16 of the CPU clock
frequency.
7.19.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),
8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored
in RB8 in Special Function Register SCON. The baud rate is variable and is determined
by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 7.19.5
“Baud rate generator and selection”).
7.19.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data
bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is
transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.
Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop
bit is not saved. The baud rate is programmable to either 1⁄16 or 1⁄32 of the CPU clock
frequency, as determined by the SMOD1 bit in PCON.
7.19.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is
the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable
and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in
Section 7.19.5 “Baud rate generator and selection”).
7.19.5 Baud rate generator and selection
The P89LPC9401 enhanced UART has an independent Baud Rate Generator. The baud
rate is determined by a baud rate preprogrammed into the BRGR1 and BRGR0 SFRs
which together form a 16-bit baud rate divisor value that works in a similar manner as
Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be
used for other timing functions.
The UART can use either Timer 1 or the baud rate generator output (see Figure 8). Note
that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses OSCCLK.
timer 1 overflow
SMOD1 = 1
(PCLK-based)
SBRGS = 0
SBRGS = 1
÷2
baud rate modes 1 and 3
002aaa897
SMOD1 = 0
baud rate generator
(CCLK-based)
Fig 8. Baud rate sources for UART (Modes 1, 3)
7.19.6 Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)
is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is
logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up
when SMOD0 is logic 0.
7.19.7 Break detect
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the device
and force the device into ISP mode.
7.19.8 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be
written to SBUF while the first character is being transmitted. Double buffering allows
transmission of a string of characters with only one stop bit between any two characters,
as long as the next character is written between the start bit and the stop bit of the
previous character.
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Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SnBUF while the previous data is being shifted out. Double buffering is only allowed in
Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled
(DBMOD = 0).
7.19.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the TX interrupt is generated
when the double buffer is ready to receive new data.
7.19.10 The 9th bit (bit 8) in double buffering (modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the TX interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will
be double-buffered together with SBUF data.
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
7.20 I2C-bus serial interface
The I2C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
• Bidirectional data transfer between masters and slaves
• Multi master bus (no central master)
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
• The I2C-bus may be used for test and diagnostic purposes.
A typical I2C-bus configuration is shown in Figure 9. The P89LPC9401 device provides a
byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.
R
P
R
P
SDA
SCL
2
I C-bus
OTHER DEVICE
WITH I C-BUS
INTERFACE
OTHER DEVICE
WITH I C-BUS
INTERFACE
P1.3/SDA
P1.2/SCL
2
2
P89LPC9401
002aab465
Fig 9. I2C-bus configuration
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
8
I2ADR
ADDRESS REGISTER
COMPARATOR
P1.3
INPUT
FILTER
P1.3/SDA
SHIFT REGISTER
8
ACK
I2DAT
OUTPUT
STAGE
BIT COUNTER /
ARBITRATION &
SYNC LOGIC
CCLK
INPUT
FILTER
TIMING
AND
CONTROL
LOGIC
P1.2/SCL
SERIAL CLOCK
GENERATOR
OUTPUT
STAGE
interrupt
timer 1
overflow
I2CON
I2SCLH
I2SCLL
P1.2
CONTROL REGISTERS &
SCL DUTY CYCLE REGISTERS
8
STATUS
DECODER
status bus
I2STAT
STATUS REGISTER
8
002aaa899
Fig 10. I2C-bus serial interface block diagram - P89LPC931
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7.21 SPI
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
The P89LPC9401 provides another high-speed serial communication interface—the SPI
interface. SPI is a full-duplex, high-speed, synchronous communication bus with two
operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in
Master mode or up to 3 Mbit/s in Slave mode. It has a transfer completion flag and write
collision flag protection.
S
M
CPU clock
MISO
P2.3
M
S
8-BIT SHIFT REGISTER
READ DATA BUFFER
PIN
MOSI
P2.2
DIVIDER
BY 4, 16, 64, 128
CONTROL
LOGIC
SPICLK
P2.5
clock
SPI clock (master)
S
M
SELECT
CLOCK LOGIC
MSTR
SPEN
SPI CONTROL
SPI CONTROL REGISTER
SPI STATUS REGISTER
SPI
interrupt
request
internal
data
bus
002aab466
Fig 11. SPI block diagram
The SPI interface has three pins: SPICLK, MOSI, MISO and SS:
• SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows
from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output
in the master mode and is input in the slave mode. If the SPI system is disabled, i.e.,
SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
Typical connections are shown in Figure 12 through Figure 14.
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
7.21.1 Typical SPI configurations
master
slave
MISO
MOSI
MISO
MOSI
8-BIT SHIFT
REGISTER
8-BIT SHIFT
REGISTER
SPICLK
SPICLK
SPI CLOCK
GENERATOR
SS/PORT
SS/PORT
002aab467
Fig 12. SPI single master single slave configuration
master
slave
MISO
MISO
MOSI
8-BIT SHIFT
REGISTER
8-BIT SHIFT
REGISTER
MOSI
SPICLK
SPICLK
SPI CLOCK
GENERATOR
SPI CLOCK
GENERATOR
SS/PORT
SS/PORT
002aab468
Fig 13. SPI dual device configuration, where either can be a master or a slave
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
master
slave
MISO
MOSI
MISO
MOSI
8-BIT SHIFT
REGISTER
8-BIT SHIFT
REGISTER
SPICLK
port
SPICLK
SS
SPI CLOCK
GENERATOR
slave
MISO
MOSI
8-BIT SHIFT
REGISTER
SPICLK
SS
port
002aaa903
Fig 14. SPI single master multiple slaves configuration
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7.22 Analog comparators
Two analog comparators are provided on the P89LPC9401. Input and output options allow
use of the comparators in a number of different configurations. Comparator operation is
such that the output is a logic 1 (which may be read in a register and/or routed to a pin)
when the positive input (one of two selectable pins) is greater than the negative input
(selectable from a pin or an internal reference voltage). Otherwise the output is a zero.
Each comparator may be configured to cause an interrupt when the output value changes.
The overall connections to both comparators are shown in Figure 15. The comparators
function to VDD = 2.4 V.
When each comparator is first enabled, the comparator output and interrupt flag are not
guaranteed to be stable for 10 µs. The corresponding comparator interrupt should not be
enabled during that time, and the comparator interrupt flag must be cleared before the
interrupt is enabled in order to prevent an immediate interrupt service.
CP1
OE1
comparator 1
CO1
(P0.4) CIN1A
(P0.3) CIN1B
CMP1 (P0.6)
(P0.5) CMPREF
change detect
V
ref(bg)
CMF1
CMF2
CN1
CP2
interrupt
change detect
EC
comparator 2
(P0.2) CIN2A
(P0.1) CIN2B
CMP2 (P0.0)
CO2
OE2
002aaa904
CN2
Fig 15. Comparator input and output connections
7.22.1 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to as
Vref(bg), is 1.23 V ± 10 %.
7.22.2 Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag is
set whenever the comparator output changes state. The flag may be polled by software or
may be used to generate an interrupt. The two comparators use one common interrupt
vector. If both comparators enable interrupts, after entering the interrupt service routine,
the user needs to read the flags to determine which comparator caused the interrupt.
7.22.3 Comparators and power reduction modes
Either or both comparators may remain enabled when Power-down or Idle mode is
activated, but both comparators are disabled automatically in Total Power-down mode.
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If a comparator interrupt is enabled (except in Total Power-down mode), a change of the
comparator output state will generate an interrupt and wake-up the processor. If the
comparator output to a pin is enabled, the pin should be configured in the push-pull mode
in order to obtain fast switching times while in Power-down mode. The reason is that with
the oscillator stopped, the temporary strong pull-up that normally occurs during switching
on a quasi-bidirectional port pin does not take place.
Comparators consume power in Power-down and Idle modes, as well as in the normal
operating mode. This fact should be taken into account when system power consumption
is an issue. To minimize power consumption, the user can disable the comparators via
PCONA.5, or put the device in Total Power-down mode.
7.23 Keypad interrupt
The Keypad Interrupt (KBI) function is intended primarily to allow a single interrupt to be
generated when Port 0 is equal to or not equal to a certain pattern. This function can be
used for bus address recognition or keypad recognition. The user can configure the port
via SFRs for different tasks.
The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins
connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is
used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag
(KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is
matched while the Keypad Interrupt function is active. An interrupt will be generated if
enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to
define equal or not-equal for the comparison.
In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series,
the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key
connected to Port 0 which is enabled by the KBMASK register will cause the hardware to
set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to
wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in
handheld, battery-powered systems that need to carefully manage power consumption
yet also need to be convenient to use.
In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer
than six CCLKs.
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7.24 Watchdog timer
The watchdog timer causes a system reset when it underflows as a result of a failure to
feed the timer prior to the timer reaching its terminal count. It consists of a programmable
12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap
taken from the prescaler. The clock source for the prescaler is either the PCLK or the
nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a
power-on reset. When the watchdog feature is disabled, it can be used as an interval timer
and may generate an interrupt. Figure 16 shows the watchdog timer in Watchdog mode.
Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog
clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a
time-out period that ranges from a few µs to a few seconds. Please refer to the
P89LPC9401 User manual for more details.
WDL (C1H)
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
watchdog
oscillator
8-BIT DOWN
COUNTER
(1)
PRESCALER
reset
÷32
PCLK
SHADOW REGISTER
PRE2
PRE1
PRE0
-
-
WDRUN WDTOF WDCLK
WDCON (A7H)
002aaa905
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a
feed sequence.
Fig 16. Watchdog timer in Watchdog mode (WDTE = 1)
7.25 Additional features
7.25.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog reset had occurred. Care should be taken when writing
to AUXR1 to avoid accidental software resets.
7.25.2 Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address
used with certain instructions. The DPS bit in the AUXR1 register selects one of the two
Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may
be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
7.26 LCD driver
7.26.1 General description
The LCD segment driver in the P89LPC9401 can interface to most LCDs using low
multiplex rates. It generates the drive signals for static or multiplexed LCDs containing up
to four backplanes and up to 32 segments. The LCD controller communicates to a host
using the I2C-bus. The I2C-bus clock and data signals for both the microcontroller and the
LCD driver are available on the P89LPC9401 providing system flexibility. Communication
overhead to manage the display is minimized by an on-chip display RAM with
auto-increment addressing, hardware subaddressing, and display memory switching
(static and duplex drive modes).
7.26.2 Functional description
The LCD controller is a versatile peripheral device designed to interface microcontrollers
to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up
to four backplanes and up to 32 segments. The display configurations possible with the
LCD controller depend on the number of active backplane outputs required. A selection of
display configurations is shown in Table 7. All of these configurations can be implemented
in a typical system.
The microcontroller communicates to the LCD controller using the I2C-bus.The
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are to the power supplies
(VDD, VSS and VLCD) and the LCD panel chosen for the application.
Table 7:
Selection of display configurations
7-segments numeric
Number of
Backplanes
14- segments alphanumeric
Dot matrix
Segments
Digits
Indicator
Characters
Indicator
symbols
symbols
4
3
2
1
128
96
16
12
8
16
12
8
8
6
4
2
16
12
8
128
96
64
64
32
4
4
4
32
7.26.3 LCD bias voltages
LCD biasing voltages are obtained from an internal voltage divider consisting of three
series resistors connected between VLCD and VSS. The LCD voltage can be temperature
compensated externally via the supply to pin VLCD. A voltage selector drives the
multiplexing of the LCD based on programmable configurations.
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7.26.4 Oscillator
7.26.4.1 Internal clock
An internal oscillator provides the clock signals for the internal logic of the LCD controller
and its LCD drive signals. After power-up, pin SDA must be HIGH to guarantee that the
clock starts.
7.26.5 Timing
The LCD controller timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. The timing
also generates the LCD frame signal whose frequency is derived from the clock
frequency. The frame signal frequency is a fixed division of the clock frequency from either
the internal or an external clock.
Frame frequency = fosc(LCD) / 24.
7.26.6 Display register
A display latch holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display latch, the
LCD segment outputs, and each column of the display RAM.
7.26.7 Segment outputs
The LCD drive section includes 32 segment outputs S0 to S31. The segment output
signals are generated according to the multiplexed backplane signals and the display
latch data. When less than 32 segment outputs are required, the unused segment outputs
should be left open-circuit.
7.26.8 Backplane outputs
The LCD drive section has four backplane outputs BP0 to BP3. The backplane output
signals are generated in based on the selected LCD drive mode. If less than four
backplane outputs are required, the unused outputs can be left open-circuit. In the 1:3
multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent
outputs can be tied together to give enhanced drive capabilities. In the 1:2 multiplex drive
mode, BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be
paired to increase the drive capabilities. In the static drive mode the same signal is carried
by all four backplane outputs and they can be connected in parallel for very high drive
requirements.
7.26.9 Display RAM
The display RAM is a static 32 × 4-bit RAM which stores LCD data. There is a one-to-one
correspondence between the RAM addresses and the segment outputs, and between the
individual bits of a RAM word and the backplane outputs. The first RAM column
corresponds to the 32 segments for backplane 0 (BP0). In multiplexed LCD applications
the segment data of the second, third and fourth column of the display RAM are
time-multiplexed with BP1, BP2 and BP3 respectively.
7.26.10 Data pointer
The Display RAM is addressed using the data pointer. Either a single byte or a series of
display bytes may be loaded into any location of the display RAM.
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7.26.11 Output bank selector
The LCD controller includes a RAM bank switching feature in the static and 1:2 drive
modes. In the static drive mode, the BANK SELECT command may request the contents
of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 mode, the contents
of bits 2 and 3 may be selected instead of bits 0 and 1. This allows display information to
be prepared in an alternative bank and then selected for display when it is assembled.
7.26.12 Input bank selector
The input bank selector loads display data into the display RAM based on the selected
LCD drive configuration. The BANK SELECT command can be used to load display data
in bit 2 in static drive mode or in bits 2 and 3 in 1:2 mode. The input bank selector
functions are independent of the output bank selector.
7.26.13 Blinker
The LCD controller has a very versatile display blinking capability. The whole display can
blink at a frequency selected by the BLINK command. Each blink frequency is a multiple
integer value of the clock frequency; the ratio between the clock frequency and blink
frequency depends on the blink mode selected, as shown in Table 8.
An additional feature allows an arbitrary selection of LCD segments to be blinked in the
static and 1 : 2 drive modes. This is implemented without any communication overheads
by the output bank selector which alternates the displayed data between the data in the
display RAM bank and the data in an alternative RAM bank at the blink frequency. This
mode can also be implemented by the BLINK command.
The entire display can be blinked at a frequency other than the nominal blink frequency by
sequentially resetting and setting the display enable bit E at the required rate using the
MODE SET command.
Table 8:
Blink mode
Off
Blinking frequencies
Normal operating mode ratio Normal blink frequency
-
Blinking off
2 Hz
fosc(LCD) / 768
2 Hz
1 Hz
fosc(LCD) / 1536
fosc(LCD) / 3072
1 Hz
0.5 Hz
0.5 Hz
Blink modes 0.5 Hz, 1 Hz and 2 Hz, and nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz
correspond to an oscillator frequency (fosc(LCD)) of 1536 Hz at pin CLK. The oscillator
frequency range is 397 Hz to 3046 Hz.
7.26.13.1 I2C-bus controller
The LCD controller acts as an I2C-bus slave receiver. In the P89LPC9401 the hardware
subaddress inputs A0, A,1 and A2 are tied to VSS setting the hardware subaddress = 0.
7.26.14 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
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7.26.15 I2C-bus slave addresses
The I2C-bus slave address is 0111 0000. The LCD controller is a write-only device and will
not respond to a read access.
7.27 Flash program memory
7.27.1 General description
The P89LPC9401 flash memory provides in-circuit electrical erasure and programming.
The flash can be erased, read, and written as bytes. The Sector and Page Erase functions
can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase
the entire program memory. ICP using standard commercial programmers is available. In
addition, IAP and byte-erase allows code memory to be used for non-volatile data storage.
On-chip erase and write timing generation contribute to a user-friendly programming
interface. The P89LPC9401 flash reliably stores memory contents even after
100,000 erase and program cycles. The cell is designed to optimize the erase and
programming mechanisms. The P89LPC9401 uses VDD as the supply voltage to perform
the Program/Erase algorithms.
7.27.2 Features
• Programming and erase over the full operating voltage range.
• Byte erase allows code memory to be used for data storage.
• Read/Programming/Erase using ISP/IAP/ICP.
• Internal fixed boot ROM, containing low-level IAP routines available to user code.
• Default loader providing ISP via the serial port, located in upper end of user program
memory.
• Boot vector allows user-provided flash loader code to reside anywhere in the flash
memory space, providing flexibility to the user.
• Any flash program or erase operation in 2 ms.
• Programming with industry-standard commercial programmers.
• Programmable security for the code in the flash for each sector.
• 100,000 typical erase/program cycles for each byte.
• 10 year minimum data retention.
7.27.3 Flash organization
The program memory consists of eight 1 kB sectors on the P89LPC9401 device. Each
sector can be further divided into 64-byte pages. In addition to sector erase, page erase,
and byte erase, a 64-byte page register is included which allows from 1 byte to 64 bytes of
a given page to be programmed at the same time, substantially reducing overall
programming time.
7.27.4 Using flash as data storage
The flash code memory array of this device supports individual byte erasing and
programming. Any byte in the code memory array may be read using the MOVC
instruction, provided that the sector containing the byte has not been secured (a MOVC
instruction is not allowed to read code memory contents of a secured sector). Thus any
byte in a non-secured sector may be used for non-volatile data storage.
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7.27.5 Flash programming and erasing
Four different methods of erasing or programming of the flash are available. The flash may
be programmed or erased in the end-user application (IAP) under control of the
application’s firmware. Another option is to use the ICP mechanism. This ICP system
provides for programming through a serial clock - serial data interface. As shipped from
the factory, the upper 512 bytes of user code space contains a serial ISP routine allowing
for the device to be programmed in circuit through the serial port. The flash may also be
programmed or erased using a commercially available EPROM programmer which
supports this device. This device does not provide for direct verification of code memory
contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire
user code space.
7.27.6 In-circuit programming
ICP is performed without removing the microcontroller from the system. The ICP facility
consists of internal hardware resources to facilitate remote programming of the
P89LPC9401 through a two-wire serial interface. The Philips ICP facility has made ICP in
an embedded application—using commercially available programmers—possible with a
minimum of additional expense in components and circuit board area. The ICP function
uses five pins. Only a small connector needs to be available to interface your application
to a commercial programmer in order to use this feature. Additional details may be found
in the P89LPC9401 User manual.
7.27.7 In-application programming
IAP is performed in the application under the control of the microcontroller’s firmware. The
IAP facility consists of internal hardware resources to facilitate programming and erasing.
The Philips IAP has made IAP in an embedded application possible without additional
components. Two methods are available to accomplish IAP. A set of predefined IAP
functions are provided in a Boot ROM and can be called through a common interface,
PGM_MTP. Several IAP calls are available for use by an application program to permit
selective erasing and programming of flash sectors, pages, security bits, configuration
bytes, and device ID. These functions are selected by setting up the microcontroller’s
registers before making a call to PGM_MTP at FF03H. The Boot ROM occupies the
program memory space at the top of the address space from FF00 to FEFFH, thereby not
conflicting with the user program memory space.
In addition, IAP operations can be accomplished through the use of four SFRs consisting
of a control/status register, a data register, and two address registers. Additional details
may be found in the P89LPC9401 User manual.
7.27.8 In-system programming
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal firmware to
facilitate remote programming of the P89LPC9401 through the serial port. This firmware is
provided by Philips and embedded within each P89LPC9401 device. The Philips ISP
facility has made ISP in an embedded application possible with a minimum of additional
expense in components and circuit board area. The ISP function uses five pins (VDD, VSS
TXD, RXD, and RST). Only a small connector needs to be available to interface your
application to an external circuit in order to use this feature.
,
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7.27.9 Power-on reset code execution
The P89LPC9401 contains two special flash elements: the Boot Vector and the Boot
Status Bit. Following reset, the P89LPC9401 examines the contents of the Boot Status
Bit. If the Boot Status Bit is set to zero, power-up execution starts at location 0000H, which
is the normal start address of the user’s application code. When the Boot Status Bit is set
to a value other than zero, the contents of the Boot Vector are used as the high byte of the
execution address and the low byte is set to 00H.
Table 9 shows the factory default Boot Vector settings for these devices. Note: These
settings are different than the original P89LPC932. Tools designed to support the
P89LPC9401 should be used to program this device, such as Flash Magic version
1.98, or later. A factory-provided boot loader is preprogrammed into the address space
indicated and uses the indicated boot loader entry point to perform ISP functions. This
code can be erased by the user. Users who wish to use this loader should take
precautions to avoid erasing the 1 kB sector that contains this boot loader. Instead,
the page erase function can be used to erase the first eight 64-byte pages located in
this sector. A custom boot loader can be written with the Boot Vector set to the custom
boot loader, if desired.
Table 9:
Device
Default Boot Vector values and ISP entry points
Default
Default
Defaultboot loader 1 kB sector
Boot Vector
boot loader
entry point
code range
range
P89LPC9401
1FH
1F00H
1E00H to 1FFFH
1C00H to 1FFFH
7.27.10 Hardware activation of the boot loader
The boot loader can also be executed by forcing the device into ISP mode during a
power-on sequence (see the P89LPC9401 User manual for specific information). This has
the same effect as having a non-zero status byte. This allows an application to be built that
will normally execute user code but can be manually forced into ISP operation. If the
factory default setting for the Boot Vector (1FH) is changed, it will no longer point to the
factory preprogrammed ISP boot loader code. After programming the flash, the status
byte should be programmed to zero in order to allow execution of the user’s application
code beginning at address 0000H.
7.28 User configuration bytes
Some user-configurable features of the P89LPC9401 must be defined at power-up and
therefore cannot be set by the program after start of execution. These features are
configured through the use of the flash byte UCFG1. Please see the P89LPC9401 User
manual for additional details.
7.29 User sector security bytes
There are eight User Sector Security Bytes on the P89LPC9401 device. Each byte
corresponds to one sector. Please see the P89LPC9401 User manual for additional
details.
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
8. Limiting values
Table 10: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). [1]
Symbol
Tamb(bias)
Tstg
Parameter
Conditions
Min
Max
+125
+150
20
Unit
°C
bias ambient temperature
storage temperature
−55
−65
°C
IOH(I/O)
IOL(I/O)
HIGH-state output current per I/O pin
LOW-state output current per I/O pin
-
-
-
-
-
mA
mA
mA
V
20
II/O(tot)(max) maximum total I/O current
100
3.5
Vn
voltage on any other pin (except VSS
)
with respect to VDD
Ptot(pack)
package total power dissipation
based on package heat
transfer, not device power
consumption
1.5
W
[1] The following applies to Table 10:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
9. Static characteristics
Table 11: Static electrical characteristics
VDD = 2.4 V to 3.6 V unless otherwise specified.
T
amb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ [1]
11
Max
15
23
5
Unit
mA
mA
mA
mA
µA
[2]
[2]
[2]
[2]
[2]
IDD(oper)
IDD(idle)
IDD(pd)
operating supply current
VDD = 3.6 V; fosc = 12 MHz
VDD = 3.6 V; fosc = 18 MHz
VDD = 3.6 V; fosc = 12 MHz
VDD = 3.6 V; fosc = 18 MHz
-
-
-
-
-
17
Idle mode supply current
3.7
6
8
Power-down mode supply
current
VDD = 3.6 V; voltage
comparators powered
down
60
85
[3]
IDD(tpd)
total Power-down mode supply VDD = 3.6 V
current
-
9
25
µA
(dV/dt)r
(dV/dt)f
VDDR
Vth(HL)
VIL
rise rate
of VDD
of VDD
-
-
2
mV/µs
fall rate
-
-
50
mV/µs
data retention voltage
1.5
-
-
V
V
V
V
V
V
V
HIGH-LOW threshold voltage except SCL, SDA
LOW-state input voltage SCL, SDA only
LOW-HIGH threshold voltage except SCL, SDA
0.22VDD
0.4VDD
-
−0.5
-
0.3VDD
0.7VDD
5.5
Vth(LH)
VIH
-
0.6VDD
-
HIGH-state input voltage
hysteresis voltage
SCL, SDA only
port 1
0.7VDD
Vhys
-
-
0.2VDD
0.6
-
[4]
[4]
VOL
LOW-state output voltage
IOL = 20 mA;
1.0
VDD = 2.4 V to 3.6 V,
all ports, all modes except
high-Z
IOL = 3.2 mA; VDD = 2.4 V
-
0.2
0.3
-
V
V
to 3.6 V; all ports; all
modes except high-Z
VOH
HIGH-state output voltage
IOH = −20 µA;
V
V
DD − 0.3
V
DD − 0.2
VDD = 2.4 V to 3.6 V;
all ports;
quasi-bidirectional mode
IOH = −3.2 mA;
DD − 0.7
V
DD − 0.4
-
V
VDD = 2.4 V to 3.6 V;
all ports; push-pull mode
Vxtal
Vn
crystal voltage
with respect to VSS
−0.5
−0.5
-
-
+4.0
+5.5
V
V
voltage on any other pin
with respect to VSS
(except XTAL1, XTAL2, VDD
)
[5]
[6]
[7]
[8]
Ciss
IIL
input capacitance
-
-
-
-
-
15
pF
µA
µA
µA
LOW-state input current
input leakage current
VI = 0.4 V
-
−80
±10
−450
ILI
VI = VIL, VIH or Vth(HL)
VI = 1.5 V at VDD = 3.6 V
-
ITHL
HIGH-LOW transition current
(all ports)
−30
RRST_N(int) internal pull-up resistance on
pin RST_N
pin RST
10
-
30
kΩ
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
Table 11: Static electrical characteristics …continued
VDD = 2.4 V to 3.6 V unless otherwise specified.
T
amb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ [1]
Max
Unit
Vbo
brownout trip voltage
2.4 V < VDD < 3.6 V; with
BOV = 1, BOPD = 0
2.40
-
2.70
V
Vref(bg)
TCbg
band gap reference voltage
1.11
-
1.23
10
1.34
20
V
band gap temperature
coefficient
ppm/°
C
[1] Typical ratings are not guaranteed. The values listed are at room temperature, VDD = 3 V.
[2] The IDD(oper), IDD(idle), and IDD(pd) specifications are measured using an external clock with the following functions disabled: comparators,
real-time clock, and watchdog timer.
[3] The IDD(tpd) specification is measured using an external clock with the following functions disabled: comparators, real-time clock,
brownout detect, and watchdog timer.
[4] See Section 8 “Limiting values” on page 43 for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition,
VOL/VOH may exceed the related specification.
[5] Pin capacitance is characterized but not tested.
[6] Measured with port in quasi-bidirectional mode.
[7] Measured with port in high-impedance mode.
[8] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is
highest when VI is approximately 2 V.
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
10. Dynamic characteristics
Table 12: Dynamic characteristics (12 MHz)
VDD = 2.4 V to 3.6 V unless otherwise specified.
T
amb = −40 °C to +85 °C for industrial applications, unless otherwise specified. [1] [2]
Symbol
Parameter
Conditions
Variable clock
fosc = 12 MHz Unit
Min Max
7.189 7.557 MHz
Min
Max
7.557
520
fosc(RC)
fosc(WD)
internal RC oscillator frequency
7.189
320
internal watchdog oscillator
frequency
320
520 kHz
fosc
oscillator frequency
0
83
0
12
-
-
-
-
-
-
-
MHz
ns
Tcy(CLK)
fCLKLP
Glitch filter
tgr
clock cycle time
see Figure 18
P1.5/RST pin
active frequency on pin CLKLP
8
MHz
glitch rejection
-
-
50
15
-
-
50
15
ns
ns
any pin except
P1.5/RST
tsa
signal acceptance time
P1.5/RST pin
125
50
-
-
125
50
-
-
ns
ns
any pin except
P1.5/RST
External clock
tCHCX
tCLCX
tCLCH
tCHCL
clock HIGH time
see Figure 18
see Figure 18
see Figure 18
see Figure 18
33
33
-
T
cy(CLK) − tCLCX
33
33
-
-
-
ns
ns
ns
ns
clock LOW time
clock rise time
clock fall time
Tcy(CLK) − tCHCX
8
8
8
8
-
-
Shift register (UART mode 0)
TXLXL serial port clock cycle time
tQVXH
see Figure 17
see Figure 17
16Tcy(CLK)
13Tcy(CLK)
-
-
1333
1083
-
-
ns
ns
output data set-up to clock rising
edge time
tXHQX
tXHDX
tXHDV
output data hold after clock rising
edge time
see Figure 17
-
-
Tcy(CLK) + 20
-
-
103 ns
input data hold after clock rising edge see Figure 17
time
0
-
0
-
ns
ns
input data valid to clock rising edge
time
see Figure 17
150
150
SPI interface
fSPI
SPI operating frequency
CCLK
slave
0
-
⁄
0
-
2.0 MHz
3.0 MHz
6
CCLK
master
⁄
4
TSPICYC
SPI cycle time
see Figure 19,
20, 21, 22
6
slave
⁄
-
-
-
500
333
250
-
-
-
ns
ns
ns
CCLK
4
master
⁄
CCLK
tSPILEAD
tSPILAG
SPI enable lead time (slave)
see Figure 21,
22
250
SPI enable lag time (slave)
see Figure 21,
22
250
-
250
-
ns
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
Table 12: Dynamic characteristics (12 MHz) …continued
VDD = 2.4 V to 3.6 V unless otherwise specified.
T
amb = −40 °C to +85 °C for industrial applications, unless otherwise specified. [1] [2]
Symbol
Parameter
Conditions
Variable clock
fosc = 12 MHz Unit
Min
Max
Min
Max
tSPICLKH
SPICLK HIGH time
master
see Figure 19,
20, 21, 22
2
3
⁄
⁄
-
-
165
250
-
-
ns
ns
CCLK
CCLK
slave
tSPICLKL
SPICLK LOW time
master
see Figure 19,
20, 21, 22
2
3
⁄
⁄
-
-
-
165
250
100
-
-
-
ns
ns
ns
CCLK
CCLK
slave
tSPIDSU
tSPIDH
tSPIA
SPI data set-up time (master or
slave)
see Figure 19,
20, 21, 22
100
100
0
SPI data hold time (master or slave) see Figure 19,
20, 21, 22
-
100
-
ns
SPI access time (slave)
see Figure 21,
22
120
240
0
-
120 ns
240 ns
tSPIDIS
tSPIDV
SPI disable time (slave)
see Figure 21,
22
0
SPI enable to output data valid time see Figure 19,
20, 21, 22
slave
-
-
240
167
-
-
-
240 ns
167 ns
master
tSPIOH
tSPIR
SPI output data hold time
see Figure 19,
20, 21, 22
0
0
-
ns
SPI rise time
see Figure 19,
20, 21, 22
SPI outputs
-
-
100
-
-
100 ns
2000 ns
(SPICLK, MOSI, MISO)
SPI inputs
2000
(SPICLK, MOSI, MISO, SS)
tSPIF
SPI fall time
see Figure 19,
20, 21, 22
SPI outputs
-
-
100
-
-
100 ns
2000 ns
(SPICLK, MOSI, MISO)
SPI inputs
2000
(SPICLK, MOSI, MISO, SS)
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
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8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
Table 13: Dynamic characteristics (18 MHz)
VDD = 3.0 V to 3.6 V unless otherwise specified.
T
amb = −40 °C to +85 °C for industrial applications, unless otherwise specified. [1] [2]
Symbol
Parameter
Conditions
Variable clock
fosc = 18 MHz Unit
Min Max
7.189 7.557 MHz
Min
Max
7.557
520
18
fosc(RC)
fosc(WD)
fosc
internal RC oscillator frequency
internal watchdog oscillator frequency
oscillator frequency
7.189
320
0
320
520 kHz
-
-
-
-
-
-
MHz
ns
Tcy(CLK)
fCLKLP
Glitch filter
tgr
clock cycle time
see Figure 18
P1.5/RST pin
55
-
active frequency on pin CLKLP
0
8
MHz
glitch rejection time
signal acceptance
-
50
-
-
50
-
ns
ns
any pin except
P1.5/RST
125
125
tsa
P1.5/RST pin
-
15
-
-
15
-
ns
ns
any pin except
P1.5/RST
50
50
External clock
tCHCX
tCLCX
tCLCH
tCHCL
clock HIGH time
see Figure 18
see Figure 18
see Figure 18
see Figure 18
22
22
-
T
cy(CLK) − tCLCX
22
22
-
-
-
ns
ns
ns
ns
clock LOW time
clock rise time
clock fall time
T
cy(CLK) − tCHCX
5
5
5
5
-
-
Shift register (UART mode 0)
TXLXL serial port clock cycle time
tQVXH
see Figure 17
16Tcy(CLK)
13Tcy(CLK)
-
-
888
722
-
-
ns
ns
output data set-up to clock rising edge see Figure 17
time
tXHQX
tXHDX
tXHDV
output data hold after clock rising
edge time
see Figure 17
-
-
Tcy(CLK) + 20
-
-
75
0
ns
ns
ns
input data hold after clock rising edge see Figure 17
time
0
-
input data valid to clock rising edge
time
see Figure 17
150
150
-
SPI interface
fSPI
SPI operating frequency
CCLK
slave
0
-
⁄
0
-
3.0
4.5
MHz
MHz
6
CCLK
master
⁄
4
TSPICYC
SPI cycle time
see Figure 19,
20, 21, 22
6
slave
⁄
-
-
-
333
222
250
-
-
-
ns
ns
ns
CCLK
4
master
⁄
CCLK
tSPILEAD
tSPILAG
SPI enable lead time (slave)
see Figure 21,
22
250
SPI enable lag time (slave)
see Figure 21,
22
250
-
250
-
ns
P89LPC9401_1
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Preliminary data sheet
Rev. 01 — 5 September 2005
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P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
Table 13: Dynamic characteristics (18 MHz) …continued
VDD = 3.0 V to 3.6 V unless otherwise specified.
T
amb = −40 °C to +85 °C for industrial applications, unless otherwise specified. [1] [2]
Symbol
Parameter
Conditions
Variable clock
fosc = 18 MHz Unit
Min
Max
Min
Max
tSPICLKH
SPICLK HIGH time
master
see Figure 19,
20, 21, 22
2
3
⁄
-
-
111
167
-
-
ns
ns
CCLK
CCLK
slave
⁄
tSPICLKL
SPICLK LOW time
master
see Figure 19,
20, 21, 22
2
3
⁄
-
-
-
111
167
100
-
-
-
ns
ns
ns
CCLK
CCLK
slave
⁄
tSPIDSU
tSPIDH
tSPIA
SPI data set-up time (master or slave) see Figure 19,
20, 21, 22
100
100
0
SPI data hold time (master or slave)
see Figure 19,
20, 21, 22
-
100
-
ns
ns
SPI access time (slave)
see Figure 21,
22
80
0
-
80
tSPIDIS
tSPIDV
SPI disable time (slave)
see Figure 21,
22
0
160
160 ns
SPI enable to output data valid time
see Figure 19,
20, 21, 22
slave
-
-
160
111
-
-
-
160 ns
111 ns
master
tSPIOH
tSPIR
SPI output data hold time
see Figure 19,
20, 21, 22
0
0
-
ns
SPI rise time
see Figure 19,
20, 21, 22
SPI outputs (SPICLK, MOSI, MISO)
-
-
100
-
-
100 ns
2000 ns
SPI inputs
2000
(SPICLK, MOSI, MISO, SS)
tSPIF
SPI fall time
see Figure 19,
20, 21, 22
SPI outputs (SPICLK, MOSI, MISO)
-
-
100
-
-
100 ns
2000 ns
SPI inputs
2000
(SPICLK, MOSI, MISO, SS)
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
P89LPC9401_1
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Preliminary data sheet
Rev. 01 — 5 September 2005
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P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
10.1 Waveforms
T
XLXL
clock
t
XHQX
1
t
QVXH
output data
write to SBUF
input data
0
2
3
4
5
6
7
t
XHDX
set TI
valid
t
XHDV
valid
valid
valid
valid
valid
valid
valid
clear RI
set RI
002aaa906
Fig 17. Shift register mode timing
V
− 0.5 V
DD
0.2V
+ 0.9 V
DD
0.2V
− 0.1 V
DD
0.45 V
t
CHCX
t
t
CLCX
t
CHCL
CLCH
T
cy(CLK)
002aaa907
Fig 18. External clock timing
P89LPC9401_1
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Preliminary data sheet
Rev. 01 — 5 September 2005
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P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
SS
T
SPICYC
t
t
SPIR
SPIF
t
SPICLKL
t
SPICLKH
SPICLK
(CPOL = 0)
(output)
t
t
SPIF
SPIR
t
SPICLKL
t
SPICLKH
SPICLK
(CPOL = 1)
(output)
t
t
SPIDH
SPIDSU
MISO
(input)
LSB/MSB in
MSB/LSB in
t
t
t
t
SPIR
SPIDV
SPIOH
SPIDV
t
MOSI
SPIF
(output)
master MSB/LSB out
master LSB/MSB out
002aaa908
Fig 19. SPI master timing (CPHA = 0)
SS
T
SPICYC
t
t
SPIR
SPIF
t
SPICLKL
t
SPICLKH
SPICLK
(CPOL = 0)
(output)
t
t
SPIR
SPIF
t
SPICLKL
t
SPICLK
(CPOL = 1)
(output)
SPICLKH
t
t
SPIDH
SPIDSU
MISO
(input)
LSB/MSB in
MSB/LSB in
t
t
t
t
SPIDV
SPIOH
SPIDV
SPIDV
t
t
SPIF
SPIR
MOSI
(output)
master MSB/LSB out
master LSB/MSB out
002aaa909
Fig 20. SPI master timing (CPHA = 1)
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
51 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
SS
t
t
SPIR
SPIR
T
SPICYC
t
t
SPIR
t
SPIF
t
SPILEAD
SPILAG
t
SPICLKL
t
SPICLKH
SPICLK
(CPOL = 0)
(input)
t
t
SPIR
SPIF
t
SPICLKL
t
SPICLK
(CPOL = 1)
(input)
SPICLKH
t
t
SPIOH
t
t
SPIDIS
t
SPIOH
SPIOH
SPIA
t
t
SPIDV
SPIDV
MISO
(output)
slave MSB/LSB out
slave LSB/MSB out
not defined
t
t
t
t
t
SPIDH
SPIDSU
SPIDH
SPIDSU
SPIDSU
MOSI
(input)
MSB/LSB in
LSB/MSB in
002aaa910
Fig 21. SPI slave timing (CPHA = 0)
SS
t
t
SPIR
SPIR
T
SPICYC
t
t
t
SPIR
SPIF
t
t
SPILAG
SPILEAD
SPICLKL
t
SPICLKH
SPICLK
(CPOL = 0)
(input)
t
t
SPIR
SPIF
t
SPICLKL
SPICLK
(CPOL = 1)
(input)
t
SPICLKH
t
t
t
SPIOH
SPIOH
SPIOH
t
t
t
t
SPIDIS
SPIDV
SPIDV
SPIDV
t
SPIA
MISO
(output)
slave LSB/MSB out
slave MSB/LSB out
not defined
t
t
t
t
t
SPIDH
SPIDSU
SPIDH
SPIDSU
SPIDSU
MOSI
(input)
MSB/LSB in
LSB/MSB in
002aaa911
Fig 22. SPI slave timing (CPHA = 1)
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
52 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
10.2 ISP entry mode
Table 14: Dynamic characteristics, ISP entry mode
VDD = 2.4 V to 3.6 V, unless otherwise specified.
T
amb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Symbol Parameter Conditions
Min
Typ
Max
Unit
tVR
VDD active to RST_N active delay pin RST
time
50
-
-
µs
tRH
tRL
RST_N HIGH time
RST_N LOW time
pin RST
pin RST
1
1
-
-
32
-
µs
µs
V
DD
t
VR
t
RH
RST
t
RL
002aaa912
Fig 23. ISP entry waveform
11. Other characteristics
11.1 Comparator electrical characteristics
Table 15: Comparator electrical characteristics
VDD = 2.4 V to 3.6 V, unless otherwise specified.
amb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
T
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
mV
V
VIO
input offset voltage
-
-
±20
VIC
common-mode input voltage
common-mode rejection ratio
total response time
0
-
-
VDD − 0.3
[1]
CMRR
tres(tot)
t(CE-OV)
ILI
-
−50
500
10
dB
ns
-
250
comparator enable to output valid time
input leakage current
-
-
-
µs
0 V < VI < VDD
-
±10
µA
[1] This parameter is characterized, but not tested in production.
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
53 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
12. Package outline
LQFP64: plastic low profile quad flat package; 64 leads; body 14 x 14 x 1.4 mm
SOT791-1
y
X
A
33
48
49
32
Z
E
e
A
H
2
E
A
E
(A )
3
A
1
w M
θ
b
p
L
p
L
pin 1 index
detail X
64
17
16
1
Z
D
v
v
M
M
A
e
w M
b
p
D
B
H
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.15 1.45
0.05 1.35
0.45 0.20 14.1 14.1
0.30 0.09 13.9 13.9
16.15 16.15
15.85 15.85
0.75
0.45
1.2
0.8
1.2
0.8
mm
1.6
0.25
0.8
1
0.2
0.2
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-22
SOT791-1
136E18
MS-026
ED-7311EC
Fig 24. Package outline SOT791-1 (LQFP64)
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
54 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
13. Abbreviations
Table 16: Acronym list
Acronym
CPU
Description
Central Processing Unit
EPROM
EMI
Erasable Programmable Read-Only Memory
Electro-Magnetic Interference
Liquid Crystal Display
LCD
LED
Light Emitting Diode
PWM
RAM
RC
Pulse Width Modulator
Random Access Memory
Resistance-Capacitance
Special Function Register
Serial Peripheral Interface
Universal Asynchronous Receiver/Transmitter
SFR
SPI
UART
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
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P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
14. Revision history
Table 17: Revision history
Document ID
Release date Data sheet status
20050905 Preliminary data sheet
Change notice Doc. number
Supersedes
P89LPC9401_1
-
-
-
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
56 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
15. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
16. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
18. Trademarks
Notice — All referenced brands, product names, service names and
trademarks are the property of their respective owners.
I2C-bus — wordmark and logo are trademarks of Koninklijke Philips
Electronics N.V.
17. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
57 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
20. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
7.16.1
7.17
Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Timers/counters 0 and 1 . . . . . . . . . . . . . . . . 25
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Timer overflow toggle output . . . . . . . . . . . . . 26
RTC/system timer. . . . . . . . . . . . . . . . . . . . . . 26
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Baud rate generator and selection. . . . . . . . . 27
Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 27
Break detect. . . . . . . . . . . . . . . . . . . . . . . . . . 27
Double buffering. . . . . . . . . . . . . . . . . . . . . . . 27
Transmit interrupts with double buffering
2
2.1
2.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Principal features . . . . . . . . . . . . . . . . . . . . . . . 1
Additional features . . . . . . . . . . . . . . . . . . . . . . 1
7.17.1
7.17.2
7.17.3
7.17.4
7.17.5
7.17.6
7.18
3
3.1
4
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 6
5
7.19
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 7
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.19.1
7.19.2
7.19.3
7.19.4
7.19.5
7.19.6
7.19.7
7.19.8
7.19.9
7
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.4
Functional description . . . . . . . . . . . . . . . . . . 11
Special function registers . . . . . . . . . . . . . . . . 11
Enhanced CPU. . . . . . . . . . . . . . . . . . . . . . . . 16
Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 16
CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 16
Low speed oscillator option . . . . . . . . . . . . . . 16
Medium speed oscillator option . . . . . . . . . . . 16
High speed oscillator option . . . . . . . . . . . . . . 16
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 17
On-chip RC oscillator option. . . . . . . . . . . . . . 17
Watchdog oscillator option . . . . . . . . . . . . . . . 17
External clock input option . . . . . . . . . . . . . . . 17
CPU Clock (CCLK) wake-up delay . . . . . . . . . 19
CCLK modification: DIVM register . . . . . . . . . 19
Low power select . . . . . . . . . . . . . . . . . . . . . . 19
Memory organization . . . . . . . . . . . . . . . . . . . 19
Data RAM arrangement . . . . . . . . . . . . . . . . . 20
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
External interrupt inputs . . . . . . . . . . . . . . . . . 20
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Port configurations . . . . . . . . . . . . . . . . . . . . . 21
enabled (modes 1, 2 and 3) . . . . . . . . . . . . . . 28
7.19.10 The 9th bit (bit 8) in double buffering
(modes 1, 2 and 3). . . . . . . . . . . . . . . . . . . . . 28
7.20
7.21
7.21.1
7.22
7.22.1
7.22.2
7.22.3
7.23
7.24
7.25
7.25.1
7.25.2
7.26
7.26.1
7.26.2
7.26.3
7.26.4
I2C-bus serial interface. . . . . . . . . . . . . . . . . . 29
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Typical SPI configurations . . . . . . . . . . . . . . . 32
Analog comparators. . . . . . . . . . . . . . . . . . . . 34
Internal reference voltage. . . . . . . . . . . . . . . . 34
Comparator interrupt . . . . . . . . . . . . . . . . . . . 34
Comparators and power reduction modes . . . 34
Keypad interrupt. . . . . . . . . . . . . . . . . . . . . . . 35
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 36
Additional features . . . . . . . . . . . . . . . . . . . . . 36
Software reset . . . . . . . . . . . . . . . . . . . . . . . . 36
Dual data pointers . . . . . . . . . . . . . . . . . . . . . 36
LCD driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
General description . . . . . . . . . . . . . . . . . . . . 37
Functional description . . . . . . . . . . . . . . . . . . 37
LCD bias voltages . . . . . . . . . . . . . . . . . . . . . 37
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.12.1
7.13
7.13.1
7.13.1.1 Quasi-bidirectional output configuration . . . . . 22
7.13.1.2 Open-drain output configuration . . . . . . . . . . . 22
7.13.1.3 Input-only configuration . . . . . . . . . . . . . . . . . 22
7.13.1.4 Push-pull output configuration . . . . . . . . . . . . 22
7.13.2
7.13.3
7.14
7.14.1
7.14.2
7.15
7.15.1
7.15.2
7.15.3
7.16
Port 0 analog functions. . . . . . . . . . . . . . . . . . 22
Additional port features. . . . . . . . . . . . . . . . . . 23
Power monitoring functions. . . . . . . . . . . . . . . 23
Brownout detection. . . . . . . . . . . . . . . . . . . . . 23
Power-on detection. . . . . . . . . . . . . . . . . . . . . 23
Power reduction modes . . . . . . . . . . . . . . . . . 23
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power-down mode . . . . . . . . . . . . . . . . . . . . . 24
Total Power-down mode . . . . . . . . . . . . . . . . . 24
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.26.4.1 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.26.5
7.26.6
7.26.7
7.26.8
7.26.9
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Display register. . . . . . . . . . . . . . . . . . . . . . . . 38
Segment outputs . . . . . . . . . . . . . . . . . . . . . . 38
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 38
Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.26.10 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.26.11 Output bank selector . . . . . . . . . . . . . . . . . . . 39
7.26.12 Input bank selector. . . . . . . . . . . . . . . . . . . . . 39
continued >>
P89LPC9401_1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 — 5 September 2005
58 of 59
P89LPC9401
Philips Semiconductors
8-bit two-clock 80C51 microcontroller with 32 segment × 4 LCD driver
7.26.13 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.26.13.1 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 39
7.26.14 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.26.15 I2C-bus slave addresses. . . . . . . . . . . . . . . . . 40
7.27
Flash program memory. . . . . . . . . . . . . . . . . . 40
General description. . . . . . . . . . . . . . . . . . . . . 40
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Flash organization . . . . . . . . . . . . . . . . . . . . . 40
Using flash as data storage . . . . . . . . . . . . . . 40
Flash programming and erasing. . . . . . . . . . . 41
In-circuit programming . . . . . . . . . . . . . . . . . . 41
In-application programming . . . . . . . . . . . . . . 41
In-system programming . . . . . . . . . . . . . . . . . 41
Power-on reset code execution. . . . . . . . . . . . 42
7.27.1
7.27.2
7.27.3
7.27.4
7.27.5
7.27.6
7.27.7
7.27.8
7.27.9
7.27.10 Hardware activation of the boot loader. . . . . . 42
7.28
7.29
User configuration bytes. . . . . . . . . . . . . . . . . 42
User sector security bytes . . . . . . . . . . . . . . . 42
8
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 43
Static characteristics. . . . . . . . . . . . . . . . . . . . 44
10
10.1
10.2
Dynamic characteristics . . . . . . . . . . . . . . . . . 46
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
ISP entry mode. . . . . . . . . . . . . . . . . . . . . . . . 53
11
11.1
12
13
14
15
16
17
18
19
Other characteristics. . . . . . . . . . . . . . . . . . . . 53
Comparator electrical characteristics . . . . . . . 53
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 54
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 55
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 56
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 57
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Contact information . . . . . . . . . . . . . . . . . . . . 57
© Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 5 September 2005
Document number: P89LPC9401_1
Published in the Netherlands
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