P89LPC952FA,512 [NXP]

P89LPC952/954 - 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC LCC 44-Pin;


型号：	P89LPC952FA,512
厂家：	NXP
描述：	P89LPC952/954 - 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB/16 kB 3 V byte-erasable flash with 10-bit ADC LCC 44-Pin 时钟 PC 微控制器外围集成电路
文件：	总69页 (文件大小：339K)
中文：	中文翻译
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P89LPC952/954

8-bit microcontroller with accelerated two-clock 80C51 core

8 kB/16 kB 3 V byte-erasable ﬂash with 10-bit ADC

Rev. 04 — 24 July 2008

Product data sheet

1. General description

The P89LPC952/954 is a single-chip microcontroller, available in low cost packages,

based on a high performance processor architecture that executes instructions in two to

four clocks, six times the rate of standard 80C51 devices. Many system-level functions

have been incorporated into the P89LPC952/954 in order to reduce component count,

board space, and system cost.

2. Features

2.1 Principal features

I 8 kB/16 kB byte-erasable ﬂash code memory organized into 1 kB sectors and 64-byte

pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.

I 256-byte RAM data memory and a 256-byte auxiliary on-chip RAM.

I 8-input multiplexed 10-bit ADC with window comparator that can generate an interrupt

for in or out of range results. Two analog comparators with selectable inputs and

reference source.

I Two 16-bit counter/timers (each may be conﬁgured to toggle a port output upon timer

overﬂow or to become a PWM output) and a 23-bit system timer that can also be used

as a RTC.

I Two enhanced UARTs with a fractional baud rate generator, break detect, framing

error detection, and automatic address detection; 400 kHz byte-wide I²C-bus

communication port and SPI communication port.

I High-accuracy internal RC oscillator option, with clock doubler option, allows operation

without external oscillator components. The RC oscillator option is selectable and ﬁne

tunable. Fast switching between the internal RC oscillator and any oscillator source

provides optimal support of minimal power active mode with fast switching to

maximum performance.

I 2.4 V to 3.6 V V_DDoperating range. I/O pins are 5 V tolerant (may be pulled up or

driven to 5.5 V).

I 44-pin and 48-pin packages with 40 and 42 I/O pins minimum while using on-chip

oscillator and reset options.

I Port 5 has high current sourcing/sinking (20 mA) for all Port 5 pins. All other port pins

have high sinking capability (20 mA). A maximum limit is speciﬁed for the entire chip.

I Watchdog timer with separate on-chip oscillator, requiring no external components.

The watchdog prescaler is selectable from eight values.

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

2.2 Additional features

I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns

for all instructions except multiply and divide when executing at 18 MHz. This is six

times the performance of the standard 80C51 running at the same clock frequency. A

lower clock frequency for the same performance results in power savings and reduced

EMI.

I Serial ﬂash In-Circuit Programming (ICP) allows simple production coding with

commercial EPROM programmers. Flash security bits prevent reading of sensitive

application programs.

I Serial ﬂash In-System Programming (ISP) allows coding while the device is mounted

in the end application.

I In-Application Programming (IAP) of the ﬂash code memory. This allows changing the

code in a running application.

I Low voltage (brownout) detect allows a graceful system shutdown when power fails.

May optionally be conﬁgured as an interrupt.

I Idle and two different power-down reduced power modes. Improved wake-up from

Power-down mode (a LOW interrupt input starts execution). Typical power-down

current is 1 µA (total power-down with voltage comparators disabled).

I On-chip power-on reset allows operation without external reset components. A

software reset function is also available.

I Programmable external reset pin (P1.5) conﬁguration options: open drain bidirectional

reset input/output, reset input with pull-up, push-pull reset output, input-only port. A

reset counter and reset glitch suppression circuitry prevent spurious and incomplete

resets.

I Only power and ground connections are required to operate the P89LPC952/954

when internal reset option is selected.

I Conﬁgurable on-chip oscillator with frequency range options selected by user

programmed ﬂash conﬁguration bits. Oscillator options support frequencies from

20 kHz to the maximum operating frequency of 18 MHz.

I Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator

allowing it to perform an oscillator fail detect function.

I Programmable port output conﬁguration options: quasi-bidirectional, open drain,

push-pull, input-only.

I Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of

the pins match or do not match a programmable pattern.

I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns

minimum ramp times.

I Four interrupt priority levels.

I Eight keypad interrupt inputs, plus two additional external interrupt inputs.

I Schmitt trigger port inputs.

I Second data pointer.

I Extended temperature range.

I Emulation support.

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

2 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

P89LPC952FA

PLCC44

LQFP44

plastic leaded chip carrier; 44 leads

SOT187-2

SOT389-1

P89LPC952FBD

plastic low proﬁle quad ﬂat package; 44 leads;

body 10 × 10 × 1.4 mm

P89LPC954FA

PLCC44

LQFP44

plastic leaded chip carrier; 44 leads

SOT187-2

SOT389-1

P89LPC954FBD44

plastic low proﬁle quad ﬂat package; 44 leads;

body 10 × 10 × 1.4 mm

P89LPC954FBD48

LQFP48

plastic low proﬁle quad ﬂat package; 48 leads;

SOT313-2

body 7 × 7 × 1.4 mm

3.1 Ordering options

Table 2.

Ordering options

Flash memory

Type number

P89LPC952FA

P89LPC952FBD

P89LPC954FA

P89LPC954FBD44

P89LPC954FBD48

Temperature range

−40 °C to +85 °C

Frequency

0 MHz to 18 MHz

8 kB

0 MHz to 18 MHz

16 kB

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

3 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

4. Block diagram

P89LPC952/954

ACCELERATED 2-CLOCK 80C51 CPU

TXD0

8 kB/16 kB

CODE FLASH

UART0

RXD0

internal

bus

256-BYTE

DATA RAM

TXD1

UART1

RXD1

256-BYTE

AUXILIARY RAM

SCL

SDA

I C-BUS

AD00

AD01

AD02

PORT 5

CONFIGURABLE I/Os

P5[7:0]

P4[7:0]

P3[1:0]

AD03

ADC0

AD04

AD05

AD06

AD07

PORT 4

CONFIGURABLE I/Os

SPICLK

MOSI

MISO

PORT 3

CONFIGURABLE I/Os

SPI

(1)

P2[5:0]

PORT 2

CONFIGURABLE I/Os

REAL-TIME CLOCK/

SYSTEM TIMER

(2)

P2[7:0]

PORT 1

CONFIGURABLE I/Os

TIMER 0

TIMER 1

P1[7:0]

P0[7:0]

CMP2

CIN2A

CIN1A

PORT 0

CONFIGURABLE I/Os

CIN2B

CMP1

CIN1B

ANALOG

COMPARATORS

KEYPAD

INTERRUPT

TRIG

TCLK

TDI

DEBUGGER

INTERFACE

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU

clock

XTAL1

CRYSTAL

ON-CHIP RC

OSCILLATOR WITH

CLOCK DOUBLER

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

CONFIGURABLE

OSCILLATOR

RESONATOR

XTAL2

002aab305

(1) 44-pin package.

(2) 48-pin package.

Fig 1. Block diagram

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

4 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

5. Functional diagram

TXD0

RXD0

INT0

INT1

RST

KBI0

KBI1

KBI2

KBI3

KBI4

KBI5

KBI6

KBI7

CMP2

CIN2B

CIN2A

CIN1B

CIN1A

CMPREF

CMP1

AD05

AD00

AD01

AD02

AD03

SCL

SDA

PORT 0

PORT 3

PORT 1

AD04

AD07

AD06

MOSI

MISO

CLKOUT

XTAL2

XTAL1

P89LPC952

P89LPC954

PORT 2

SPICLK

(1)

PORT 5

TRIG

TXD1

RXD1

PORT 4

TDI

TCLK

002aab358

(1) 48-pin package.

Fig 2. Functional diagram

P89LPC952_954_4

Product data sheet

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P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

6. Pinning information

6.1 Pinning

P1.3/INT0/SDA

P0.4/CIN1A/KBI4/AD03

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

P1.2/T0/SCL

P1.1/RXD0

P1.0/TXD0

P3.1/XTAL1

P0.7/T1/KBI7

P2.2/MOSI

P2.3/MISO

P2.4/SS

P3.0/XTAL2/CLKOUT

P89LPC952FA

P89LPC954FA

P5.7

P5.6

P5.5

P5.4

P2.5/SPICLK

P4.0

P4.1/TRIG

002aab307

Fig 3. PLCC44 pin conﬁguration

P89LPC952_954_4

Product data sheet

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P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

P1.3/INT0/SDA

P1.2/T0/SCL

P0.4/CIN1A/KBI4/AD03

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

P1.1/RXD0

P1.0/TXD0

P3.1/XTAL1

P0.7/T1/KBI7

P2.2/MOSI

P2.3/MISO

P2.4/SS

P3.0/XTAL2/CLKOUT

P89LPC952FBD

P89LPC954FBD

P5.7

P5.6

P5.5

P5.4

P2.5/SPICLK

P4.0

P4.1/TRIG

002aab306

Fig 4.

LQFP44 pin conﬁguration

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

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P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

P1.3/INT0/SDA

P1.2/T0/SCL

P1.1/RXD0

P0.4/CIN1A/KBI4/AD03

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

VREFP

P1.0/TXD0

P2.7

P3.1/XTAL1

P0.7/T1/KBI7

P2.2/MOSI

P2.3/MISO

P2.4/SS

P89LPC954FBD48

P3.0/XTAL2/CLKOUT

P5.7

P5.6

P5.5

P5.4

P2.5/SPICLK

P2.6

P4.0

002aad095

Fig 5.

LQFP48 pin conﬁguration

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

8 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

6.2 Pin description

Table 3.

Symbol

Pin description

Type Description

LQFP48

PLCC44

LQFP44

P0.0 to P0.7

I/O

Port 0: Port 0 is an 8-bit I/O port with a user-conﬁgurable

output type. During reset Port 0 latches are conﬁgured in the

input only mode with the internal pull-up disabled. The

operation of Port 0 pins as inputs and outputs depends upon

the port conﬁguration selected. Each port pin is conﬁgured

independently. Refer to Section 7.13.1 “Port conﬁgurations”

and Table 11 “Static characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described

below:

P0.0/CMP2/

KBI0/AD05

I/O

P0.0 — Port 0 bit 0.

CMP2 — Comparator 2 output.

KBI0 — Keyboard input 0.

AD05 — ADC0 channel 5 analog input.

P0.1 — Port 0 bit 1.

P0.1/CIN2B/

KBI1/AD00

I/O

CIN2B — Comparator 2 positive input B.

KBI1 — Keyboard input 1.

AD00 — ADC0 channel 0 analog input.

P0.2 — Port 0 bit 2.

P0.2/CIN2A/

KBI2/AD01

I/O

CIN2A — Comparator 2 positive input A.

KBI2 — Keyboard input 2.

AD01 — ADC0 channel 1 analog input.

P0.3 — Port 0 bit 3.

P0.3/CIN1B/

KBI3/AD02

I/O

CIN1B — Comparator 1 positive input B.

KBI3 — Keyboard input 3.

AD02 — ADC0 channel 2 analog input.

P0.4 — Port 0 bit 4.

P0.4/CIN1A/

KBI4/AD03

I/O

CIN1A — Comparator 1 positive input A.

KBI4 — Keyboard input 4.

AD03 — ADC0 channel 3 analog input.

P0.5 — Port 0 bit 5.

P0.5/CMPREF/ 35

KBI5

I/O

CMPREF — Comparator reference (negative) input.

KBI5 — Keyboard input 5.

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

9 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

Table 3.

Symbol

Pin description …continued

Type Description

LQFP48

PLCC44

LQFP44

P0.6/CMP1/

KBI6

I/O

P0.6 — Port 0 bit 6.

CMP1 — Comparator 1 output.

KBI6 — Keyboard input 6.

P0.7 — Port 0 bit 7.

P0.7/T1/KBI7

P1.0 to P1.7

I/O

T1 — Timer/counter 1 external count input or overﬂow

output.

KBI7 — Keyboard input 7.

I/O, I Port 1: Port 1 is an 8-bit I/O port with a user-conﬁgurable

[1]

output type, except for three pins as noted below. During

reset Port 1 latches are conﬁgured in the input only mode

with the internal pull-up disabled. The operation of the

conﬁgurable Port 1 pins as inputs and outputs depends upon

the port conﬁguration selected. Each of the conﬁgurable port

pins are programmed independently. Refer to Section 7.13.1

“Port conﬁgurations” and Table 11 “Static characteristics” for

details. P1.2 to P1.3 are open drain when used as outputs.

P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described

below:

P1.0/TXD0

P1.1/RXD0

P1.2/T0/SCL

I/O

P1.0 — Port 1 bit 0.

TXD0 — Transmitter output for serial port 0.

P1.1 — Port 1 bit 1.

I/O

RXD0 — Receiver input for serial port 0.

P1.2 — Port 1 bit 2 (open-drain when used as output).

I/O

T0 — Timer/counter 0 external count input or overﬂow

output (open-drain when used as output).

I/O

SCL — I²C-bus serial clock input/output.

P1.3 — Port 1 bit 3 (open-drain when used as output).

INT0 — External interrupt 0 input.

SDA — I²C-bus serial data input/output.

P1.4 — Port 1 bit 4.

P1.3/INT0/SDA

P1.4/INT1

I/O

INT1 — External interrupt 1 input.

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

10 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

Table 3.

Symbol

Pin description …continued

Type Description

LQFP48

PLCC44

LQFP44

P1.5/RST

P1.5 — Port 1 bit 5 (input only).

RST — External Reset input during power-on or maybe a

reset input/output if selected via UCFG1 and UCFG2. When

functioning as a reset input or input/output, a LOW on this

pin resets the microcontroller, causing I/O ports and

peripherals to take on their default states, and the processor

begins execution at address 0. When functioning as a reset

output or input/output an internal reset source will drive this

pin LOW. Also used during a power-on sequence to force

ISP mode. When using an oscillator frequency above

12 MHz, the reset input function of P1.5 must be

enabled. An external circuit is required to hold the

device in reset at power-up until V_DDhas reached its

speciﬁed level. When system power is removed V_DDwill

fall below the minimum speciﬁed operating voltage.

When using an oscillator frequency above 12 MHz, in

some applications, an external brownout detect circuit

may be required to hold the device in reset when V_DD

falls below the minimum speciﬁed operating voltage.

P1.6

I/O

P1.6 — Port 1 bit 6.

P1.7/AD04

P1.7 — Port 1 bit 7.

AD04 — ADC0 channel 4 analog input.

P2.0 to P2.5

I/O

Port 2: Port 2 is an 8-bit I/O port with a user-conﬁgurable

output type. During reset Port 2 latches are conﬁgured in the

input only mode with the internal pull-up disabled. The

operation of Port 2 pins as inputs and outputs depends upon

the port conﬁguration selected. Each port pin is conﬁgured

independently. Refer to Section 7.13.1 “Port conﬁgurations”

and Table 11 “Static characteristics” for details.

All pins have Schmitt triggered inputs.

Port 2 also provides various special functions as described

below:

P2.0/AD07

P2.1/AD06

P2.2/MOSI

I/O

P2.0 — Port 2 bit 0.

AD07 — ADC0 channel 7 analog input.

P2.1 — Port 2 bit 1.

I/O

AD06 — ADC0 channel 6 analog input.

P2.2 — Port 2 bit 2.

I/O

MOSI — SPI master out slave in. When conﬁgured as

master, this pin is output; when conﬁgured as slave, this pin

is input.

P2.3/MISO

P2.4/SS

I/O

P2.3 — Port 2 bit 3.

MISO — When conﬁgured as master, this pin is input, when

conﬁgured as slave, this pin is output.

I/O

P2.4 — Port 2 bit 4.

SS — SPI Slave select.

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

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P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

Table 3.

Symbol

Pin description …continued

Type Description

LQFP48

PLCC44

LQFP44

P2.5/SPICLK

I/O

P2.5 — Port 2 bit 5.

SPICLK — SPI clock. When conﬁgured as master, this pin is

output; when conﬁgured as slave, this pin is input.

P2.6

I/O

P2.6 — Port 2 bit 6.

P2.7 — Port 2 bit 7.

P2.7

P3.0 to P3.1

Port 3: Port 3 is a 2-bit I/O port with a user-conﬁgurable

output type. During reset Port 3 latches are conﬁgured in the

input only mode with the internal pull-up disabled. The

operation of Port 3 pins as inputs and outputs depends upon

the port conﬁguration selected. Each port pin is conﬁgured

independently. Refer to Section 7.13.1 “Port conﬁgurations”

and Table 11 “Static characteristics” for details.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described

below:

P3.0/XTAL2/

CLKOUT

I/O

P3.0 — Port 3 bit 0.

XTAL2 — Output from the oscillator ampliﬁer (when a crystal

oscillator option is selected via the ﬂash conﬁguration.

CLKOUT — CPU clock divided by 2 when enabled via SFR

bit (ENCLK -TRIM.6). It can be used if the CPU clock is the

internal RC oscillator, watchdog oscillator or external clock

input, except when XTAL1/XTAL2 are used to generate clock

source for the RTC/system timer.

P3.1/XTAL1

I/O

P3.1 — Port 3 bit 1.

XTAL1 — Input to the oscillator circuit and internal clock

generator circuits (when selected via the ﬂash conﬁguration).

It can be a port pin if internal RC oscillator or watchdog

oscillator is used as the CPU clock source, and if

XTAL1/XTAL2 are not used to generate the clock for the

RTC/system timer.

P4.0 to P4.7

I/O

Port 4: Port 4 is an 8-bit I/O port with a user-conﬁgurable

output type. During reset Port 4 latches are conﬁgured in the

input only mode with the internal pull-up disabled. The

operation of Port 4 pins as inputs and outputs depends upon

the port conﬁguration selected. Each port pin is conﬁgured

independently. Refer to Section 7.13.1 “Port conﬁgurations”

and Table 11 “Static characteristics” for details.

All pins have Schmitt triggered inputs.

Port 4 also provides various special functions as described

below:

P4.0

I/O

P4.0 — Port 4 bit 0.

P4.1/TRIG

P4.1 — Port 4 bit 1.

TRIG — Debugger trigger output.

P4.2 — Port 4 bit 2.

P4.2/TXD1

P4.3/RXD1

I/O

TXD1 — Transmitter output for serial port 1.

P4.3 — Port 4 bit 3.

I/O

RXD1 — Receiver input for serial port 1.

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

12 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

Table 3.

Symbol

Pin description …continued

Type Description

LQFP48

PLCC44

LQFP44

P4.4

I/O

P4.4 — Port 4 bit 4.

P4.5 — Port 4 bit 5.

P4.5/TDI

TDI — Serial data input/output for debugger interface.

P4.6 — Port 4 bit 6.

P4.6

P4.7/TCLK

P4.7 — Port 4 bit 7.

TCLK — Serial clock input for debugger interface.

P5.0 to P5.7

I/O

Port 5: Port 5 is an 8-bit I/O port with a user-conﬁgurable

output type. During reset Port 5 latches are conﬁgured in the

input only mode with the internal pull-up disabled. The

operation of Port 5 pins as inputs and outputs depends upon

the port conﬁguration selected. Each port pin is conﬁgured

independently. Refer to Section 7.13.1 “Port conﬁgurations”

and Table 11 “Static characteristics” for details.

All pins have Schmitt triggered inputs.

Port 5 also provides various special functions as described

below:

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

P5.6

P5.7

V_SS

I/O

P5.0 — Port 5 bit 0. High current source.

P5.1 — Port 5 bit 1. High current source.

P5.2 — Port 5 bit 2. High current source.

P5.3 — Port 5 bit 3. High current source.

P5.4 — Port 5 bit 4. High current source.

P5.5 — Port 5 bit 5. High current source.

P5.6 — Port 5 bit 6. High current source.

P5.7 — Port 5 bit 7. High current source.

Ground: 0 V reference.

17, 45

3, 22

16, 41

VREFN

V_DD

negative ADC reference voltage

8, 32

13, 36

7, 30

Power supply: This is the power supply voltage for normal

operation as well as Idle and Power-down modes.

VREFP

positive ADC reference voltage

[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

13 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

7. Functional description

Remark: Please refer to the P89LPC952/954 User’s Manual for a more detailed functional

description.

7.1 Special function registers

Remark: SFR accesses are restricted in the following ways:

• User must not attempt to access any SFR locations not deﬁned.

• Accesses to any deﬁned SFR locations must be strictly for the functions for the SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise speciﬁed, must be written with ‘0’, but can return any value

when read (even if it was written with ‘0’). It is a reserved bit and may be used in

future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

14 of 69

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Table 4.

Name

Special function registers

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

ACC^[1]

Accumulator

E0H

97H

0000 0000

AD0CON

ADC0 control

ENBI0

ADI07

BNDI0

CLK2

ENADCI0

ADI06

TMM0

ADI05

SCC0

CLK0

ENT1

EDGE0

ADI04

SCAN0

ADCI0

ENADC0

ADCS01

ADCS00 00

AD0INS

ADC0 input

select

A3H

C0H

A1H

A2H

ADI03

ADI02

ADI01

ADI00

0000 0000

000x 0000

0000 00x0

AD0MODA ADC0 mode

BURST0

CLK1

AD0MODB ADC0 mode

AUXR1

Auxiliary

function

CLKLP

EBRR

ENT0

SRST

DPS

Bit address

F0H

B^[1]

B register

Baud rate

0000 0000

BRGR0_0

BEH

generator 0

rate low

BRGR1_0

Baud rate

generator 0

rate high

BFH

BDH

0000 0000

xxxx xx00

BRGCON_0 Baud rate

generator 0

SBRGS_0 BRGEN_0 00^[3]

control

CMP1

CMP2

DIVM

Comparator 1

control register

ACH

ADH

95H

CE1

CE2

CP1

CP2

CN1

CN2

OE1

OE2

CO1

CO2

CMF1

CMF2

00^[2]

xx00 0000

0000 0000

Comparator 2

control register

CPU clock

divide-by-M

control

DPTR

Data pointer

(2 bytes)

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Table 4.

Name

Special function registers …continued

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

DPH

DPL

Data pointer

high

83H

82H

E7H

E6H

0000 0000

0111 0000

Data pointer

low

FMADRH

FMADRL

FMCON

Program ﬂash

address high

Program ﬂash

address low

Program ﬂash

control (Read)

E4H

BUSY

HVA

HVE

Program ﬂash

control (Write)

E4H FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 FMCMD.3 FMCMD.2 FMCMD.1 FMCMD.0

E5H

FMDATA

I2ADR

Program ﬂash

data

0000 0000

I²C-bus slave

address

DBH

I2ADR.6

I2ADR.5

I2ADR.4

I2ADR.3

I2ADR.2

I2ADR.1

I2ADR.0

Bit address

I2CON^[1]

I2DAT

I²C-bus control D8H

I2EN

STA

STO

CRSEL 00

x000 00x0

I²C-bus data

DAH

I2SCLH

Serial clock

generator/SCL

duty cycle

DDH

0000 0000

1111 1000

I2SCLL

I2STAT

Serial clock

generator/SCL

duty cycle

I²C-bus status D9H

DCH

STA.4

STA.3

STA.2

STA.1

STA.0

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Table 4.

Name

Special function registers …continued

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

IEN0^[1]

Interrupt

enable 0

A8H

EWDRT

EBO

ES/ESR

ET1

EX1

ET0

EX0

0000 0000

Bit address

IEN1^[1]

IEN2

Interrupt

enable 1

E8H

EST

ESPI

EKBI

EI2C

00^[2]

00x0 0000

Interrupt

enable 2

D5H

EST1

ES1/ESR1

EADC

Bit address

IP0^[1]

IP0H

Interrupt

priority 0

B8H

PWDRT

PBO

PS/PSR

PT1

PX1

PT0

PX0

00^[2]

x000 0000

Interrupt

B7H

PWDRTH

PBOH

PSH/

PT1H

PX1H

PT0H

PX0H

priority 0 high

PSRH

Bit address

IP1^[1]

Interrupt

priority 1

F8H

F7H

D6H

D7H

PST

PSPI

PKBI

PI2C

00^[2]

00x0 0000

xxxx xx00

0000 0000

IP1H

Interrupt

priority 1 high

PSTH

PSPIH

PEST1

PEST1H

PCH

PKBIH

PADC

PI2CH

IP2

Interrupt

priority 2

PES1/

PESR1

IP2H

Interrupt

priority 2 high

PES1H/

PESR1H

PADCH

KBCON

KBMASK

Keypad control 94H

PATN

_SEL

KBIF

Keypad

86H

interrupt mask

KBPATN

P0^[1]

Keypadpattern 93H

1111 1111

Bit address

[2]

Port 0

Port 1

80H

T1/KB7

CMP1

/KB6

CMPREF

/KB5

CIN1A

/KB4

CIN1B

/KB3

CIN2A

/KB2

CIN2B

/KB1

CMP2

/KB0

Bit address

P1^[1]

90H

RST

INT1

INT0/SDA

T0/SCL

RXD0

TXD0

[2]

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Table 4.

Name

Special function registers …continued

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

[2]

P2^[1]

Port 2

A0H

Bit address

B0H

SPICLK

MISO

MOSI

[2]

P3^[1]

Port 3

Port 4

Port 5

TMS

RXD1

TXD1

XTAL1

TRIG

XTAL2

T3EX

B3H

B4H

P0M1

Port 0 output

mode 1

84H

85H

91H

92H

(P0M1.7)

(P0M1.6)

(P0M1.5)

(P0M1.4)

(P0M1.3)

(P0M1.2)

(P0M1.1)

(P0M1.0) FF^[2]

(P0M2.0) 00^[2]

(P1M1.0) D3^[2]

(P1M2.0) 00^[2]

(P2M1.0) FF^[2]

(P2M2.0) 00^[2]

(P3M1.0) 03^[2]

(P3M2.0) 00^[2]

PMOD0 00

1111 1111

0000 0000

11x1 xx11

00x0 xx00

1111 1111

0000 0000

xxxx xx11

xxxx xx00

0000 0000

P0M2

P1M1

P1M2

P2M1

P2M2

P3M1

P3M2

PCON

PCONA

Port 0 output

mode 2

(P0M2.7)

(P1M1.7)

(P1M2.7)

(P0M2.6)

(P1M1.6)

(P1M2.6)

(P2M1.6)

(P2M2.6)

(P0M2.5)

(P0M2.4)

(P1M1.4)

(P1M2.4)

(P2M1.4)

(P2M2.4)

(P0M2.3)

(P1M1.3)

(P1M2.3)

(P2M1.3)

(P2M2.3)

(P0M2.2)

(P1M1.2)

(P1M2.2)

(P2M1.2)

(P2M2.2)

(P0M2.1)

(P1M1.1)

(P1M2.1)

(P2M1.1)

(P2M2.1)

(P3M1.1)

(P3M2.1)

PMOD1

SPD

Port 1 output

mode 1

Port 1 output

mode 2

(P2M1.5)

(P2M2.5)

Port 2 output

mode 1

A4H (P2M1.7)

A5H (P2M2.7)

Port 2 output

mode 2

Port 3 output

mode 1

B1H

B2H

87H

B5H

Port 3 output

mode 2

Power control

SMOD1

RTCPD

SMOD0

BOPD

VCPD

BOI

GF1

GF0

Power control

ADPD

I2PD

SPPD

00^[2]

Bit address

PSW^[1]

Program

status word

D0H

RS1

RS0

0000 0000

xx00 000x

PT0AD

RSTSRC

Port 0 digital

input disable

F6H

DFH

PT0AD.5

BOF

PT0AD.4

POF

PT0AD.3

R_BK

PT0AD.2

R_WD

PT0AD.1

R_SF

[4]

Reset source

R_EX

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Table 4.

Name

Special function registers …continued

Description

SFR Bit functions and addresses

Reset value

Hex Binary

RTCEN 60^[2][7]011x xx00

addr.

MSB

LSB

RTCCON

RTCH

RTC control

D1H

D2H

RTCF

RTCS1

RTCS0

ERTC

RTC register

high

00^[7]

0000 0000

RTCL

RTC register

low

D3H

A9H

S0ADDR

Serial port

address

S0ADEN

S0BUF

Serial port

address

enable

B9H

99H

0000 0000

xxxx xxxx

Serial Port

data buffer

Bit address

S0CON^[1]

S0STAT

Serial port

control

98H SM0_0/FE SM1_00

SM2_0

REN_0

TB8_0

RB8_0

TI_0

RI_0

0000 0000

Serial port

extended

BAH DBMOD_0 INTLO_0

CIDIS_0 DBISEL_0

FE_0

BR_0

OE_0

STINT_0 00

status register

Stack pointer

81H

0000 0111

0000 0100

SPCTL

SPI control

E2H

E1H

E3H

SSIG

SPIF

SPEN

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

SPSTAT

SPDAT

S1CON

S1STAT

SPI status

WCOL

00xx xxxx

0000 0000

SPI data

Serial port 1

control

B6H SM0_1/FE

SM1_1

SM2_1

REN_1

TB8_1

FE_1

RB8_1

BR_1

TI_1

RI_1

Serial port 1

extended

D4H DBMOD_1 INTLO_1

CIDIS_1 DBISEL_1

OE_1

STINT_1 00

status register

TAMOD

Timer 0 and 1

auxiliary mode

8FH

T1M2

T0M2

xxx0 xxx0

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Table 4.

Name

Special function registers …continued

Description

SFR Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

TCON^[1]

Timer 0 and 1

control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

0000 0000

TH0

TH1

TL0

Timer 0 high

Timer 1 high

Timer 0 low

Timer 1 low

8CH

8DH

8AH

8BH

89H

0000 0000

TL1

TMOD

Timer 0 and 1

mode

T1GATE

RCCLK

T1C/T

T1M1

T1M0

T0GATE

TRIM.3

T0C/T

T0M1

T0M0

[6] [7]

TRIM

Internal

oscillator trim

96H

A7H

ENCLK

TRIM.5

TRIM.4

TRIM.2

TRIM.1

TRIM.0

[5] [7]

WDCON

Watchdog

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

control register

WDL

Watchdog load C1H

1111 1111

WFEED1

Watchdog

feed 1

C2H

WFEED2

Watchdog

feed 2

C3H

[1] Indicates SFRs that are bit addressable.

[2] All ports are in input only (high-impedance) state after power-up.

[3] BRGR1_0 and BRGR0_0 must only be written if BRGEN_0 in BRGCON_0 SFR is logic 0. If any are written while BRGEN_0 = 1, the result is unpredictable.

[4] The RSTSRC register reﬂects the cause of the P89LPC952/954 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset value is

xx11 0000.

[5] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

[6] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[7] The only reset source that affects these SFRs is power-on reset.

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Table 5.

Name

Extended special function registers

Description

SFR

Bit functions and addresses

MSB

Reset value

Hex Binary

addr.

LSB

ADC0HBND ADC0 high_boundary

FFEFH

FFEEH

1111 1111

ADC0LBND ADC0 low_boundary

0000 0000

AD0DAT0R ADC0 data register 0, right FFFEH

(LSB)

AD0DAT0[7:0]

AD0DAT0[9:2]

AD0DAT1[7:0]

AD0DAT1[9:2]

AD0DAT2[7:0]

AD0DAT2[9:2]

AD0DAT3[7:0]

AD0DAT3[9:2]

AD0DAT4[7:0]

AD0DAT4[9:2]

AD0DAT5[7:0]

AD0DAT5[9:2]

AD0DAT6[7:0]

AD0DAT6[9:2]

AD0DAT7[7:0]

AD0DAT0L

ADC0 data register 0, left

(MSB)

FFFFH

AD0DAT1R ADC0 data register 1, right FFFCH

(LSB)

AD0DAT1L

ADC0 data register 1, left

(MSB)

FFFDH

AD0DAT2R ADC0 data register 2, right FFFAH

(LSB)

AD0DAT2L

ADC0 data register 2, left

(MSB)

FFFBH

AD0DAT3R ADC0 data register 3, right FFF8H

(LSB)

AD0DAT3L

ADC0 data register 3, left

(MSB)

FFF9H

AD0DAT4R ADC0 data register 4, right FFF6H

(LSB)

AD0DAT4L

ADC0 data register 4, left

(MSB)

FFF7H

AD0DAT5R ADC0 data register 5, right FFF4H

(LSB)

AD0DAT5L

ADC0 data register 5, left

(MSB)

FFF5H

AD0DAT6R ADC0 data register 6, right FFF2H

(LSB)

AD0DAT6L

ADC0 data register 6, left

(MSB)

FFF3H

AD0DAT7R ADC0 data register 7, right FFF0H

(LSB)

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Table 5.

Name

Extended special function registers …continued

Description

SFR

Bit functions and addresses

MSB

Reset value

Hex Binary

addr.

LSB

AD0DAT7L

BNDSTA0

ADC0 data register 7, left

(MSB)

FFF1H

FFEDH

FFB3H

AD0DAT7[9:2]

ADC0 boundary status

BRGCON_1 Baud rate generator 1

control

SBRGS_1 BRGEN_1 00^[2]xxxx xx00

BRG0_1

Baud rate generator 1 rate FFB4H

low

BRG1_1

Baud rate generator 1 rate FFB5H

high

FREEZE

P4M1

Peripheral clock freeze

Port 4 output mode 1

Port 4 output mode 2

Port 5 output mode 1

Port 5 output mode 3

FFD0H

RTC_F

CCU_F

WDT_F T1_F

T0_F

xxx0 0000

FFB8H (P4M1.7) (P4M1.6) (P4M1.5) (P4M1.4) (P4M1.3) (P4M1.2) (P4M1.1) (P4M1.0) FF^[1]1111 1111

FFB9H (P4M2.7) (P4M2.6) (P4M2.5) (P4M2.4) (P4M2.3) (P4M2.2) (P4M2.1) (P4M2.0) 00^[1]0000 0000

FFBAH (P5M1.7) (P5M1.6) (P5M1.5) (P5M1.4) (P5M1.3) (P5M1.2) (P5M1.1) (P5M1.0) FF^[1]1111 1111

FFBBH (P5M2.7) (P5M2.6) (P5M2.5) (P5M2.4) (P5M2.3) (P5M2.2) (P5M2.1) (P5M2.0) 00^[1]0000 0000

P4M2

P5M1

P5M2

S1ADDR

Serial port 1 address

FFB2H

FFB1H

FFB0H

0000 0000

xxxx xxxx

S1ADEN

S1BUF

Serial port 1 address

enable

Serial port 1 data buffer

[1] Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are

used to access these extended SFRs.

[2] BRGR1_1 and BRGR0_1 must only be written if BRGEN_1 in BRGCON_1 SFR is logic 0. If any are written while BRGEN_1 = 1, the result is unpredictable.

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

7.2 Enhanced CPU

The P89LPC952/954 uses an enhanced 80C51 CPU which runs at six times the speed of

standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most

instructions execute in one or two machine cycles.

7.3 Clocks

7.3.1 Clock deﬁnitions

The P89LPC952/954 device has several internal clocks as deﬁned below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock

sources (see Figure 6) and can also be optionally divided to a slower frequency (see

Section 7.8 “CCLK modiﬁcation: DIVM register”).

Note: f_oscis deﬁned as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine

cycle, and most instructions are executed in one to two machine cycles (two or four CCLK

cycles).

RCCLK — The internal 7.373 MHz RC oscillator output. The clock doubler option, when

enabled, provides an output frequency of 14.746 MHz.

PCLK — Clock for the various peripheral devices and is ^CCLK⁄₂.

7.3.2 CPU clock (OSCCLK)

The P89LPC952/954 provides several user-selectable oscillator options in generating the

CPU clock. This allows optimization for a range of needs from high precision to lowest

possible cost. These options are conﬁgured when the ﬂash is programmed and include an

on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external

crystal, or an external clock source. The crystal oscillator can be optimized for low,

medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.

7.3.3 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic

resonators are also supported in this conﬁguration.

7.3.4 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic

resonators are also supported in this conﬁguration.

7.3.5 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic

resonators are also supported in this conﬁguration. When using a clock frequency

above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit

is required to hold the device in reset at power-up until V_DDhas reached its

speciﬁed level. When system power is removed V_DDwill fall below the minimum

speciﬁed operating voltage. When using a clock frequency above 12 MHz, in some

applications, an external brownout detect circuit may be required to hold the device

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

23 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

in reset when V_DDfalls below the minimum speciﬁed operating voltage. These

requirements for clock frequencies above 12 MHz do not apply when using the

internal RC oscillator in clock doubler mode.

7.3.6 Clock output

The P89LPC952/954 supports a user-selectable clock output function on the

XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if

another clock source has been selected (on-chip RC oscillator, watchdog oscillator,

external clock input on XTAL1) and if the RTC is not using the crystal oscillator as its clock

source. This allows external devices to synchronize to the P89LPC952/954. This output is

enabled by the ENCLK bit in the TRIM register.

The frequency of this clock output is ¹⁄₂that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power.

7.4 On-chip RC oscillator option

The P89LPC952/954 has a 6-bit TRIM register that can be used to tune the frequency of

the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed

value to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature.

End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to

other frequencies. When the clock doubler option is enabled (UCFG1.3 = 1), the output

frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can

be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing

highest performance access. This bit can then be set in software if CCLK is running at

8 MHz or slower.

The requirements in Section 7.3.5 “High speed oscillator option” for conﬁguring P1.5 as

an external reset input and using an external reset circuit when the clock frequency is

greater than 12 MHz do not apply when using the internal RC oscillator’s clock doubler

option.

7.5 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator

can be used to save power when a high clock frequency is not needed.

7.6 External clock input option

In this conﬁguration, the processor clock is derived from an external source driving the

P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be

used as a standard port pin or a clock output.

When using an external clock input frequency above 12 MHz, the reset input

function of P1.5 must be enabled. An external circuit is required to hold the device

in reset at power-up until V_DDhas reached its speciﬁed level. When system power is

removed V_DDwill fall below the minimum speciﬁed operating voltage. When using

an external clock input frequency above 12 MHz, in some applications, an external

brownout detect circuit may be required to hold the device in reset when V_DDfalls

below the minimum speciﬁed operating voltage. These requirements for clock

frequencies above 12 MHz do not apply when using the internal RC oscillator in

clock doubler mode.

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

24 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

XTAL1

XTAL2

RTC

ADC0

RCCLK

OSCCLK

CCLK

CPU

DIVM

RCCLK

RC OSCILLATOR

WITH CLOCK DOUBLER

÷2

PCLK

WDT

(7.3728 MHz/14.7456 MHz ± 1 %)

WATCHDOG

OSCILLATOR

PCLK

(400 kHz +30 % −20 %)

TIMER 0 AND

TIMER 1

I C-BUS

SPI

UARTS

002aab409

Fig 6. Block diagram of oscillator control

7.7 CCLK wake-up delay

The P89LPC952/954 has an internal wake-up timer that delays the clock until it stabilizes

depending on the clock source used. If the clock source is any of the three crystal

selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus

60 µs to 100 µs. If the clock source is either the internal RC oscillator, watchdog oscillator,

or external clock, the delay is 224 OSCCLK cycles plus 60 µs to 100 µs.

7.8 CCLK modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can

retain the ability to respond to events that would not exit Idle mode by executing its normal

program at a lower rate. This can also allow bypassing the oscillator start-up time in cases

where Power-down mode would otherwise be used. The value of DIVM may be changed

by the program at any time without interrupting code execution.

7.9 Low power select

The P89LPC952/954 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK

is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power

consumption further. On any reset, CLKLP is ‘0’ allowing highest performance access.

This bit can then be set in software if CCLK is running at 8 MHz or slower.

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8-bit microcontroller with 10-bit ADC

7.10 Memory organization

The various P89LPC952/954 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect

addressing, using instructions other than MOVX and MOVC. All or part of the Stack

may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via

indirect addressing using instructions other than MOVX and MOVC. All or part of the

Stack may be in this area. This area includes the DATA area and the 128 bytes

immediately above it.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and status

registers, accessible only via direct addressing.

• XDATA

‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space

addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this

space could be implemented on-chip. The P89LPC952/954 has 256 bytes of on-chip

XDATA memory, plus extended SFRs located in XDATA.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC952/954 has 8 kB/16 kB of on-chip Code memory.

7.11 Data RAM arrangement

The 768 bytes of on-chip RAM are organized as shown in Table 6.

Table 6.

Type

On-chip data memory usages

Data RAM

Size (bytes)

128

DATA

Memory that can be addressed directly and indirectly

Memory that can be addressed indirectly

IDATA

XDATA

256

Auxiliary (‘External Data’) on-chip memory that is accessed

using the MOVX instructions

256

7.12 Interrupts

The P89LPC952/954 uses a four priority level interrupt structure. This allows great

ﬂexibility in controlling the handling of the many interrupt sources. The P89LPC952/954

supports 17 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port 0 TX,

serial port 0 RX, combined serial port 0 RX/TX, serial port 1 TX, serial port 1 RX,

combined serial port 1 RX/TX, brownout detect, watchdog/RTC, I²C-bus, keyboard,

comparators 1 and 2, SPI, and ADC completion.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in

the interrupt enable registers IEN0, IEN1 or IEN2. The IEN0 register also contains a

global disable bit, EA, which disables all interrupts.

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8-bit microcontroller with 10-bit ADC

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, IP1H, IP2, and

IP2H. An interrupt service routine in progress can be interrupted by a higher priority

interrupt, but not by another interrupt of the same or lower priority. The highest priority

interrupt service cannot be interrupted by any other interrupt source. If two requests of

different priority levels are pending at the start of an instruction, the request of higher

priority level is serviced.

If requests of the same priority level are pending at the start of an instruction, an internal

polling sequence determines which request is serviced. This is called the arbitration

ranking. Note that the arbitration ranking is only used to resolve pending requests of the

same priority level.

7.12.1 External interrupt inputs

The P89LPC952/954 has two external interrupt inputs as well as the Keypad Interrupt

function. The two interrupt inputs are identical to those present on the standard 80C51

microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by

setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle

and a LOW in the next cycle, the interrupt request ﬂag IEn in TCON is set, causing an

interrupt request.

If an external interrupt is enabled when the P89LPC952/954 is put into Power-down or Idle

mode, the interrupt will cause the processor to wake-up and resume operation. Refer to

Section 7.15 “Power reduction modes” for details.

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8-bit microcontroller with 10-bit ADC

IE0

EX0

IE1

EX1

BOF

EBO

wake-up

(if in power-down)

RTCF

KBIF

EKBI

ERTC

(RTCCON.1)

WDOVF

EWDRT

CMF2

CMF1

EA (IE0.7)

TF0

ET0

TF1

ET1

TI_0 and RI_0/RI_0

ES/ESR

TI_0

EST

interrupt

to CPU

EI2C

SPIF

ESPI

TI_1 and RI_1/RI_1

ES1/ESR1

TI_1

EST1

ENADCI0

ADCI0

ENBI0

BNDI0

EADC

002aab408

Fig 7. Interrupt sources, interrupt enables, and power-down wake-up sources

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8-bit microcontroller with 10-bit ADC

7.13 I/O ports

The P89LPC952/954 has six I/O ports: Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5.

Ports 0, 1, 2, 4, and 5 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O

pins available depends upon the clock and reset options and package chosen, as shown

in Table 7.

Table 7.

Number of I/O pins available

Clock source

Reset option

Number of I/O pins Number of I/O pins

(48-pin package)

No external reset (except during power-up) 42

External RST pin supported 41

No external reset (except during power-up) 41

External RST pin supported^[1]

(44-pin package)

On-chip oscillator or watchdog

oscillator

External clock input

Low/medium/high speed oscillator No external reset (except during power-up) 40

(external crystal or resonator)

External RST pin supported^[1]

[1] Required for operation above 12 MHz.

7.13.1 Port conﬁgurations

All but three I/O port pins on the P89LPC952/954 may be conﬁgured by software to one of

four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port

outputs), push-pull, open drain, and input-only. Two conﬁguration registers for each port

select the output type for each port pin.

1. P1.5/RST can only be an input and cannot be conﬁgured.

2. P1.2/T0/SCL and P1.3/INT0/SDA may only be conﬁgured to be either input-only or

open-drain.

7.13.1.1 Quasi-bidirectional output conﬁguration

Quasi-bidirectional output type can be used as both an input and output without the need

to reconﬁgure the port. This is possible because when the port outputs a logic HIGH, it is

weakly driven, allowing an external device to pull the pin LOW. When the pin is driven

LOW, it is driven strongly and able to sink a fairly large current. These features are

somewhat similar to an open-drain output except that there are three pull-up transistors in

the quasi-bidirectional output that serve different purposes.

The P89LPC952/954 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional

mode, if a user applies 5 V on the pin, there will be a current ﬂowing from the pin to V_DD

causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is

discouraged.

A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch

suppression circuit.

7.13.1.2 Open-drain output conﬁguration

The open-drain output conﬁguration turns off all pull-ups and only drives the pull-down

transistor of the port driver when the port latch contains a logic 0. To be used as a logic

output, a port conﬁgured in this manner must have an external pull-up, typically a resistor

tied to V_DD

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8-bit microcontroller with 10-bit ADC

An open-drain port pin has a Schmitt triggered input that also has a glitch suppression

circuit.

7.13.1.3 Input-only conﬁguration

The input-only port conﬁguration has no output drivers. It is a Schmitt triggered input that

also has a glitch suppression circuit.

7.13.1.4 Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes, but provides a continuous strong

pull-up when the port latch contains a logic 1. The push-pull mode may be used when

more source current is needed from a port output. A push-pull port pin has a

Schmitt triggered input that also has a glitch suppression circuit.

7.13.2 Port 0 analog functions

The P89LPC952/954 incorporates two Analog Comparators. In order to give the best

analog function performance and to minimize power consumption, pins that are being

used for analog functions must have the digital outputs and digital inputs disabled.

Digital outputs are disabled by putting the port output into the Input-Only

(high-impedance) mode.

Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5.

On any reset, PT0AD[1:5] defaults to ‘0’s to enable digital functions.

7.13.3 Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different from

the LPC76x series of devices.

• After power-up, all I/O pins except P1.5, may be conﬁgured by software.

• Pin P1.5 is input only. Pins P1.2 and P1.3 are conﬁgurable for either input-only or

open-drain.

Every output on the P89LPC952/954 has been designed to sink typical LED drive current.

However, there is a maximum total output current for all ports which must not be

exceeded. Please refer to Table 11 for detailed speciﬁcations.

All ports pins that can function as an output have slew rate controlled outputs to limit noise

generated by quickly switching output signals. The slew rate is factory-set to

approximately 10 ns rise and fall times.

7.14 Power monitoring functions

The P89LPC952/954 incorporates power monitoring functions designed to prevent

incorrect operation during initial power-up and power loss or reduction during operation.

This is accomplished with two hardware functions: Power-on detect and brownout detect.

7.14.1 Brownout detection

The brownout detect function determines if the power supply voltage drops below a

certain level. The default operation is for a brownout detection to cause a processor reset,

however it may alternatively be conﬁgured to generate an interrupt.

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Brownout detection may be enabled or disabled in software.

If brownout detection is enabled the brownout condition occurs when V_DDfalls below the

brownout trip voltage, V_bo(see Table 11 “Static characteristics”), and is negated when V_DD

rises above V_bo. If the P89LPC952/954 device is to operate with a power supply that can

be below 2.7 V, BOE should be left in the unprogrammed state so that the device can

operate at 2.4 V, otherwise continuous brownout reset may prevent the device from

operating.

For correct activation of brownout detect, the V_DDrise and fall times must be observed.

Please see Table 11 “Static characteristics” for speciﬁcations.

7.14.2 Power-on detection

The Power-on detect has a function similar to the brownout detect, but is designed to work

as power comes up initially, before the power supply voltage reaches a level where

brownout detect can work. The POF ﬂag in the RSTSRC register is set to indicate an

initial power-up condition. The POF ﬂag will remain set until cleared by software.

7.15 Power reduction modes

The P89LPC952/954 supports three different power reduction modes. These modes are

Idle mode, Power-down mode, and total Power-down mode.

7.15.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor

when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle

mode.

7.15.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. The

P89LPC952/954 exits Power-down mode via any reset, or certain interrupts. In

Power-down mode, the power supply voltage may be reduced to the data retention supply

voltage V_DDR. This retains the RAM contents at the point where Power-down mode was

entered. SFR contents are not guaranteed after V_DDhas been lowered to V_DDR, therefore

it is highly recommended to wake-up the processor via reset in this case. V_DDmust be

raised to within the operating range before the Power-down mode is exited.

Some chip functions continue to operate and draw power during Power-down mode,

increasing the total power used during power-down. These include: Brownout detect,

watchdog timer, comparators (note that comparators can be powered down separately),

and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator

has been selected as the system clock and the RTC is enabled.

7.15.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and

the voltage comparators are also disabled to conserve additional power. The internal RC

oscillator is disabled unless both the RC oscillator has been selected as the system clock

and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during

power-down, there will be high power consumption. Please use an external low frequency

clock to achieve low power with the RTC running during power-down.

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7.16 Reset

8-bit microcontroller with 10-bit ADC

The P1.5/RST pin can function as either a digital input (P1.5), an active-LOW reset input

with an internal pull-up, a bidirectional reset input/output (open drain output with an

internal pull-up), or as push-pull reset output. These modes are selected by the RPE

(Reset Pin Enable) bit in UCFG1 and the RPE1 (Reset Pin Enable 1) bit in UCFG2.

Table 8.

Reset pin modes

P1.5/RST mode

RPE1 (UCFG2.0) RPE (UCFG1.6)

General purpose input

Reset input with pull-up

Bidirectional reset input/output (open drain with pull-up)

Reset output

Remark: During a power-up sequence, the RPE and RPE1 selection is overridden and

this pin always functions as a reset input. An external circuit connected to this pin

should not hold this pin LOW during a power-on sequence as this will keep the

device in reset. After power-up this pin will function as deﬁned by the RPE and RPE1

bits. Only a power-up reset will temporarily override the selection deﬁned by RPE and

RPE1 bits. Other sources of reset will not override the RPE and RPE1 bits.

Remark: During a power cycle, V_DDmust fall below V_PORbefore power is reapplied, in

order to ensure a power-on reset (see Table 11 “Static characteristics” on page 51).

Remark: When using an oscillator frequency above 12 MHz, the reset input function of

P1.5 must be enabled. An external circuit is required to hold the device in reset at

power-up until V_DDhas reached its speciﬁed level. When system power is removed V_DD

will fall below the minimum speciﬁed operating voltage. When using an oscillator

frequency above 12 MHz, in some applications, an external brownout detect circuit may

be required to hold the device in reset when V_DDfalls below the minimum speciﬁed

operating voltage.

Reset can be triggered from the following sources:

• External reset pin (during power-up or if user conﬁgured via UCFG1, UCGF2);

• Power-on detect;

• Brownout detect;

• Watchdog timer;

• Software reset;

• UART break character detect reset.

For every reset source, there is a ﬂag in the Reset Register, RSTSRC. The user can read

this register to determine the most recent reset source. These ﬂag bits can be cleared in

software by writing a ‘0’ to the corresponding bit. More than one ﬂag bit may be set:

• During a power-on reset, both POF and BOF are set but the other ﬂag bits are

cleared.

• For any other reset, previously set ﬂag bits that have not been cleared will remain set.

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8-bit microcontroller with 10-bit ADC

7.16.1 Reset vector

Following reset, the P89LPC952/954 will fetch instructions from either address 0000H or

the Boot address. The Boot address is formed by using the boot vector as the high byte of

the address and the low byte of the address = 00H.

The Boot address will be used if a UART break reset occurs, or the non-volatile Boot

Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see

P89LPC952/954 User’s Manual). Otherwise, instructions will be fetched from address

0000H.

7.17 Timers/counters 0 and 1

The P89LPC952/954 has two general purpose counter/timers which are upward

compatible with the standard 80C51 Timer 0 and Timer 1. Both can be conﬁgured to

operate either as timers or event counters. An option to automatically toggle the T0 and/or

T1 pins upon timer overﬂow has been added.

In the ‘Timer’ function, the register is incremented every machine cycle.

In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin, T0 or T1. In this function, the external input is sampled

once during every machine cycle.

Timer 0 and Timer 1 have ﬁve operating modes (Modes 0, 1, 2, 3 and 6). Modes 0, 1, 2

and 6 are the same for both Timers/Counters. Mode 3 is different.

7.17.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit

Counter with a divide-by-32 prescaler. In this mode, the Timer register is conﬁgured as a

13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

7.17.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

7.17.3 Mode 2

Mode 2 conﬁgures the Timer register as an 8-bit Counter with automatic reload. Mode 2

operation is the same for Timer 0 and Timer 1.

7.17.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit

counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is

in Mode 3 it can still be used by the serial port as a baud rate generator.

7.17.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of

256 timer clocks.

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8-bit microcontroller with 10-bit ADC

7.17.6 Timer overﬂow toggle output

Timers 0 and 1 can be conﬁgured to automatically toggle a port output whenever a timer

overﬂow occurs. The same device pins that are used for the T0 and T1 count inputs are

also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the ﬁrst

timer overﬂow when this mode is turned on.

7.18 RTC/system timer

The P89LPC952/954 has a simple RTC that allows a user to continue running an accurate

timer while the rest of the device is powered down. The RTC can be a wake-up or an

interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a

16-bit loadable down counter. When it reaches all ‘0’s, the counter will be reloaded again

and the RTCF ﬂag will be set. The clock source for this counter can be either the CPU

clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not being used as

the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use

CCLK as its clock source. Only power-on reset will reset the RTC and its associated SFRs

to the default state.

7.19 UARTs

The P89LPC952/954 has two enhanced UARTs that are compatible with the conventional

80C51 UART except that Timer 2 overﬂow cannot be used as a baud rate source. The

P89LPC952/954 does include an independent Baud Rate Generator for each UART

(BRG0 for UART 0 and BRG1 for UART 1). The baud rate can be selected from the

oscillator (divided by a constant), Timer 1 overﬂow, or the independent Baud Rate

Generator associated with the speciﬁc UART. In addition to the baud rate generation,

enhancements over the standard 80C51 UART include Framing Error detection,

automatic address recognition, selectable double buffering and several interrupt options.

The UARTs can be operated in 4 modes: shift register, 8-bit UART, 9-bit UART, and CPU

clock/32 or CPU clock/16.

7.19.1 Mode 0

Serial data enters and exits through RXDn. TXDn outputs the shift clock. 8 bits are

transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at ¹⁄₁₆of the CPU clock

frequency.

7.19.2 Mode 1

10 bits are transmitted (through TXDn) or received (through RXDn): a start bit (logic 0),

8 data bits (LSB ﬁrst), and a stop bit (logic 1). When data is received, the stop bit is stored

in RB8_n in Special Function Register SnCON. The baud rate is variable and is

determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in Section

7.19.5 “Baud rate generator and selection”).

7.19.3 Mode 2

11 bits are transmitted (through TXDn) or received (through RXDn): start bit (logic 0),

8 data bits (LSB ﬁrst), a programmable 9^thdata bit, and a stop bit (logic 1). When data is

transmitted, the 9^thdata bit (TB8_n in SnCON) can be assigned the value of ‘0’ or ‘1’. Or,

for example, the parity bit (P, in the PSW) could be moved into TB8_n. When data is

received, the 9^thdata bit goes into RB8_n in Special Function Register SnCON, while the

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8-bit microcontroller with 10-bit ADC

stop bit is not saved. The baud rate is programmable to either ¹⁄₁₆or ¹⁄₃₂of the CPU clock

frequency, as determined by the SMOD1 bit in PCON. The SMOD1 bit controls the Timer

1 output rate available to both UARTs.

7.19.4 Mode 3

11 bits are transmitted (through TXDn) or received (through RXDn): a start bit (logic 0), 8

data bits (LSB ﬁrst), a programmable 9^thdata bit, and a stop bit (logic 1). In fact, Mode 3 is

the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable

and is determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in

Section 7.19.5 “Baud rate generator and selection”).

7.19.5 Baud rate generator and selection

Each enhanced UART has an independent Baud Rate Generator. The baud rate is

determined by a baud-rate preprogrammed into the BRGR1_n and BRGR0_n SFRs

which together form a 16-bit baud rate divisor value that works in a similar manner as

Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be

used for other timing functions.

The UARTs can use either Timer 1 or their respective baud rate generator output (see

Figure 8). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared.

The independent Baud Rate Generators use OSCCLK.

timer 1 overflow

SMOD1 = 1

(PCLK-based)

SBRGS = 0

SBRGS = 1

÷2

baud rate modes 1 and 3

002aaa897

SMOD1 = 0

baud rate generator

(CCLK-based)

Fig 8. Baud rate sources for UART (Modes 1, 3)

7.19.6 Framing error

Framing error is reported in the status register (SnSTAT). In addition, if SMOD0 (PCON.6)

is ‘1’, framing errors can be made available in SnCON.7 respectively. If SMOD0 is ‘0’,

SnCON.7 is SM0_n. It is recommended that SM0_n and SM1_n (SnCON.7:6) are set up

when SMOD0 is ‘0’.

7.19.7 Break detect

Break detect is reported in the status register (SnSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the device

and force the device into ISP mode.

7.19.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be

written to SnBUF while the ﬁrst character is being transmitted. Double buffering allows

transmission of a string of characters with only one stop bit between any two characters,

as long as the next character is written between the start bit and the stop bit of the

previous character.

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8-bit microcontroller with 10-bit ADC

Double buffering can be disabled. If disabled (DBMOD_n, i.e., SnSTAT.7 = 0), the UART is

compatible with the conventional 80C51 UART. If enabled, the UART allows writing to

SnBUF while the previous data is being shifted out. Double buffering is only allowed in

Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled

(DBMOD_n = 0).

7.19.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the TI_n interrupt is generated

when the double buffer is ready to receive new data.

7.19.10 The 9^thbit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8_n can be written before or after SnBUF is written, as

long as TB8_n is updated some time before that bit is shifted out. TB8_n must not be

changed until the bit is shifted out, as indicated by the TI_n interrupt.

If double buffering is enabled, TB8_n must be updated before SnBUF is written, as TB8_n

will be double-buffered together with SnBUF data.

7.20 I²C-bus serial interface

I²C-bus uses two wires (SDA and SCL) to transfer information between devices connected

to the bus, and it has the following features:

• Bidirectional data transfer between masters and slaves

• Multi master bus (no central master)

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer

• The I²C-bus may be used for test and diagnostic purposes.

A typical I²C-bus conﬁguration is shown in Figure 9. The P89LPC952/954 device provides

a byte-oriented I²C-bus interface that supports data transfers up to 400 kHz.

SDA

SCL

I C-bus

OTHER DEVICE

WITH I C-BUS

INTERFACE

OTHER DEVICE

WITH I C-BUS

INTERFACE

P1.3/SDA

P1.2/SCL

I C MCU

002aab410

Fig 9. I²C-bus conﬁguration

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8-bit microcontroller with 10-bit ADC

I2ADR

ADDRESS REGISTER

COMPARATOR

P1.3

INPUT

FILTER

P1.3/SDA

SHIFT REGISTER

ACK

I2DAT

OUTPUT

STAGE

BIT COUNTER /

ARBITRATION

AND SYNC LOGIC

CCLK

INPUT

FILTER

TIMING

AND

CONTROL

LOGIC

P1.2/SCL

SERIAL CLOCK

GENERATOR

OUTPUT

STAGE

interrupt

timer 1

overflow

P1.2

I2CON

I2SCLH

I2SCLL

CONTROL REGISTERS AND

SCL DUTY CYCLE REGISTERS

STATUS

DECODER

status bus

I2STAT

STATUS REGISTER

002aaa899

Fig 10. I²C-bus serial interface block diagram

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P89LPC952/954

NXP Semiconductors

7.21 SPI

8-bit microcontroller with 10-bit ADC

The P89LPC952/954 provides another high-speed serial communication interface — the

SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two

operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either

Master or Slave mode. It has a Transfer Completion Flag and Write Collision Flag

Protection.

MISO

P2.3

CPU clock

8-BIT SHIFT REGISTER

READ DATA BUFFER

MOSI

P2.2

CONTROL

LOGIC

DIVIDER

BY 4, 16, 64, 128

SPICLK

P2.5

clock

SPI clock (master)

SELECT

P2.4

CLOCK LOGIC

MSTR

SPEN

SPI CONTROL

SPI CONTROL REGISTER

SPI STATUS REGISTER

SPI

interrupt

request

internal

data

bus

002aaa900

Fig 11. SPI block diagram

The SPI interface has four pins: SPICLK, MOSI, MISO and SS:

• SPICLK, MOSI and MISO are typically tied together between two or more SPI

devices. Data ﬂows from master to slave on MOSI (Master Out Slave In) pin and ﬂows

from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output

in the Master mode and is input in the Slave mode. If the SPI system is disabled, i.e.,

SPEN (SPCTL.6) = 0 (reset value), these pins are conﬁgured for port functions.

• SS is the optional slave select pin. In a typical conﬁguration, an SPI master asserts

one of its port pins to select one SPI device as the current slave. An SPI slave device

uses its SS pin to determine whether it is selected.

Typical connections are shown in Figure 12 through Figure 14.

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P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

7.21.1 Typical SPI conﬁgurations

master

slave

MISO

MOSI

MISO

8-BIT SHIFT

MOSI

SPICLK

PORT

SPICLK

SPI CLOCK

GENERATOR

002aaa901

Fig 12. SPI single master single slave conﬁguration

master

slave

MISO

MOSI

8-BIT SHIFT

MOSI

SPICLK

SPI CLOCK

GENERATOR

SPI CLOCK

GENERATOR

002aaa902

Fig 13. SPI dual device conﬁguration, where either can be a master or a slave

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P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

master

slave

MISO

MOSI

MISO

8-BIT SHIFT

MOSI

SPICLK

port

SPICLK

SPI CLOCK

GENERATOR

slave

MISO

MOSI

8-BIT SHIFT

SPICLK

port

002aaa903

Fig 14. SPI single master multiple slaves conﬁguration

7.22 Analog comparators

Two analog comparators are provided on the P89LPC952/954. Input and output options

allow use of the comparators in a number of different conﬁgurations. Comparator

operation is such that the output is a logical one (which may be read in a register and/or

routed to a pin) when the positive input (one of two selectable pins) is greater than the

negative input (selectable from a pin or an internal reference voltage). Otherwise the

output is a zero. Each comparator may be conﬁgured to cause an interrupt when the

output value changes.

The overall connections to both comparators are shown in Figure 15. The comparators

function to V_DD= 2.4 V.

When each comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are not

guaranteed to be stable for 10 µs. The corresponding comparator interrupt should not be

enabled during that time, and the comparator interrupt ﬂag must be cleared before the

interrupt is enabled in order to prevent an immediate interrupt service.

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P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

CP1

OE1

comparator 1

CO1

(P0.4) CIN1A

(P0.3) CIN1B

CMP1 (P0.6)

(P0.5) CMPREF

change detect

ref(bg)

CMF1

CMF2

CN1

CP2

interrupt

change detect

comparator 2

(P0.2) CIN2A

(P0.1) CIN2B

CMP2 (P0.0)

002aaa904

CO2

OE2

CN2

Fig 15. Comparator input and output connections

7.22.1 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single

comparator input pin is used. The value of the internal reference voltage, referred to as

V_ref(bg), is 1.23 V ± 10 %.

7.22.2 Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag is

set whenever the comparator output changes state. The ﬂag may be polled by software or

may be used to generate an interrupt. The two comparators use one common interrupt

vector. If both comparators enable interrupts, after entering the interrupt service routine,

the user needs to read the ﬂags to determine which comparator caused the interrupt.

7.22.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is

activated, but both comparators are disabled automatically in Total Power-down mode.

If a comparator interrupt is enabled (except in Total Power-down mode), a change of the

comparator output state will generate an interrupt and wake-up the processor. If the

comparator output to a pin is enabled, the pin should be conﬁgured in the push-pull mode

in order to obtain fast switching times while in Power-down mode. The reason is that with

the oscillator stopped, the temporary strong pull-up that normally occurs during switching

on a quasi-bidirectional port pin does not take place.

Comparators consume power in Power-down and Idle modes, as well as in the normal

operating mode. This fact should be taken into account when system power consumption

is an issue. To minimize power consumption, the user can disable the comparators via

PCONA.5, or put the device in Total Power-down mode.

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7.23 KBI

8-bit microcontroller with 10-bit ADC

The Keypad Interrupt function is intended primarily to allow a single interrupt to be

generated when Port 0 is equal to or not equal to a certain pattern. This function can be

used for bus address recognition or keypad recognition. The user can conﬁgure the port

via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to deﬁne which input pins

connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is

used to deﬁne a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag

(KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is

matched while the Keypad Interrupt function is active. An interrupt will be generated if

enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to

deﬁne equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series,

the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key

connected to Port 0 which is enabled by the KBMASK register will cause the hardware to

set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to

wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in

handheld, battery-powered systems that need to carefully manage power consumption

yet also need to be convenient to use.

In order to set the ﬂag and cause an interrupt, the pattern on Port 0 must be held longer

than six CCLKs.

7.24 Watchdog timer

The watchdog timer causes a system reset when it underﬂows as a result of a failure to

feed the timer prior to the timer reaching its terminal count. It consists of a programmable

12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap

taken from the prescaler. The clock source for the prescaler is either the PCLK or the

nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a

power-on reset. When the watchdog feature is disabled, it can be used as an interval timer

and may generate an interrupt. Figure 16 shows the watchdog timer in Watchdog mode.

Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog

clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a

time-out period that ranges from a few µs to a few seconds. Please refer to the

P89LPC952/954 User’s Manual for more details.

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P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

WDL (C1H)

MOV WFEED1, #0A5H

MOV WFEED2, #05AH

watchdog

oscillator

PCLK

8-BIT DOWN

COUNTER

(1)

PRESCALER

reset

÷32

SHADOW REGISTER

PRE2

PRE1

PRE0

WDRUN WDTOF WDCLK

WDCON (A7H)

002aaa905

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed

sequence.

Fig 16. Watchdog timer in Watchdog mode (WDTE = 1)

7.25 Additional features

7.25.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,

as if an external reset or watchdog reset had occurred. Care should be taken when writing

to AUXR1 to avoid accidental software resets.

7.25.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address

used with certain instructions. The DPS bit in the AUXR1 register selects one of the two

Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may

be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,

without the possibility of inadvertently altering other bits in the register.

7.25.3 Debugger interface

This device contains a two-wire serial debugger interface designed to be used with

commercially available debugging tools. An additional trigger output is provided that

maybe triggered using the two-wire debugger interface.

The Freeze register allows the user to selectively disable clocking of peripheral device

timers while in the debugger mode.

The two-wire serial debugger interface can also be used be used to program the code

memory of these devices.

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P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

7.26 Flash program memory

7.26.1 General description

The P89LPC952/954 ﬂash memory provides in-circuit electrical erasure and

programming. The ﬂash can be erased, read, and written as bytes. The Sector and Page

Erase functions can erase any ﬂash sector (1 kB) or page (64 bytes). The Chip Erase

operation will erase the entire program memory. ICP using standard commercial

programmers is available. In addition, IAP and byte-erase allows code memory to be used

for non-volatile data storage. On-chip erase and write timing generation contribute to a

user-friendly programming interface. The P89LPC952/954 ﬂash reliably stores memory

contents even after 400,000 erase and program cycles. The cell is designed to optimize

the erase and programming mechanisms. The P89LPC952/954 uses V_DDas the supply

voltage to perform the Program/Erase algorithms.

7.26.2 Features

• Programming and erase over the full operating voltage range.

• Byte erase allows code memory to be used for data storage.

• Read/Programming/Erase using ISP, IAP, ICP, or two-wire serial debugger.

• Internal ﬁxed boot ROM, containing low-level IAP routines available to user code.

• Default loader providing ISP via the serial port, located in upper end of user program

memory.

• Boot vector allows user-provided ﬂash loader code to reside anywhere in the ﬂash

memory space, providing ﬂexibility to the user.

• Any ﬂash program/erase operation in 2 ms.

• Programming with industry-standard commercial programmers.

• Programmable security for the code in the ﬂash for each sector.

• 400,000 typical erase/program cycles for each byte.

• 20 year minimum data retention.

7.26.3 Flash organization

The program memory consists of eight/sixteen 1 kB sectors on the P89LPC952/954

devices. Each sector can be further divided into 64-byte pages. In addition to sector

erase, page erase, and byte erase, a 64-byte page register is included which allows from

1 to 64 bytes of a given page to be programmed at the same time, substantially reducing

overall programming time.

7.26.4 Using ﬂash as data storage

The ﬂash code memory array of this device supports individual byte erasing and

programming. Any byte in the code memory array may be read using the MOVC

instruction, provided that the sector containing the byte has not been secured (a MOVC

instruction is not allowed to read code memory contents of a secured sector). Thus any

byte in a non-secured sector may be used for non-volatile data storage.

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P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

7.26.5 Flash programming and erasing

Four different methods of erasing or programming of the ﬂash are available. The ﬂash may

be programmed or erased in the end-user application (IAP) under control of the

application’s ﬁrmware. Another option is to use the ICP mechanism. This ICP system

provides for programming through a serial clock/serial data interface. As shipped from the

factory, the upper 512 bytes of user code space contains a serial ISP routine allowing for

the device to be programmed in circuit through the serial port. The ﬂash may also be

programmed or erased using a commercially available EPROM programmer which

supports this device. This device does not provide for direct veriﬁcation of code memory

contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire

user code space.

7.26.6 ICP

ICP is performed without removing the microcontroller from the system. The ICP facility

consists of internal hardware resources to facilitate remote programming of the

P89LPC952/954 through a two-wire serial interface. The Philips ICP facility has made

in-circuit programming in an embedded application—using commercially available

programmers—possible with a minimum of additional expense in components and circuit

board area. The ICP function uses ﬁve pins. Only a small connector needs to be available

to interface your application to a commercial programmer in order to use this feature.

Additional details may be found in the P89LPC952/954 User’s Manual.

7.26.7 IAP

IAP is performed in the application under the control of the microcontroller’s ﬁrmware. The

IAP facility consists of internal hardware resources to facilitate programming and erasing.

The Philips IAP has made in-application programming in an embedded application

possible without additional components. Two methods are available to accomplish IAP. A

set of predeﬁned IAP functions are provided in a Boot ROM and can be called through a

common interface, PGM_MTP. Several IAP calls are available for use by an application

program to permit selective erasing and programming of ﬂash sectors, pages, security

bits, conﬁguration bytes, and device ID. These functions are selected by setting up the

microcontroller’s registers before making a call to PGM_MTP at FF03H. The Boot ROM

occupies the program memory space at the top of the address space from FF00H to

FEFFH, thereby not conﬂicting with the user program memory space.

In addition, IAP operations can be accomplished through the use of four SFRs consisting

of a control/status register, a data register, and two address registers. Additional details

may be found in the P89LPC952/954 User’s Manual.

7.26.8 ISP

ISP is performed without removing the microcontroller from the system. The ISP facility

consists of a series of internal hardware resources coupled with internal ﬁrmware to

facilitate remote programming of the P89LPC952/954 through the serial port. This

ﬁrmware is provided by Philips and embedded within each P89LPC952/954 device. The

Philips ISP facility has made in-system programming in an embedded application possible

with a minimum of additional expense in components and circuit board area. The ISP

function uses ﬁve pins (V_DD, V_SS, TXD, RXD, and RST). Only a small connector needs to

be available to interface your application to an external circuit in order to use this feature.

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P89LPC952/954

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8-bit microcontroller with 10-bit ADC

7.26.9 Power-on reset code execution

The P89LPC952/954 contains two special ﬂash elements: the Boot Vector and the Boot

Status bit. Following reset, the P89LPC952/954 examines the contents of the Boot Status

bit. If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which

is the normal start address of the user’s application code. When the Boot Status bit is set

to a value other than zero, the contents of the Boot Vector are used as the high byte of the

execution address and the low byte is set to 00H.

Table 9 shows the factory default Boot Vector setting for these devices. A factory-provided

bootloader is pre-programmed into the address space indicated and uses the indicated

bootloader entry point to perform ISP functions. This code can be erased by the user.

Users who wish to use this loader should take precautions to avoid erasing the

1 kB sector that contains this bootloader. Instead, the page erase function can be

used to erase the ﬁrst eight 64-byte pages located in this sector. A custom

bootloader can be written with the Boot Vector set to the custom bootloader, if desired.

Table 9.

Device

Default boot vector values and ISP entry points

Default

Default bootloader 1 kB sector

boot vector

bootloader

entry point

code range

range

P89LPC952

P89LPC954

1FH

3FH

1F00H

3F00H

1E00H to 1FFFH

3E00H to 3FFFH

1C00H to 1FFFH

3C00H to 3FFFH

7.26.10 Hardware activation of the bootloader

The bootloader can also be executed by forcing the device into ISP mode during a

power-on sequence (see the P89LPC952/954 User’s Manual for speciﬁc information).

This has the same effect as having a non-zero status byte. This allows an application to

be built that will normally execute user code but can be manually forced into ISP

operation. If the factory default setting for the boot vector (1FH/3FH) is changed, it will no

longer point to the factory pre-programmed ISP bootloader code. After programming the

ﬂash, the status byte should be programmed to zero in order to allow execution of the

user’s application code beginning at address 0000H.

7.27 User conﬁguration bytes

Some user-conﬁgurable features of the P89LPC952/954 must be deﬁned at power-up and

therefore cannot be set by the program after start of execution. These features are

conﬁgured through the use of the ﬂash byte UCFG1. Please see the P89LPC952/954

User’s Manual for additional details.

7.28 User sector security bytes

There are eight/sixteen User Sector Security Bytes on the P89LPC952/954. Each byte

corresponds to one sector. Please see the P89LPC952/954 User’s Manual for additional

details.

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8-bit microcontroller with 10-bit ADC

8. ADC

8.1 General description

The P89LPC952/954 has a 10-bit, 8-channel multiplexed successive approximation ADC

module. A block diagram of the ADC is shown in Figure 17. The ADC consists of an

8-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one

of two comparator inputs. The control logic in combination with the SAR drives a DAC

which provides the other input to the comparator. The output of the comparator is fed to

the SAR.

8.2 Features

I 10-bit, 8-channel multiplexed input, successive approximation ADC.

I Eight result register pairs.

I Six operating modes:

N Fixed channel, single conversion mode.

N Fixed channel, continuous conversion mode.

N Auto scan, single conversion mode.

N Auto scan, continuous conversion mode.

N Dual channel, continuous conversion mode.

N Single step mode.

I Three conversion start modes:

N Timer triggered start.

N Start immediately.

N Edge triggered.

I 10-bit conversion time of 4 µs at an A/D clock of 9 MHz.

I Interrupt or polled operation.

I High and low boundary limits interrupt; selectable in or out-of-range.

I Clock divider.

I Power-down mode.

8.3 Block diagram

comp

INPUT

MUX

SAR

–

CONTROL

LOGIC

DAC0

CCLK

002aab103

Fig 17. ADC block diagram

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8-bit microcontroller with 10-bit ADC

8.4 ADC operating modes

8.4.1 Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be

performed and the result placed in the result register pair which corresponds to the

selected input channel. An interrupt, if enabled, will be generated after the conversion

completes.

8.4.2 Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the

conversions will be sequentially placed in the eight result register pairs. The user may

select whether an interrupt can be generated after every four or every eight conversions.

Additional conversion results will again cycle through the result register pairs, overwriting

the previous results. Continuous conversions continue until terminated by the user.

8.4.3 Auto scan, single conversion mode

Any combination of the eight input channels can be selected for conversion. A single

conversion of each selected input will be performed and the result placed in the result

whether an interrupt, if enabled, will be generated after either the ﬁrst four conversions

have occurred or all selected channels have been converted. If the user selects to

generate an interrupt after the four input channels have been converted, a second

interrupt will be generated after the remaining input channels have been converted. If only

a single channel is selected this is equivalent to single channel, single conversion mode.

8.4.4 Auto scan, continuous conversion mode

Any combination of the eight input channels can be selected for conversion. A conversion

of each selected input will be performed and the result placed in the result register pair

which corresponds to the selected input channel. The user may select whether an

interrupt, if enabled, will be generated after either the ﬁrst four conversions have occurred

or all selected channels have been converted. If the user selects to generate an interrupt

after the four input channels have been converted, a second interrupt will be generated

after the remaining input channels have been converted. After all selected channels have

been converted, the process will repeat starting with the ﬁrst selected channel. Additional

conversion results will again cycle through the eight result register pairs, overwriting the

previous results. Continuous conversions continue until terminated by the user.

8.4.5 Dual channel, continuous conversion mode

This is a variation of the auto scan continuous conversion mode where conversion occurs

on two user-selectable inputs. The result of the conversion of the ﬁrst channel is placed in

the result register pair, AD0DAT0R and AD0DAT0L. The result of the conversion of the

second channel is placed in result register pair, AD0DAT1R and AD0DAT1L. The ﬁrst

channel is again converted and its result stored in AD0DAT2R and AD0DAT2L. The

second channel is again converted and its result placed in AD0DAT3R and AD0DAT3L,

etc. An interrupt is generated, if enabled, after every set of four or eight conversions (user

selectable).

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8-bit microcontroller with 10-bit ADC

8.4.6 Single step mode

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any

combination of the eight input channels can be selected for conversion. After each

channel is converted, an interrupt is generated, if enabled, and the ADC waits for the next

start condition. May be used with any of the start modes.

8.5 Conversion start modes

8.5.1 Timer triggered start

An A/D conversion is started by the overﬂow of Timer 0. Once a conversion has started,

additional Timer 0 triggers are ignored until the conversion has completed. The Timer

triggered start mode is available in all ADC operating modes.

8.5.2 Start immediately

Programming this mode immediately starts a conversion. This start mode is available in all

ADC operating modes.

8.5.3 Edge triggered

An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has

started, additional edge triggers are ignored until the conversion has completed. The edge

triggered start mode is available in all ADC operating modes.

8.6 Boundary limits interrupt

The ADC has both a high and low boundary limit register. The user may select whether an

interrupt is generated when the conversion result is within (or equal to) the high and low

boundary limits or when the conversion result is outside the boundary limits. An interrupt

will be generated, if enabled, if the result meets the selected interrupt criteria. The

boundary limit may be disabled by clearing the boundary limit interrupt enable.

An early detection mechanism exists when the interrupt criteria has been selected to be

outside the boundary limits. In this case, after the four MSBs have been converted, these

four bits are compared with the four MSBs of the boundary high and low registers. If the

four MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits)

an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt

criteria, the boundary limits will again be compared after all 8 MSBs have been converted.

A boundary status register (BNDSTA0) ﬂags the channels which caused a boundary

interrupt.

8.7 Clock divider

The ADC requires that its internal clock source be in the range of 320 kHz to 9 MHz to

maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is

provided for this purpose.

8.8 Power-down and Idle mode

In Idle mode the ADC, if enabled, will continue to function and can cause the device to exit

Idle mode when the conversion is completed if the A/D interrupt is enabled. In

Power-down mode or Total Power-down mode, the ADC does not function. If the ADC is

enabled, it will consume power. Power can be reduced by disabling the ADC.

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P89LPC952/954

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8-bit microcontroller with 10-bit ADC

9. Limiting values

Table 10. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).^[1]

Symbol

T_amb(bias)

T_stg

Parameter

Conditions

Min

−55

−65

Max

+125

+150

Unit

°C

bias ambient temperature

storage temperature

°C

I_OH(I/O)

HIGH-level output current per

input/output pin

I_OL(I/O)

LOW-level output current per

input/output pin

I_I/Otot(max)

V_n

maximum total input/output current

voltage on any other pin

100

3.5

except V_SS, with respect to

V_DD

P_tot(pack)

total power dissipation (per package) based on package heat

transfer, not device power

1.5

consumption

[1] The following applies to Table 10:

a) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

b) Parameters are valid over ambient temperature range unless otherwise speciﬁed. All voltages are with respect to V_SSunless

otherwise noted.

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8-bit microcontroller with 10-bit ADC

10. Static characteristics

Table 11. Static characteristics

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

Symbol

I_DD(oper)

Parameter

Conditions

Min

Typ^[1]

Max

Unit

[2]

operating supply current

V_DD= 3.6 V;

_osc= 12 MHz

V_DD= 3.6 V;

_osc= 18 MHz

V_DD= 3.6 V;

_osc= 12 MHz

V_DD= 3.6 V;

_osc= 18 MHz

3.25

µA

I_DD(idle)

Idle mode supply current

I_DD(pd)

Power-down mode supply

current

V_DD= 3.6 V; voltage

comparators powered

down

[3]

I_DD(tpd)

total Power-down mode supply V_DD= 3.6 V

current

0.5

µA

(dV/dt)_r

(dV/dt)_f

V_POR

V_DDR

V_th(HL)

V_IL

rise rate

of V_DD

mV/µs

fall rate

mV/µs

power-on reset voltage

data retention supply voltage

HIGH-LOW threshold voltage

LOW-level input voltage

LOW-HIGH threshold voltage

HIGH-level input voltage

hysteresis voltage

0.5

1.5

except SCL, SDA

SCL, SDA only

except SCL, SDA

SCL, SDA only

port 1

0.22V_DD

0.4V_DD

−0.5

0.3V_DD

V_th(LH)

V_IH

0.6V_DD0.7V_DD

0.7V_DD

5.5

V_hys

0.2V_DD

0.6

[4]

V_OL

LOW-level output voltage

I_OL= 20 mA;

1.0

V_DD= 2.4 V to 3.6 V

all ports, all modes except

high-Z

I_OL= 3.2 mA; V_DD= 2.4 V

0.2

0.3

to 3.6 V all ports, all

modes except high-Z

V_OH

HIGH-level output voltage

I_OH= −20 µA;

_DD− 0.3

_DD− 0. -

V_DD= 2.4 V to 3.6 V;

all ports,

quasi-bidirectional mode

_OH= −3.2 mA;

_DD= 2.4 V to 3.6 V;

all ports, push-pull mode

_DD− 0.7

_DD− 0. -

I_OH= −20 mA;

0.8V_DD

V_DD= 2.4 V to 3.6 V;

Port 5, push-pull mode

V_xtal

V_n

crystal voltage

on XTAL1, XTAL2 pins;

with respect to V_SS

−0.5

+4.0

+5.5

[5]

voltage on any other pin

except XTAL1, XTAL2,

V_DD; with respect to V_SS

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

51 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

Table 11. Static characteristics …continued

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ^[1]

Max

Unit

[6]

[7]

[8]

[9]

C_iss

I_IL

input capacitance

LOW-level input current

input leakage current

HIGH-LOW transition current

V_I= 0.4 V

−80

±1

µA

I_LI

V_I= V_IL, V_IH, or V_th(HL)

µA

I_THL

all ports; V_I= 1.5 V at

−30

−450

µA

V_DD= 3.6 V

R_{RST_N(int)}internal pull-up resistance on

pin RST

kΩ

V_bo

brownout trip voltage

BOE = 1

2.4

1.19

2.7

1.27

V_ref(bg)

TC_bg

band gap reference voltage

1.23

band gap temperature

coefﬁcient

ppm/°C

[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.

[2] The I_DD(oper), I_DD(idle), and I_DD(pd)speciﬁcations are measured using an external clock with the following functions disabled: comparators,

real-time clock, and watchdog timer.

[3] The I_DD(tpd)speciﬁcation is measured using an external clock with the following functions disabled: comparators, real-time clock,

brownout detect, and watchdog timer.

[4] See Section 9 “Limiting values” for steady state (non-transient) limits on I_OLor I_OH. If I_OL/I_OHexceeds the test condition, V_OL/V_OHmay

exceed the related speciﬁcation.

[5] This speciﬁcation can be applied to pins which have A/D input or analog comparator input functions when the pin is not being used for

those analog functions. When the pin is being used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 V with

respect to V_SS

[6] Pin capacitance is characterized but not tested.

[7] Measured with port in quasi-bidirectional mode.

[8] Measured with port in high-impedance mode.

[9] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is

highest when V_Iis approximately 2 V.

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

52 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

11. Dynamic characteristics

Table 12. Dynamic characteristics (12 MHz)

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.^[1][2]

Symbol

Parameter

Conditions

Variable clock

f_osc= 12 MHz Unit

Min Max

Min

Max

f_osc(RC)

internal RC oscillator

frequency

nominal f = 7.3728 MHz

trimmed to ± 1 % at

7.189

7.557

7.189 7.557 MHz

_amb= 25 °C; clock

doubler option = OFF

(default)

nominal f = 14.7456 MHz;

clock doubler option = ON,

14.378

320

15.114

520

14.378 15.114 MHz

V_DD= 2.7 V to 3.6 V

f_osc(WD)

internal watchdog

oscillator frequency

320

520 kHz

f_osc

oscillator frequency

clock cycle time

MHz

T_cy(clk)

f_CLKLP

see Figure 19

low-power select clock

frequency

MHz

Glitch ﬁlter

t_gr

glitch rejection time

P1.5/RST pin

any pin except P1.5/RST

t_sa

signal acceptance time P1.5/RST pin

125

any pin except P1.5/RST

External clock

t_CHCX

t_CLCX

t_CLCH

t_CHCL

clock HIGH time

see Figure 19

_cy(clk)− t_CLCX

clock LOW time

clock rise time

clock fall time

T_cy(clk)− t_CHCX

Shift register (UART mode 0)

T_XLXL

t_QVXH

t_XHQX

t_XHDX

t_XHDV

serial port clock cycle

time

see Figure 18

16T_cy(clk)

1333

1083

output data set-up to

clock rising edge time

13T_cy(clk)

output data hold after

clock rising edge time

T_cy(clk)+ 20

103 ns

input data hold after

clock rising edge time

input data valid to clock see Figure 18

rising edge time

150

SPI interface

f_SPI

SPI operating frequency

CCLK

slave

⁄

2.0

3.0

MHz

CCLK

master

⁄

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

53 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

Table 12. Dynamic characteristics (12 MHz) …continued

V_DD= 2.4 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.^[1][2]

Symbol

Parameter

Conditions

Variable clock

f_osc= 12 MHz Unit

Min

Max

Min

Max

T_SPICYC

SPI cycle time

slave

see Figure 20, 21, 22, 23

⁄

500

333

CCLK

master

⁄

CCLK

t_SPILEAD

SPI enable lead time

slave

see Figure 22, 23

250

t_SPILAG

SPI enable lag time

slave

see Figure 22, 23

t_SPICLKH

SPICLK HIGH time

master

see Figure 20, 21, 22, 23

⁄

165

250

CCLK

slave

⁄

CCLK

t_SPICLKL

SPICLK LOW time

master

see Figure 20, 21, 22, 23

⁄

165

250

CCLK

slave

⁄

CCLK

t_SPIDSU

t_SPIDH

t_SPIA

SPI data set-up time

master or slave

SPI data hold time

master or slave

SPI access time

slave

see Figure 20, 21, 22, 23

see Figure 22, 23

100

120

240

120 ns

240 ns

t_SPIDIS

SPI disable time

slave

see Figure 22, 23

t_SPIDV

SPI enable to output

data valid time

see Figure 20, 21, 22, 23

slave

240

167

240 ns

167 ns

master

t_SPIOH

t_SPIR

SPI output data hold

time

see Figure 20, 21, 22, 23

SPI rise time

SPI outputs (SPICLK,

MOSI, MISO)

100

100 ns

2000 ns

SPI inputs (SPICLK,

MOSI, MISO, SS)

2000

t_SPIF

SPI fall time

see Figure 20, 21, 22, 23

SPI outputs (SPICLK,

MOSI, MISO)

100

100 ns

2000 ns

SPI inputs (SPICLK,

MOSI, MISO, SS)

2000

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

54 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

Table 13. Dynamic characteristics (18 MHz)

V_DD= 3.0 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.^[1][2]

Symbol Parameter

Conditions

Variable clock

f_osc= 18 MHz Unit

Min Max

Min

Max

f_osc(RC)

internal RC oscillator

frequency

nominal f = 7.3728 MHz

trimmed to ± 1 % at

7.189

7.557

7.189 7.557 MHz

_amb= 25 °C; clock

doubler option = OFF

(default)

nominal f = 14.7456 MHz;

clock doubler option = ON

14.378

320

15.114

520

14.378 15.114 MHz

f_osc(WD)internal watchdog

oscillator frequency

320

520 kHz

f_osc

oscillator frequency

clock cycle time

MHz

T_cy(clk)

f_CLKLP

see Figure 19

low-power select clock

frequency

MHz

Glitch ﬁlter

t_gr

glitch rejection time

P1.5/RST pin

any pin except P1.5/RST

t_sa

signal acceptance time P1.5/RST pin

125

any pin except P1.5/RST

External clock

t_CHCX

t_CLCX

t_CLCH

t_CHCL

clock HIGH time

see Figure 19

_cy(clk)− t_CLCX

clock LOW time

clock rise time

clock fall time

_cy(clk)− t_CHCX

Shift register (UART mode 0)

T_XLXL

t_QVXH

t_XHQX

t_XHDX

t_XHDV

serial port clock cycle

time

see Figure 18

16T_cy(clk)

888

722

output data set-up to

clock rising edge time

13T_cy(clk)

output data hold after

clock rising edge time

T_cy(clk)+ 20

input data hold after

clock rising edge time

input data valid to clock see Figure 18

rising edge time

150

SPI interface

f_SPISPI operating frequency

CCLK

slave

⁄

3.0

4.5

MHz

CCLK

master

⁄

T_SPICYCSPI cycle time

see Figure 20, 21, 22, 23

slave

⁄

333

222

CCLK

master

⁄

CCLK

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

55 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

Table 13. Dynamic characteristics (18 MHz) …continued

V_DD= 3.0 V to 3.6 V unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.^[1][2]

Symbol Parameter

Conditions

Variable clock

f_osc= 18 MHz Unit

Min

250

Max

Min

250

Max

t_SPILEADSPI enable lead time

slave

see Figure 22, 23

see Figure 20, 21, 22, 23

t_SPILAG

SPI enable lag time

slave

t_SPICLKHSPICLK HIGH time

slave

⁄

167

111

CCLK

master

t_SPICLKLSPICLK LOW time

slave

⁄

CCLK

see Figure 20, 21, 22, 23

⁄

167

111

CCLK

master

⁄

CCLK

t_SPIDSU

t_SPIDH

t_SPIA

SPI data set-up time

master or slave

SPI data hold time

master or slave

SPI access time

slave

see Figure 20, 21, 22, 23

see Figure 22, 23

100

160

t_SPIDIS

SPI disable time

slave

see Figure 22, 23

160 ns

t_SPIDV

SPI enable to output

data valid time

see Figure 20, 21, 22, 23

slave

160

111

160 ns

111 ns

master

t_SPIOH

t_SPIR

SPI output data hold

time

see Figure 20, 21, 22, 23

SPI rise time

SPI outputs (SPICLK,

MOSI, MISO)

100

100 ns

2000 ns

SPI inputs (SPICLK,

MOSI, MISO, SS)

2000

t_SPIF

SPI fall time

see Figure 20, 21, 22, 23

SPI outputs (SPICLK,

MOSI, MISO)

100

100 ns

2000 ns

SPI inputs (SPICLK,

MOSI, MISO, SS)

2000

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed.

[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

56 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

11.1 Waveforms

XLXL

clock

XHQX

QVXH

output data

write to SBUF

input data

XHDX

set TI

valid

XHDV

valid

clear RI

set RI

002aaa906

Fig 18. Shift register mode timing

CHCX

CHCL

CLCX

CLCH

cy(clk)

002aaa907

Fig 19. External clock timing

SPICYC

SPIR

SPIF

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(output)

SPIF

SPIR

SPICLKL

SPICLKH

SPICLK

(CPOL = 1)

(output)

SPIDH

SPIDSU

MISO

(input)

LSB/MSB in

MSB/LSB in

SPIR

SPIDV

SPIOH

SPIDV

MOSI

SPIF

(output)

master MSB/LSB out

master LSB/MSB out

002aaa908

Fig 20. SPI master timing (CPHA = 0)

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

57 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

SPICYC

SPIR

SPIF

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(output)

SPIR

SPIF

SPICLKL

SPICLK

(CPOL = 1)

(output)

SPICLKH

SPIDH

SPIDSU

MISO

(input)

LSB/MSB in

MSB/LSB in

SPIDV

SPIOH

SPIDV

SPIF

SPIR

MOSI

(output)

master MSB/LSB out

master LSB/MSB out

002aaa909

Fig 21. SPI master timing (CPHA = 1)

SPIR

SPICYC

SPIR

SPIF

SPILAG

SPILEAD

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(input)

SPIR

SPIF

SPICLKL

SPICLK

(CPOL = 1)

(input)

SPICLKH

SPIOH

SPIDIS

SPIOH

SPIA

SPIDV

MISO

(output)

slave MSB/LSB out

slave LSB/MSB out

not defined

SPIDH

SPIDSU

SPIDH

SPIDSU

MOSI

(input)

MSB/LSB in

LSB/MSB in

002aaa910

Fig 22. SPI slave timing (CPHA = 0)

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

58 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

SPIR

SPICYC

SPIR

SPIF

SPILAG

SPILEAD

SPICLKL

SPICLKH

SPICLK

(CPOL = 0)

(input)

SPIR

SPIF

SPICLKL

SPICLK

(CPOL = 1)

(input)

SPICLKH

SPIOH

SPIDIS

SPIDV

SPIA

MISO

(output)

slave LSB/MSB out

slave MSB/LSB out

not defined

SPIDH

SPIDSU

SPIDH

SPIDSU

MOSI

(input)

MSB/LSB in

LSB/MSB in

002aaa911

Fig 23. SPI slave timing (CPHA = 1)

11.2 ISP entry mode

Table 14. Dynamic characteristics, ISP entry mode

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

Symbol Parameter Conditions

V_DDactive to RST active delay time pin RST

Min

Typ

Max

Unit

µs

t_VR

t_RH

t_RL

RST HIGH time

RST LOW time

pin RST

µs

RST

002aaa912

Fig 24. ISP entry waveform

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

59 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

12. Other characteristics

12.1 Comparator electrical characteristics

Table 15. Comparator electrical characteristics

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IO

input offset voltage

±10

V_IC

common-mode input voltage

common-mode rejection ratio

total response time

V_DD− 0.3

[1]

CMRR

t_res(tot)

t_(CE-OV)

I_LI

−50

500

250

chip enable to output valid time

input leakage current

µs

0 V < V_I< V_DD

±10

µA

[1] This parameter is characterized, but not tested in production.

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

60 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

12.2 ADC electrical characteristics

Table 16. ADC electrical characteristics

V_DD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

_amb= −40 °C to +85 °C for industrial applications, unless otherwise speciﬁed.

All limits valid for an external source impedance of less than 10 kΩ.

Symbol

Parameter

Conditions

Min

Typ

_DD− 0.4 -

_SS− 0.4 -

Max

Unit

V_DDA(ADC)ADC analog supply voltage

V_DD+ 0.4

V_SS+ 0.4

V_DD+ 0.4

V_SS+ 0.4

V_DD+ 0.4

V_SSA

V_VREFP

V_VREFN

V_IA

analog ground voltage

voltage on pin VREFP

voltage on pin VREFN

analog input voltage

analog input capacitance

differential linearity error

integral non-linearity

offset error

_DD− 0.4 -

_SS− 0.4 -

C_ia

E_D

±1

LSB

E_L(adj)

E_O

±2

E_G

gain error

±2

E_u(tot)

M_CTC

α_ct(port)

SR_in

total unadjusted error

channel-to-channel matching

crosstalk between port inputs

input slew rate

+4/−3

±1

0 kHz to 100 kHz

ADC enabled

−60

100

V/ms

T_cy(ADC)

t_ADC

ADC clock cycle time

ADC conversion time

111

3125

36T_cy(ADC)

µs

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

61 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

13. Package outline

PLCC44: plastic leaded chip carrier; 44 leads

SOT187-2

pin 1 index

(A )

detail X

10 mm

scale

DIMENSIONS (mm dimensions are derived from the original inch dimensions)

(1)

UNIT

max.

min.

max. max.

4.57

4.19

0.81 16.66 16.66

0.66 16.51 16.51

16.00 16.00 17.65 17.65 1.22 1.44

14.99 14.99 17.40 17.40 1.07 1.02

0.53

0.33

0.51 0.25 3.05

0.02 0.01 0.12

1.27

0.05

0.18 0.18

0.1

2.16 2.16

0.180

0.165

0.032 0.656 0.656

0.026 0.650 0.650

0.63 0.63 0.695 0.695 0.048 0.057

0.59 0.59 0.685 0.685 0.042 0.040

0.021

0.013

inches

0.007 0.007 0.004 0.085 0.085

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

01-11-14

SOT187-2

112E10

MS-018

EDR-7319

Fig 25. Package outline SOT187-2 (PLCC44)

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

62 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

LQFP44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm

SOT389-1

(A )

w M

pin 1 index

detail X

w M

v M

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.45 0.20 10.1 10.1

0.30 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.14 1.14

0.85 0.85

1.6

0.25

0.8

0.2

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

02-06-07

SOT389-1

136E08

MS-026

Fig 26. Package outline SOT389-1 (LQFP44)

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

63 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

(A )

w M

pin 1 index

detail X

v M

w M

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 7.1

0.17 0.12 6.9

7.1

6.9

9.15 9.15

8.85 8.85

0.75

0.45

0.95 0.95

0.55 0.55

1.6

0.25

0.5

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT313-2

136E05

MS-026

Fig 27. Package outline SOT313-2 (LQFP48)

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

64 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

14. Abbreviations

Table 17. Abbreviations

Acronym

ADC

BOE

CPU

CCU

CRC

DAC

EPROM

EMI

Description

Analog-to-Digital Converter

BrownOut Enable

Central Processing Unit

Capture/Compare Unit

Cyclic Redundancy Check

Digital-to-Analog Converter

Erasable Programmable Read-Only Memory

ElectroMagnetic Interference

In-Application Programming

Least Signiﬁcant Bit

IAP

LSB

MSB

PWM

RAM

Most Signiﬁcant Bit

Pulse Width Modulator

Random Access Memory

Resistance-Capacitance

RTC

SAR

SFR

Real-Time Clock

Successive Approximation Register

Special Function Register

Serial Peripheral Interface

Universal Asynchronous Receiver/Transmitter

SPI

UART

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

65 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

15. Revision history

Table 18. Revision history

Document ID

Release date

20080724

Data sheet status

Change notice

Supersedes

P89LPC952_954_4

Modiﬁcations:

Product data sheet

P89LPC952_954_3

• Figure 2 “Functional diagram”: Updated port 2 information.

P89LPC952_954_3

P89LPC952_954_2

P89LPC952_1

20080605

20071219

20050916

Product data sheet

P89LPC952_954_2

Preliminary data sheet

P89LPC952_1

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

66 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

to result in personal injury, death or severe property or environmental

16.2 Deﬁnitions

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

I²C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

67 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

18. Contents

General description . . . . . . . . . . . . . . . . . . . . . . 1

7.16.1

7.17

Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Timers/counters 0 and 1 . . . . . . . . . . . . . . . . 33

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Timer overﬂow toggle output . . . . . . . . . . . . . 34

RTC/system timer. . . . . . . . . . . . . . . . . . . . . . 34

UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Baud rate generator and selection. . . . . . . . . 35

Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 35

Break detect. . . . . . . . . . . . . . . . . . . . . . . . . . 35

Double buffering. . . . . . . . . . . . . . . . . . . . . . . 35

Transmit interrupts with double buffering

2.1

2.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Principal features . . . . . . . . . . . . . . . . . . . . . . . 1

Additional features . . . . . . . . . . . . . . . . . . . . . . 2

7.17.1

7.17.2

7.17.3

7.17.4

7.17.5

7.17.6

7.18

3.1

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5

7.19

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.19.1

7.19.2

7.19.3

7.19.4

7.19.5

7.19.6

7.19.7

7.19.8

7.19.9

7.1

7.2

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.6

7.4

Functional description . . . . . . . . . . . . . . . . . . 14

Special function registers . . . . . . . . . . . . . . . . 14

Enhanced CPU. . . . . . . . . . . . . . . . . . . . . . . . 23

Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Clock deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . 23

CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 23

Low speed oscillator option . . . . . . . . . . . . . . 23

Medium speed oscillator option . . . . . . . . . . . 23

High speed oscillator option . . . . . . . . . . . . . . 23

Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 24

On-chip RC oscillator option. . . . . . . . . . . . . . 24

Watchdog oscillator option . . . . . . . . . . . . . . . 24

External clock input option . . . . . . . . . . . . . . . 24

CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 25

CCLK modiﬁcation: DIVM register . . . . . . . . . 25

Low power select . . . . . . . . . . . . . . . . . . . . . . 25

Memory organization . . . . . . . . . . . . . . . . . . . 26

Data RAM arrangement . . . . . . . . . . . . . . . . . 26

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

External interrupt inputs . . . . . . . . . . . . . . . . . 27

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Port conﬁgurations . . . . . . . . . . . . . . . . . . . . . 29

enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . 36

7.19.10 The 9^thbit (bit 8) in double buffering

(Modes 1, 2 and 3). . . . . . . . . . . . . . . . . . . . . 36

7.20

7.21

7.21.1

7.22

7.22.1

7.22.2

7.22.3

7.23

7.24

7.25

7.25.1

7.25.2

7.25.3

7.26

7.26.1

7.26.2

7.26.3

7.26.4

7.26.5

7.26.6

7.26.7

7.26.8

7.26.9

I²C-bus serial interface. . . . . . . . . . . . . . . . . . 36

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Typical SPI conﬁgurations . . . . . . . . . . . . . . . 39

Analog comparators. . . . . . . . . . . . . . . . . . . . 40

Internal reference voltage. . . . . . . . . . . . . . . . 41

Comparator interrupt . . . . . . . . . . . . . . . . . . . 41

Comparators and power reduction modes . . . 41

KBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 42

Additional features . . . . . . . . . . . . . . . . . . . . . 43

Software reset . . . . . . . . . . . . . . . . . . . . . . . . 43

Dual data pointers . . . . . . . . . . . . . . . . . . . . . 43

Debugger interface. . . . . . . . . . . . . . . . . . . . . 43

Flash program memory . . . . . . . . . . . . . . . . . 44

General description . . . . . . . . . . . . . . . . . . . . 44

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Flash organization . . . . . . . . . . . . . . . . . . . . . 44

Using ﬂash as data storage . . . . . . . . . . . . . . 44

Flash programming and erasing. . . . . . . . . . . 45

ICP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

IAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Power-on reset code execution . . . . . . . . . . . 46

7.5

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.12.1

7.13

7.13.1

7.13.1.1 Quasi-bidirectional output conﬁguration . . . . . 29

7.13.1.2 Open-drain output conﬁguration . . . . . . . . . . . 29

7.13.1.3 Input-only conﬁguration . . . . . . . . . . . . . . . . . 30

7.13.1.4 Push-pull output conﬁguration . . . . . . . . . . . . 30

7.13.2

7.13.3

7.14

7.14.1

7.14.2

7.15

7.15.1

7.15.2

7.15.3

7.16

Port 0 analog functions. . . . . . . . . . . . . . . . . . 30

Additional port features. . . . . . . . . . . . . . . . . . 30

Power monitoring functions. . . . . . . . . . . . . . . 30

Brownout detection. . . . . . . . . . . . . . . . . . . . . 30

Power-on detection. . . . . . . . . . . . . . . . . . . . . 31

Power reduction modes . . . . . . . . . . . . . . . . . 31

Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Power-down mode . . . . . . . . . . . . . . . . . . . . . 31

Total Power-down mode . . . . . . . . . . . . . . . . . 31

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7.26.10 Hardware activation of the bootloader . . . . . . 46

7.27

7.28

User conﬁguration bytes. . . . . . . . . . . . . . . . . 46

User sector security bytes . . . . . . . . . . . . . . . 46

continued >>

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

68 of 69

P89LPC952/954

NXP Semiconductors

8-bit microcontroller with 10-bit ADC

ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.1

8.2

8.3

8.4

General description. . . . . . . . . . . . . . . . . . . . . 47

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 47

ADC operating modes . . . . . . . . . . . . . . . . . . 48

Fixed channel, single conversion mode . . . . . 48

Fixed channel, continuous conversion mode . 48

Auto scan, single conversion mode . . . . . . . . 48

Auto scan, continuous conversion mode . . . . 48

Dual channel, continuous conversion mode . . 48

Single step mode . . . . . . . . . . . . . . . . . . . . . . 49

Conversion start modes . . . . . . . . . . . . . . . . . 49

Timer triggered start . . . . . . . . . . . . . . . . . . . . 49

Start immediately . . . . . . . . . . . . . . . . . . . . . . 49

Edge triggered . . . . . . . . . . . . . . . . . . . . . . . . 49

Boundary limits interrupt. . . . . . . . . . . . . . . . . 49

Clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Power-down and Idle mode . . . . . . . . . . . . . . 49

8.4.1

8.4.2

8.4.3

8.4.4

8.4.5

8.4.6

8.5

8.5.1

8.5.2

8.5.3

8.6

8.7

8.8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 50

Static characteristics. . . . . . . . . . . . . . . . . . . . 51

11.1

11.2

Dynamic characteristics . . . . . . . . . . . . . . . . . 53

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

ISP entry mode. . . . . . . . . . . . . . . . . . . . . . . . 59

12.1

12.2

Other characteristics. . . . . . . . . . . . . . . . . . . . 60

Comparator electrical characteristics . . . . . . . 60

ADC electrical characteristics. . . . . . . . . . . . . 61

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 62

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 65

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 66

Legal information. . . . . . . . . . . . . . . . . . . . . . . 67

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 67

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 67

16.1

16.2

16.3

16.4

Contact information. . . . . . . . . . . . . . . . . . . . . 67

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 24 July 2008

Document identifier: P89LPC952_954_4

P89LPC952FA,512 [NXP]

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