P90CE201AEB [NXP]
16-bit microcontroller; 16位微控制器
| 型号： | P90CE201AEB |
| 厂家： | 
NXP |
| 描述： | 16-bit microcontroller |
| 文件： | 总77页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
P90CE201
16-bit microcontroller
August 1993
Product specification
File under Integrated Circuits, IC21
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
CONTENTS
1
2
3
4
FEATURES
10
8-BIT GENERAL PORT
GENERAL DESCRIPTION
ORDERING INFORMATION
PINNING INFORMATION
10.1
11
8-bit General Port registers
8-BIT AUXILIARY PORT
8-bit Auxiliary Port registers
WATCHDOG TIMER
TIMERS
11.1
12
4.1
4.2
Pinning
Pin description
13
5
CPU FUNCTIONAL DESCRIPTION
13.1
13.2
13.3
General
Timer operating modes
Timer registers
5.1
5.2
5.3
5.4
5.5
5.6
General
5.2 Programming model and data organization
Internal and external operation
Processing states and exception processing
Stack format
14
ELECTROMAGNETIC COMPATIBILITY
(EMC) IMPROVEMENTS
15
ELECTRICAL SPECIFICATIONS
CPU interrupt processing
15.1
15.2
15.3
Limiting values
DC Characteristics
AC Characteristics
6
SYSTEM CONTROL
6.1
6.2
6.3
6.4
6.5
Memory mapping
Interrupt controller
System Control Registers
Reset
16
17
18
REGISTER MAP
PACKAGE OUTLINE
SOLDERING
Clock circuitry
7
INSTRUCTION SET
18.1
18.2
18.3
18.4
Introduction
Reflow soldering
Wave soldering
7.1
7.2
Addressing modes
Instruction timing
I2C-BUS INTERFACE
Repairing soldered joints
8
19
20
21
DEFINITIONS
8.1
8.2
General
I2C-bus interface registers
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I2C COMPONENTS
9
UART SERIAL INTERFACE
9.1
9.2
9.3
General
Operating modes
UART registers
August 1993
2
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
1
FEATURES
2
GENERAL DESCRIPTION
• CMOS technology
The P90CE201 is a member of the P9XCXXX family of
highly integrated 16-bit microcontrollers for use in a wide
variety of applications. It is fully software compatible with
the 68070/68000. The complete set of system functions
available on the chip results in reduced system cost.
Additionally, its modular design concept permits future
extension to the family.
• Full 68000 software compatibility
• 32-bit internal structure
• 16-bit internal data transfer
• 8-bit access to external ROM/RAM
• External addressing range 16 Mbytes for ROM and
16 Mbytes for RAM
• Unused address pins can be used as quasi-bidirectional
ports
• On-chip address decoder for ROM/RAM
• 8 edge triggered programmable interrupts that can also
be used as quasi-bidirectional ports
• Reset control
• Built-in clock generator
• 2 fully independent fast I2C-bus serial interfaces
• UART serial interface (4 modes)
• 3 fully independent 16-bit timers
• Watchdog timer
• 8-bit quasi-bidirectional port, 4-bits with high drive
capability
• EMC optimized layout and pinning
• 64-pin QFP package
3
ORDERING INFORMATION
PACKAGE
CLOCK
EXTENDED
TYPE NUMBER
TEMPERATURE RANGE
FREQUENCY
(°C)
PINS PIN POSITION MATERIAL
64 QFP plastic
CODE
(MHz)
P90CE201AEB
Note
1. SOT319-2; 1996 November 28.
SOT319(1)
24.0
−25 to 85
August 1993
3
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
A0-A15
CSRAMN
D0-D7
GP0-GP7
(1)
A16-A23
CSROMN
R/WN
ADDRESS
DECODER
ADDRESS
BUFFER
DATA
INTERFACE
PORT
OCD (15 : 0)
TIMER 0
TIMER 1
TIMER 2
T0
CPU
SYSTEM
CONTROL
T2
WATCHDOG
TIMER
TXD
RXD
UART
RESET
LOGIC
RESET
XTAL1
XTAL2
2
CLOCK
I
I
C 1
C 2
INTN0 -
INTN7
SCL2
SDA2
INTERRUPT
CONTROLLER
2
MLB015
1. The General Port lines GP5, GP6 and GP7 have alternate functions for Timer 1, SCL1 and SDA1
respectively; see Table 1.
Fig.1 Block diagram
August 1993
4
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
4
PINNING INFORMATION
Pinning
4.1
V
RXD
1
2
3
4
5
6
7
8
9
51
50
SS2
CSRAMN
SDA2
SCL2
49 D3
48
GP7/SDA1
GP6/SCL1
D2
47 D4
46 D1
GP0
GP1
GP2
GP3
45
D5
44 D0
43 D6
42 A0
P90CE201
GP4 10
D7
GP5/T1 11
41
40 A1
39
A23/AP7
12
A22/AP6 13
A2
38 A10
A21/AP5
A20/AP4
14
15
A3
37
36
35
CSROMN
XTAL2 16
XTAL1 17
V
A4
18
19
34 A11
33 A5
DD1
SS1
V
MLB003
Fig.2 Pin configuration for QFP64.
5
August 1993
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
4.2
Pin description
Table 1 QFP64 package.
MNEMONIC
RXD
TYPE
I/O
PIN NO.
FUNCTION
1
2
Receive Data. RXD is the data input for the UART interface.
SDA2
I/O
Serial Data 2 (open drain). SDA2 is the data signal for the second
I2C-bus serial interface.
SCL2
I/O
I/O
3
Serial Clock 2 (open drain). SCL2 is the clock signal for the second
I2C-bus serial interface.
GP7/SDA1
GP6/SCL1
GP0
4
5
6
7
General Purpose Port (active HIGH, 3-state). The alternative functions
are as follows. SCL1 is the clock signal for the first I2C-bus serial
interface. SDA1 is the data signal for the first I2C-bus serial interface.
T1 is the input pin for Timer 1.
GP1
GP2
8
GP3
9
GP4
GP5/T1
10
11
A23/AP7
to
A16/AP0
I/O
O
12 to 15, 21,
22, 24, 23
Address Bus. Upper 8-bits of the address bus (A23 to A16). The unused
address bits can be selected as a quasi-bidirectional port (AP).
A15 to A0
25, 26, 28, 27, Address Bus. Lower 16-bits of the address bus.
34, 38, 32, 30,
29, 31, 33, 35,
37, 39, 40, 42
XTAL2
XTAL1
O
I
16
17
Oscillator output. Not connected if an external clock generator is used.
Oscillator input. XTAL1 can also be used as an external clock input if
an external clock generator is used.
VDD1
VSS1
−
−
18
19
20
36
Supply voltage. For internal logic, address bus, data bus, RWN,
CSRAMN, CSROMN, XTAL1 and XTAL2.
Ground. For internal logic, address bus, data bus, RWN, CSRAMN,
CSROMN, XTAL1 and XTAL2.
R/WN
O
Read (active HIGH)/Write (active LOW). This controls the direction of
data flow.
CSROMN
D0 to D7
O
O
Chip Select ROM (active LOW). This signal selects external ROM.
44, 46, 48, 49, Data Bus. 8-bit data bus.
47, 45, 43, 41
CSRAMN
VSS2
O
−
−
I
50
51
52
53
54
55
Chip Select RAM (active LOW). This signal enables external RAM.
Ground. For all other periphery pins (quiet port).
VDD2
RESET
T0
Supply voltage. For all other periphery pins (quiet port).
Reset (active HIGH). Input pin for an external reset.
Timer 0. Input pin for cycle and event counting using Timer 0.
Timer 2. Input pin for cycle and event counting using Timer 2.
I
T2
I
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
MNEMONIC
TYPE
PIN NO.
FUNCTION
LP0/INTN0
LP1/INTN1
LP2/INTN2
LP3/INTN3
LP4/INTN4
LP5/INTN5
LP6/INTN6
LP7/INTN7
I/O
56
57
58
59
60
61
62
63
Latched Interrupt inputs (active LOW). A LOW level of ≥ 1 clock pulse
will be stored as a pending interrupt request. Priority levels are
programmable. Unused interrupt inputs can be used as a
quasi-bidirectional port (LP).
TXD
O
64
Transmit Data. TXD is the data output for the UART serial interface.
August 1993
7
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
5
CPU FUNCTIONAL DESCRIPTION
General
5.2
5.2 Programming model and data organization
The programming model is identical to that of the 68000
and is shown in Fig.3. It contains seventeen 32-bit
5.1
The CPU of the P90CE201 is software compatible with the
68000, consequently programs written for the 68000 will
run on the P90CE201 unchanged. However, for certain
applications the following differences between the
processors should be noted:
registers, a 32-bit Program Counter and a 16-bit Status
Register. The first eight registers (D0 to D7) are used as
data registers for byte, word and long-word operations.
The second group of registers (A0 to A6) and the System
Stack Pointer (A7) can be used as software stack pointers
and base address registers. In addition, these registers
can be used for word and long-word address operations.
All seventeen registers can be used as Index Registers.
• The initialization of the System Control Registers.
• Differences exist in the address error exception
processing since the P90CE201 can provide full error
recovery.
The P90CE201 supports 8, 16 and 32-bit integer data,
BCD data 32-bit addresses. Each data type is arranged in
memory as shown in Fig.4.
• The timing is different because of the P90CE201’s new
architecture and technology. The instruction execution
timing is completely different for the same reason.
31
16 15
8
7
0
DO
D1
D2
D3
D4
D5
D6
D7
Eight
Data
Registers
31
16 15
0
A0
A1
A2
Seven
A3 Address
Registers
A4
A5
A6
USER STACK POINTER
SUPERVISOR STACK POINTER
Two Stack
A7
Pointers
31
0
0
Program
Counter
15
8
7
Status
Register
USER
BYTE
SYSTEM
BYTE
MCD504
Fig.3 Programming model.
8
August 1993
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
7
6
5
4
3
2
1
0
bit
(a) Bit data (1 Byte = 8 bits).
bit 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MSB
BYTE 0
BYTE 2
LSB
BYTE 1
BYTE 3
(b) Integer data (1 Byte = 8 bits).
bit 15 14 13 12 11 10
MSB
9
8
7
6
5
4
3
2
1
0
WORD 0
WORD 1
WORD 2
LSB
(c) Word data (16 bits).
bit 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MSB
HIGH ORDER
LOW ORDER
HIGH ORDER
LOW ORDER
HIGH ORDER
LOW ORDER
LONG WORD 0
LSB
LONG WORD 1
LONG WORD 2
(d) Long-word data (32 bits).
bit 15 14 13 12 11 10
MSB
9
8
7
6
5
4
3
2
1
0
HIGH ORDER
LOW ORDER
HIGH ORDER
LOW ORDER
HIGH ORDER
LOW ORDER
ADDRESS 0
LSB
ADDRESS 1
ADDRESS 2
(e) Addresses (1 address =32 bits).
bit 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MSB BCD 0
BCD 4
BCD 1
BCD 5
LSB
BCD 2
BCD 6
BCD 3
BCD 7
(f) BCD data (2 BCD digits = 1 Byte).
MCD505
Fig.4 Memory data organization.
9
August 1993
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
BIT 15
13
S
10
8
4
0
T
–
–
–
12 11 10
–
–
–
X
N
Z
V
C
Supervisor
State
Interrupt
Mask
Carry
Trace
Mode
Overflow
Zero
Negative
Extend
MCD506
Fig.5 Status Register.
The halted processing state is an indication of a
catastrophic hardware failure. For example, if during
exception processing of a bus error another bus error
occurs, the CPU assumes that the system is unusable and
halts. Only an external reset can restart a halted
processor. Note that a CPU in the stopped state is not in
the halted state or vice versa.
5.3
Internal and external operation
The P90CE201 operates with an internal clock frequency
of half the oscillator frequency (fOSC/2). Each internal clock
cycle is divided into 2 states. A non-access machine cycle
has 3 clock cycles or 6 states (S0 to S5). A minimum bus
cycle normally consists of 3 clock cycles (6 states). When
data transfer has not yet been terminated, wait states (SW)
are inserted in multiples of 2. For external memory access,
2 wait states (bus states SB) are added automatically.
The processor can work in the “user” or “supervisor” state
determined by the state of the S-bit in the Status Register.
Accesses to the on-chip peripherals are achieved in the
supervisor state.
5.4
Processing states and exception processing
All exception processing is performed in the supervisor
state once the current content of the Status Register has
been copied. The exception vector number is then
determined and copies of the Status Register, the
Program Counter value and the format/vector number are
saved on the supervisor stack using the Supervisor Stack
Pointer. Finally, the contents of the exception vector
location is fetched and loaded into the Program Counter.
The CPU is always in one of three processing states:
normal, exception or halted.
The normal processing state is that associated with
instruction execution; the memory references are to fetch
instructions and operands and to store results. A special
case of the normal state is the stopped state which the
processor enters when a STOP instruction is executed. In
this state the CPU makes no further memory references.
The exception processing state is associated with
interrupts, trap instructions, tracing and other exceptional
conditions. The exception may be generated internally by
an instruction or by an unusual condition arising during the
execution of an instruction. Externally, exception
processing can be forced by an interrupt or a reset.
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
5.4.1
EXCEPTION VECTORS
Exception vectors are memory locations from which the
CPU fetches the address of a routine that will handle that
exception. All exception vectors are 2 words long (see Fig.6)
except for the reset vector which is made up of 4 words,
containing the Program Counter (PC) and the
Supervisor Stack Pointer (SSP). All exception vectors are
contained in the supervisor data space.
A vector number is an 8-bit number that, when multiplied
by 4, gives the address of an exception vector. Vector
numbers are generated internally. The memory map for
the exception vectors is given in Table 2.
handbook, halfpage
Word 0
NEW PROGRAM COUNTER (HIGH)
NEW PROGRAM COUNTER (LOW)
Word 1
MCD509
Fig.6 Exception vector format.
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
Table 2 Exception vector assignment.
VECTOR NO.
DEC
HEX
ASSIGNMENT
0
1
2
3
4
5
6
7
8
9
0
000
004
008
00C
010
014
018
01C
020
024
028
02C
030
034
038
03C
Reset: initial SSP
Reset: initial PC
Bus error
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
Address error
Illegal instruction
Zero divide
CHK instruction
TRAPV instruction
Privilege violation
Trace
10
Line 1010 emulator
Line 1111 emulator
Unassigned, reserved
Unassigned, reserved
Format error
11
12
13 (note 1)
14
15
Uninitialized interrupt vector
Unassigned, reserved
16 to 23 (note 1)
64 − 92
96
040 − 05C
060
24
Spurious interrupt
25
100
064
Level 1 on-chip interrupt autovector
Level 2 on-chip interrupt autovector
Level 3 on-chip interrupt autovector
Level 4 on-chip interrupt autovector
Level 5 on-chip interrupt autovector
Level 6 on-chip interrupt autovector
Level 7 on-chip interrupt autovector
TRAP instruction vectors
26
104
068
27
108
06C
28
112
070
29
116
074
30
120
078
31
124
07C
32 to 47
128 − 188
192 − 252
256 − 1020
080 − 0BC
0C0 − 0FC
100 − 3FC
48 to 63 (note 1)
64 to 255
Unassigned, reserved
User interrupt vectors
Note
1. Vectors 12, 13, 16 to 23 and 48 to 63 are reserved for future enhancements. No user peripheral devices should be
assigned to these numbers.
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
• STOP
5.4.2
MULTIPLE EXCEPTIONS
• RESET
As two or more exceptions can occur simultaneously,
exceptions are grouped in order of priority; as is shown in
Table 3.
• RTE
• MOVE TO SR
• AND (word) immediate to SR
• EOR (word) immediate to SR
• OR (word) immediate to SR
• MOVE USP.
5.4.3
INSTRUCTION TRAPS
Traps are exceptions caused by instructions arising either
from CPU recognition of abnormal conditions during
instruction execution or from instructions whose normal
behaviour is to cause traps.
5.4.6
TRACING
Some instructions are used specifically to generate traps.
The TRAP instruction always forces an exception, and is
useful for implementing system calls for user programs.
The TRAPV and CHK instructions force an exception if the
user program detects a run-time error, possibly an
arithmetic overflow or a subscript out of bounds. The
signed divide (DIVS) and unsigned divide (DIVU)
instructions will force an exception if a divide-by-zero
operation is attempted.
The CPU includes a facility to trace instructions one by one
to assist in program development. In the trace state, after
each instruction is executed, an exception is forced so that
a debugging program can monitor execution of the
program under test.
The trace facility uses the T-bit in the supervisor part of the
Status Register. If the T-bit is cleared, tracing is disabled
and instructions execute normally. If the T-bit is set at the
beginning of the execution of an instruction, a trace
exception will be generated after that instruction is
executed. If the instruction is not executed, either because
of an interrupt, or because the instruction is illegal or
privileged, the trace exception does not occur. Also, the
trace exception does not occur if the instruction is aborted
by a reset, bus error, or address error exception. If the
instruction is executed and an interrupt is pending, the
trace exception is processed before the interrupt. If the
execution of an instruction forces an exception, the forced
exception is processed before the trace exception.
5.4.4
ILLEGAL AND UNIMPLEMENTED INSTRUCTIONS
Illegal instruction is the term used to refer to any word that
is not the first word of a legal instruction. During instruction
execution, if such an instruction is fetched, an illegal
instruction exception occurs. Words with bits 15 to 12
equal to 1010 or 1111 are defined as unimplemented
instructions and separate exception vectors are allocated
to these patterns for efficient emulation. This facility allows
the operating system to detect program errors, or to
emulate unimplemented instructions in software.
As an extreme illustration of the above rules, consider the
arrival of an interrupt during the execution of a TRAP
instruction while tracing is enabled. First the trap exception
is processed, then the trace exception, and finally the
interrupt is processed. Instruction execution resumes in
the interrupt handling routine.
5.4.5
PRIVILEGE VIOLATIONS
To provide system security, various instructions are
privileged and any attempt to execute one of the privileged
and any attempt to execute one of the privileged
instructions while the CPU is in the user state causes an
exception. The privileged instructions are:
Table 3 Exception grouping and priority.
GROUP
EXCEPTION
PROCESSING
0
RESET, ADDRESS ERROR
BUS ERROR
Exception processing begins at the next machine cycle.
1
2
TRACE, INTERRUPT,
ILLEGAL, PRIVILEGE
Exception processing begins before the next instruction.
TRAP, TRAPV, CHK, ZERO,
DIVIDE, FORMAT ERROR
Exception processing is started through normal instruction
execution.
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
5.5
Stack format
The stack format for exception processing is similar to the 68010 (rather than the 68000) although the information stored
is not the same due to the different architecture. To handle this format the P90CE201 differs from the 68000 in that:
• The stack format has changed.
• The minimum number of words put into, or restored from, the stack is 4 (68010 compatible; not 3 as with the 68000).
• The RTE instruction decides (with the aid of the 4 format bits) whether or not more information has to be restored. The
P90CE201 long format is used for bus error and address error exceptions; all other exceptions use the short format.
• If another format code, other than one of the two listed above, is detected during the restore action, a Format Error
occurs.
If the user wants to finish the instruction in which the bus or address error occurred, the P90CE201 format must be used
on RTE. If no changes to the stack are required during exception processing, the stack format is transparent to the user.
5.5.1
LONG AND SHORT STACK FORMATS
SR
Status Register.
PCH/PCL
FORMAT
Program Counter High/Low Word.
handbook, 4 columns
SP
SR
Indicating either a short stack
(only the first 4 words), or the long
stack format for bus and address
error exceptions. See Fig.9.
PCH
PCL
Short
Stack
Format
VECTOR NUMBER The vector number of the
exception in the vector table; e.g.
2 for a bus error and 3 for an
FORMAT (4 bits)
VECTOR NUMBER
SSW
MM
address error. See Fig.9.
SSW
Special Status Word; see Fig.8.
Current Move Multiple Mask.
INTERNAL INFORMATION
MM
INTERNAL INFORMATION
TDPH/TDPL
In the event of a faulty write cycle,
the data can be found here.
Long
Stack
Format
TPDH
TPDL
TPFH/TPFL
The address used during the faulty
bus cycle.
TPFH
DBINH/DBINL
Data that has been read prior to
the faulty cycle can in some cases
be found here.
TPFL
DBINH
IR
Holds the current instruction
being executed.
DBINL
IR
IRC
IRC
Holds either the present
instruction being executed or the
prefetched instruction.
INTERNAL INFORMATION
MCD512
Fig.7 Stack format.
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
5.5.2
THE SPECIAL STATUS WORD (SSW)
bit
15 14 13 12 11 10
9
8
7
6
5
*
4
*
3
*
2
1
0
RR IF DF RM HB BY RW HW LC
FC FC FC
2
*
1
0
MCD513
Fig.8 Special Status Word.
Table 4 Description of SSW.
SYMBOL
BIT
FUNCTION
RR
SSW.15
Rerun. By default this bit is a logic 0. If set to a logic 1, the CPU will not re-run the
faulty bus cycle on return from exception (RTE).
−
IF
SSW.14
SSW.13
SSW.12
SSW.11
SSW.10
SSW.9
SSW.8
SSW.7
SSW.6
SSW.5
SSW.4
SSW.3
Undefined, reserved
The faulty cycle was an instruction fetch.
The faulty cycle was a data fetch.
The error occurred during a read-modify-write cycle.
High Byte
DF
RM
HB
BY
RW
HW
LC
−
The faulty cycle was a byte transfer.
Read/Write cycle
High Word
The faulty cycle was during a long-word access.
Undefined, reserved
−
Undefined, reserved
−
Undefined, reserved
FC2
FC1
FC0
SSW.2
SSW.1
SSW.0
Function Code. These three bits hold the internal function code during the faulty
bus cycle. The function codes are the same as for the 68000 and affect the status
of the CPU during the faulty bus cycle. See Table 5.
Table 5 Internal function codes.
FC2
FC1
FC0
ADDRESS SPACE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
User data
User program
Reserved
Reserved
Supervisor data
Supervisor program
Interrupt acknowledge
August 1993
15
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
bit 15 14 13 12 11 10
FORMAT CODE
9
8
7
6
5
4
3
2
1
0
0
0
0
VECTOR NUMBER
0
FORMAT CODE
either 0000
INFORMATION STACKED
Short Format (4 words)
68070 Format (17 words)
or
1111
MCD514
Fig.9 Vector number and format code.
The processor then starts normal exception processing by
saving the format word, Program Counter, and Status
Register in the supervisor stack. The value of the vector in
the format word is either supplied externally by the
requesting device or is an internally generated vector
number multiplied by four (format is all zeros). The
Program Counter value is the address of the instruction
that would have been executed if the interrupt had not
been present. Then the interrupt vector contents are
fetched and loaded into the Program Counter. The
interrupt handling routine starts with normal instruction
execution.
5.6
CPU interrupt processing
An Interrupt Controller handles all interrupts, solves any
priority problems and passes the highest level interrupt to
the CPU. The general interrupt handling mechanism and
the Interrupt Controller are described in section 6.2.
The CPU interrupt handling follows the same basic rules
as in the 68000. However, the following changes have
been made to simplify system development:
• Interrupts with a priority level equal to or less than the
priority level actually running will not be accepted.
• During the acknowledge cycle of an interrupt, the IPL
bits of the Status Register are set to the priority level of
the acknowledged interrupt. An exception to this is when
the IM bit in SYSCON2 is a logic 0. In this case level 7
is loaded into the Status Register. See section 6.1.2.
Priority level 7 is a special case; it can only be detected if
the priority level was set to a lower value in between.
If the priority of the interrupt pending is greater than the
current processor priority then:
• The exception processing sequence is started.
• A copy of the Status Register is saved.
• The privilege level is set to supervisor state.
• Tracing is suppressed.
• The priority level of the processor is set to that of the
interrupt being acknowledged.
The processor then gets the vector number from the
interrupting device, classifies it as an interrupt
acknowledge, and displays the interrupt level number
being acknowledged on the address bus.
If autovectoring is requested by the interrupting device, the
processor internally generates a vector number that
corresponds to the interrupt level number.
August 1993
16
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
• Maximum flexibility for RAM and ROM sizes.
6
SYSTEM CONTROL
Memory mapping
• The full physical memory size can be used without any
restrictions.
6.1
The P90CE201 accesses the external ROM and RAM via
8 data lines and up to 24 address lines. Data access to or
from the memories is bytewise. The data will be split or
restructured internally to match the internal 16-bit data
format. The upper byte (bits 15 to 8) of the data is taken
from the even address, the lower byte (bits 7 to 0) from the
odd address (MSB address + 1).
• The minimum number of address pins are used.
The validity of data is signalled to the CPU by the internal
signal DTACKN. This signal is generated internally after a
programmable delay (wait states). By programming the
number of wait cycles the user can adapt the program
execution times to his memory access times. After reset
the delay for the DTACKN signal is set to its maximum
value. Programming the number of wait cycles is
described in section 6.3.2.
For external memory control the device provides the R/WN
signal together with chip enable signals for ROM
(CSROMN) and RAM (CSRAMN). CSROMN is activated
in the internal address range 0H to FFFFFFH. The
CSRAMN signal is activated in the internal address range
1000000H to 1FFFFFFH. In the external world RAM and
ROM are wired in parallel with a maximum address range
of 16 Mbytes each. If the larger memory of RAM or ROM
is smaller than 16 Mbytes the unused address pins can be
used as port pins. The advantages of this addressing
scheme are:
S0
S1
S2
S3
SB
SB
S4
S5
S0
S1
S2
S3
SB
SB
S4
S5
S0
S1
PHI1
A0 A23
D0 D7
R/WN
CSRxMN
(Additional
Wait States)
byte write
byte read
MLB004
Fig.10 External memory interface timing - Word access.
17
August 1993
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
S0
S1
S2
S3
SB
SB
S4
S5
S0
S1
S2
S3
SB
SB
S4
S5
S0
S1
PHI1
A0 A23
D0 D7
R/WN
CSRxMN
(Additional
Wait States)
byte write
byte read
MLB005
Fig.11 External memory interface timing - Byte access.
August 1993
18
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
The execution of interrupt routines may be interrupted by
another higher priority level interrupt request (nested
interrupts). In the 68070 mode (SYSCON2.7 = 1), when an
interrupt is serviced by the CPU, the corresponding level is
loaded into the Status Register. This prevents the current
interrupt from getting interrupted by another interrupt
request with the same or lower priority level. If
6.2
Interrupt controller
An interrupt controller handles all internal and external
interrupts. It passes the interrupt with the highest level
priority to the CPU.
The following interrupt requests are generated by the
on-chip peripherals.
SYSCON2.7 = 0, priority level 7 will always be loaded into
the Status Register and therefore the current interrupt
cannot be interrupted by any other interrupt request.
• I2C1
• I2C2
• UART receiver
• UART transmitter
• Timer 2
6.2.2
ACKNOWLEDGE AND INTERRUPT VECTORS
When the CPU is ready to service a particular interrupt
request, it initiates an “interrupt acknowledge cycle” in
order to obtain the interrupt vector from the requesting
device. When the device recognizes that its interrupt
request has been accepted it either provides an 8-bit
interrupt vector together with an internal DTACKN signal
(vector mode), or it asserts an internal AVN signal and the
interrupt vector is calculated from the interrupt level.
• Timer 1
• Timer 0.
The following interrupt requests are sent via external pins.
• INTN0 to INTN7
6.2.1
INTERRUPT ARBITRATION
The priority level of all interrupts are programmable and
each may be allocated a value between 0 and 7. Level 7
has the highest priority, level 0 disables the corresponding
interrupt source. In the event of interrupt requests of equal
priority level occurring at the same time, then a hardware
mechanism gives the following order.
6.2.3
EXTERNAL LATCHED INTERRUPTS
INTN7 to INTN0 are 8 external interrupt inputs; each
triggered on the falling edge of the input. Their priority
levels as well as their interrupt vectors are programmable.
As an alternative function INTN7 to INTN0 may be used as
I/O ports. When an interrupt pin is programmed as a port,
the corresponding bit in the Port Control Register LPCRH
(or LPCRL) is used for port I/O. A read from either of these
two registers reads the value from the corresponding bit in
the Port Control Register. A read from the Port Pad Control
Register LPPH (or LPPL) reads the value from the
corresponding port input pin. A write to LPCRH (or LPCRL)
or to LPPH (or LPPL) writes the value to the corresponding
port register, from where it is driven to the corresponding
port pin.
• INTN7
• INTN6
• INTN5
• INTN4
• INTN3
• INTN2
• INTN1
• INTN0
The port function is configured as a quasi-bidirectional
port. A bit is set to input mode by writing a logic 1 to the
corresponding Port Control Register bit. This drives a
“weak” logic 1 to the corresponding output pin, which can
be overwritten by an external signal.
• Timer 2
• Timer 1
• Timer 0
• UART receiver
• UART transmitter
• I2C2
In the following register descriptions “n” represents the
external interrupt number (0 to 7), its associated registers
are identified using the same number.
• I2C1.
August 1993
19
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
6.2.4
LATCHED INTERRUPT REGISTER n (LIRn)
bit 7
bit 6
bit 5
AVN
bit 4
bit 3
PIR
bit 2
IPL2
bit 1
IPL1
bit 0
IPL0
INTNC1
INTNC0
−
Fig.12 Latched Interrupt Register n (LIRn).
Table 6 Description of LIRn bits.
SYMBOL
BIT
FUNCTION
INTNC1
INTNC0
LIRn.7
LIRn.6
Interrupt Control. These two bits enable/disable the external interrupt INTNn, or
select the pin as an I/O port. See Table 7.
AVN
LIRn.5
Autovector. When AVN = 0; INTNn is an autovectored interrupt and the processor
calculates the appropriate vector from a fixed vector table. This is also the default
value. When AVN = 1; INTNn is a vectored interrupt and the peripheral must provide
an 8-bit vector number.
−
LIRn.4
LIRn.3
Not used; reserved
PIR
Pending Interrupt Request. If PIR = 1; then a valid interrupt request has been
detected. It is automatically reset by the interrupt acknowledge cycle from the
CPU. If PIR = 0; there is no pending interrupt request; this is also the default value.
PIR can be set or reset by software by writing a logic 1 or logic 0 respectively to PIRn.
IPL2
IPL1
IPL0
LIRn.2
LIRn.1
LIRn.0
Interrupt Priority Level. These three bits select the interrupt priority level for the
external interrupt INTNn. See Table 8.
Table 7 Interrupt INTNn control.
INTNC1
INTNC0
INTERRUPT CONTROL
0
0
1
1
0
1
0
1
Interrupt disabled; this is also the default value.
interrupt enabled
Interrupt pin is selected as an I/O port.
Reserved
Table 8 Selection of interrupt priority level.
IPL2
IPL1
IPL0
PRIORITY LEVEL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt inhibited; this is also the default value.
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
August 1993
20
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
6.2.5
LATCHED INTERRUPT VECTOR n (LIVn)
bit 7
IV.7
bit 6
IV.6
bit 5
IV.5
bit 4
IV.4
bit 3
IV.3
bit 2
IV.2
bit 1
IV.1
bit 0
IV.0
Fig.13 Latched Interrupt Vector n (LIVn).
Table 9 Description of LIVn bits.
SYMBOL
BIT
FUNCTION
IV.7 to IV.0
LIVn.7 to LIVn.0 8-bit interrupt vector number. The default value of this register is 0FH.
6.2.6
LATCHED PORT CONTROL REGISTER HIGH (LPCRH)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INTN7
−
INTN6
−
INTN5
−
INTN4
−
Fig.14 Latched Port Control Register High (LPCRH).
6.2.7
LATCHED PORT CONTROL REGISTER LOW (LPCRL)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
INTN0
bit 0
INTN3
−
INTN2
−
INTN1
−
−
Fig.15 Latched Port Control Register Low (LPCRL).
August 1993
21
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
6.2.8
LATCHED PORT PIN REGISTER HIGH (LPPH)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
INTN4
bit 0
INTN7
−
INTN6
−
INTN5
−
−
Fig.16 Latched Port Pin Register High (LPPH).
6.2.9
LATCHED PORT PIN REGISTER LOW (LPPL)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
INTN0
bit 0
INTN3
−
INTN2
−
INTN1
−
−
Fig.17 Latched Port Pin Register Low (LPPL).
August 1993
22
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
6.3
System Control Registers
The P90CE201 has two System Control Registers SYSCON1 and SYSCON2 which allow system parameters to be
selected.
6.3.1
SYSTEM CONTROL REGISTER 1 (SYSCON1)
bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
NROD2 NROD1 NROD0
NRAD2 NRAD1 NRAD0
MLB011
Fig.18 System Control Register 1 (SYSCON1).
Table 10 Description of SYSCON1 bits.
SYMBOL
BIT
FUNCTION
−
SYSCON1.15
to
These eight bits are not used.
SYSCON1.8
NROD2
NROD1
NROD0
SYSCON1.7
SYSCON1.6
SYSCON1.5
These three bits select the access time for the ROM area. After a reset operation
these bits are logic 0’s. See Table 11.
−
−
SYSCON1.4
SYSCON1.3
not used
not used
NRAD2
NRAD1
NRAD0
SYSCON1.2
SYSCON1.1
SYSCON1.0
These three bits select the access time for the RAM area. After a reset operation
these bits are logic 0’s. See Table 11
Table 11 Selection of memory access times for ROM and RAM areas.
NROD2
NRAD2
NROD1
NRAD1
NROD0
NRAD0
fXTAL (MHz)
ADD WAIT
STATES
UNIT
24
20
16
12
0
0
0
0
0
0
1
1
0
1
0
1
8
4
2
0
185
101
60
235
135
85
310
185
122
60
435
268
185
101
ns
ns
ns
ns
18
35
Notes
1. 1 internal clock cycle contains 2 wait states.
2. All other states are undefined and reserved.
August 1993
23
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
6.3.2
SYSTEM CONTROL REGISTER 2 (SYSCON2)
bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
2
2
2
TOED T1 T1
TO TOED
T2 PSBPCLK PSBPCLK
I C2 I C1
CON CON
I C1
PO
IM WD
0
PS PO
SEL
1
0
PS
1
MLB012
Fig.19 System Control Register 2 (SYSCON2).
Table 12 Description of SYSCON2 bits.
SYMBOL
BIT
FUNCTION
−
SYSCON2.15 These three bits are not used.
to
SYSCON2.13
I2C2CON
I2C1CON
T2SEL
SYSCON2.12 This bit along with the three bits CR0, CR1 and CR2 held in the Serial Control
Register (S2CON), are used to select the bitrate of the I2C-bus 2 interface.
If I2C2CON = 0; the interface operates with a high bitrate. If I2C2CON = 1; the
interface operates with a low bitrate.
SYSCON2.11 This bit along with the three bits CR0, CR1 and CR2 held in the Serial Control
Register (S1CON), are used to select the bitrate of the I2C-bus 1 interface.
If I2C1CON = 0; the interface operates with a high bitrate. If I2C1CON = 1; the
interface operates with a low bitrate.
SYSCON2.10 This bit selects the frequency of the clock for Timer 2. If T2SEL = 0; the timer
operates at a frequency of fXTAL/2. If T2SEL = 1; the timer operates at a frequency
of BPCLK/4.
PSBPCLK1
PSBPCLK0
SYSCON2.9
SYSCON2.8
These two bits control the prescaler for the basic peripheral clock. See Table 13.
IM
SYSCON2.7
If IM = 0; level 7 is loaded into the Status Register during interrupt processing to
prevent the CPU from being interrupted by another interrupt source. If IM = 1; the
current interrupt level is loaded into the Status Register allowing nested interrupts.
WD
SYSCON2.6
This bit enables or disables the Watchdog timer for bus error (internal) detection.
If WD = 0; the timer is disabled. If WD = 1; the timer is enabled for bus error
detection. If no acknowledge has been sent by the addressed device after 128 × 16
internal clock cycles the on-chip bus error signal is activated.
I2C1PO
T0PS
SYSCON2.5
SYSCON2.4
The state of this bit determines whether general port pins GP.7/SDA1 and
GP.6/SCL1 are used as port pins or in their I2C-bus function. When I2C1P0 = 0; the
port function is selected. When I2C1P0 = 1; the I2C-bus is selected.
This bit enables or disables the prescaler for Timer 0. If T0PS = 0; the prescaler is
disabled and the timer operates at a frequency of fXTAL/2. If T0PS = 1; the prescaler
is enabled and the timer operates at a frequency of fXTAL/32.
T0ED1
T0ED0
SYSCON2.3
SYSCON2.2
These two bits select which transition at the external input will trigger an increment
of Timer 0. See Table 14.
August 1993
24
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
SYMBOL
T1PS
BIT
FUNCTION
SYSCON2.1
This bit enables or disables the prescaler for Timer 1. If T1PS = 0; the prescaler is
disabled and the timer operates at a frequency of fXTAL/2. If T1PS = 1; the prescaler
is enabled and the timer operates at a frequency of fXTAL/32.
T1PO
SYSCON2.0
This bit selects whether bit 5 of the general purpose port acts as a port or as an
input to Timer 1. If T1PO = 0; bit 5 of the general purpose port acts as a port. If
T1PO = 1; bit 5 of the general purpose port acts as an input to Timer 1.
Note
1. All bits of this register have a default value of logic 0 except TOED1 which has a default value of logic 1.
Table 13 Selection of basic peripheral clock for BPCLK = 4 MHz.
PSBPCLK1
PSBPCLK0
DIVISOR
fXTAL (MHz)
0
0
1
1
0
1
0
1
3.0
2.5
2.0
1.5
24
20
16
12
Table 14 Selection of input trigger for T0.
TOED1
TOED0
TRANSITION
0
0
1
0
1
0
Edge detection disabled
LOW-to-HIGH transitions will be monitored.
HIGH-to-LOW transitions will be monitored. This is the default value after a reset
operation.
1
1
Any transition will be monitored.
August 1993
25
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
6.4
Reset
6.4.3
RESET ACTIVATED BY AN OVERFLOW OF THE
WATCHDOG TIMER
The reset input for the P90CE201 is RESET (pin 53). A
Schmitt trigger is used at the input for noise rejection. The
output of the Schmitt trigger is sampled by the reset
circuitry every machine cycle. The internal reset circuitry
has an additional input which is activated by an overflow of
the Watchdog Timer (WDTIM). The On-chip Reset
configuration is shown in Fig.20.
A reset can also be initiated by an overflow of the
Watchdog Timer (see Fig.20). After a reset operation the
Watchdog Timer is disabled.
Note that when the CPU executes a RESET instruction,
the CPU is not affected, only the on-chip peripherals are
reset.
A global reset may be performed by three different
methods:
• Applying an external signal to the RESET pin
• Automatic Power-on-reset circuitry
• Activated by an overflow of the Watchdog Timer.
During the reset operation the CPU and peripherals are
reset. After an internal start-up time, the CPU reads the
reset vectors (the reset vectors are four words long).
Address 000000H is loaded into the Supervisor Stack
Pointer (SSP), and address 000004H is loaded into the
Program Counter (PC). As soon as the SSP and PC have
been loaded, the CPU initializes the Status Register to
interrupt level 7. Instruction execution then starts at the
address indicated by the Program Counter.
Watchdog
timer overflow
SCHMITT
TRIGGER
RESET
CIRCUITRY
RESET
on-chip
resistor
MLB007
6.4.1
EXTERNAL RESET USING THE RESET PIN
An external reset is accomplished by applying an external
signal to the RESET pin. To ensure that the oscillator is
stable before the controller starts, the external signal must
be held HIGH for at least 100 ms.
Fig.20 On-chip reset configuration.
6.4.2
AUTOMATIC POWER-ON RESET
Providing the rise time of VDD does not exceed 10 ms, an
automatic reset can be obtained by connecting the RESET
pin to VDD, via a 2.2 µF capacitor. When the power is
switched on, the voltage on the RESET pin is equal to VDD
minus the capacitor voltage, and decreases from VDD as
the capacitor charges through the internal resistor
(RRESET) to ground. The larger the capacitor, the more
slowly VRESET decreases. VRESET must remain above the
lower threshold of the Schmitt trigger long enough to effect
a complete reset. The time required is the oscillator
start-up time, plus 2 machine cycles. The Power-on reset
circuitry is shown in Fig.21.
V
DD
handbook, halfpage
V
DD
2.2 µF
P90CE201
RESET
R
RESET
MLB006
Fig.21 Power-on reset circuitry.
August 1993
26
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
The P90CE201 is specified for a maximum crystal
6.5
Clock circuitry
frequency of 24 MHz. The internal clock frequency is the
crystal frequency (fXTAL) divided by 2. For some
peripherals such as the UART and Watchdog Timer, a
main prescaler generates a basic peripheral clock.
Frequencies other than the basic peripheral clock will be
generated within the peripherals. The prescaler is
programmed by register SYSCON2. Table 15 shows the
frequencies of the basic peripheral clock generated by the
main prescaler.
The oscillator circuit of the P90CE201 is a single-stage
inverting amplifier in a Pierce oscillator configuration. The
circuitry between XTAL1 and XTAL2 is basically an
inverter biased to the transfer point. Either a crystal or
ceramic resonator can be used as the feedback element to
complete the oscillator circuitry. Both are operated in
parallel resonance. XTAL1 is the high gain amplifier input,
and XTAL2 is the input; see Fig.22. To drive the
P90CE201 externally, XTAL1 is driven from an external
source and XTAL2 left open-circuit; see Fig.23.
Table 15 Basic peripheral clock frequencies.
fINT DIVISOR (MHz)
fXTAL (MHz)
fINT (MHz)
3
2.5
2
1.5
24
20
16
12
12
10
8
4.00
3.33
2.66
2.00
4.80
4.00
3.20
2.40
6.00
5.00
4.00
3.00
8.00
6.66
5.33
4.00
6
handbook, halfpage
handbook, halfpage
C1
XTAL1
external clock
XTAL1
(not TTL compatible)
20 pF
C2
XTAL2
XTAL2
not connected
20 pF
MLA763
MLA764
Fig.23 Driving from an external source.
Fig.22 Oscillator circuit.
August 1993
27
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
7
INSTRUCTION SET
The P90CE201 is completely code compatible with the 68000. Consequently, programs developed for the 68000 will
run on the P90CE201. This applies to both the source and object codes. The instruction set was designed to minimize
the number of mnemonics that the programmer has to remember.
CONDITION CODES
MNEMONIC
DESCRIPTION
OPERATION
X
N
Z
V
C
ABCD
ADD
Add Decimal with Extend (Destination)10 + (Source)10 + X → Destination
*
*
U
*
*
*
U
*
*
*
Add Binary
(Destination) + (Source) → Destination
(Destination) + (Source) → Destination
(Destination) + Immediate Data → Destination
(Destination) + Immediate Data → Destination
(Destination) + (Source) + X → Destination
(Destination) Λ (Source) → Destination
(Destination) Λ Immediate Data → Destination
(Destination) Shifted by < count > → Destination
If CC then PC + d → PC
ADDA
ADDI
Add Address
−
*
−
*
−
*
−
*
−
*
Add Immediate
Add Quick
ADDQ
ADDX
AND
*
*
*
*
*
Add Extended
AND Logical
*
*
*
*
*
−
−
*
*
*
0
0
*
0
0
*
ANDI
AND Immediate
Arithmetic Shift
Branch Conditionally
Test a Bit and Change
*
*
ASL, ASR
BCC
*
*
−
−
−
−
−
*
−
−
−
−
BCHG
~(< bit number >) of Destination → Z
~(< bit number >) of Destination →
< bit number > of Destination
BCLR
BRA
Test a Bit and Clear
Branch Always
~(< bit number >) of Destination → Z
PC + d → PC
−
−
−
−
−
−
*
−
*
−
−
−
−
−
−
BSET
Test a Bit and Set
~(< bit number >) of Destination → Z
1 → < bit number > of Destination
BSR
BTST
CHK
Branch to Subroutine
Test a Bit
PC → SP @ −; PC + d → PC
−
−
−
−
−
*
−
*
−
−
−
−
~(< bit number >) of Destination → Z
If Dn < 0 or Dn > (< source >) then TRAP
Check Register against
Bounds
U
U
U
CLR
Clear an Operand
Compare
0 → Destination
−
−
−
−
−
−
0
*
1
*
0
*
0
*
CMP
(Destination) − (Source)
(Destination) − (Source)
(Destination) − Immediate Data
(Destination) − (Source)
CMPA
CMPI
CMPM
DBCC
Compare Address
Compare Immediate
Compare Memory
*
*
*
*
*
*
*
*
*
*
*
*
Test Condition,
Decrement & Branch
If (not CC) then Dn − 1 → Dn; if Dn ≠ −1 then PC
+d → PC
−
−
−
−
DIVS
DIVU
Signed Divide
(Destination) / (Source) → Destination
(Destination) / (Source) → Destination
−
−
*
*
*
*
*
*
0
0
Unsigned Divide
August 1993
28
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
CONDITION CODES
MNEMONIC
DESCRIPTION
OPERATION
X
N
Z
V
C
EOR
Exclusive OR Logical
(Destination) (Source) → Destination
−
−
−
−
−
−
−
−
*
*
*
*
*
0
0
−
0
−
−
−
−
0
0
0
0
−
0
−
−
−
−
*
EORI
EXG
Exclusive OR Immediate (Destination) Immediate Data → Destination
Exchange Register
Sign Extend
Rx ↔ Ry
−
*
−
*
EXT
(Destination) Sign − extended → Destination
Destination → PC
JMP
Jump
−
−
−
−
*
−
−
−
−
*
JSR
Jump to Subroutine
Load Effective Address
Link and Allocate
Logical Shift
PC → SP @ − ; Destination → PC
Destination → An
LEA
LINK
LSL, LSR
MOVE
An → SP @ − ; SP → An; SP + d → SP
(Destination) Shifted by < count > → Destination
Move Data from Source (Source) → Destination
−
*
*
0
to Destination
MOVE to
CCR
Move to Condition Code (Source) → CCR
*
*
*
*
*
*
*
*
*
*
MOVE to
SR
Move to the Status
Register
(Source) → SR
MOVE from
SR
Move from the Status
Register
SR → Destination
−
−
−
−
−
MOVE USP Move User Stack Pointer USP → An; An → USP
−
−
−
−
−
−
−
*
−
−
−
−
*
−
−
−
−
*
−
−
−
−
0
*
−
−
−
−
0
0
0
*
MOVEA
MOVEM
MOVEP
MOVEQ
MULS
Move Address
(Source) → Destination
Move Multiple Registers Registers → Destination; (Source) → Registers
Move Peripheral Data
Move Quick
(Source) → Destination
Immediate Data → Destination
(Destination) * (Source) → Destination
(Destination) * (Source) → Destination
0 − (Destination)10 − X → Destination
Signed Multiply
Unsigned Multiply
*
*
MULU
*
*
*
NBCD
Negate Decimal with
Extend
U
*
U
NEG
Negate
0 − (Destination) → Destination
*
*
*
*
*
*
*
*
*
*
NEGX
NOP
Negate with Extend
No Operation
0 − (Destination) − X → Destination
−
−
−
−
−
−
August 1993
29
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
CONDITION CODES
MNEMONIC
DESCRIPTION
OPERATION
X
N
Z
V
C
NOT
Logical Complement
Inclusive OR Logical
~(Destination) → Destination
−
−
−
−
−
−
*
*
*
*
*
0
0
0
−
−
0
0
0
0
0
−
−
*
OR
(Destination) v (Source) → Destination
ORI
Inclusive OR Immediate (Destination) v Immediate Data → Destination
*
*
PEA
Push Effective Address
Reset External Devices
Destination → SP @−
−
−
*
−
−
*
RESET
ROL, ROR
−
Rotate (Without Extend) (Destination) Rotated by < count > → Destination
ROXL,
ROXR
Rotate with Extend
(Destination) Rotated by < count > → Destination
*
*
*
RTE
RTR
Return from Exception
SP @ + → SR; SP @ + → PC
SP @ + → SR; SP @ + → PC
*
*
*
*
*
*
*
*
*
*
Return and Restore
Condition Codes
RTS
Return from Subroutine
SP @ + → PC
−
−
−
−
−
SBCD
Subtract Decimal with
Extend
(Destination)10 − (Source)10 − X → Destination
*
U
*
U
*
SCC
Set According to
Condition
if CC then 1 → Destination; else 0 → Destination
Immediate Data → SR; STOP
−
−
−
−
−
STOP
Load Status Register
and Stop
*
*
*
*
*
SUB
Subtract Binary
(Destination) − (Source) → Destination
(Destination) − (Source) → Destination
(Destination) − Immediate Data → Destination
(Destination) − Immediate Data → Destination
(Destination) − (Source) − X → Destination
Register [ 31:16 ] ↔ Register [ 15:0 ]
*
−
*
*
−
*
*
*
*
*
*
−
*
*
*
*
*
*
−
*
*
−
*
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
Subtract Address
Subtract Immediate
Subtract Quick
*
*
*
Subtract with Extend
Swap Register Halves
*
*
*
−
−
0
0
0
0
Test and Set an Operand (Destination) Tested → CC; 1 → [ 7 ] of
Destination
TRAP
TRAPV
TST
Trap
PC → SSP @ − ; SR → SSP @ − ; (Vector) →PC
If V then TRAP
−
−
−
−
−
−
*
−
−
*
−
−
0
−
−
−
0
−
Trap on Overflow
Test and Operand
Unlink
(Destination) Tested → CC
An →SP; SP @ + → An
UNLK
−
−
Notes
1. [ ] = bit number
2. * = affected
3. − = unaffected
4. 0 = cleared
5. 1 = set
6. U = defined
7. @ = location addressed by
August 1993
30
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
7.1
Table 16 Data addressing modes.
MODE
Addressing modes
GENERATION
Register Direct Addressing
Data Register Direct
EA = Dn
EA = An
Address Register Direct
Absolute Data Addressing
Absolute Short
Absolute Long
EA = (Next Words)
EA = (Next Two Words)
Program Counter Relative Addressing
Relative with Offset
EA = (PC) + d16
Relative with Index and Offset
EA = (PC) + (Xn) + d8
Register Indirect Addressing
Register Indirect
EA = (An)
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset
EA = (An), An ← An + N
An ← An − N, EA = (An)
EA = (An) + d16
EA = (An) + (Xn) + d8
Immediate Data Addressing
Immediate
DATA = Next Word(s)
Inherent Data
Quick Immediate
Implied Addressing
Implied Register
EA = SR, USP, SSP, PC, SP
Notes
1. EA = Effective Address
2. An = Address Register
3. Dn = Data Register
4. Xn = Address or Data Register used as Index Register
5. N = 1 for bytes; 2 for words; 4 for long words
6. ← = Replaces
7. SR = Status Register
8. PC = Program Counter
9. () = Contents of
10. d8 = 8-bit offset (displacement)
11. d16 = 16-bit offset (displacement)
12. SP = Stack Pointer
13. SSP = System Stack Pointer
14. USP = User Stack Pointer
August 1993
31
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
7.2
Instruction timing
This data assumes that both memory read and write cycle times are four internal clock periods (no additional wait states).
Additional wait states for memory accesses have to be added to the total instruction time.
Accesses to registers listed in the Register Map are only three clock periods, therefore one clock period can be
subtracted for each access to such a register. However, access to the UART registers takes up to ten clock periods due
to synchronization. Consequently, ten clock periods have to be added for UART register accesses.
Table 17 Effective address calculation times.
SOURCE
Rn
ADDRESSING MODE
Data Address Register Direct
BYTE, WORD
LONG
0
4
(0/0)
(1/0)
(1/0)
(1/0)
(2/0)
(2/0)
(2/0)
(3/0)
(2/0)
(2/0)
(1/0)
0
(0/0)
(2/0)
(2/0)
(2/0)
(3/0)
(3/0)
(3/0)
(4/0)
(3/0)
(3/0)
(2/0)
(An)
Address Register Indirect
8
(An)+
−(An)
d(An)
d(An, Xi)
xxx.S
xxx.L
Address Register Indirect postincrement
Address Register Indirect predecrement
Address Register Indirect Displacement
Address Register Indirect with Index
Absolute Short
4
8
7
11
15
18
12
16
15
18
8
11
14
8
Absolute Long
12
11
14
4
d(PC)
d(PC, Xi)
#xxx
Program Counter with Displacement
Program Counter with Index
Immediate
Note
1. The number of bus read and write cycles are shown in parentheses as (R/W).
Table 18 MOVE Byte and Move Word instruction clock periods.
SOURCE
Rn
(1/0) 11
(An)
(1/1) 11
(An)+
(1/1) 14
−(An)
(1/1) 18
d(An)
d(An,Xi)
xxx.S
xxx.L
Rn
7
(1/1) 21
(1/1) 15
(2/1) 19
(2/1) 19
(2/1) 22
(3/1) 26
(3/1) 29
(3/1) 23
(4/1) 27
(3/1) 26
(3/1) 29
(2/1) 19
(1/1) 19
(2/1) 23
(2/1) 23
(2/1) 26
(3/1) 30
(3/1) 33
(3/1) 27
(4/1) 31
(3/1) 30
(3/1) 33
(2/1) 23
(1/1)
(An)
11 (2/0) 15
11 (2/0) 15
14 (2/0) 18
18 (3/0) 22
21 (3/0) 25
15 (3/0) 19
19 (4/0) 23
18 (3/0) 22
(2/1) 15
(2/1) 15
(2/1) 18
(3/1) 22
(3/1) 25
(3/1) 19
(4/1) 23
(3/1) 22
(3/1) 25
(2/1) 15
(2/1) 18
(2/1) 18
(2/1) 22
(3/1) 25
(3/1) 28
(3/1) 22
(4/1) 26
(3/1) 25
(3/1) 28
(2/1) 18
(2/1) 22
(2/1) 22
(2/1) 25
(3/1) 29
(3/1) 32
(3/1) 26
(4/1) 30
(3/1) 29
(3/1) 32
(2/1) 22
(2/1) 25
(2/1) 25
(2/1) 28
(3/1) 32
(3/1) 35
(3/1) 29
(4/1) 33
(3/1) 32
(3/1) 35
(2/1) 25
(2/1)
(2/1)
(2/1)
(3/1)
(3/1)
(3/1)
(4/1)
(3/1)
(3/1)
(2/1)
(An)+
−(An)
d(An)
d(An,Xi)
xxx.S
xxx.L
d(PC)
d(PC,Xi) 21 (3/0) 25
#xxx
11 (2/0) 15
August 1993
32
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
Table 19 MOVE Long instruction clock periods.
SOURCE
Rn
(1/0) 15
(An)
(1/2) 15
(An)+
(1/2) 18
−(An)
(1/2) 22
d(An)
d(An,Xi)
xxx.S
xxx.L
(3/2)
Rn
7
(2/2) 25
(2/2) 19
(4/2) 27
(4/2) 27
(4/2) 30
(5/2) 34
(5/2) 37
(5/2) 31
(6/2) 35
(5/2) 34
(5/2) 37
(4/2) 27
(2/2) 23
(4/2) 31
(4/2) 31
(4/2) 34
(5/2) 38
(5/2) 41
(5/2) 35
(6/2) 39
(5/2) 38
(5/2) 41
(4/2) 31
(An)
15 (3/0) 23
15 (3/0) 23
18 (3/0) 26
22 (4/0) 30
25 (4/0) 33
19 (4/0) 27
23 (5/0) 31
22 (4/0) 30
(3/2) 23
(3/2) 23
(3/2) 26
(4/2) 30
(4/2) 33
(4/2) 27
(5/2) 31
(4/2) 30
(4/2) 33
(3/2) 23
(3/2) 26
(3/2) 26
(3/2) 29
(4/2) 33
(4/2) 36
(4/2) 30
(5/2) 34
(4/2) 33
(4/2) 36
(3/2) 26
(3/2) 30
(3/2) 30
(3/2) 33
(4/2) 37
(4/2) 40
(4/2) 34
(5/2) 38
(4/2) 37
(4/2) 40
(3/2) 30
(4/2) 33
(4/2) 33
(4/2) 36
(5/2) 40
(5/2) 43
(5/2) 37
(6/2) 41
(5/2) 40
(5/2) 43
(4/2) 33
(5/2)
(5/2)
(5/2)
(6/2)
(6/2)
(6/2)
(7/2)
(6/2)
(6/2)
(5/2)
(An)+
−(An)
d(An)
d(An,Xi)
xxx.S
xxx.L
d(PC)
d(PC,Xi) 25 (4/0) 33
#xxx 15 (3/0) 23
Table 20 Standard instruction clock periods.
INSTR
SIZE
op < ea > ,An
op < ea > ,Dn
op < Dn > ,M
ADD
Byte, Word
Long
7 + (1/0)
7 + (1/0)
7 + (1/0)
11 + (1/1)
7 + (1/0)
15 + (1/2)
AND
CMP
Byte, Word
Long
−
7 + (1/0)
11 + (1/1)
−
7 + (1/0)
15 + (1/2)
Byte, Word
Long
7 + (1/0)
7 + (1/0)
−
7 + (1/0)
7 + (1/0)
−
DIVS
DIVU
EOR
−
−
169 + ** (1/0) (3)
130 + * (1/0) (2)
7 + (1/0)
−
−
−
−
Byte, Word
Long
−
11 + (1/1)
15 + (1/2)
−
−
7 + (1/0)
MULS
MULU
OR
−
−
76 + * (1/0) (2)
76 + * (1/0) (2)
7 + (1/0)
−
−
Byte, Word
Long
−
11 + (1/1)
15 + (1/2)
11 + (1/1)
15 + (1/2)
−
7 + (1/0)
SUB
Byte, Word
Long
7 + (1/0)
7 + (1/0)
7 + (1/0)
7 + (1/0)
Notes
1. + = add effective address calculation time
2. * = the duration of the instruction is constant
3. ** = indicates maximum value.
August 1993
33
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
Table 21 Immediate instruction clock periods.
INSTR.
SIZE
op < # > ,Dn
op < # > ,An
op < # > ,< M >
ADDI
Byte, Word
Long
14 (2/0)
18 (3/0)
7 (1/0)
−
18 + (2/1)
26 + (3/2)
11 + (1/1)
15 + (1/2)
18 + (2/1)
24 + (3/2)
14 + (2/0)
18 + (3/0)
18 + (2/1)
26 + (3/2)
−
−
ADDQ
ANDI
CMPI
EORI
Byte, Word
Long
7 (1/0)
7 (1/0)
7 (1/0)
Byte, Word
Long
14 (2/0)
18 (3/0)
14 (2/0)
18 (3/0)
14 (2/0)
18 (3/0)
7 (1/0)
−
−
Byte, Word
Long
−
−
Byte, Word
Long
−
−
MOVEQ
ORI
Long
−
Byte, Word
Long
14 (2/0)
18 (3/0)
14 (2/0)
18 (3/0)
7 (1/0)
−
18 + (2/1)
26 + (3/2)
18 + (2/1)
26 + (3/2)
11 + (1/1)
15 + (1/2)
−
−
SUBI
Byte, Word
Long
−
SUBQ
Byte, Word
Long
7 (1/0)
7 (1/0)
7 (1/0)
Note
1. + = add effective calculation time.
August 1993
34
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
Table 22 Single operand instruction clock periods.
INSTRUCTION
SIZE
REGISTER
MEMORY
CLR
Byte, Word
Long
7 (1/0)
7 (1/0)
10 (1/0)
7 (1/0)
7 (1/0)
7 (1/0)
7 (1/0)
7 (1/0)
7 (1/0)
13 (1/0)
13 (1/0)
10 (1/0)
7 (1/0)
7 (1/0)
11 (1/1)+ * (2)
15 (1/2)+ ** (3)
14 (1/1)(2)
11 (1/1)+
NBCD
NEG
Byte
Byte, Word
Long
15 (1/2)+
11 (1/1)+
NEGX
NOT
Scc
Byte, Word
Long
15 (1/2)+
11 (1/1)+
Byte, Word
Long
15 (1/2)+
17 (1/1)+
14 (1/1)+
15 (2/1)+ * (2)
7 (1/0)+
Byte, Word
Long
TAS
TST
Byte, Word
Byte, Word
Long
7 (1/0)+
Notes
1. + = add effective calculation time
2. * = subtract one read cycle (−4(1/0)) from effective address calculation
3. ** = subtract two read cycles (−8(2/0)) from effective address calculation.
Table 23 Shift/rotate instruction clock periods.
INSTRUCTION
SIZE
REGISTER
MEMORY
ASR,ASL
Byte, Word
Long
13 + 3n (1/0)
13 + 3n (1/0)
13 + 3n (1/0)
13 + 3n (1/0)
13 + 3n (1/0)
13 + 3n (1/0)
13 + 3n (1/0)
13 + 3n (1/0)
14 (1/1)+
−
LSR,LSL
ROR,ROL
Byte, Word
Long
14 (1/1)+
−
Byte, Word
Long
14 (1/1)+
−
14 (1/1)+
−
ROXR,ROXL
Byte, Word
Long
Note
1. + = add effective calculation time.
August 1993
35
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
Table 24 Bit manipulation instruction clock periods.
DYNAMIC
REGISTER
STATIC
INSTRUCTION
SIZE
MEMORY
REGISTER
MEMORY
BCHG
Byte
Long
Byte
Long
Byte
Long
Byte
Long
−
10 (1/0)
−
14 (1/1)+
−
17 (2/0)
−
21 (2/1)+
−
−
BCLR
BSET
BTST
14 (1/1)+
21 (2/1)+
10 (1/0)
−
−
17 (2/0)
−
−
14 (1/1)+
21 (2/1)+
10 (1/0)
−
−
7 (1/0)+
−
17 (2/0)
−
−
14 (2/0)+
−
7 (1/0)
14 (2/0)
Note
1. + = add effective calculation time.
Table 25 Conditional instruction clock periods.
INSTRUCTION
DISPLACEMENT
TRAP/BRANCH TAKEN
TRAP/BRANCH NOT TAKEN
Bcc
.B
13 (1/0)
14 (2/0)
13 (1/0)
14 (2/0)
21 (1/2)
25 (2/2)
−
13 (1/0)
14 (2/0)
−
.W
BRA
BSR
DBcc
.B
.W
−
.B
.W
−
−
cc True
cc False
−
14 (2/0)
17 (3/2)
19 (1/0)+
10 (1/0)
17 (2/0)
70 (3/4)
55 (3/4)
CHK
TRAPV
−
Note
1. + = add effective calculation time.
August 1993
36
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
Table 26 JMP, JSR, LEA, PEA, MOVEM instruction clock periods.
INSTR
JMP
Size
(An)
(An)+
−(An)
d(An)
14
d(An, Xi)
xxx.S
14
xxx.L
18
d(PC)
14
d(PC,Xi)
−
−
−
−
−
−
−
−
7
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
17
17
(1/0)
18
(2/0)
25
(2/0)
28
(2/0)
25
(3/0)
29
(2/0)
25
(2/0)
28
JSR
LEA
PEA
(1/2)
7
(2/2)
14
(2/2)
17
(2/2)
14
(3/2)
18
(2/2)
14
(2/2)
17
(1/0)
18
(2/0)
25
(2/0)
28
(2/0)
25
(3/0)
29
(2/0)
25
(2/0)
28
(1/2)
(2/2)
(2/2)
(2/2)
(3/2)
(2/2)
(2/2)
MOVEM .W
M → R
26 + 7n
(2+n/0)
26 + 7n
(2+n/0)
−
−
30 + 7n
(3+n/0)
33 + 7n
(3+n/0)
30 + 7n 34 + 7n 30 + 7n 33 + 7n
(3+n/0) (4+n/0) (3+n/0) (3+n/0)
.L
26 + 11n 26 + 11n
(2+2n/0)
−
30 + 11n 33 + 11n 30 + 11n 34 + 11n 30 + 11n 33 + 11n
(3+2n/0) (3+2n/0)
(3+2n/0)
(2+2n/0)
(3+2n/0) (4+2n/0) (3+2n/0)
MOVEM .W
R → M
23 + 7n
(2/n)
−
−
23 + 7n
(2/n)
27 + 7n
(3/n)
30 + 7n
(3/n)
27 + 7n 31 + 7n
(3/n) (4/n)
−
−
−
−
.L
23 + 11n
(2/2N)
−
−
23 + 11n 27 + 11n 30 + 11n 27 + 11n 31 + 11n
−
−
−
−
(2/2n)
(3/2n)
(3/2n)
(3/2n)
(4/2n)
Note
1. n = number of registers to move.
Table 27 Multi-precision instruction clock periods.
INSTRUCTION
SIZE
Byte, Word
op Dn, Dn
op M, M
ADDX
7 (1/0)
7 (1/0)
−
28 (3/1)
40 (5/2)
18 (3/0)
26 (5/0)
28 (3/1)
40 (5/2)
31 (3/1)
31 (3/1)
Long
Byte, Word
Long
CMPM
SUBX
−
Byte, Word
Long
7 (1/0)
7 (1/0)
10 (1/0)
10 (1/0)
ABCD
SBCD
Byte
Byte
August 1993
37
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
Table 28 Miscellaneous clock periods.
REGISTER to
MEMORY
MEMORY to
REGISTER
INSTRUCTION
ANDI to CCR
SIZE
REGISTER
MEMORY
−
−
−
−
−
14
14
14
14
13
7
(2/0)
(2/0)
(2/0)
(2/0)
(1/0)
(1/0)
(1/0)
(2/2)
(1/0)
(1/0)
(1/0)
(1/0)
(1/0)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ANDI to SR
EORI to CCR
EORI to SR
EXG
−
−
−
−
−
−
−
−
−
−
−
−
EXT
WORD
LONG
7
LINK
−
25
7
MOVE from SR
MOVE to CCR
MOVE to SR
MOVE from USP
MOVE to USP
MOVEP
−
11
(1/1)+
(1/0)+
(1/0)+
−
10
10
7
10
10
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
7
WORD
−
25
39
(2/2)
(2/4)
22
36
(4/0)
(6/0)
LONG
−
−
NOP
−
−
−
−
−
−
−
−
−
−
−
−
−
−
7
(1/0)
(2/0)
(2/0)
(1/0)
(5/0)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ORI to CCR
ORI to SR
RESET
14
14
154
39
RTE - short format
RTE - long format
no rerun
140
146
151
22
(18/0)
(18/0)
(19/0)
(4/0)
with rerun
return of TAS
RTR
RTS
15
(3/0)
STOP
17
(2/0)
SWAP
7
(1/0)
UNLK
15
(3/0)
Note
1. + = add effective address calculation time.
August 1993
38
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
Table 29 Exception processing clock periods.
EXCEPTION
NUMBER OF CLOCK PERIODS
Address error
Interrupt
158 (3/17)
65 (4/4), note 1
55 (3/4)
Illegal instruction
Privilege instruction
Trace
55 (3/4)
55 (3/4)
Trap
52 (3/4)
Divide by Zero
RESET (note 2)
64 (3/4)+
43 (4/0)
Note
1. The interrupt acknowledge bus cycle is assumed to take four clock periods.
2. The maximum time from when RESET is first sampled as released to first instruction fetch.
August 1993
39
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
8
I2C-BUS INTERFACE
General
8.1
The P90CE201 contains two fully independent I2C-bus serial interfaces (I2C1 and I2C2); the functionality of both is
identical. The I2C-bus interfaces can operate in four modes:
1. Master transmitter
2. Master receiver
3. Slave transmitter
4. Slave receiver.
The I2C-bus interface is connected to the I2C-bus by a data pin (SDA) and by a clock pin (SCL). Data transport, clock
generation, address recognition and bus arbitration are all controlled by hardware. Each I2C-bus interface is controlled
by a set of six registers.
GC
SLAVE ADDRESS
SHIFT REGISTER
SnADR
SnDAT
SDAn
ARBITRATION LOGIC
SCLn
BUS CLOCK GENERATOR
7
6
6
5
5
4
4
3
3
2
2
1
1
0
SnCON
7
0
MLB252
SnSTA
Fig.24 Block diagram of I2C-bus serial interface.
August 1993
40
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
8.2
I2C-bus interface registers
In the following register descriptions “n” represents the I2C-bus serial interface number (1 or 2); its associated registers
are identified using the same number.
8.2.1
SERIAL CONTROL REGISTER (SnCON)
S1CON is located at address 8000 2007H; S2CON is located at address 8000 2017H. These registers have a default
value of 00H.
bit 7
CR2
bit 6
ENS
bit 5
STA
bit 4
STO
bit 3
SI
bit 2
AA
bit 1
CR1
bit 0
CR0
Fig.25 Serial Control Register (SnCON)
Table 30 Description of SnCON bits.
SYMBOL
BIT
FUNCTION
CR2
CR1
CR0
SnCON.7
SnCON.1
SnCON.0
Clock Rate. These three bits along with bit SYSCON2.12 (or SYSCON2.11) determine
the serial clock frequency that is generated in the master mode of operation. The
frequencies of 100 kHz and 400 kHz can be selected for the oscillators frequencies of
12, 16, 20 and 24 MHz, as shown in Table 31.
ENS
STA
SnCON.6
SnCON.5
Enable Serial I/O. When ENS = 0; the serial interface I/O is disabled and reset. When
ENS = 1; the serial interface is enabled.
Start flag. When this bit is set in slave mode, the hardware checks the I2C-bus and
generates a START condition if the bus is free or after the bus becomes free. If the
device operates in Master Mode it will generate a repeated START condition.
STO
SnCON.4
Stop flag. If this bit is set in the master mode a STOP condition is generated. A STOP
condition detected on the I2C-bus clears this bit. The STOP bit may also be set in Slave
Mode in order to recover from an error condition. In this case no STOP condition is
generated to the I2C-bus, but the hardware releases the SDA and SCL lines and
switches to the not selected slave receiver mode. The STOP flag is cleared by the
hardware.
SI
SnCON.3
Serial Interrupt flag. This flag is set, and an interrupt is generated, after any of the
following events occur:
-
-
-
-
-
-
A START condition is generated in Master Mode
The own slave address has been received during AA = 1
The general call address has been received while SnADR.0 = 1 and AA = 1
A data byte has been received or transmitted in master mode
A data byte has been received or transmitted as selected slave
A STOP or START condition is received as selected slave receiver or transmitter.
While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must
be reset by software.
August 1993
41
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
SYMBOL
BIT
FUNCTION
AA
SnCON.2
Assert Acknowledge. When this bit is set, an acknowledge is returned after any one of
the following conditions:
-
-
-
-
Own slave address is received
The general call address is received (S1ADR.0 = 1)
A data byte is received, while the device is programmed to be a master receiver
A data byte is received, while the device is a selected slave receiver.
When this bit is reset, no acknowledge is returned. Consequently, no interrupt is
requested when the own slave address or general call address is received.
Table 31 Selection of I2C-bus bit rate.
BIT RATE at fCLK (MHz)
CR3
(note 1)
CR2
CR1
CR0
UNIT
DEVICE
Fast I2C-bus
12
16
20
24
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
200
240
300
400
50
266.66
320
400
−
333.33
400
−
400
−
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
−
−
−
66.67
80
83.33
100
−
100
−
Standard I2C-bus
60
75
100
−
−
100
6.25
7.5
−
−
8.33
10
10.42
12.5
15.63
20.83
5.21
6.25
7.81
10.42
12.5
15
9.38
12.5
3.13
3.75
4.69
6.25
12.5
16.67
4.17
5
18.75
25
6.25
7.5
9.38
12.5
6.25
8.33
Note
1. CR3 is defined by SYSCON2.12 (or SYSCON2.11).
August 1993
42
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
8.2.2
SERIAL STATUS REGISTER (SnSTA)
S1STA resides at address 8000 2005H; S2STA resides at address 8000 2015H. The contents of the Serial Status
Registers may be used as vectors to service routines. This optimizes the response time of the software and consequently
that of the I2C-bus. S1STA and S2STA are read-only registers. These registers have a default value of F8H.
bit 7
SC4
bit 6
SC3
bit 5
SC2
bit 4
SC1
bit 3
SC0
bit 2
0
bit 1
0
bit 0
0
Fig.26 Serial Status Register (SnSTA).
Table 32 Description of SnSTA bits.
SYMBOL
BIT
FUNCTION
SC4
SC3
SC2
SC1
SC0
SnSTA.7
SnSTA.6
SnSTA.5
SnSTA.4
SnSTA.3
Status Code. These 5 bits may be read in order to determine the status of the
I2C-bus. Tables 33 to 37 show all the status codes.
−
−
−
S1STA.2
S1STA.1
S1STA.0
These three bits are held LOW and allow the user to use the status code directly
as a vector to a service routine.
Table 33 Master Transmitter Mode.
S1STA VALUE
DESCRIPTION
08H
10H
18H
20H
28H
30H
38H
A START condition has been transmitted
A repeated START condition has been transmitted
SLA and W have been transmitted, ACK has been received
SLA and W have been transmitted, ACK received
DATA of SnDAT has been transmitted, ACK received
DATA of SnDAT has been transmitted, ACK received
Arbitration lost in SLA, R/W or DATA
Table 34 Master Receiver Mode.
S1STA VALUE
DESCRIPTION
A START condition has been transmitted
A repeated START condition has been transmitted
08H
10H
38H
40H
48H
50H
58H
Arbitration lost while returning ACK
SLA and R have been transmitted, ACK received
SLA and R have been transmitted, ACK received
DATA has been received, ACK returned
DATA has been received, ACK returned
August 1993
43
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
Table 35 Slave Receiver Mode.
S1STA VALUE
DESCRIPTION
Own SLA and W have been received, ACK returned
60H
68H
70H
78H
80H
88H
90H
98H
A0H
Arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned
General call has been received, ACK returned
Arbitration lost in SLA, R/W as MST. General call received, ACK returned
Previously addressed with own SLA. DATA byte received, ACK returned
Previously addressed with own SLA. DATA byte received, ACK returned
Previously addressed with general call. DATA byte received, ACK has been returned
Previously addressed with general call. DATA byte received, ACK has been returned
A STOP condition or repeated START condition received while still addressed as SLV/REC or
SLV/TRX
Table 36 Slave Transmitter Mode.
S1STA VALUE
DESCRIPTION
A8H
B0H
B8H
C0H
C8H
Own SLA and R received, ACK returned
Arbitration lost in SLA, R/W as MST. Own SLA and R received, ACK returned
DATA byte has been transmitted, ACK received
DATA byte has been transmitted, ACK received
Last DATA byte has been transmitted, ACK received
Table 37 Miscellaneous.
S1STA VALUE
DESCRIPTION
00H
Bus error during MST mode or selected SLV mode, due to an erroneous START or STOP
condition
F8H
No relevant information available, SI not set
ABBREVIATIONS USED:
SLA:
R:
7-bit slave address
Read bit
Write bit
W:
ACK:
ACK:
DATA:
MST:
SLV:
TRX:
REC:
Acknowledgement (acknowledge bit = logic 0)
No acknowledgement (acknowledge bit = logic 1)
8-bit data byte to or from I2C-bus
Master
Slave
Transmitter
Receiver.
August 1993
44
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
8.2.3
DATA SHIFT REGISTER (SnDAT)
S1DAT is located at address 8000 2001H; S2DAT is located at address 8000 2011H. These two identical registers
contain the serial data to be transmitted or data that has just been received. Bit 7 is transmitted or received first; i.e. data
shifted from right to left. These registers have a default value of 00H.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DATA.7
DATA.6
DATA.5
DATA.4
DATA.3
DATA.2
DATA.1
DATA.0
Fig.27 Data Shift Register (SnDAT).
8.2.4
ADDRESS REGISTER (SnADR)
S1ADR resides at address 8000 2003H; S2ADR resides at address 8000 2013H. These two identical 8-bit registers may
be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave
receiver/transmitter. The LSB (GC) is used to determine whether the general call address is recognized. These registers
have a default value of 00H.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GC
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
Fig.28 Address Register (SnADR).
Table 38 Description of SnADR bits.
SYMBOL
BIT
FUNCTION
SLA6 to SLA0
GC
SnADR.7 to SnADR.1 Own slave address
SnADR.0
When a logic 0, the general call address is not recognized. When a logic 1,
the general call address is recognized
August 1993
45
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
8.2.5
INTERRUPT REGISTERS
The I2C-bus interface contains four registers for the control of I2C-bus interrupts. One pair of registers (S1IR and S1IV)
provide independent control of the I2C1 interface interrupts; the other pair of registers (S2IR and S2IV) provide
independent control of the I2C2 interface interrupts.
In the following register descriptions “n” represents the I2C-bus interface number (1 or 2), its associated registers are
identified using the same number.
8.2.6
INTERRUPT REGISTERS (SnIR)
These registers have a default value of XX0X0000b.
bit 7
bit 6
bit 5
AVN
bit 4
bit 3
PIR
bit 2
IPL2
bit 1
IPL1
bit 0
IPL0
−
−
−
Fig.29 Interrupt Register (SnIR).
Table 39 Description of SnIR bits.
SYMBOL
BIT
FUNCTION
−
−
SnIR.7 Reserved
SnIR.6 Reserved
AVN
SnIR.5 Autovector. When AVN = 0; the interrupt is an autovectored interrupt and the processor
calculates the appropriate vector from a fixed vector table. AVN = 0 is also the default
value. When AVN = 1; the interrupt is a vectored interrupt and the peripheral must provide
an 8-bit vector number.
−
SnIR.4 Reserved
PIR
SnIR.3 Pending Interrupt Request. This bit is set to a logic 1 when a valid interrupt request has
been detected. It is automatically reset by the interrupt acknowledge cycle from the CPU.
If PIR = 0, there is no pending interrupt request; this is also the default value. The PIR bit
can also be reset by software by writing a logic 0 to this location.
IPL2
IPL1
IPL0
SnIR.2 Interrupt Priority Level. These three bits select the interrupt priority level. See Table 40.
SnIR.1
SnIR.1
Table 40 Selection of interrupt priority level.
IPL2
IPL1
IPL0
PRIORITY LEVEL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt inhibited; this is also the default value.
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
August 1993
46
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
8.2.7
INTERRUPT VECTOR (SnIV)
These registers have a default value of 0FH.
bit 7
IV.7
bit 6
IV.6
bit 5
IV.5
bit 4
IV.4
bit 3
IV.3
bit 2
IV.2
bit 1
IV.1
bit 0
IV.0
Fig.30 Interrupt Vector (SnIV).
Table 41 Description of SnIV bits.
SYMBOL
BIT
FUNCTION
IV.7 to IV.0
SnIV.7 to SnIV.0 8-bit interrupt vector number. The default value of this register is 0FH.
August 1993
47
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
9
UART SERIAL INTERFACE
General
Mode 2:
11 bits are transmitted (through TXD) or
received (through RXD): a start bit (0),
8 data bits (LSB first), a programmable 9th
data bit, and a stop bit (1). On transmit, the
9th data bit (TB8 in SCON) usually
9.1
This serial port is full duplex which means that it can
transmit and receive simultaneously. It is also
receive-buffered and can commence reception of a
second byte before a previously received byte has been
read from the receive register. (However, if the first byte
has not been read by the time the reception of the second
byte is complete, one of the bytes will be lost). The serial
port receive and transmit registers are both accessed as
register SBUF. Writing to SBUF loads the Transmit
Register and reading SBUF accesses the physically
separate Receive Register. The baud rate for receiver and
transmitter can be generated by any timer using its baud
rate generator output.
represents the parity bit. On receive, the 9th
data bit is stored in RB8 in SCON, while the
stop bit is ignored. The baud rate is fixed at
3/32 of the BPCLK frequency.
Mode 3:
11 bits are transmitted (through TXD) or
received (through RXD): a start bit (0), 8
data bits (LSB first), a programmable 9th
data bit and a stop bit (1). Mode 3 is the
same as Mode 2 except that the baud rate
in Mode 3 is variable.
In all four modes, transmission is initiated by any
instruction that uses SBUF as a destination register.
Reception is initiated in Mode 0 by the condition RI = 0 and
REN = 1. Reception is initiated in the other modes by the
incoming start bit if REN = 1.
9.2
Operating modes
The serial port can operate in one of four modes:
Mode 0:
Mode 1:
Serial data enters and exits through RXD.
TXD outputs the shift clock. 8 data bits are
transmitted or received (LSB first).
The baud rate is fixed at 1/4 the basic
peripheral clock.
10 bits are transmitted (through TXD) or
received (through RXD): a start bit (0),
8 data bits (LSB first), and a stop bit (1).
On receive, the stop bit is stored in RB8 in
register SCON. The baud rate is variable.
9.3
9.3.1
UART registers
UART SHIFT REGISTER (SBUF)
The UART Shift Register resides at address 8000 2021H. SBUF contains the serial data to be transmitted or data just
being received. Bit 0 is transmitted or received first; i.e data is shifted from left to right.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SBUF.7
SBUF.6
SBUF.5
SBUF.4
SBUF.3
SBUF.2
SBUF.1
SBUF.0
Fig.31 UART Shift Register (SBUF).
August 1993
48
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
9.3.2
UART CONTROL REGISTER (SCON)
The Serial Port Control Register and Status Register (SCON) contains not only the mode selection bits, but also the 9th
data bit for transmit and receive (TB8 and RB8), and the serial port interrupt bits (TI and RI). SCON has a default value
of 00H.
bit 7
SM0
bit 6
SM1
bit 5
SM2
bit 4
bit 3
TB8
bit 2
RB8
bit 1
TI
bit 0
RI
REN
Fig.32 UART Control Register (SCON).
Table 42 Description of SCON bits.
SYMBOL
BIT
FUNCTION
These two bits are used to select the serial port mode. See Table 43.
SM0
SM1
SCON.7
SCON.6
SM2
SCON.5
Enables the multiprocessor communication feature in Modes 2 and 3. In Modes 2
and 3, if SM2 = 1, then RI will not be activated if the received 9th data bit (RB8) is
a logic 0. In Mode 1, if SM2 = 1, then RI will not be activated unless a valid stop bit
was received. In Mode 0, SM2 should be a logic 0.
REN
TB8
RB8
TI
SCON.4
SCON.3
SCON.2
SCON.1
Enables serial reception and is set by software to enable reception, and cleared
by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or cleared by
software as required.
In Modes 2 and 3, RB8 is the 9th data bit that is received. In Mode 1, if SM2 = 0,
then RB8 is the stop bit that was received. In Mode 0, RB8 is not used.
Transmit Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or
at the beginning of the stop bit time in the other modes, in any serial transmission.
Must be cleared by software.
RI
SCON.0
Receive Interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or
halfway through the stop bit time in the other modes, in any serial transmission
(however see SM2). Must be cleared by software.
Table 43 Selection of the serial port modes.
SM0
SM1
MODE
DESCRIPTION
BAUD RATE
0
0
1
1
0
1
0
1
0
1
2
3
Shift register
8-bit UART
9-bit UART
9-bit UART
BPCLK/4
variable
3/32 BPCLK
variable
August 1993
49
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
9.3.3
UART INTERRUPT REGISTERS
The UART interface contains four registers for the control of the transmitter and receiver interrupts. One pair of registers
(UTIR and UTIV) provide independent control of transmitter interrupts; the other pair of registers (URIR and URIV)
provide independent control of receiver interrupts.
In the following register descriptions “x” can be replaced by “T” for transmitter, or “R” for receiver.
9.3.4
UART TRANSMITTER/RECEIVER INTERRUPT REGISTER (UXIR)
These registers have a default value of XX0X0000b.
bit 7
bit 6
bit 5
AVN
bit 4
bit 3
PIR
bit 2
IPL2
bit 1
IPL1
bit 0
IPL0
−
−
−
Fig.33 UART Transmitter/Receiver Interrupt Register (UxIR).
Table 44 Description of UxIR bits.
SYMBOL
BIT
FUNCTION
−
−
UxIR.7
UxIR.6
UxIR.5
Reserved
Reserved
AVN
Autovector. When AVN = 0; the transmitter/receiver interrupt is an autovectored
interrupt and the processor calculates the appropriate vector from a fixed vector
table. AVN = 0 is also the default value. When AVN = 1; the transmitter/receiver
interrupt is a vectored interrupt and the peripheral must provide an 8-bit vector
number.
−
UxIR.4
UxIR.3
Reserved
PIR
Pending Interrupt Request. This bit is set to a logic 1 when a valid interrupt request
has been detected. It is automatically reset by the interrupt acknowledge cycle from
the CPU. If PIR = 0; there is no pending interrupt request; this is also the default
value. PIR can be reset by software by writing a logic 0 to this location.
IPL2
IPL1
IPL0
UxIR.2
UxIR.1
UXIR.0
Interrupt Priority Level. These three bits determine the interrupt priority level of the
interrupt requested by the transmitter/receiver. See Table 45.
August 1993
50
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
Table 45 Selection of transmitter/receiver interrupt priority level.
IPL2
IPL1
IPL0
PRIORITY LEVEL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt inhibited; this is also the default value.
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
9.3.5
UART TRANSMITTER/RECEIVER INTERRUPT VECTOR (UXIV)
These registers have a default value of 0FH.
bit 7
IV.7
bit 6
IV.6
bit 5
IV.5
bit 4
IV.4
bit 3
IV.3
bit 2
IV.2
bit 1
IV.1
bit 0
IV.0
Fig.34 UART Transmitter/Receiver Interrupt Vector (UxIV).
Table 46 Description of UxIV bits.
SYMBOL
BIT
FUNCTION
8-bit interrupt vector number. The default value of this register is 0FH.
IV.7 to IV.0
UTIV.7 to UTIV.0
August 1993
51
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
10 8-BIT GENERAL PORT
The port is configured as a quasi-bidirectional port. A port
pin is set to input mode by writing a logic 1 to the
corresponding General Port Register (GP) bit. This drives a
“hard” logic 1 to the corresponding output pin for a short
period. After this period the logic 1 level is maintained by a
weak pull-up transistor, which can be overwritten by an
external signal.
A read from GP reads the value from the corresponding
General Port Register bit. A read from the General Port
Pad/Register (GPP) reads the value from the corresponding
port input pin. A write to either GP or GPP writes the value
to the port register (GP) from where it is driven to the
corresponding port pins. After RESET the port is set to input
mode. Bits 0 to 3 can be used as high current drive outputs
at a logic 0. Bits 6 and 7 may also be used for I2C1 and
therefore no internal pull-ups are implemented.
10.1 8-bit General Port registers
10.1.1 GENERAL PORT REGISTER (GP)
This register is located at address 8000 2073H.
bit 7
GP7
bit 6
GP6
bit 5
GP5
bit 4
GP4
bit 3
GP3
bit 2
GP2
bit 1
bit 0
GP0
GP1
Fig.35 General Port Register (GP).
10.1.2 GENERAL PORT PAD/REGISTER (GPP)
This register is located at address 8000 2071H.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GPP7
GPP6
GPP5
GPP4
GPP3
GPP2
GPP1
GPP0
Fig.36 General Port Pad/Register (GPP).
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
The Auxiliary Port is configured as a quasi-bidirectional
port in the same way as described for the 8-bit General
Port. A port pin is set to input mode by writing a logic 1 to
the corresponding port register bit. This drives a “hard”
logic 1 to the corresponding output pin for a short period.
After this period the logic 1 level is maintained by a weak
pull-up transistor, which can be overwritten by an external
signal.
11 8-bit AUXILIARY PORT
Unused address pins can be used as auxiliary ports. The
selection of unused address pins (A23 to A16) for use as
auxiliary ports is controlled by the Auxiliary Port Control
Register (APCON).
Each bit in APCON controls one address pin. A logic 1
written to APCON.n enables the auxiliary port function of
the address pin A(n + 16). The APCON bits and their
associated address pins are shown in Fig.37. A logic 0
written to APCON.n disables the auxiliary port function and
drives the internal address bus to A(n + 16).
If bit APCON.n is set, a read from the corresponding bit
APP.n in the Auxiliary Port Pad/Register (APP), reads the
value from the address pin A(n + 16). A write to APP.n
when APCON.n is set, drives the value of APP.n to the
address pin A(n + 16). After RESET the auxiliary port
function is disabled (APCON = 00H).
11.1 8-bit Auxiliary Port registers
11.1.1 AUXILIARY PORT CONTROL REGISTER (APCON)
This register is located at address 8000 2083H.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
APCON.7
(A23)
APCON.6
(A22)
APCON.5
(A21)
APCON.4
(A20)
APCON.3
(A19)
APCON.2
(A18)
APCON.1
(A17)
APCON.0
(A16)
Fig.37 Auxiliary Port Control Register (APCON).
11.1.2 AUXILIARY PORT PAD/REGISTER (APP)
This register is located at address 8000 2081H.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
APP7
APP6
APP5
APP4
APP3
APP2
APP1
APP0
Fig.38 Auxiliary Port/Pad Register (APP).
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
written to by software. After RESET, the Watchdog Timer
is disabled and WDCON contains A5H which clears both
the prescaler and WDTIM. The Watchdog Timer is
enabled by the first write operation to WDCON after
RESET. A running Watchdog Timer can only be disabled
by resetting the device.
12 WATCHDOG TIMER
The P90CE201 contains a Watchdog Timer. Its purpose is
to reset the microcontroller, after a programmable time
interval, in the event of the microcontroller entering an
erroneous processor state. Erroneous processor states
can be caused by noise or RFI.
WDTIM can be read on the fly but can only be written to if
WDCON has been loaded with 5AH. A successful write
operation to WDTIM also clears the prescaler and sets
WDCON to 00H in order to prevent further, unintentional,
write operations to WDTIM.
The Watchdog Timer consists of a 14-bit prescaler and an
8-bit timer (WDTIM). The prescaler is incremented by the
basic peripheral clock. WDTIM is incremented every
16384 cycles of the basic peripheral clock. It is the value
written to WDTIM that determines the Watchdog Timer
interval. If the timer interval is exceeded, the Watchdog
Timer overflows and the microcontroller is reset. In order
to prevent a timer overflow, the user program must reload
the Watchdog Timer within a time period shorter than the
programmed Watchdog Timer interval.
The Watchdog Timer interval (t) may be calculated as
(256 – WDTIM value) × 16384
basic peripheral clock frequency
follows:t =
---------------------------------------------------------------------------------------
For example, if the basic peripheral clock frequency is 4
MHz, the Watchdog Timer interval will be within the range
4.1 ms to 1 second.
The Watchdog Timer is controlled by the Watchdog
Control Register (WDCON). WDCON can be read and
INTERNAL BUS
PRESCALER
(14-BIT)
WDTIM
(8-BIT)
to reset circuitry
BPCLK
CLEAR
CLEAREN
LOAD
LOADEN
CLEAR
write
WDTIM
WDCON
from reset circuitry
INTERNAL BUS
MLB253
Fig.39 Watchdog Timer.
August 1993
54
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
13 TIMERS
13.2 Timer operating modes
The Timer Control Register (TnCON) controls the
selection of the timer operating modes; this is described in
section 13.3.1 Timer Control Register (TnCON).
13.1 General
The P90CE201 contains three almost identical, fully
independent 16-bit timers (T0, T1 and T2). In the following
general description of the timer block, “n” represents the
number of the Timer (0, 1 or 2).
13.2.1 CAPTURE MODE
In the Capture mode there are two options which are
selected by the EXENn bit in TnCON. If EXENn = 0, then
Timer n is a 16-bit timer/counter which on overflow sets the
Overflow bit TFn. The overflow can be used to generate an
interrupt. If EXENn = 1, then Timer n operates in the same
way as EXENn = 0 but with the additional feature that a
valid transition at the external input Tn causes the current
value in Timer n registers (TLn and THn) to be captured
into registers RCAPLn and RCAPHn, respectively. The
transition at input Tn also causes the EXFn bit in TnCON
to be set; this can also be used to generate an interrupt.
Timer n is a 16-bit timer/counter which is formed by the two
8-bit registers TLn and THn. Another pair of registers,
RCAPLn and RCAPHn, form a 16-bit capture register or a
16-bit reload register. The timers can operate either as a
timer or as an event counter. The selection of the clock
source for each timer is done in register SYSCON2 (see
Table 12). The timers have three operation modes.
Mode 1:
Mode 2:
mode 3:
Timer/counter in capture mode
Timer/counter in auto-reload mode
Timer/counter in baud rate generator mode
for UART
13.2.2 AUTO-RELOAD MODE
In the Auto-reload mode there are two options which are
selected by the EXENn bit in TnCON. If EXENn = 0, then
a Timer n overflow sets the TFn bit and causes the Timer
n registers to be reloaded with the 16-bit value held in
registers RCAPLn and RCAPHn. This 16-bit value is
preset by software. The overflow can be used to generate
an interrupt. If EXENn = 1, then Timer n operates as above
but with the additional feature that a valid transition at the
external input Tn triggers the 16-bit reload and sets the
EXFn bit. The transition can also be used to generate an
interrupt.
The differences between the three timers are listed below:
Timer 0: Operates in all modes with the internal
frequency of fXTAL/2 or fXTAL/32.
Timer 0 contains a transition detection
circuit for the external input. The detection
circuitry is controlled by two bits in
SYSCON2; all possible transitions can be
monitored. Table 47 shows the selection of
the trigger pulse.
Table 47 Selection of the trigger pulse.
13.2.3 BAUD RATE GENERATOR MODE
SYSCON2.3 SYSCON2.2
TRANSITION
no edge detection
rising edge detection
The baud rate generator mode for the UART is selected by
RCLKn and/or TCLKn in TnCON. Overflows of Timer n can
be used or generating baud rates for transmit and receive
of the UART in its Modes 1 and 3. See Table 50. The baud
rate generation mode is similar to the auto-reload mode, in
that a rollover in THn causes the Timer n registers to be
reloaded with the 16-bit value held in registers RCAPLn
and RCAPHn, which are preset by software. The baud rate
for the UART is determined by Timer n’s overflow rate as
specified below.
0
0
1
0
1
0
falling edge detection
(default value)
1
1
falling and rising edge
detection
Timer 1: Operates in all modes with the internal
frequency of fXTAL/2 or fXTAL/32. Transition
detection for the external input is fixed to
falling edge detection.
Timer n overflow rate
Baud rate =
----------------------------------------------------------
16
Timer 2: Operates in all modes with the internal
frequency of fXTAL/2 or BPCLK/4. Transition
detection for the external input is fixed to
falling edge detection.
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
Timer n can be configured for either timer or counter
operation. In timer operation the internal timer frequency
(fINT) is given by fXTAL/2, fXTAL/32 or BPCLK/4. The baud
rate may be calculated as
follows:
fINT
Baud rate =
------------------------------------------------------------------------------------------------------
16 × (65536 – (RCAPnH, RCAPnL) )
In this mode an overflow of Timer n does not set TFn and
does not generate an interrupt. If EXENn = 1, a valid
transition at input pin Tn sets EXFn and can be used to
generate an interrupt.
OSC
PRESCALER
C/Tn = 0
C/Tn = 1
TLn
(8 BITS)
THn
(8 BITS)
TFn
control
TRn
timer n
interrupt
capture
RCAPnL
RCAPnH
transition
detector
external
pin Tn
EXFn
MLB008
control
EXENn
Fig.40 Timer/Counter in Capture Mode - Mode 1.
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
OSC
PRESCALER
C/Tn = 0
C/Tn = 1
TLn
(8 BITS)
THn
(8 BITS)
TFn
control
TRn
timer n
interrupt
reload
RCAPnL
RCAPnH
transition
detector
external
pin Tn
EXFn
MLB009
control
EXENn
Fig.41 Timer/Counter in Auto-reload Mode - Mode 2.
OSC
PRESCALER
C/Tn = 0
TLn
(8 BITS)
THn
(8 BITS)
C/Tn = 1
control
TRn
UART clock
reload
timer n
interrupt
RCAPnL
RCAPnH
transition
detector
external
pin Tn
EXFn
MLB010
control
EXENn
Fig.42 Timer/Counter in Baud rate generator Mode - Mode 3.
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
13.3 Timer registers
13.3.1 TIMER CONTROL REGISTER (TnCON)
The Timer Control Register (TnCON) controls the selection of the timer operating modes and the UART clock source.
bit 7
TFn
bit 6
bit 5
bit 4
bit 3
bit 2
TRn
bit 1
bit 0
EXFn
RCLKn
TCLKn
EXENn
C/Tn
CP/RLn
Fig.43 Timer Control Registers (TnCON).
Table 48 Description of TnCON bits.
SYMBOL
BIT
FUNCTION
TFn
TnCON.7
Timer n overflow flag. Set by a Timer n overflow and must be cleared by software.
TFn will not be set when either RCLKn = 1 or TCLKn = 1.
EXFn
TnCON.6
Timer n external flag. Set when either a capture or reload is caused by a negative
transition on external input Tn and when EXENn = 1. EXFn must be cleared by
software.
RCLKn
TCLKn
EXENn
TnCON.5
TnCON.4
TnCON.3
Receive Clock flag. When set, causes the UART to use Timer n overflow pulses
for its receive clock in Modes 1 and 3. See Table 50.
Transmit Clock flag. When set, causes the UART to use Timer n overflow pulses
for its transmit clock in Modes 1 and 3. See Table 50.
Timer n external enable flag. When set, allows a capture or reload to occur as a
result of a negative transition on external input Tn, if Timer n is not being used to
clock the UART. EXENn = 0 causes Timer 2 to ignore events at external input Tn.
TRn
TnCON.2
TnCON.1
Start/Stop control. TRn = 1 starts Timer n; TRn = 0 stops the timer.
C/Tn
Timer or Counter select. C/Tn = 0 selects the internal timer. C/Tn = 1 selects the
external event counter (edge triggered).
CP/RLn
TnCON.0
Capture/Reload flag. When set, captures will occur on valid transitions at external
input Tn, if EXEn2 = 1. When cleared, auto-reloads will occur upon either Timer n
overflows or valid transitions at Tn, if EXENn = 1. When either RCLKn = 1 or
TCLKn = 1, this bit is ignored and the timer is forced to auto-reload on a Timer n
overflow.
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
Table 49 Selection of Timer n operating modes.
RCLKn + TCLKn
CP/RLn
TRn
MODE
0
0
1
X
0
1
1
1
1
0
16-bit automatic reload
16-bit capture
Baud rate generator
off
X
X
Table 50 UART clock source for Receive and Transmit - Modes 1 and 3.
RCLK2
TCLK2
RCLK1
TCLK1
RCLK0
TCLK0
UART CLOCK SOURCE
0
0
0
1
X
1
1
0
0
1
0
1
X
1
0
1
0
0
1
1
X
None
Timer 0
Timer 1
Timer 2
Not usable, see note 1
Not usable, see note 1
Not usable, see note 1
Note
1. These combinations lead to the addition of clock pulses from different timers giving an irregular baud rate clock and
therefore should not be used.
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
13.3.2 TIMER INTERRUPT REGISTER (TnIR)
Each Timer contains a register for the control of interrupts.
bit 7
bit 6
bit 5
AVN
bit 4
bit 3
PIR
bit 2
IPL2
bit 1
IPL1
bit 0
IPL0
−
−
−
Fig.44 Timer Interrupt Register (TnIR).
Table 51 Description of TnIR bits.
SYMBOL
BIT
FUNCTION
−
−
TnIR.7
TnIR.6
TnIR.5
Reserved
Reserved
AVN
Autovector. When AVN = 0; the timer interrupt is an autovectored interrupt and the
processor calculates the appropriate vector from a fixed vector table. AVN = 0 is
also the default value. When AVN = 1; the timer interrupt is a vectored interrupt
and the peripheral must provide an 8-bit vectored interrupt.
−
TnIR.4
TnIR.3
Reserved
PIR
Pending Interrupt Request. This bit is set to a logic 1 when a valid interrupt
request has been detected. It is automatically reset by the interrupt acknowledge
cycle from the CPU. If PIR = 0, there is no pending interrupt request; this is also
the default value. The PIR bit can be reset by software by writing a logic 0 to this
location.
IPL2
IPL1
IPL0
TnIR.2
TnIR.1
TnIR.0
Interrupt Priority Level. These three bits determine the interrupt priority level of the
interrupt requested by the timer. See Table 52.
Table 52 Selection of interrupt priority level.
IPL2
IPL1
IPL0
PRIORITY LEVEL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt inhibited; this is also the default value.
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
13.3.3 TIMER INTERRUPT VECTOR (TnIV)
bit 7
IV.7
bit 6
IV.6
bit 5
IV.5
bit 4
IV.4
bit 3
IV.3
bit 2
IV.2
bit 1
IV.1
bit 0
IV.0
Fig.45 Interrupt Vector Register (TnIV).
Table 53 Description of TnIV bits.
SYMBOL
BIT
FUNCTION
8-bit interrupt vector number. The default value of this register is 0FH.
IV.7 to IV.0
TnIV.7 to TnIV.0
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
14 ELECTROMAGNETIC COMPATIBILITY (EMC) IMPROVEMENTS
Primary attention has been paid to the reduction of electromagnetic emission of the microcontroller. The following
features result in a reduction of the electromagnetic emission and additionally improve the electromagnetic susceptibility:
• Two supply voltage pins (VDD1 and VDD2) and two ground pins (VSS1 and VSS2) are provided. VDD1 and VSS1 are
adjacent pins located on one side of the package; VDD2 and VSS2 are also adjacent pins located diagonally opposite
the VDD1 and VSS1 pins.
• Separate power supply pins for internal logic/memory interface and peripheral pins (quiet port)
• Internal decoupling capacitance improves the EMC radiation behaviour and the EMC immunity
• External capacitors are to be connected as close as possible between pins VDD1 and VSS1 and also VDD2 and VSS2
.
Ceramic chip capacitors are recommended (100 nF).
15 ELECTRICAL SPECIFICATIONS
15.1 Limiting values
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
+6.5
DD + 0.5
UNIT
VDD
VI
supply voltage
−0.5
−0.5
−
V
V
input voltage on any pin with respect to ground (VSS
total power dissipation; see note 1
storage temperature
)
V
Ptot
Tstg
Tamb
0.75
+150
+ 85
W
°C
°C
−65
−25
operating ambient temperature
Note
1. This value is based on the maximum allowable die temperature and the thermal resistance of the package; not on
device power consumption.
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
15.2 DC Characteristics
VDD = 5 V ±10%; VSS = 0 V; Tamb = −25 to +85 °C; all voltages with respect to VSS unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Supply
VDD
IDD
supply voltage
4.5
5.5
V
supply current operating
VDD = 5.5 V; fCLK = 24 MHz
note 1
−
70
mA
RRST
Inputs
VIL
RESET pull-down resistor
50
150
kΩ
LOW level input voltage
(except SCLn and SDAn)
−0.5
−0.5
2.0
0.8
1.5
V
V
V
VIL1
VIH
LOW level input voltage
SCLn and SDAn
note 2
HIGH level input voltage
(except RESET, XTAL1, SCLn,
SDAn)
VDD + 0.5
VIH1
VIH2
IIL
HIGH level input voltage
RESET, XTAL1
0.7VDD + 0.1
V
DD + 0.5
V
V
HIGH level input voltage
SCLn, SDAn
note 2
3.0
6.0
LOW level input current
GP0-5, A16-23 in port mode,
INTN0 - 7
VIN = 0.45 V
−
−50
µA
ITL
input current HIGH-to-LOW
transition for externally driven
port pins
VIN = 2.0 V
−
−650
µA
(except GP6 and GP7)
ILI
input leakage current
D0 to D7
0.45 V ≤ VIN ≤ VDD
−
−
±10
±10
µA
µA
ILI1
input leakage current
SCLn, SDAn
0.4 V ≤ VIN ≤ 4.95 V
note 2
Outputs
VOL
LOW level output voltage
(except GP0-3, SCLn,SDAn)
IOL = 1.6 mA; note 3
−
−
0.45
V
VOL1
VOL2
VOH
LOW level output voltage
GP0-3
IOL = 6.4 mA; note 3
IIOL = 20 mA; note 3
0.45
1.2
V
V
LOW level output voltage
SCLn, SDAn
IOL = 3.0 mA; notes 2 and 3
IOL = 60 mA; notes 2 and 3
−
−
0.4
0.6
V
V
HIGH level output voltage
(except SCLn,SDAn)
IOH = −60 µA
2.4
−
V
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
Notes
1. The operating supply current is measured during the STOP instruction executed immediately after RESET. All inputs
are driven HIGH and outputs are loaded with CL = 50 pF, R = 1 MΩ; XTAL1 is driven with tr = tf = 5 ns;
VIL = VSS + 0.5 V; VIH1 = VDD − 0.5 V; XTAL2 not connected.
2. The parameter meets the I2C-bus specification for standard mode and fast mode devices.
3. Under steady state (non-transient) conditions, IOL must be externally limited as shown in Table 54. If IOL exceeds the
test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the
listed test conditions.
Table 54 Maximum IOL values.
PARAMETER
MAX
UNIT
Maximum IOL per port pin
10
20
mA
mA
mA
Maximum IOL per high drive port pin (GP0 - GP3)
Maximum total IOL for all output pins
100
15.3 AC Characteristics
VDD = 5 V ±10%; VSS = 0 V; TCLCLmin = 1/fCLKmax = 42 ns; Tamb = −25 to +85 °C.
15.3.1 AC TESTING INPUT AND OUTPUT WAVEFORMS.
AC test inputs are driven at 2.4 V for a logic 1 and 0.45 V for a logic 0. Timing measurements are taken at 2.0 V for a
logic 1 and 0.8 V for a logic 0. See Fig.46(a).
The float state is defined as the point at which the pin sinks 3.2 mA or sources 400 µA at the voltage test levels. See
Fig.46(b).
2.0 V
0.8 V
2.0 V
0.8 V
2.4 V
test points
0.45 V
(a)
float
2.4 V
2.0 V
0.8 V
2.0 V
0.8 V
0.45 V
MLA769
(b)
Fig.46 AC testing input, output waveform (a) and float waveform (b).
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
15.3.2 EXTERNAL CLOCK DRIVE XTAL1
Table 55 External clock drive XTAL1.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
clock period
HIGH time
LOW time
rise time
42
15
15
−
250
tCLCL − CLCX
tCLCL − CHCX
ns
ns
ns
ns
ns
t
t
20
20
fall time
−
t
t
t
CHCX
CLCH
CHCL
V
V
V
V
IH1
IH1
IH1
IH1
0.8 V
0.8 V
0.8 V
0.8 V
t
CLCX
t
MLA856
CLCL
Fig.47 External clock drive XTAL1.
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
15.3.3 EXTERNAL MEMORY INTERFACE
Table 56 External memory read cycle timing.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
tAVSL
tSLDV
tAXDX
tAVDV
tSHAX
tSHDX
address valid to CSROMN/CSRAMN LOW
CSROMN/CSRAMN LOW to data valid; note 1
address invalid to data invalid
t
CLCL − 25
−
ns
ns
ns
ns
ns
ns
−
0
−
(2 + WS/2)tCLCL − 65
−
address valid to data valid; note 1
(2 + WS/2)tCLCL − 65
CSROMN/CSRAMN HIGH to address invalid
CSROMN/CSRAMN HIGH to data invalid
tCLCL − 15
−
−
0
Note
1. WS is the number of additional wait states access time values. See Table 11 in section 6.
Address
even address
address 1
R/WN
t
SHAX
t
t
AVDV
AVSL
CSRAMN
CSROMN
t
t
AXDX
t
SLDV
SHDX
D0 D7
LSB data
MSB data
MLB013
Fig.48 External memory read cycle.
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
Table 57 External memory write cycle timing.
SYMBOL
PARAMETER
MIN.
UNIT
ns
tAVSL
tWLSL
tSHWH
tSLSH
tSHAX
tQVSH
tSHQX
address valid to CSROMN/CSRAMN LOW
RWN LOW to CSROMN/CSRAMN LOW
CSROMN/CSRAMN HIGH to RWN HIGH
CSROMN/CSRAMN LOW; note 1
t
t
t
CLCL − 25
CLCL − 25
CLCL − 15
ns
ns
(2 + WS/2)tCLCL − 15
CLCL − 15
(2 + WS/2)tCLCL − 20
CLCL − 15
ns
ns
ns
ns
CSROMN/CSRAMN HIGH to address invalid
data set-up to CSROMN/CSRAMN HIGH; note 1
CSROMN/CSRAMN HIGH to data invalid
t
t
Note
1. WS is the number of additional wait states access time values. See Table 11 in section 6.
Address
MSB address
LSB address
t
WLSL
R/WN
t
t
SHAX
AVSL
t
SHWH
t
SLSH
CSRAMN
CSROMN
t
SHQX
t
QVSH
D0 D7
MLB123
Fig.49 External memory write cycle.
August 1993
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Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
15.3.4 FAST I2C-BUS TIMING.
Table 58 Fast I2C-bus timing.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
fSCL
SCL clock frequency
0
400
−
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
tBUF
bus free time between a STOP and START condition
hold time (repeated) START condition
LOW period of the SCL clock
1300
600
1300
600
600
0
tHD; STA
tLOW
−
−
tHIGH
HIGH period of the SCL clock
−
tSU; STA
tHD; DAT
tSU; DAT
set-up time (repeated) START
−
data hold time (note 1)
900
−
data set-up time (note 2)
100
t
RC;tRD
FC;tFD
rise time of both SDA and SCL lines (note 3)
fall time of both SDA and SCL lines (note 3)
set-up time for STOP condition
(20 + 0.1Cb)
300
300
−
t
(20 + 0.1Cb)
tSU; STO
Cb
600
capacitive load of each bus line
−
400
Notes
1. A device must internally provide a hold time of at least 300 ns for the SDA signal, referenced to VIHmin of the SCL
signal, in order to bridge the undefined region of the falling edge of SCL. The maximum tHD;DAT has to be met only if
the device does not stretch the SCL LOW period (tLOW).
2. A fast-mode I2C-bus device can be used in a “0-to-100 kbit/s” I2C-bus system and then the requirement
tSU;DAT > 250 ns must be fulfilled. This will automatically be the case if the device does not stretch the LOW period
of the SCL signal. But if such a device stretches the LOW period of the SCL signal, it must output the next data bit
to the SDA line (tRDmax + tSU;DAT) = 1000 + 250 = 1250 ns before the SCL line is released according to the existing
“0-to-100 kbit/s” I2C-bus specification.
3. Cb = Total capacitance value of one bus line in pF.
August 1993
68
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
BM4C82
a n d b o o k , f u l l p a g e w
August 1993
69
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
15.3.5 UART SHIFT REGISTER MODE TIMING
Table 59 Basic peripheral clock set to 4 MHz; CL = 80 pF.
SYMBOL
PARAMETER
serial port clock cycle time
MIN.
MAX.
UNIT
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
1000
700
50
−
−
ns
ns
ns
ns
ns
output data set-up to clock rising edge
output data hold after clock rising edge
input data hold after clock rising edge
clock rising edge to input data valid
−
0
−
−
700
t
XLXL
CLOCK
t
XHQX
1
t
QVXH
0
2
3
4
5
6
7
OUTPUT DATA
t
XHDX
t
XHDV
SET TI
WRITE TO SBUF
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
MLB124
CLEAR RI
SET RI
Fig.51 UART Shift Register mode timing.
August 1993
70
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
16 REGISTER MAP
The internal register map of the P90CE201 is summarized in the following tables.
ADDRESS (HEX)
System registers
SYMBOL
REGISTER
8000 1000
SYSCON1H
SYSCON1
SYSCON2
System Control Register 1 High
System Control Register 1 Low
System Control Register 2 High
System Control Register 2 Low
Reserved
R/W
R/W
R/W
R/W
8000 1001
SYSCON1L
SYSCON2H
SYSCON1L
8000 1002
8000 1003
8000 1004 to 800 101F
Interrupt registers
8000 1020
8000 1021
8000 1022
8000 1023
8000 1024
8000 1025
8000 1026
8000 1027
8000 1028
8000 1029
8000 102A
8000 102B
8000 102C
8000 102D
8000 102E
8000 102F
8000 1030
8000 1031
8000 1032
8000 1033
8000 1034 to 8000 1040
8000 1041
8000 1042
8000 1043
8000 1044
8000 1045
8000 1046
8000 1047
Reserved
LIR7
LIV7
LIR6
LIV6
LIR5
LIV5
LIR4
LIV4
LPCRH
LPPH
LIR3
LIV3
LIR2
LIV2
Latched Interrupt 7 Register
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Latched Interrupt 7 vector
Reserved
Latched Interrupt 6 Register
Reserved
Latched Interrupt 6 vector
Reserved
Latched Interrupt 5 Register
Reserved
Latched Interrupt 5 vector
Reserved
Latched Interrupt 4 Register
Reserved
Latched Interrupt 4 vector
Reserved
Port Control Register bit 7 to 4
Reserved
Port Pad/Control Register bit 7 to 4
Reserved
Latched Interrupt 3 Register
Reserved
Latched Interrupt 3 vector
Reserved
Latched Interrupt 2 Register
Reserved
Latched Interrupt 2 vector
August 1993
71
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
ADDRESS (HEX)
SYMBOL
REGISTER
8000 1048
Reserved
8000 1049
LIR1
Latched Interrupt 1 Register
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
8000 104A
8000 104B
8000 104C
8000 104D
8000 104E
8000 104F
LIV1
Latched Interrupt 1 vector
Reserved
LIR0
Latched Interrupt 0 Register
Reserved
LIV0
Latched Interrupt 0 vector
Reserved
8000 1050
8000 1051
LPCRL
LPPL
Port Control Register bit 3 to 0
Reserved
8000 1052
8000 1053
Port Pad/Control Register bit 3 to 0
Reserved
8000 1054 to 8000 105F
I2C Registers
8000 2000
Reserved
8000 2001
S1DAT
S1ADR
S1STA
S1CON
S1IR
I2C1 Data Register
R/W
R/W
R
8000 2002
Reserved
8000 2003
I2C1 Address Register
Reserved
I2C1 Status Register
8000 2004
8000 2005
8000 2006
Reserved
8000 2007
I2C1 Control Register
Reserved
I2C1 Interrupt Register
R/W
R/W
R/W
R/W
R/W
R
8000 2008
8000 2009
8000 200A
8000 200B
8000 200C to 8000 2010
8000 2011
Reserved
S1IV
I2C1 Interrupt vector
Reserved
I2C2 Data Register
S2DAT
S2ADR
S2STA
S2CON
S2IR
8000 2012
Reserved
8000 2013
I2C2 Address Register
Reserved
I2C2 Status Register
8000 2014
8000 2015
8000 2016
Reserved
8000 2017
I2C2 Control Register
Reserved
I2C2 Interrupt Register
R/W
R/W
R/W
8000 2018
8000 2019
8000 201A
8000 201B
8000 201C to 8000 201F
Reserved
S2IV
I2C2 Interrupt vector
Reserved
August 1993
72
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
ADDRESS (HEX)
SYMBOL
REGISTER
UART registers
8000 2020
Reserved
8000 2021
SBUF
SCON
URIR
URIV
UTIR
UTIV
UART Transmit/Receive Register
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
8000 2022
8000 2023
UART Control Register
Reserved
8000 2024
8000 2025
UART Receiver Interrupt Register
Reserved
8000 2026
8000 2027
UART Receiver Interrupt vector
Reserved
8000 2028
8000 2029
UART Transmitter Interrupt Register
Reserved
8000 202A
8000 202B
8000 202C to 8000 202F
UART Transmitter Interrupt vector
Reserved
Timers registers
8000 2030
TH0
T0
Timer 0 High Order Register
Timer 0 Low Order Register
R/W
R/W
8000 2031
TL0
8000 2032
RCAPH0
RCAPL0
RCAP0
Timer 0 Reload/Capture High Order Register
Timer 0 Reload/Capture Low Order Register
Reserved
R/W
R/W
8000 2033
8000 2034
8000 2035
T0CON
T0IR
Timer 0 Control Register
Reserved
R/W
R/W
R/W
8000 2036
8000 2037
Timer 0 Interrupt Register
Reserved
8000 2038
8000 2039
T0IV
Timer 0 Interrupt vector
Reserved
8000 203A to 800 203F
8000 2040
TH1
T1
Timer 1 High Order Register
Timer 1 Low Order Register
Timer 1 Reload/Capture High Order Register
Timer 1 Reload/Capture Low Order Register
Reserved
R/W
R/W
R/W
R/W
8000 2041
TL0
8000 2042
RCAPH1
RCAPL1
RCAP1
8000 2043
8000 2044
8000 2045
T1CON
T1IR
Timer 1 Control Register
Reserved
R/W
R/W
R/W
8000 2046
8000 2047
Timer 1 Interrupt Register
Reserved
8000 2048
8000 2049
T1IV
Timer 1 Interrupt vector
Reserved
8000 204A to 8000 204F
8000 2050
TH2
TL2
T2
Timer 2 High Order Register
Timer 2 Low Order Register
R/W
R/W
8000 2051
August 1993
73
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
ADDRESS (HEX)
SYMBOL
RCAP2
REGISTER
8000 2052
RCAPH2
Timer 2 Reload/Capture Low Order Register
Timer 2 Reload/Capture Low Order Register
Reserved
R/W
R/W
8000 2053
RCAPL2
T2CON
T2IR
8000 2054
8000 2055
Timer 2 Control Register
Reserved
R/W
R/W
R/W
8000 2056
8000 2057
Timer 2 Interrupt Register
Reserved
8000 2058
8000 2059
T2IV
Timer 2 Interrupt vector
Reserved
8000 205A to 8000 205F
Watchdog registers
8000 2060
Reserved
8000 2061
WDTIM
Watchdog Timer Register
Reserved
R/W
R/W
8000 2062
8000 2063
WDCON
Watchdog Control Register
Reserved
8000 2064 to 8000 206F
General Port registers
8000 2070
Reserved
8000 2071
GPP
GP
Port Pad/Register
Reserved
R/W
R/W
8000 2072
8000 2073
Port Register
Reserved
8000 2074 to 8000 207F
Auxiliary Port registers
8000 2080
Reserved
8000 2081
APP
Auxiliary Port Pad/Register
Reserved
R/W
R/W
8000 2082
8000 2083
APCON
Auxiliary Port Control Register
Reserved
8000 2084 to 8000 208F
August 1993
74
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
17 PACKAGE OUTLINE
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT319-2
y
X
A
51
33
52
32
Z
E
e
A
2
H
A
E
(A )
3
E
A
1
θ
w M
p
pin 1 index
L
p
b
L
20
64
detail X
1
19
w M
Z
D
v
M
A
b
p
e
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.25 2.90
0.05 2.65
0.50 0.25 20.1 14.1
0.35 0.14 19.9 13.9
24.2 18.2
23.6 17.6
1.0
0.6
1.2
0.8
1.2
0.8
mm
3.20
0.25
1
1.95
0.2
0.2
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-08-01
SOT319-2
August 1993
75
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
If wave soldering cannot be avoided, the following
conditions must be observed:
18 SOLDERING
18.1 Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
QFP100 (SOT382-1) or QFP160 (SOT322-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
18.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
18.4 Repairing soldered joints
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
18.3 Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
August 1993
76
Philips Semiconductors
Product specification
16-bit microcontroller
P90CE201
19 DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
20 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
21 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
August 1993
77
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