PCA2001CX81 [NXP]
32 kHz watch circuit with programmable adaptive motor pulse; 32 kHz的时钟电路与可编程自适应电机脉冲型号: | PCA2001CX81 |
厂家: | NXP |
描述: | 32 kHz watch circuit with programmable adaptive motor pulse |
文件: | 总30页 (文件大小:563K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PCA2000; PCA2001
32 kHz watch circuit with programmable adaptive motor pulse
Rev. 08 — 23 August 2010
Product data sheet
1. General description
The PCA2000 and PCA2001 are CMOS integrated circuits for battery operated wrist
watches with a 32 kHz quartz crystal as timing element and a bipolar 1 Hz stepping motor.
The quartz crystal oscillator and the frequency divider are optimized for minimum power
consumption. A timing accuracy of 1 ppm is achieved with a programmable, digital
frequency adjustment.
To obtain the minimum overall power consumption for the watch, an automatic motor
pulse adaptation function is provided. The circuit supplies only the minimum drive current,
which is necessary to ensure a correct motor step. Changing the drive current of the
motor is achieved by chopping the motor pulse with a variable duty cycle. The pulse width
and the range of the variable duty cycle can be programmed to suit different types of
motors. The automatic pulse adaptation scheme is based on a safe dynamic detection of
successful motor steps.
A pad RESET is provided (used for stopping the motor) for accurate time setting and for
accelerated testing of the watch.
The PCA2000 has a battery End Of Life (EOL) warning function. If the battery voltage
drops below the EOL threshold voltage (which can be programmed for silver oxide or
lithium batteries), the motor steps change from one pulse per second to a burst of four
pulses every 4 seconds.
The PCA2001 uses the same circuit as the PCA2000, but without the EOL function.
2. Features and benefits
Amplitude-regulated 32 kHz quartz crystal oscillator, with excellent frequency stability
and high immunity to leakage currents
Electrically programmable time calibration with 1 ppm resolution stored in One Time
Programmable (OTP) memory
The quartz crystal is the only external component connected
Very low power consumption, typical 90 nA
One second output pulses for bipolar stepping motor
Minimum power consumption for the entire watch, due to self adaptation of the motor
drive according to the required torque
Reliable step detection circuit
Motor pulse width, pulse modulation, and pulse adaptation range programmable in a
wide range, stored in OTP memory
Stop function for accurate time setting and power saving during shelf life
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
End Of Life (EOL) indication for silver oxide or lithium battery (only the PCA2000 has
the EOL feature)
Test mode for accelerated testing of the mechanical parts of the watch and the IC
Test bits for type recognition
3. Applications
Driver circuits for bipolar stepping motors
High immunity motor drive circuits
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Delivery form
Version
PCA2000U/AC/1
PCA2001U/AC/1
PCA200xU
wire bond die; 8 bonding pads;
1.16 × 0.86 × 0.22 mm
chip in tray
PCA200xU
PCA200xU
wire bond die; 8 bonding pads;
1.16 × 0.86 × 0.22 mm
chip in tray
PCA200xU
PCA200xU
PCA200xU
PCA200xCX
PCA200xCX
PCA200xCX
PCA2000U/10AC/1 PCA200xU
PCA2001U/10AC/1 PCA200xU
PCA2000CX8/5/1 PCA200xCX
PCA2001CX8/5/1 PCA200xCX
PCA2000CX8/12/1 PCA200xCX
wire bond die; 8 bonding pads;
1.16 × 0.86 × 0.22 mm
chip on film frame carrier
chip on film frame carrier
wire bond die; 8 bonding pads;
1.16 × 0.86 × 0.22 mm
wafer level chip-size package;
8 bumps
unsawn wafer with lead free
solder bumps
wafer level chip-size package;
8 bumps
unsawn wafer with lead free
solder bumps
wafer level chip-size package;
8 bumps
sawn wafer with lead free
solder bumps on Film Frame
Carrier (FFC)
PCA2000_2001
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 23 August 2010
2 of 30
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
5. Block diagram
32 Hz
8 kHz
3
4
OSCIN
OSCOUT
8
OSCILLATOR
DIVIDER
RESET
reset
÷4
RESET
TIMING ADJUSTMENT,
INHIBITION
5
1
V
DD
VOLTAGE DETECTOR,
OTP-CONTROLLER
1 Hz
OTP-MEMORY
V
SS
MOTOR CONTROL WITH
ADAPTIVE PULSE MODULATION
EOL
PCA2000 only
2
STEP
DETECTION
i.c.
PCA2000
PCA2001
6
7
mgw567
MOT1
MOT2
Fig 1. Block diagram of PCA2000 and PCA2001
6. Pinning information
6.1 Pinning
PCA200xCX
PCA200xU
V
1
2
8
7
RESET
MOT2
V
1
2
8
7
RESET
MOT2
SS
SS
i.c.
i.c.
x
x
0
0
y
0
0
y
OSCIN
3
4
6
MOT1
OSCIN
3
4
6
MOT1
OSCOUT
5
V
OSCOUT
5
V
DD
DD
001aai177
001aai176
a. Top view. For mechanical details, see
Figure 13.
b. Top view. For mechanical details, see
Figure 14.
Fig 2. Pad and bump configuration of PCA2000 and PCA2001
PCA2000_2001
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 23 August 2010
3 of 30
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
6.2 Pin description
Table 2.
Symbol
VSS
Pin description
Pin
1
Description
ground
i.c.
2
internally connected
oscillator input
oscillator output
supply voltage
motor 1 output
motor 2 output
reset input
OSCIN
OSCOUT
VDD
3
4
5
MOT1
MOT2
RESET
6
7
8
7. Functional description
7.1 Motor pulse
The motor output supplies pulses of different driving stages, depending on the torque
required to turn on the motor. The number of different stages can be selected between
three and six. With the exception of the highest driving stage, each motor pulse (tp in
Figure 3 and Figure 6) is followed by a detection phase during which the motor movement
is monitored, in order to check whether the motor has turned correctly or not.
1.96 ms
t
t
2t
p
detection phase
p
p
mgw350
0.98 ms
31.25 ms
31.25 ms
Fig 3. Correction sequence after failed motor step
If a missing step is detected, a correction sequence is generated (see Figure 3) and the
driving stage is switched to the next level. The correction sequence consists of two
pulses: first a short pulse in the opposite direction (0.98 ms, modulated with the maximum
duty cycle) to give the motor a defined position, followed by a motor pulse of the strongest
driving level. Every 4 minutes, the driving level is lowered again by one stage.
The motor pulse has a constant pulse width. The driving level is regulated by chopping the
driving pulse with a variable duty cycle. The driving level starts from the programmed
minimum value and increases by 6.25 % after each failed motor step. The strongest
driving stage, which is not followed by a detection phase, is programmed separately.
PCA2000_2001
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 23 August 2010
4 of 30
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
Therefore it is possible to program a larger energy gap between the pulses with step
detection and the strongest, not monitored, pulse. This might be necessary to ensure a
reliable and stable operation under adverse conditions (magnetic fields and vibrations). If
the watch works in the highest driving stage, the driving level jumps after the 4-minute
period directly to the lowest stage, and not just one stage lower.
To optimize the performance for different motors, the following parameters can be
programmed:
• Pulse width: 0.98 ms to 7.8 ms in steps of 0.98 ms
• Duty cycle of lowest driving level: 37.5 % to 56.25 % in steps of 6.25 %
• Number of driving levels (including the highest driving level): 3 to 6
• Duty cycle of the highest driving level: 75 % or 100 %
• Enlargement pulse for the highest driving level: on or off
The enlargement pulse has a duty cycle of 25 % and a pulse width which is twice the
programmed motor pulse width. The repetition period for the chopping pattern is 0.98 ms.
Figure 4 shows an example of a 3.9 ms pulse.
0.244 ms
0.122 ms
DUTY CYCLE
37.5 %
43.75 %
50 %
56.25 %
62.5 %
68.75 %
75 %
81.25 %
100 %
mgw351
0.98 ms
0.98 ms
0.98 ms
0.98 ms
Fig 4. Possible modulations for a 3.9 ms motor pulse
PCA2000_2001
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 23 August 2010
5 of 30
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
7.2 Step detection
Figure 5 shows a simplified diagram of the motor driving and step detection circuit, and
Figure 6 shows the step detection sequence and corresponding sampling current.
Between the motor driving pulses, the switches P1 and P2 are closed, which means the
motor is short-circuited. For a pulse in one direction, P1 and N2 are open, and P2 and N1
are closed with the appropriate duty cycle; for a pulse in the opposite direction, P2 and N1
are open, and P1 and N2 closed.
V
DD
R
D
D1
P2
N2
P1
N1
P3
MOTOR
P4
MOT1
MOT2
V
SS
mgw352
Fig 5. Simplified diagram of motor driving and step detection circuit
The step detection phase is initiated after the motor driving pulse. In phase 1 P1 and P2
are first closed for 0.98 ms and then in phase 2 all four drive switches (P1, N1, P2 and N2)
are opened for 0.98 ms. As a result, the energy stored in the motor inductance is reduced
as fast as possible.
The induced current caused by the residual motor movement is then sampled in phase 3
(closing P3 and P2) and in phase 4 (closing P1 and P4). For step detection in the opposite
direction P1 and P4 are closed during phase 3 and P2 and P3 during phase 4 (see
Figure 6).
PCA2000_2001
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 23 August 2010
6 of 30
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
I
motor
positive detection level
t
negative detection level
t
p
0.98 ms
(motor shorted)
programmable time limit
t
= 0.98 ms
sampling
OTP C4 to C6
d
sampling
voltage
t
t
sampling
voltage
positive detection
motor shorted
negative detection
sampling results
sampling
mgw569
61 μs
0.49 ms
Fig 6. Step detection sequence and corresponding sampling voltage
The condition for a successful motor step is a positive step detection pulse (current in the
same direction as in the driving phase) followed by a negative detection pulse within a
given time limit. This time limit can be programmed between 3.9 ms and 10.7 ms (in steps
of 0.98 ms) in order to ensure a safe and correct step detection under all conditions (for
instance magnetic fields). The step detection phase stops after the last 31.25 ms, after the
start of the motor driving pulse.
7.3 Time calibration
The quartz crystal oscillator has an integrated capacitance of 5.2 pF, which is lower than
the specified capacitance (CL) of 8.2 pF for the quartz crystal (see Table 10). Therefore,
the oscillator frequency is typically 60 ppm higher than 32.768 kHz. This positive
frequency offset is compensated by removing the appropriate number of 8192 Hz pulses
in the divider chain (maximum 127 pulses), every 1 or 2 minutes. The time correction is
given in Table 3.
Table 3.
Time calibration
Correction per step (n = 1)
Calibration
period
Correction per step (n = 127)
seconds per day ppm seconds per day
22.3
11.15
ppm
2.03
1 minute
0.176
0.088
258
129
2 minutes
1.017
After measuring the effective oscillator frequency, the number of correction pulses must
be calculated and stored together with the calibration period in the OTP memory (see
Section 7.7).
PCA2000_2001
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 23 August 2010
7 of 30
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
The oscillator frequency can be measured at pad RESET, where a square wave signal
1
1024
-----------
with the frequency of
× fosc is provided.
This frequency shows a jitter every minute or every two minutes, depending on the
programmed calibration period, which originates from the time calibration.
Details on how to measure the oscillator frequency and the programmed inhibition time
are given in Section 7.10.
7.4 Reset
1
1024
-----------
At pad RESET an output signal with a frequency of
× fosc = 32 Hz is provided.
Connecting pad RESET to VDD stops the motor drive and opens all four (P1, N1, P2 and
N2) driver switches (see Figure 5). Connecting pad RESET to VSS activates the test
mode. In this mode the motor output frequency is 32 Hz, which can be used to test the
mechanical function of the watch.
After releasing the pad RESET, the motor starts exactly one second later with the smallest
duty cycle and with the opposite polarity to the last pulse before stopping.
The debounce time for the RESET function is between 31 ms and 62 ms.
7.5 Programming possibilities
The programming data is stored in OTP cells (EPROM cells). At delivery, all memory cells
are in state 0. The cells can be programmed to the state 1, but then there is no more set
back to state 0.
The programming data is organized in an array of four 8-bit words: word A contains the
time calibration, words B and C contain the setting for the monitor pulses and word D
contains the type recognition (see Table 4).
Table 4.
Word Bit
1
Words and bits
2
3
4
5
6
7
8
A
number of 8192 Hz pulses to be removed
calibration
period
B
lowest stage: duty cycle
number of driving stages
highest
stage:
pulse
stretching
factory test bits
duty cycle
C
D
pulse width
type
maximum time delay between positive
and negative detection pulses
EOL voltage factory test
bit
factory test bits
PCA2000_2001
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 23 August 2010
8 of 30
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
Table 5.
Description of word A bits
Bit
Value
Description
Inhibition time
1 to 7
-
adjust the number of the 8192 Hz pulses to be removed;
bit 1 is the MSB and bit 7 is the LSB
Calibration period
8
0
1
1 minute
2 minutes
Table 6.
Bit
Description of word B bits
Value
Description
Duty cycle lowest driving stage
1 to 2
00
01
10
11
37.5 %
43.75 %
50 %
56.25 %
Number of driving stages
3 to 4
00
01
10
11
3
4
5
6[1]
Duty cycle highest driving stage
5
0
1
75 %[2]
100 %
Pulse stretching
6
0
1
no pulse stretching
pulse of 2 × tp and duty cycle of 25 % are added
Factory test bits
7 to 8
-
-
[1] Including the highest driving stage, which one has no motor step detection.
[2] If the maximum duty cycle of 75 % is selected, not all programming combinations are possible since the
second highest level must be smaller than the highest driving level.
PCA2000_2001
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 23 August 2010
9 of 30
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
Table 7.
Bit
Description of word C bits
Value
Description
Pulse width tp
1 to 3
000
001
010
011
100
101
110
111
0.98 ms
1.95 ms
2.90 ms
3.90 ms
4.90 ms
5.90 ms
6.80 ms
7.80 ms
[1]
Time delay td(max)
4 to 6
000
001
010
011
100
101
110
111
3.91 ms
4.88 ms
5.86 ms
6.84 ms
7.81 ms
8.79 ms
9.77 ms
10.74 ms
EOL voltage of the battery
7
0
1
1.38 V (silver-oxide)
2.5 V (lithium)
Factory test bit
8
-
-
[1] Between positive and negative detection pulses.
Byte D is read to determine which type of the PCA200X family is used in a particular
application.
Table 8.
Bit
Description of word D bits
Value
Description
Type recognition
1 to 4
0000
1000
0100
1100
PCA2002
PCA2000
PCA2001
PCA2003
Factory test bits
5 to 8
-
-
PCA2000_2001
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 23 August 2010
10 of 30
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
7.6 Programming procedure
For a watch it is essential that the timing calibration can be made after the watch is fully
assembled. In this situation, the supply pads are often the only terminals which are still
accessible.
Writing to the OTP cells and performing the related functional checks is achieved in the
PCA2000 and PCA2001 by modulating the supply voltage. The necessary control circuit
consists basically of a voltage level detector, an instruction counter which determines the
function to be performed, and an 8-bit shift register which allows writing to the OTP cells of
an 8-bit word in one step and acts as a data pointer for checking the OTP content.
There are six different instruction states (state 3 and state 5 are handled as state 4):
• State 1: measurement of the quartz crystal oscillator frequency (divided by 1024)
• State 2: measurement of the inhibition time
• State 3: write/check word A
• State 4: write/check word B
• State 5: write/check word C
• State 6: check word D (type recognition)
Each instruction state is switched on with a pulse to VP(prog)(start). After this large pulse, an
initial waiting time of t0 is required. The programming instructions are then entered by
modulating the supply voltage with small pulses (amplitude VP(mod) and pulse width tmod).
The first small pulse defines the start time, the following pulses perform three different
functions, depending on the time delay (td) from the preceding pulse
(see Figure 7, Figure 8, Figure 11 and Figure 12):
• td = t1 (0.7 ms); increments the instruction counter
• td = t2 (1.7 ms); clocks the shift register with data = logic 0
• td = t3 (2.7 ms); clocks the shift register with data = logic 1
The programming procedure requires a stable oscillator. This means that a waiting time,
determined by the start-up time of the oscillator is necessary after power-up of the circuit.
After the VP(prog)(start) pulse, the instruction counter is in state 1 and the data shift register
is cleared.
The instruction state ends with a second pulse to VP(prog)(stop) or with a pulse to Vstore
.
In any case, the instruction states are terminated automatically 2 seconds after the last
supply modulation pulse.
7.7 Programming the memory cells
Applying the two-stage programming pulse (see Figure 7) transfers the stored data in the
shift register to the OTP cells.
Perform the following to program a memory word:
1. Starting with a VP(prog)(start) pulse wait for the time period t0 then set the instruction
counter to the word to be written (td = t1).
PCA2000_2001
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 23 August 2010
11 of 30
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
2. Enter the data to be stored in the shift register (td = t2 or t3). LSB first (bit 8) and the
MSB last (bit 1).
3. Applying the two-stage programming pulse Vprestore followed by Vstore stores the word.
The delay between the last data bit and the prestore pulse Vprestore is td = t4. Store the
word by raising the supply voltage to Vstore; the delay between the last data bit and the
store pulse is td.
The example shown in Figure 7 performs the following functions:
• Start
• Setting instruction counter to state 4 (word B)
• Entering data word 110101 into the shift register (sequence: LSB first and MSB last)
• Writing to the OTP cells for word B
t
w(prestore)
V
DD
V
store
t
p(start)
V
P(prog)(start)
V
prestore
t
t
1
t
1
t
1
t
3
t
t
3
t
2
t
t
3
t
4
t
w(store)
0
2
3
V
P(mod)
V
DD(nom)
V
SS
mgw356
The example shows the programming of B = 110101 (the sequence is LSB first and MSB last).
Fig 7. Supply voltage modulation for programming
PCA2000_2001
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 23 August 2010
12 of 30
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
7.8 Checking memory content
The stored data of the OTP array can be checked bit wise by measuring the supply
current. The array word is selected by the instruction state and the bit is addressed by the
shift register.
To read a word, the word is first selected (td = t1), and a logic 1 is written into the first cell
of the shift register (td = t3). This logic 1 is then shifted through the entire shift register
(td = t2), so that it points with each clock pulse to the next bit.
If the addressed OTP cell contains a logic 1, a 30 kΩ resistor is connected between VDD
and VSS, which increases the supply current accordingly.
Figure 8 shows the supply voltage modulation for reading word B, with the corresponding
supply current variation for word B = 110101 (sequence: first MSB and last LSB).
V
DD
t
p(start)
t
p(stop)
V
P(prog)(start)
V
P(prog)(stop)
t
0
t
1
t
1
t
1
t
t
t
2
t
2
t
2
t
2
3
2
V
P(mod)
V
DD(nom)
V
SS
I
DD
(1)
mgw357
VDD
(1) ΔIDD
=
---------------
30 kΩ
Fig 8. Supply voltage modulation and corresponding supply current variation for
reading word B
PCA2000_2001
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 23 August 2010
13 of 30
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
7.9 Frequency tuning of assembled watch
Figure 9 shows the test set-up for frequency tuning the assembled watch.
32 kHz
M
PCA200x
FREQUENCY
COUNTER
motor
PROGRAMMABLE
DC POWER SUPPLY
battery
PC INTERFACE
PC
mgw568
Fig 9. Frequency tuning at assembled watch
7.10 Measurement of oscillator frequency and inhibition time
The output of the two measuring states can either be monitored directly at pad RESET or
as a modulation of the supply voltage (a modulating resistor of 30 kΩ is connected
between VDD and VSS when the signal at pad RESET is at HIGH-level).
The supply voltage modulation must be followed as shown in Figure 10 in order to
guarantee the correct start-up of the circuit during production and testing.
V
DD
t
p(stop)
V
P(prog)(stop)
t
> 500 ms
d(start)
V
DD(nom)
V
SS
001aac503
Fig 10. Supply voltage at start-up during production and testing
PCA2000_2001
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 23 August 2010
14 of 30
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
Measuring states:
• State 1: quartz crystal oscillator frequency divided by 1024; state 1 starts with a pulse
to VP and ends with a second pulse to VP
• State 2: inhibition time has a value of n × 0.122 ms. A signal with periodicity of
31.25 ms + n × 0.122 ms appears at pad RESET and as current modulation at
pad VDD (see Figure 11 and Figure 12)
31.25 ms + inhibition time
V
DD
V
O(dif)
V
SS
mgw355
Fig 11. Output waveform at pad RESET for instruction state 2
V
DD
t
t
p(stop)
p(start)
V
V
P(prog)(stop)
P(prog)(start)
t
t
1
0
V
P(mod)
V
DD(nom)
V
SS
mgu719
Fig 12. Supply voltage modulation for starting and stopping of instruction state 2
7.11 Customer testing
Connecting pad RESET to VSS activates the test mode. In this test mode, the motor
output frequency is 8 Hz; the duty cycle reduction and battery check occurs every second,
instead of every 4 minutes. If the supply voltage drops below the EOL threshold voltage,
the motor output frequency is 32 Hz with the highest driving level.
7.12 EOL of battery
The supply voltage is checked every 4 minutes. If it drops below the EOL threshold
voltage (1.38 V for silver-oxide, 2.5 V for lithium batteries), the motor steps change from
one pulse per second to a burst of four pulses every 4 seconds. The step detection is
switched off, and the motor is driven with the highest pulse level.
Only the PCA2000 has an EOL function.
PCA2000_2001
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 23 August 2010
15 of 30
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
8. Limiting values
Table 9.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VSS = 0 V
on all supply pins
output
Min
−1.8
−0.5
-
Max
Unit
V
[1][2]
VDD
VI
supply voltage
+7.0
input voltage
+7.5
V
tsc
short circuit duration time
indefinite
±2000
s
[3]
VESD
electrostatic discharge
voltage
HBM
-
V
[4]
[5]
[6]
MM
-
±200
100
V
Ilu
latch-up current
-
mA
°C
°C
Tstg
Tamb
storage temperature
ambient temperature
−30
−10
+100
+60
[1] When writing to the OTP cells, the supply voltage (VDD) can be raised to a maximum of 12 V for a period of
1 s.
[2] Connecting the battery with reversed polarity does not destroy the circuit, but in this condition a large
current flows, which rapidly discharges the battery.
[3] Pass level; Human Body Model (HBM), according to Ref. 4 “JESD22-A114”.
[4] Pass level; Machine Model (MM), according to Ref. 5 “JESD22-A115”.
[5] Pass level; latch-up testing according to Ref. 6 “JESD78” at maximum ambient temperature (Tamb(max)).
[6] According to the NXP store and transport requirements (see Ref. 8 “NX3-00092”) the devices have to be
stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products
deviant conditions are described in that document.
PCA2000_2001
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32 kHz watch circuit with programmable adaptive motor pulse
9. Characteristics
Table 10. Characteristics
VDD = 1.55 V; VSS = 0 V; fosc = 32.768 kHz; Tamb = 25 °C; quartz crystal: RS = 40 kΩ, C1 = 2 fF to 3 fF, CL = 8.2 pF; unless
otherwise specified.
Symbol
Supply
VDD
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
normal operating mode;
1.1
1.55
3.60
V
Tamb = −10 °C to +60 °C
ΔVDD
supply voltage variation ΔV/Δt = 1 V/μs
-
-
-
-
0.25
120
180
V
IDD
supply current
between motor pulses
90
120
nA
nA
between motor pulses at
VDD = 3.5 V
Tamb = −10 °C to +60 °C
-
-
-
200
135
nA
nA
stop mode;
100
pad RESET connected to
VDD
Motor output
[1]
Vsat
saturation voltage
Rmotor = 2 kΩ;
Tamb = −10 °C to +60 °C
-
-
150
200
200
300
mV
Zo(sc)
output impedance
(short circuit)
between motor pulses;
Imotor < 1 mA
Ω
Oscillator
Vstart
start voltage
1.1
5
-
-
V
gm
transconductance
start-up time
Vi(osc) ≤ 50 mV(p-p)
ΔVDD = 100 mV
10
-
μS
s
tstartup
Δf/f
-
0.3
0.05
5.2
0.9
0.20
6.3
frequency stability
-
ppm
pF
CL(itg)
integrated load
capacitance
4.3
Rpar
parasitic resistance
allowed resistance between
adjacent pads
20
-
-
MΩ
Voltage level detector
Vth(EOL) EOL threshold voltage silver-oxide battery
1.30
2.35
-
1.38
2.50
−0.07
1.46
2.65
-
V
lithium battery
V
TCEOL
EOL temperature
coefficient
%/°C
Pad RESET
fo
output frequency
-
32
-
-
-
Hz
V
[2]
VO(dif)
differential output
voltage
RL = 1 MΩ; CL = 10 pF
1.4
[2]
[2]
tr
rise time
RL = 1 MΩ; CL = 10 pF
RL = 1 MΩ; CL = 10 pF
-
-
-
1
-
μs
μs
nA
tf
fall time
1
-
Ii(AV)
average input current
pad RESET connected to
VDD or VSS
10
20
[1] P1 + ... + P4 + N1 + N2 (see Section 7.2).
[2] RL and CL are a load resistor and load capacitor, externally connected to pad RESET.
PCA2000_2001
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32 kHz watch circuit with programmable adaptive motor pulse
10. OTP programming characteristics
Table 11. Specifications for OTP programming
See Figure 7, Figure 8 and Figure 12.
Symbol
Parameter[1]
Conditions
Min
1.5
6.6
6.2
320
Typ
Max
3.0
Unit
V
VDD
supply voltage
during programming procedure
-
VP(prog)(start) programming supply voltage (start)
VP(prog)(stop) programming supply voltage (stop)
-
6.8
V
-
6.4
V
VP(mod)
supply voltage modulation
for entering instructions, referred
to VDD
350
380
mV
Vprestore
Vstore
Istore
prestore voltage
supply voltage
store current
for prestore pulse
6.2
9.9
-
-
6.4
10.1
10
V
for writing to the OTP cells
for writing to the OTP cells
10.0
-
V
mA
ms
ms
μs
tp(start)
tp(stop)
tmod
start pulse width
pulse width of stop pulse
modulation pulse width
prestore pulse width
store pulse width
time 0
8
10
-
12
0.05
25
0.5
40
30
-
tw(prestore)
tw(store)
t0
0.05
95
0.5
110
30
ms
ms
ms
ms
for writing to the OTP cells
waiting time after start pulse
100
-
20
t1
time 1
pulse distance for incrementing
the state counter
0.6
0.7
0.8
t2
time 2
pulse distance for clocking the
data register with data = logic 0
1.6
2.6
0.1
0.5
18
1.7
2.7
0.2
-
1.8
2.8
0.3
5.0
45
ms
ms
ms
V/μs
kΩ
t3
time 3
pulse distance for clocking the
data register with data = logic 1
t4
time 4
waiting time for writing to OTP
cells
SR
Rmod
slew rate
modulation resistance
for modulation of the supply
voltage
supply current modulation
read-out resistor
30
[1] Program each word once only.
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NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
11. Bare die outline
Wire bond die; 8 bonding pads; 1.16 x 0.86 x 0.22 mm
PCA200xU
A
D
P
P
1
2
e
1
e
2
E
P
4
P
3
detail X
X
e
D
DIMENSIONS (mm are the original dimensions)
UNIT
A
D
E
e
1
e
2
e
D
P
P
P
P
4
1
2
3
max 0.22
nom 0.20 1.16 0.86 0.17 0.32 0.96 0.096 0.086 0.096 0.086
min 0.18 0.093 0.083 0.093 0.083
0.099 0.089 0.099 0.089
0
0.5
1 mm
mm
scale
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
08-05-09
08-05-21
PCA200xU
Fig 13. Bare die outline PCA2000U and PCA2001U
PCA2000_2001
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32 kHz watch circuit with programmable adaptive motor pulse
WLCSP8: wafer level chip-size package; 8 bumps
PCA200xCX
D
b
e
1
A
2
e
2
A
E
A
1
detail X
e
X
D
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
08-05-21
10-08-18
PCA200xCX
Fig 14. Bare die outline PCA200xCX8 (for dimensions see Table 12)
Table 12. Dimensions of PCA200xCX
Original dimensions are in mm.
Unit (mm)
A
A1
A2
b
D
E
e1
e2
eD
PCA2000CX8/5/1 and PCA2001CX8/5/1
max
nom
min
-
0.090
0.075
0.060
-
0.12
0.10
0.08
-
-
-
-
-
0.762
-
0.69
-
1.16
-
0.86
-
0.17
-
0.32
-
0.96
-
PCA2000CX8/12/1
max
nom
min
0.310
0.090
0.075
0.060
0.22
0.20
0.18
0.12
0.10
0.08
-
-
-
-
-
0.275
0.240
1.16
-
0.86
-
0.17
-
0.32
-
0.96
-
PCA2000_2001
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32 kHz watch circuit with programmable adaptive motor pulse
Table 13. Bonding pad and solder bump locations
Symbol
Pad
Coordinates[1]
x
y
[2]
VSS
1
2
3
4
5
6
7
8
−480
+330
+160
−160
−330
−330
−160
+160
+330
i.c.[3]
−480
OSCIN
OSCOUT
VDD
−480
−480
+480
MOT1
MOT2
RESET
+480
+480
+480
[1] All coordinates are referenced, in μm, to the center of the die (see Figure 2, Figure 13 and Figure 14).
[2] The substrate (rear side of the chip) is connected to VSS. Therefore the die pad must be either floating or
connected to VSS
[3] Pad i.c. is used for factory tests; in normal operation it should be left open-circuit, and it has an internal
pull-down resistance to VSS
.
.
12. Packing information
12.1 Tray information
A
x
G
C
H
y
1,1 2,1 3,1
1,2 2,2
1,3
x,1
D
B
F
x,y
1,y
A
A
E
M
J
SECTION A-A
mgu653
Fig 15. Tray details
PCA2000_2001
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NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
mgu652
The orientation of the IC in a pocket is indicated by the position of the IC type name on the surface
of the die, with respect to the cut corner on the upper left of the tray.
Fig 16. Tray alignment
Table 14. Tray dimensions
Dimension
Description
Value
A
B
C
D
E
F
pocket pitch; x direction
pocket pitch; y direction
pocket width; x direction
pocket width; y direction
tray width; x direction
tray width; y direction
2.15 mm
2.43 mm
1.01 mm
1.39 mm
50.67 mm
50.67 mm
4.86 mm
G
distance from cut corner to pocket (1, 1)
center
H
distance from cut corner to pocket (1, 1)
center
4.66 mm
J
tray thickness
3.94 mm
0.61 mm
20
M
x
pocket depth
number of pockets in x direction
number of pockets in y direction
y
18
PCA2000_2001
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32 kHz watch circuit with programmable adaptive motor pulse
12.2 Wafer information
(1)
(1)
~18 μm
~18 μm
84 μm
84 μm
(1)
~18 μm
Saw lane
Saw lane
84 μm
detail X
detail Y
(1)
1
8
1
8
4
1
5
8
4
1
5
8
Y
X
4
1
5
8
4
1
5
8
4
1
5
8
4
1
5
8
4
1
5
8
4
1
5
8
4
1
5
8
4
1
5
8
4
5
4
5
Straight edge of the wafer
001aai236
The die are grouped in arrays of 2 × 6 devices. Each array is edged with a metal path. All this metal
paths have to be cut while dicing.
Fig 17. Wafer layout of PCA2000CX and PCA2001CX
PCA2000_2001
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32 kHz watch circuit with programmable adaptive motor pulse
13. Soldering of WLCSP packages
13.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note
AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface
mount reflow soldering description”.
Wave soldering is not suitable for this package.
All NXP WLCSP packages are lead-free.
13.2 Board mounting
Board mounting of a WLCSP requires several steps:
1. Solder paste printing on the PCB
2. Component placement with a pick and place machine
3. The reflow soldering itself
13.3 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 18) than a PbSn process, thus
reducing the process window
• Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature), and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic) while being low enough that the packages and/or boards are not
damaged. The peak temperature of the package depends on package thickness and
volume and is classified in accordance with Table 15.
Table 15. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350
260
350 to 2000
260
> 2000
260
< 1.6
1.6 to 2.5
> 2.5
260
250
245
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 18.
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32 kHz watch circuit with programmable adaptive motor pulse
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 18. Temperature profiles for large and small components
For further information on temperature profiles, refer to application note AN10365
“Surface mount reflow soldering description”.
13.3.1 Stand off
The stand off between the substrate and the chip is determined by:
• The amount of printed solder on the substrate
• The size of the solder land on the substrate
• The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
13.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been
wetted by the solder from the bump. The surface of the joint should be smooth and the
shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps
after reflow can occur during the reflow process in bumps with high ratio of bump diameter
to bump height, i.e. low bumps with large diameter. No failures have been found to be
related to these voids. Solder joint inspection after reflow can be done with X-ray to
monitor defects such as bridging, open circuits and voids.
13.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing the
chip from the substrate and replacing it with a new chip. If a chip is removed from the
substrate, most solder balls of the chip will be damaged. In that case it is recommended
not to re-use the chip again.
PCA2000_2001
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32 kHz watch circuit with programmable adaptive motor pulse
Device removal can be done when the substrate is heated until it is certain that all solder
joints are molten. The chip can then be carefully removed from the substrate without
damaging the tracks and solder lands on the substrate. Removing the device must be
done using plastic tweezers, because metal tweezers can damage the silicon. The
surface of the substrate should be carefully cleaned and all solder and flux residues
and/or underfill removed. When a new chip is placed on the substrate, use the flux
process instead of solder on the solder lands. Apply flux on the bumps at the chip side as
well as on the solder pads on the substrate. Place and align the new chip while viewing
with a microscope. To reflow the solder, use the solder profile shown in application note
AN10365 “Surface mount reflow soldering description”.
13.3.4 Cleaning
Cleaning can be done after reflow soldering.
14. Abbreviations
Table 16. Abbreviations
Acronym
HBM
LSB
Description
Human Body Model
Least Significant Bit
Machine Model
MM
MSB
Most Significant Bit
One Time Programmable
OTP
15. References
[1] AN10706 — Handling bare die
[2] IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[4] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[5] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[6] JESD78 — IC Latch-Up Test
[7] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[8] NX3-00092 — NXP store and transport requirements
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32 kHz watch circuit with programmable adaptive motor pulse
16. Revision history
Table 17. Revision history
Document ID
Release date
20100823
Data sheet status
Change notice
Supersedes
PCA2000_2001 v.8
Modifications:
Product data sheet
-
PCA2000_2001_7
• Added new product type
PCA2000_2001_7
PCA2000_2001_6
PCA2000_2001_5
PCA2000_2001_4
PCA2000_2001_3
PCA2000_2001_2
PCA2000_2001_1
20100507
20090716
20081111
20050908
20031217
20030204
20020517
Product data sheet
-
-
-
-
-
-
-
PCA2000_2001_6
PCA2000_2001_5
PCA2000_2001_4
PCA2000_2001_3
PCA2000_2001_2
PCA2000_2001_1
-
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Objective specification
Preliminary specification
PCA2000_2001
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32 kHz watch circuit with programmable adaptive motor pulse
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
17.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
17.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
PCA2000_2001
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NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA2000_2001
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 08 — 23 August 2010
29 of 30
PCA2000; PCA2001
NXP Semiconductors
32 kHz watch circuit with programmable adaptive motor pulse
19. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
18
19
Contact information . . . . . . . . . . . . . . . . . . . . 29
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 4
Motor pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Step detection. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Time calibration . . . . . . . . . . . . . . . . . . . . . . . . 7
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Programming possibilities. . . . . . . . . . . . . . . . . 8
Programming procedure. . . . . . . . . . . . . . . . . 11
Programming the memory cells . . . . . . . . . . . 11
Checking memory content . . . . . . . . . . . . . . . 13
Frequency tuning of assembled watch. . . . . . 14
Measurement of oscillator frequency and
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
inhibition time . . . . . . . . . . . . . . . . . . . . . . . . . 14
Customer testing . . . . . . . . . . . . . . . . . . . . . . 15
EOL of battery . . . . . . . . . . . . . . . . . . . . . . . . 15
7.11
7.12
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 17
OTP programming characteristics. . . . . . . . . 18
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 19
9
10
11
12
12.1
12.2
Packing information . . . . . . . . . . . . . . . . . . . . 21
Tray information . . . . . . . . . . . . . . . . . . . . . . . 21
Wafer information . . . . . . . . . . . . . . . . . . . . . . 23
13
13.1
13.2
13.3
13.3.1
13.3.2
13.3.3
13.3.4
Soldering of WLCSP packages. . . . . . . . . . . . 24
Introduction to soldering WLCSP packages . . 24
Board mounting . . . . . . . . . . . . . . . . . . . . . . . 24
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 24
Stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Quality of solder joint . . . . . . . . . . . . . . . . . . . 25
Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
14
15
16
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 26
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 28
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29
17.1
17.2
17.3
17.4
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 August 2010
Document identifier: PCA2000_2001
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