PCA2129_技术文档

PCA2131

Nano-power highly accurate RTC with integrated quartz

crystal for automotive applications

Rev. 1.0 — 26 July 2021

Product data sheet

1 General description

The PCA2131 is a CMOS Real Time Clock (RTC) and calendar with an integrated

Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz

crystal optimized for very high accuracy and ultra low power consumption. The

PCA2131 has a selectable I²C-bus or SPI-bus, a backup battery switch-over circuit, a

programmable watchdog function, four timestamps function, and many other features.

For a selection of NXP Real-Time Clocks, see Section 15.1.

2 Features and benefits

• AEC-Q100 compliant version: PCA2131TF/Q900 for automotive applications

• Operating temperature range from -40 °C to +105 °C

• Temperature Compensated Crystal Oscillator (TCXO) with trimmed integrated

capacitors

• Clock operational up to 125 °C

• Ultra low supply current: typical 106 nA at V_DD= 3.3 V

• Temperature compensated RTC, typical accuracy ±3 ppm from -40 °C to +85 °C;

±8 ppm from +85 °C to +105 °C

• Integration of a 32.768 kHz quartz crystal and oscillator in the same package

• Provides year, month, day, weekday, hours, minutes, seconds and 1/100 seconds

• Provides leap year correction

• Timestamp function

– with interrupt capability

– detection of four different events on four input pins (for example, for tamper detection)

• 2-line bidirectional 400 kHz Fast-mode I²C-bus interface

• 4-line SPI-bus with separate data input and output (maximum speed 6.5 Mbit/s)

• Battery backup input pin and switch-over circuitry

• Battery backed output voltage

• Battery low detection function

• Power-On Reset (POR)

• Power-On Reset Override (PORO) function

• Software reset function

• Two interrupt outputs (open-drain)

• Programmable 1 second or 1 minute interrupt

• Programmable watchdog timer with interrupt

• Programmable alarm function with interrupt capability

• Programmable square output

• Clock operating voltage: 1.2 V to 5.5 V

NXP Semiconductors

PCA2131

Nano-power highly accurate RTC with integrated quartz crystal for automotive applications

3 Applications

• Electronic metering for electricity, water, and gas

• Precision timekeeping

• Access to accurate time of the day

• GPS equipment to reduce time to first fix

• Applications that require an accurate process timing

• Products with long automated unattended operation time

4 Ordering information

Table 1.ꢀOrdering information

Type number

Topside

marking

Package

Name

Description

Version

PCA2131TF/Q900 A31

HLSON16

thermal enhanced low profile small outline; no leads, 16 SOT1992-1

terminals, 0.125 dimple wettable flank, 0.5 mm pitch,

4.5 mm x 3.5 mm x 1.45 mm body

4.1 Ordering options

Table 2.ꢀOrdering options

Product type

number

Orderable part

number

Package

Packing method

Minimum

Order

Temperature

Quantity

PCA2131TF/Q900

PCA2131TF/Q900Y HLSON16

REEL 13" Q1 DP

4000

T_amb= -40 °C to +105 °C

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5 Block diagram

INTA / INTB

TEMP

OSCO

32.768 kHz

Control_1

Control_2

Control_3

00h

DIVIDER

AND

TIMER

01h

OSCI

02h

TCXO

03h

Control_4

Control_5

04h

05h

Sofware Reset

100 Hz

th

06h

1/100 Seconds

CLKOUT

DIVIDER

07h

Seconds

Minutes

Hours

LOGIC

CONTROL

08h

V

DD

BATTERY BACK UP

SWITCH-OVER

CIRCUITRY

09h

V

BAT

internal operating

Days

0Ah

V

SS

voltage V

oper(int)

Weekdays

Months

Years

0Bh

BBS

0Ch

0Dh

ADDRESS

REGISTER

OSCILLATOR

MONITOR

RESET

0Eh

Second_alarm

Minute_alarm

Hour_alarm

0Fh

10h

SPI-BUS

INTERFACE

Day_alarm

11h

Weekday_alarm

CLKOUT_ctl

12h

13h

SDA/CE

SDO

SERIAL BUS

INTERFACE

SELECTOR

Timestp_ctl 1/2/3/4

14h/1Bh/22h/29h

15h/1Ch/23h/2Ah

16h/1Dh/24h/2Bh

17h/1Eh/25h/2Ch

18h/1Fh/26h/2Dh

19h/20h/27h/2Eh

1Ah/21h/28h/2Fh

30h

Sec_timestp 1/2/3/4

Min_timestp 1/2/3/4

Hour_timestp 1/2/3/4

Day_timestp 1/2/3/4

SDI

SCL

IFS

PCA2131

2

I C-BUS

INTERFACE

R

Mon_timestp 1/2/3/4

Year_timestp 1/2/3/4

Aging_offset

PU 1/2/3/4

TS1

TS2

TS3

TS4

INT_A_MASK 1/2

INT_B_MASK 1/2

31h/32h

TEMPERATURE

SENSOR

TEMP

33h/34h

35h

Watchdg_tim_ctl

Watchdg_tim_val

36h

aaa-041562

Figure 1.ꢀBlock diagram of PCA2131

PCA2131

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PCA2131

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6 Pinning information

6.1 Pinning

IFS

SCL

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

BAT

DD

SDI

BBS

INTA

INTB

TS4

TS3

TS2

SDO

PCA2131

SDA/CE

CLKOUT

V

SS

TS1

aaa-041563

Figure 2.ꢀPin configuration for PCA2131 (transparent top view)

6.2 Pin description

Table 3.ꢀPin description

Input or input/output pins must always be at a defined level (V_SSor V_DD) unless otherwise specified.

Symbol

SCL

2

Description

combined serial clock input for both I²C-bus and SPI-bus

SDI

3

serial data input for SPI-bus

connect to pin V_SSif I²C-bus is selected

SDO

4

serial data output for SPI-bus, push-pull

leave open or connect to pin V_SSif I²C-bus is selected

SDA/CE

IFS

5

1

combined serial data input and output for the I²C-bus and chip enable

input (active LOW) for the SPI-bus

interface selector input

connect to pin V_SSto select the SPI-bus

connect to pin V_DDto select the I²C-bus

TS1,TS2,TS3,TS4,

8,9,10,11

timestamp input (active LOW) with 500 kΩ internal pull-up resistor (R_PU

)

CLKOUT

V_SS

6

clock output (push-pull)

7

ground supply voltage

INTB

INTA

12

13

14

interrupt B output (open-drain; active LOW)

interrupt A output (open-drain; active LOW)

output voltage (battery backed)

BBS

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PCA2131

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Table 3.ꢀPin description...continued

Input or input/output pins must always be at a defined level (V_SSor V_DD) unless otherwise specified.

Symbol

Description

V_BAT

16

battery supply voltage (backup)

connect to V_SSif battery switch-over is not used

V_DD

15

supply voltage

Exposed Pad

Tie to V_SS(preferred)^[1]or leave floating

[1] This protects against signal feedback to the oscillator if routed close to the part.

7 Functional description

The PCA2131 is a Real Time Clock (RTC) and calendar with an on-chip Temperature

Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal integrated

into the same package.

Address and data are transferred by a selectable 400 kHz Fast-mode I²C-bus or a 4-line

SPI-bus with separate data input and output (see Section 7.16). The maximum speed of

the SPI-bus is 6.5 Mbit/s.

The PCA2131 has a backup battery input pin and backup battery switch-over circuit

which monitors the main power supply. The backup battery switch-over circuit

automatically switches to the backup battery when a power failure condition is detected

(see Section 7.5.1). Accurate timekeeping is maintained even when the main power

supply is interrupted.

A battery low detection circuit monitors the status of the battery (see Section 7.5.2).

When the battery voltage drops below a certain threshold value, a flag is set to indicate

that the battery must be replaced soon. This ensures the integrity of the data during

periods of battery backup.

7.1 Register overview

The PCA2131 contains an auto-incrementing address register: the built-in address

register will increment automatically after each read or write of a data byte up to the

register 36h. After register 36h, the auto-incrementing will wrap around to address 00h

(see Figure 3).

address register

00h

01h

02h

03h

...

auto-increment

34h

35h

36h

wrap around

aaa-041564

Figure 3.ꢀHandling address registers

• The first five registers (memory address 00h, 01h, 02h, 03h and 04h) are used as

control registers (see Section 7.2).

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Nano-power highly accurate RTC with integrated quartz crystal for automotive applications

• The register at address 05h is for software reset.

• The memory addresses 06h through to 0Dh are used as counters for the clock function

(1/100 seconds up to years). The date is automatically adjusted for months with fewer

than 31 days, including corrections for leap years. The clock can operate in 12-hour

mode with an AM/PM indication or in 24-hour mode (see Section 7.9).

• The registers at addresses 0Eh through 12h define the alarm function. It can be

selected that an interrupt is generated when an alarm event occurs (see Section 7.10).

• The register at address 13h defines the temperature measurement period and the

clock out mode. The temperature measurement can be selected from every 32 minutes

(default) down to every 4minutes (see Table 17). CLKOUT frequencies of 32.768 kHz

(default) down to 1 Hz for use as system clock, microcontroller clock, and so on, can be

chosen (see Table 18).

• The registers at addresses 14h to 2Fh are used for the timestamp function. When

the trigger event happens, the actual time is saved in the timestamp registers (see

Section 7.12).

• The register at address 30h is used for the correction of the crystal aging effect (see

Section 7.4.1).

• The registers at addresses 31h to 34h are used for interrupt configration.

• The registers at addresses 35h and 36h are used for the watchdog timer functions. The

watchdog timer has four selectable source clocks allowing for timer periods from less

than 20 ms to greater than 4 hours (see Table 59). An interrupt is generated when the

watchdog times out.

• The registers 100th Seconds, Seconds, Minutes, Hours, Days, Months, and Years

are all coded in Binary Coded Decimal (BCD) format to simplify application use. Other

registers are either bit-wise or standard binary.

When one of the RTC registers is written or read, the content of all counters is

temporarily frozen, all registers hold their state during SPI or I2C transactions. The

time stamp registers would update as soon as the bus transaction completes. This

prevents a faulty writing or reading of the clock and calendar during a carry condition

(see Section 7.9.9).

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PCA2131

Nano-power highly accurate RTC with integrated quartz crystal for automotive applications

7.2 Control registers

The first five registers of the PCA2131, with the addresses 00h, 01h, 02h, 03h and 04h,

are used as control registers.

7.2.1 Register Control_1

Table 5.ꢀControl_1 - control and status register 1 (address 00h) bit allocation

Bits labeled as T are unused and return 0 when read.

Bit

7

6

5

4

3

2

1

0

Symbol

EXT_

TEST

TC_DIS

STOP

100TH_

S_DIS

POR_

OVRD

12_24

MI

SI

Reset

value

0

1

0

Table 6.ꢀControl_1 - control and status register 1 (address 00h) bit description

Bits labeled as T are unused and return 0 when read.

Bit

Symbol

Value

Description

Reference

7

EXT_TEST

0

1

0

1

0

1

normal mode

Section 7.14

external clock test mode

6

5

TC_DIS

STOP

Temperature compensation enabled

Temperature compensation disabled

RTC source clock runs

Section 7.3.1

Section 7.15

RTC clock is stopped;

RTC divider chain flip-flops are asynchronously

set logic 0;

CLKOUT output frequencies are still available

4

3

100TH_S_DIS

POR_OVRD

0

1

100th seconds counter enabled

-

100th seconds counter Disabled, register 06h reset

to 00h.

0

1

Power-On Reset Override (PORO) facility disabled; Section 7.7.2

set logic 0 for normal operation

Power-On Reset Override (PORO) sequence

reception enabled

2

12_24

0

1

24-hour mode selected

12-hour mode selected

Table 34,

Table 50,

Table 71

1

0

MI

SI

0

1

0

1

minute interrupt disabled

minute interrupt enabled

second interrupt disabled

second interrupt enabled

Section 7.13.1

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7.2.2 Register Control_2

Table 7.ꢀControl_2 - control and status register 2 (address 01h) bit allocation

Bits labeled as T are unused and return 0 when read.

Bit

7

MSF

0

6

WDTF

0

5

T

0

4

AF

0

3

T

0

2

T

0

1

AIE

0

T

0

Symbol

Reset

value

Table 8.ꢀControl_2 - control and status register 2 (address 01h) bit description

Bits labeled as T are unused and return 0 when read.

Bit

Symbol

Value

Description

Reference

7

MSF

0

1

no minute or second interrupt generated

Section 7.13

flag set when minute or second interrupt

generated;

flag must be cleared to clear interrupt

6

WDTF

0

1

no watchdog timer interrupt generated

Section 7.13.3

flag set when watchdog timer interrupt generated;

flag cannot be cleared by command (read-only)

5

4

T

0

1

unused

-

AF

no alarm interrupt triggered

Section 7.10.6

flag set when alarm triggered;

flag must be cleared to clear interrupt

3:2

1

T

0

1

0

unused

-

AIE

no interrupt generated from the alarm flag

interrupt generated when alarm flag set

unused

Section 7.13.4

0

T

-

7.2.3 Register Control_3

Table 9.ꢀControl_3 - control and status register 3 (address 02h) bit allocation

Bit

7

6

5

4

BTSE

0

3

BF

0

2

BLF

0

1

BIE

0

BLIE

0

Symbol

PWRMNG[2:0]

1

Reset

value

1

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Table 10.ꢀControl_3 - control and status register 3 (address 02h) bit description

Bit

Symbol

Value

Description

Reference

7 to 5

PWRMNG[2:0]

see

control of the battery switch-over, battery low

Section 7.5

Table 22

detection, and extra power fail detection functions

4

3

BTSE

BF

0

1

0

1

no timestamp when battery switch-over occurs

time-stamped when battery switch-over occurs

no battery switch-over interrupt occurred

Section 7.12.4

Section 7.5.1

and

Section 7.12.4

flag set when battery switch-over occurs;

flag must be cleared to clear interrupt

2

BLF

0

1

battery status ok;

Section 7.5.2

no battery low interrupt generated

battery status low;

flag cannot be cleared by command, flag is

automatically cleared when battery is replaced.

1

0

BIE

0

1

0

1

no interrupt generated from the battery flag (BF)

interrupt generated when BF is set

Section 7.13.6

BLIE

no interrupt generated from battery low flag (BLF) Section 7.13.7

interrupt generated when BLF is set

7.2.4 Register Control_4

Table 11.ꢀControl_4 - control and status register 4 (address 03h) bit allocation

Bit

7

TSF1

0

6

TSF2

0

5

TSF3

0

4

TSF4

0

3

T

0

2

T

0

1

T

0

T

0

Symbol

Reset

value

Table 12.ꢀControl_4 - control and status register 4 (address 03h) bit description

Bit

Symbol

Value

Description

Reference

7

TSF1

0

1

no timestamp interrupt generated for pin TS1

Section 7.12.1

flag set when TS1 input is driven to ground;

flag must be cleared to clear interrupt

6

5

4

TSF2

TSF3

TSF4

T

0

1

no timestamp interrupt generated when pin TS2

Section 7.12.1

flag set when TS2 input is driven to ground;

flag must be cleared to clear interrupt

0

1

no timestamp interrupt generated for pin TS3

flag set when TS3 input is driven to ground;

flag must be cleared to clear interrupt

0

1

no timestamp interrupt generated when pin TS4

flag set when TS4 input is driven to ground;

flag must be cleared to clear interrupt

3

0

Unused

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Table 12.ꢀControl_4 - control and status register 4 (address 03h) bit description...continued

Bit

2

Symbol

Value

Description

Unused

Reference

T

0

1

Unused

0

Unused

7.2.5 Register Control_5

Table 13.ꢀControl_5 - control and status register 5 (address 04h) bit allocation

Bit

7

TSIE1

0

6

TSIE2

0

5

TSIE3

0

4

TSIE4

0

3

T

0

2

T

0

1

T

0

T

0

Symbol

Reset

value

Table 14.ꢀControl_5 - control and status register 5 (address 04h) bit description

Bit

Symbol

Value

Description

Reference

7

TSIE1

0

1

0

1

0

1

0

1

0

no interrupt generated from timestamp flag of TS1 Section 7.13.5

interrupt generated when timestamp flag set of TS1

6

TSIE2

TSIE3

TSIE4

T

no interrupt generated from timestamp flag of TS2 Section 7.13.5

interrupt generated when timestamp flag set of TS2

5

no interrupt generated from timestamp flag of TS3 Section 7.13.5

interrupt generated when timestamp flag set of TS3

4

no interrupt generated from timestamp flag of TS4 Section 7.13.5

interrupt generated when timestamp flag set of TS4

3 to 0

unused

-

7.3 Register CLKOUT_ctl

Table 15.ꢀCLKOUT_ctl - CLKOUT control register (address 13h) bit allocation

Bits labeled as T are unused and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by

subsequent resets.

Bit

7

6

5

OTPR

X

4

T

0

3

T

0

2

1

COF[2:0]

0

Symbol

TCR[1:0]

Reset

value

0

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Table 16.ꢀCLKOUT_ctl - CLKOUT control register (address 13h) bit description

Bits labeled as T are unused and return 0 when read.

Bit

7 to 6

5

Symbol

TCR[1:0]

OTPR

Value

Description

Reference

see Table 17

temperature measurement period

no OTP refresh

0

Section 7.3.2

1

OTP refresh performed

unused ^[1]

4

T

0

3

T

0

unused

2 to 0

COF[2:0]

see Table 18

CLKOUT frequency selection

Section 7.3.3

[1] programming this bit to 1 may lead to a decrease of timing accuracy.

7.3.1 Temperature compensated Real Time Clock

The frequency of tuning fork quartz crystal oscillators is temperature-dependent. In the

PCA2131, the frequency deviation caused by temperature variation is corrected by

adjusting the RTC frequency divider with digital method.

The load capacitance is trimmed to the required value at 25 °C in order to compensate

the frequency deviation over process variation.

The frequency accuracy at 25 °C can be evaluated by measuring the frequency of

the square wave signal available at the output pin CLKOUT. However, the selection of

f_CLKOUT= 32.768 kHz (default value) can lead to inaccurate measurements. Accurate

frequency measurement occurs when f_CLKOUT= 16.384 kHz or lower is selected (see

Table 18).

The temperature compensated frequency input for the Real Time Clock cannot be

observed at the CLKOUT pin but can be evaluated by following these steps.

• Set Second Interrupt, bit SI in register Control_1 to 1

• Set bit TI_TP in register Watchdg_tim_ctl to 1 for a pulsed interrupt signal

• Set bit SIA in register INTA_MASK_1 to 0 to direct the Second Interrupt to pin INTA for

a 1 Hz pulse output.

The RTC temperature compensation works by adding or deleting pulses at the 32.768

kHz level. These correction pulses are spaced evenly over a sufficiently long period

of time to reach the required resolution and accuracy. Every second corrections

with a resolution of about 30.5 ppm (1/32768) can be generated by the temperature

compensation engine. If for instance a 10 ppm correction is called for, the correction

pulses will be generated approximately once every 3 seconds, for a 50 ppm correction

every 0.6 s and so on.

The 1 Hz interrupt output signal can be measured with a counter and by selecting an

appropriate gating time the measurement resolution can be set to the desired level. A

gating time of 100 s for instance will determine the averaged 1 second period with a

resolution of 0.3 ppm.

The feature of temperature compensation can be turned off for ultra low power

consumption by first performing a software reset (SR) followed by setting TC_DIS to ‘1’

within 5 seconds.

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7.3.1.1 Temperature measurement

The PCA2131 has a temperature sensor circuit used to perform temperature

compensation of the clock input to the RTC. The temperature is measured immediately

after power-on and then periodically with a period set by the temperature conversion

rate TCR[1:0] in the register CLKOUT_ctl. During the first approximately 60 s after start-

up the compensation will be inactive, after this period the temperature compensation is

active.

Table 17.ꢀTemperature measurement period

TCR[1:0]

Temperature measurement period

[1]

00

01

10

11

32 min

16 min

8 min

4 min

[1] Default value.

7.3.2 OTP refresh

Each IC is calibrated during production and testing of the device. The calibration

parameters are stored on EPROM cells called One Time Programmable (OTP) cells. It is

recommended to process an OTP refresh once after the power is up and the oscillator is

operating stable. The OTP refresh takes less than 100 ms to complete.

To perform an OTP refresh, bit OTPR has to be cleared (set to logic 0) and then set to

logic 1 again.

When read OTPR bit, its state is:

"0" until the OTP read state machine completes copying of the eFuse data into the

shadow registers. This could be due to a POR event or to writing a 0 > 1 to the OTPR

register bit.

"1" when the OTP read state machine completes copying to the shadow registers from

the eFuse instances. During normal operation OTPR must be kept at 1 to prevent higher

power usage.

The OTP logic is not reset nor affected by the Software Reset. The OTPR functionality is

only reset by the initial digital POR.

During OTP refresh, V_DDhas to be above 1.8 V, the rising speed to 1.8 V needs to be

faster than 2 V/100 ms. After OTP refresh has finished, PCA2131 can operate with V_DD

as low as 1.2 V.

7.3.3 Clock output

A programmable square wave is available at pin CLKOUT. Operation is controlled by the

COF[2:0] control bits in register CLKOUT_ctl. Frequencies of 32.768 kHz (default) down

to 1 Hz can be generated for use as system clock, microcontroller clock, charge pump

input, or for calibrating the oscillator at 25 °C to determine aging offset. The CLKOUT

output is not temperature compensated to prevent jitter due to digital compensation

method.

CLKOUT is a push-pull output and is enabled at power-on. When disabled, the output is

high-impedance.

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Table 18.ꢀCLKOUT frequency selection

COF[2:0]

000

CLKOUT frequency (Hz)

Typical duty cycle ^[1]

[2]

32ꢀ768

60 : 40 to 40 : 60

50 : 50

-

001

16ꢀ384

010

8ꢀ192

011

4ꢀ096

100

2ꢀ048

101

1ꢀ024

110

1

111

CLKOUT = high-Z

[1] Duty cycle definition: % HIGH-level time: % LOW-level time.

[2] Default value.

The duty cycle of the selected clock is not controlled, however, due to the nature of the

clock generation all but the 32.768 kHz frequencies are 50 : 50.

7.4 Register Aging_offset

Table 19.ꢀAging_offset - crystal aging offset register (address 30h) bit allocation

Bits labeled as T are unused and return 0 when read.

Bit

7

T

0

6

T

0

5

T

0

4

T

0

3

2

1

0

Symbol

AO[3:0]

Reset

value

1

0

Table 20.ꢀAging_offset - crystal aging offset register (address 30h) bit description

Bits labeled as T are unused and return 0 when read.

Bit

Symbol

T

Value

Description

unused

7 to 4

3 to 0

0000

AO[3:0]

see Table 21

aging offset value

7.4.1 Crystal aging correction

The PCA2131 has an offset register Aging_offset to correct the crystal aging effects ¹.

The accuracy of the frequency of a quartz crystal depends on its aging. The aging offset

adds an adjustment, positive or negative, in the temperature compensation circuit which

allows correcting the aging effect.

The aging offset bits allow a frequency correction of typically 2 ppm per AO[3:0] value,

from -14 ppm to +16 ppm.

1 For further information, refer to the application note [1].

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Table 21.ꢀFrequency correction at 25 °C, typical

AO[3:0]

ppm

Decimal

Binary

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0

+16

+14

+12

+10

+8

+6

+4

+2

0

1

2

3

4

5

6

7

[1]

8

9

-2

10

11

12

13

14

15

-4

-6

-8

-10

-12

-14

[1] Default value.

7.5 Power management functions

The PCA2131 has two power supplies:

V_DD- the main power supply

V_BAT- the battery backup supply

Internally, PCA2131 operates with the internal operating voltage V_oper(int)which is also

available as V_BBSon the battery backed output voltage pin, BBS. Depending on the

condition of the main power supply and the selected power management function,

V_oper(int)is either on the potential of V_DDor V_BAT

.

Two power management functions are implemented:

Battery switch-over function - monitors the main power supply V_DDand switching to

V_BATin case a power fail condition is detected (see Section 7.5.1).

Battery low detection function - monitors the status of the battery, V_BAT(see

Section 7.5.2).

The power management functions are controlled by the control bits PWRMNG[2:0] (see

Table 22) in register Control_3 (see Table 10):

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Table 22.ꢀPower management control bit description

PWRMNG[2:0]

Function

000

battery switch-over function is enabled in standard mode;

battery low detection function is enabled

001,010

011

battery switch-over function is enabled in standard mode;

battery low detection function is disabled

battery switch-over function is enabled in direct switching mode;

battery low detection function is enabled

100,101

110,111

battery switch-over function is enabled in direct switching mode;

battery low detection function is disabled

[1] [2]

battery switch-over function is disabled, only one power supply

(V_DD);

battery low detection function is disabled

[1] Default value.

[2] When the battery switch-over function is disabled, the device works only with the power supply V_DD. V_BATmust be put to

ground and the battery low detection function is disabled.

7.5.1 Battery switch-over function

PCA2131 has a backup battery switch-over circuit which monitors the main power supply

V_DD. When a power failure condition is detected, it automatically switches to the backup

battery.

One of two operation modes can be selected:

Standard mode - the power failure condition happens when:

V_DD< V_BATAND V_DD< V_th(sw)bat

V_th(sw)batis the battery switch threshold voltage. Typical value is 2.5 V. The battery

switch-over in standard mode works only for V_DD> 2.5 V. Applying back-up battery

voltage to V_BATwithout applying V_DDsupply will not power on the device; only when V_DD

main power is supplied the device will start operating.

Direct switching mode - the power failure condition happens when V_DD< V_BAT. Direct

switching from V_DDto V_BATwithout requiring V_DDto drop below V_th(sw)bat

When a power failure condition occurs and the power supply switches to the battery, the

following sequence occurs:

1. The battery switch flag BF (register Control_3) is set to logic 1.

2. An interrupt is generated if the control bit BIE (register Control_3) is enabled (see

Section 7.13.6).

3. If the control bit BTSE (register Control_3) is logic 1, the timestamp 4 registers store

the time and date when the battery switch occurred (see Section 7.12.4).

4. The battery switch flag BF is cleared by command; it must be cleared to clear the

interrupt.

The interface and CLKOUT output are disabled in battery backup operation:

• Interface inputs are not recognized, preventing extraneous data being written to the

device

• Interface outputs are high-impedance

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For further information about I²C-bus communication and battery backup operation, see

Section 7.16.3.

7.5.1.1 Standard mode

If V_DD> V_BATOR V_DD> V_th(sw)bat: V_oper(int)is at V_DDpotential.

If V_DD< V_BATAND V_DD< V_th(sw)bat: V_oper(int)is at V_BATpotential.

backup battery operation

V

DD

V

oper(int)

V

BAT

internal operating voltage (V

)

oper(int)

V

th(sw)bat

(= 2.5 V)

V

DD

(= 0 V)

BF

INT

cleared via interface

001aaj311

V_th(sw)batis the battery switch threshold voltage. Typical value is 2.5 V. In standard mode, the

battery switch-over works only for V_DD> 2.5 V.

V_DDmay be lower than V_BAT(for example V_DD= 3 V, V_BAT= 4.1 V).

Figure 4.ꢀBattery switch-over behavior in standard mode with bit BIE set logic 1 (enabled)

7.5.1.2 Direct switching mode

If V_DD> V_BAT: V_oper(int)is at V_DDpotential.

If V_DD< V_BAT: V_oper(int)is at V_BATpotential.

The direct switching mode is useful in systems where V_DDis always higher than V_BAT

.

This mode is not recommended if the V_DDand V_BATvalues are similar (for example,

V_DD= 3.3 V, V_BAT≥ 3.0 V). In direct switching mode, the power consumption is reduced

compared to the standard mode because the monitoring of V_DDand V_th(sw)batis not

performed.

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backup battery operation

V

DD

V

oper(int)

V

BAT

internal operating voltage (V

)

oper(int)

V

th(sw)bat

(= 2.5 V)

V

DD

(= 0 V)

BF

INT

cleared via interface

001aaj312

Figure 5.ꢀBattery switch-over behavior in direct switching mode with bit BIE set logic 1

(enabled)

7.5.1.3 Battery switch-over disabled: only one power supply (V_DD

)

When the battery switch-over function is disabled:

• The power supply is applied on the V_DDpin

• The V_BATpin must be connected to ground

• V_oper(int)is at V_DDpotential

• The battery flag (BF) is always logic 0

7.5.1.4 Battery switch-over architecture

The architecture of the battery switch-over circuit is shown in Figure 6.

comparators

logic

switches

V

DD

V

th(sw)bat

V

DD

V

LOGIC

oper(int)

V

th(sw)bat

V

BAT

V

BAT

001aag061

Figure 6.ꢀBattery switch-over circuit, simplified block diagram

V_oper(int)is at V_DDor V_BATpotential.

Remark: It has to be assured that there are decoupling capacitors on the pins V_DD, V_BAT

,

and BBS.

7.5.2 Battery low detection function

The PCA2131 has a battery low detection circuit which monitors the status of the battery

V_BAT

.

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When V_BATdrops below the threshold value V_th(bat)low(typical 2.5 V), the BLF flag

(register Control_3) is set to indicate that the battery is low and that it must be replaced.

Monitoring of the battery voltage also occurs during battery operation.

An unreliable battery cannot prevent the supply voltage from dropping below V_low(typical

1.2 V) and with that the data integrity gets lost. (For further information about V_lowsee

Section 7.6.)

When V_BATdrops below the threshold value V_th(bat)low, the following sequence occurs

(see Figure 7):

1. The battery low flag BLF is set logic 1.

2. An interrupt is generated if the control bit BLIE (register Control_3) is enabled (see

Section 7.13.7).

3. The flag BLF remains logic 1 until the battery is replaced. BLF cannot be cleared by

command. It is automatically cleared by the battery low detection circuit when the

battery is replaced or when the voltage rises again above the threshold value. This

could happen if a super capacitor is used as a backup source and the main power is

applied again.

V

DD

= V

oper(int)

internal operating voltage (V

)

oper(int)

V

BAT

V

th(bat)low

(= 2.5 V)

V

BAT

BLF

INT

001aaj322

Figure 7.ꢀBattery low detection behavior with bit BLIE set logic 1 (enabled)

7.5.3 Battery backup supply

The V_BBSvoltage on the output pin BBS is at the same potential as the internal operating

voltage V_oper(int), depending on the selected battery switch-over function mode:

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Table 23.ꢀOutput pin BBS

Battery switch-over function Conditions

mode

Potential of

V_oper(int)and

V_BBS

standard

V_DD> V_BATOR V_DD> V_th(sw)bat

V_DD

V_BAT

V_DD

V_BAT

V_DD

V_DD< V_BATAND V_DD< V_th(sw)bat

V_DD> V_BAT

direct switching

disabled

V_DD< V_BAT

only V_DDavailable,

V_BATmust be put to ground

The output pin BBS can be used as a supply for external devices with battery backup

needs, such as SRAM (see [1]).

7.6 Oscillator stop detection function

The PCA2131 has an on-chip oscillator detection circuit which indicates the status of

the oscillation by monitoring the supply of oscillator: whenever the supply is out of the

expected range, a reset occurs and the oscillator stop flag OSF (in register Seconds) is

set logic 1.

• Power-on:

1. The oscillator is not running, the chip is in reset (OSF is logic 1).

2. When the oscillator starts running and supply is OK after power-on, the chip exits

from reset.

3. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command.

• Power supply failure:

1. When the power supply of the chip drops below a certain value (V_low), typically

1.2 V, the oscillator supply also fails and a reset occurs.

2. When the power supply returns to normal operation, the oscillator supply is OK

again, the chip exits from reset.

3. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command.

4. When OSF flag is cleared an OTP refresh should be performed (see Section 7.3.2).

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V

DD

V

DD

V

oper(int)

V

BAT

V

BAT

V

DD

V

th(sw)bat

(= 2.5 V)

V

DD

battery discharge

V

low

(= 1.2 V)

V

oper(int)

V

BAT

V

SS

V

SS

(1)

(2)

OSF

001aaj409

1. Theoretical state of the signals since there is no power.

2. The oscillator stop flag (OSF), set logic 1, indicates that the oscillation has stopped and a

reset has occurred since the flag was last cleared (OSF set logic 0). In this case, the integrity

of the clock information is not guaranteed. The OSF flag is cleared by command.

Figure 8.ꢀPower failure event due to battery discharge: reset occurs

7.7 Power-On Reset function

The PCA2131 has a Power-On Reset (POR) and a Power-On Reset Override (PORO)

function implemented.

7.7.1 Power-On Reset (POR)

The POR is active whenever the oscillator is stopped. The oscillator is considered to be

stopped during the time between power-on and stable crystal resonance (see Figure 9).

This time may be in the range of 200 ms to 2 s depending on temperature and supply

voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set logic

1).

The OTP refresh (see Section 7.3.2) should ideally be executed as the first instruction

after start-up and also after a reset due to an oscillator stop.

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chip in reset

chip not in reset

chip fully operative

CLKOUT

available

V

DD

oscillation

internal

reset

OTPR

t

aaa-015298

Figure 9.ꢀDependency between POR and oscillator

After POR, the following mode is entered:

• 32.768 kHz CLKOUT active

• Power-On Reset Override (PORO) available to be set

• 24-hour mode is selected

• Battery switch-over function disabled, only one power supply (V_DD

• Temperature compensation enabled

• 100th second enabled

)

• Time 00:00:00.00

• Date 2001.01.01

• Weekday Monday

The register values after power-on are shown in Table 4.

7.7.2 Power-On Reset Override (PORO)

The POR duration is directly related to the crystal oscillator start-up time. Due to the long

start-up times experienced by these types of circuits, a mechanism has been built in to

disable the POR and therefore speed up the on-board test of the device.

osc stopped

OSCILLATOR

0 = stopped, 1 = running

reset

SCL

RESET

OVERRIDE

0 = override inactive

1 = override active

SDA/CE

CLEAR

0 = clear override mode

1 = override possible

POR_OVRD

001aaj324

Figure 10.ꢀPower-On Reset (POR) system

The setting of the PORO mode requires that POR_OVRD in register Control_1 is

set logic 1 and that the signals at the interface pins SDA/CE and SCL are toggled as

illustrated in Figure 11. All timings shown are required minimum.

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power up

8 ms

minimum 500 ns

minimum 2000 ns

SDA/CE

SCL

reset override

001aaj326

Figure 11.ꢀPower-On Reset Override (PORO) sequence, valid for both I²C-bus and SPI-bus

Once the override mode is entered, the device is immediately released from the reset

state and the set-up operation can commence.

The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be logic

1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0 during

normal operation has no effect except to prevent accidental entry into the PORO mode.

7.8 Software Reset register

Table 24.ꢀReset - software reset control (address 05h) bit description

Bit

7

6

5

4

3

SR

2

1

0

Symbol

Section

CPR

0

1

0

1

0

CTS

Section 7.8.2

Section 7.8.1

Section 7.8.3

To

• trigger a software reset (SR), 0010ꢀ1100 (2Ch) must be sent to register Reset (address

05h). A software reset also triggers CPR and CTS

• clear prescaler (CPR), 1010ꢀ0100 (A4h) must be sent to register Reset (address 05h)

• clear timestamp (CTS), 0010ꢀ0101 (25h) must be sent to register Reset (address 05h)

It is possible to combine CPR and CTS by sending 1010ꢀ0101 (A5h).

Read of the SR_RESET register will return a fixed pattern of 00100100;

Remark: Any other value sent to this register is ignored.

7.8.1 SR - Software reset

A reset is automatically generated at power-on as Power-On Reset as described in

Section 7.7. A reset can also be initiated with the software reset command.

After software reset, the following mode is entered:

• 32.768 kHz CLKOUT active

• Power-On Reset Override (PORO) unchanged

• OTP not reloaded, OTPR unchanged.

• 24-hour mode is selected

• Battery switch-over function disabled, only one power supply (V_DD

• Temperature compensation enabled

• 100th second enabled

)

• Time 00:00:00.00

• Date 2001.01.01

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• Weekday Monday

slave address

address 05h

software reset 2Ch

R/W

0

s

1

0

1

0

1

A

0

1

0

1

A

0

1

0

1

0

A P/S

SDA

SCL

internal

reset signal

aaa-042191

Figure 12.ꢀSoftware reset command

7.8.2 CPR: clear prescaler

To set the time for RTC mode, the clear prescaler instruction is needed.

Before sending this instruction, it is mandatory to first set stop by the STOP bit.

See STOP definition for an explanation on using this instruction.

7.8.3 CTS: clear timestamp

The timestamp registers (address 14h to 2Fh) can be set to all 0 with this instruction.

7.9 Time and date function

Most of these registers are coded in the Binary Coded Decimal (BCD) format.

7.9.1 Register 100th Seconds

Table 25.ꢀ100th Seconds - 100th seconds (address 06h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

100TH SECONDS (0 to 99)

Reset

value

0

Table 26.ꢀ100th Seconds - 100th seconds register (address 06h) bit description

Bit

Symbol

Value

0 to 9

Place value Description

7 to 4

3 to 0

100TH SECONDS

ten’s place actual seconds coded in BCD format

unit place

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Table 27.ꢀ100th Seconds coded in BCD format

Seconds Upper-digit (ten’s place)

value in

decimal

Digit (unit place)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00

01

02

:

0

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

1

0

:

09

10

:

0

:

0

:

0

:

0

1

:

1

0

:

0

:

0

:

1

0

:

98

99

1

0

1

0

1

7.9.2 Register Seconds

Table 28.ꢀSeconds - seconds and clock integrity register (address 07h) bit allocation

Bit

7

OSF

1

6

5

4

3

2

1

0

Symbol

SECONDS (0 to 59)

0

Reset

value

0

Table 29.ꢀSeconds - seconds and clock integrity register (address 07h) bit description

Bit

Symbol

Value

Place value Description

7

OSF

0

1

-

clock integrity is guaranteed

clock integrity is not guaranteed:

oscillator has stopped and chip reset has

occurred since flag was last cleared

6 to 4

3 to 0

SECONDS

0 to 5

0 to 9

ten’s place actual seconds coded in BCD format

unit place

Table 30.ꢀSeconds coded in BCD format

Seconds Upper-digit (ten’s place)

value in

decimal

Digit (unit place)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00

01

02

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

1

0

:

09

10

0

1

0

1

0

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Table 30.ꢀSeconds coded in BCD format...continued

Seconds Upper-digit (ten’s place)

value in

decimal

Digit (unit place)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

:

58

59

1

0

1

0

1

7.9.3 Register Minutes

Table 31.ꢀMinutes - minutes register (address 08h) bit allocation

Bits labeled as T are unused and return 0 when read

Bit

7

T

0

6

5

4

3

2

1

0

Symbol

MINUTES (0 to 59)

0

Reset

value

0

Table 32.ꢀMinutes - minutes register (address 08h) bit description

Bits labeled as T are unused and return 0 when read

Bit

Symbol

T

Value

0

Place value Description

- unused

7

6 to 4

3 to 0

MINUTES

0 to 5

0 to 9

ten’s place actual minutes coded in BCD format

unit place

7.9.4 Register Hours

Table 33.ꢀHours - hours register (address 09h) bit allocation

Bits labeled as T are unused and return 0 when read

Bit

7

6

5

4

3

2

1

0

Symbol

T

AMPM

HOURS (1 to 12) in 12-hour mode

HOURS (0 0to 23) in 24-hour mode

Reset

value

0

Table 34.ꢀHours - hours register (address 09h) bit description

Bits labeled as T are unused and return 0 when read

Bit

Symbol

Value

Place value Description

7 to 6

T

00

-

unused

12-hour mode^[1]

5

AMPM

0

1

-

indicates AM

indicates PM

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Table 34.ꢀHours - hours register (address 09h) bit description...continued

Bits labeled as T are unused and return 0 when read

Bit

4

Symbol

Value

0 to 1

0 to 9

Place value Description

HOURS

ten’s place actual hours coded in BCD format when in 12-hour

mode

3 to 0

unit place

24-hour mode^[1]

5 to 4

3 to 0

HOURS

0 to 2

0 to 9

ten’s place actual hours coded in BCD format when in 24-hour

mode

unit place

[1] Hour mode is set by the bit 12_24 in register Control_1 (see Table 6).

7.9.5 Register Days

Table 35.ꢀDays - days register (address 0Ah) bit allocation

Bits labeled as T are unused and return 0 when read

Bit

7

T

0

6

T

0

5

4

3

2

1

0

Symbol

DAYS (1 to 31)

Reset

value

0

Table 36.ꢀDays - days register (address 0Ah) bit description

Bit

Symbol

Value

00

Place value Description

- unused

7 to 6

5 to 4

3 to 0

T

DAYS^[1]

0 to 3

0 to 9

ten’s place actual day coded in BCD format

unit place

[1] If the year counter contains a value which is exactly divisible by 4, excluding the year 00, the RTC compensates for leap years by adding a 29^thday to

February. Note that next time the year will roll over to 00 will be year 2100, which is not going to be leap year.

7.9.6 Register Weekdays

Table 37.ꢀWeekdays - weekdays register (address 0Bh) bit allocation

Bits labeled as T are unused and return 0 when read

Bit

7

T

0

6

T

0

5

T

0

4

T

0

3

T

0

2

1

0

Symbol

WEEKDAYS (0 to 6)

0

Reset

value

0

1

Table 38.ꢀWeekdays - weekdays register (address 0Bh) bit description

Bits labeled as T are unused and return 0 when read

Bit

Symbol

T

Value

000

Description

7 to 3

2 to 0

unused

WEEKDAYS

0 to 6

actual weekday value, see Table 39

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Although the association of the weekdays counter to the actual weekday is arbitrary, the

PCA2131 assumes that Sunday is 000 and Monday is 001 for the purpose of determining

the increment for calendar weeks.

Table 39.ꢀWeekday assignments

Day^[1]

Bit

2

1

0

1

0

1

0

1

0

1

0

1

0

Sunday

0

Monday

Tuesday

Wednesday

Thursday

Friday

0

1

Saturday

1

[1] Definition may be reassigned by the user.

7.9.7 Register Months

Table 40.ꢀMonths - months register (address 0Ch) bit allocation

Bits labeled as T are unused and return 0 when read

Bit

7

T

0

6

T

0

5

T

0

4

3

2

1

0

Symbol

MONTHS (1 to 12)

0

Reset

value

0

1

Table 41.ꢀMonths - months register (address 0Ch) bit description

Bits labeled as T are unused and return 0 when read

Bit

Symbol

T

Value

000

Place value Description

- unused

7 to 5

4

MONTHS

0 to 1

0 to 9

ten’s place actual month coded in BCD format, see Table 42

unit place

3 to 0

Table 42.ꢀMonth assignments in BCD format

Month

Upper-digit

(ten’s place)

Digit (unit place)

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

January

February

March

0

1

0

1

0

1

0

1

0

April

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Table 42.ꢀMonth assignments in BCD format...continued

Month

Upper-digit

(ten’s place)

Digit (unit place)

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

May

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

June

July

August

September

October

November

December

7.9.8 Register Years

Table 43.ꢀYears - years register (address 0Dh) bit allocation

Bits labeled as T are unused and return 0 when read

Bit

7

6

5

4

3

2

1

0

Symbol

YEARS (0 to 99)

Reset

value

0

1

Table 44.ꢀYears - years register (address 0Dh) bit description

Bits labeled as T are unused and return 0 when read

Bit

Symbol

Value

0 to 9

Place value Description

7 to 4

3 to 0

YEARS

ten’s place actual year coded in BCD format

unit place

7.9.9 Setting and reading the time

Figure 13 shows the data flow and data dependencies starting from the 100 Hz/1 Hz

clock tick.

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100 Hz tick

100TH_SECOND

1 Hz tick

100TH

SECONDS

MINUTES

12_24

HOURS

DAYS

LEAP YEAR

CALCULATION

WEEKDAY

MONTHS

YEARS

aaa-009580

Figure 13.ꢀData flow for the time function

Write access requires setting the STOP bit. The flow for accurately setting the time in

RTC mode is:

• start an I2C access at register control_1

• set STOP bit

• set CPR (register SR_RESET, CPR is logic 1)

• address counter rolls over to address 06h

• set time (100th seconds, seconds to years)

• end I2C access

• wait for external time reference to indicate that time counting should start

• start an I2C access at register control_1

• clear STOP bit (time starts counting from now)

• end I2C access

The first increment of the time circuits is between 0 s and 122 ms after STOP is released.

See description for STOP bit in Section 7.15

During read operations, the time counting circuits (memory locations 06h through 0Dh)

are blocked. This prevents

• Faulty reading of the clock and calendar during a carry condition

• Incrementing the time registers during the read cycle

After this read access is completed, the time circuit is released again. Any pending

request to increment the time counters that occurred during the read access is serviced.

As a consequence of this method, it is very important to make a read access in one go.

That is, reading seconds through to years should be made in one single access. Failing

to comply with this method could result in the time becoming corrupted.

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As an example, a roll-over may occur between reads thus giving the minutes from one

moment and the hours from the next. Therefore it is advised to read all time and date

registers in one access.

7.10 Alarm function

When one or more of the alarm bit fields are loaded with a valid second, minute, hour,

day, or weekday and its corresponding alarm enable bit (AE_x) is logic 0, then that

information is compared with the actual second, minute, hour, day, and weekday (see

Figure 14).

example

check now signal

AE_S

AE_S = 1

SECOND ALARM

=

1

0

SECOND TIME

AE_M

AE_H

AE_D

AE_W

MINUTE ALARM

MINUTE TIME

=

HOUR ALARM

HOUR TIME

(1)

set alarm flag AF

DAY ALARM

DAY TIME

WEEKDAY ALARM

WEEKDAY TIME

013aaa236

1. Only when all enabled alarm settings are matching.

Figure 14.ꢀAlarm function block diagram

The generation of interrupts from the alarm function is described in Section 7.13.4.

7.10.1 Register Second_alarm

Table 45.ꢀSecond_alarm - second alarm register (address 0Eh) bit allocation

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

7

AE_S

1

6

5

4

3

2

1

0

Symbol

SECOND_ALARM (0 to 59)

Reset

value

0

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Table 46.ꢀSecond_alarm - second alarm register (address 0Eh) bit description

Bit

Symbol

Value

0

Place value Description

7

AE_S

-

second alarm is enabled

second alarm is disabled

1

6 to 4

3 to 0

SECOND_ALARM

0 to 5

0 to 9

ten’s place second alarm information coded in BCD format

unit place

7.10.2 Register Minute_alarm

Table 47.ꢀMinute_alarm - minute alarm register (address 0Fh) bit allocation

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

7

AE_M

1

6

5

4

3

2

1

0

Symbol

MINUTE_ALARM (0 to 59)

Reset

value

0

Table 48.ꢀMinute_alarm - minute alarm register (address 0Fh) bit description

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

Symbol

Value

0

Place value Description

7

AE_M

-

minute alarm is enabled

minute alarm is disabled

1

6 to 4

3 to 0

MINUTE_ALARM

0 to 5

0 to 9

ten’s place minute alarm information coded in BCD format

unit place

7.10.3 Register Hour_alarm

Table 49.ꢀHour_alarm - hour alarm register (address 10h) bit allocation

Bits labeled as T are unused and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by

subsequent resets.

Bit

7

6

5

4

3

2

1

0

Symbol

AE_H

T

AMPM

HOUR_ALARM (1 to 12) in 12-hour mode

HOUR_ALARM (0 to 23) in 24-hour mode

Reset

value

1

0

Table 50.ꢀHour_alarm - hour alarm register (address 10h) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

Value

Place value Description

7

AE_H

0

1

-

hour alarm is enabled

hour alarm is disabled

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Table 50.ꢀHour_alarm - hour alarm register (address 10h) bit description...continued

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

Value

Place value Description

6

T

0

-

unused

12-hour mode^[1]

5

AMPM

0

-

indicates AM

indicates PM

1

4

HOUR_ALARM

0 to 1

0 to 9

ten’s place hour alarm information coded in BCD format when in

12-hour mode

3 to 0

unit place

24-hour mode^[1]

5 to 4

3 to 0

HOUR_ALARM

0 to 2

0 to 9

ten’s place hour alarm information coded in BCD format when in

24-hour mode

unit place

[1] Hour mode is set by the bit 12_24 in register Control_1.

7.10.4 Register Day_alarm

Table 51.ꢀDay_alarm - day alarm register (address 11h) bit allocation

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

7

AE_D

1

6

T

0

5

4

3

2

1

0

Symbol

DAY_ALARM (1 to 31)

Reset

value

0

Table 52.ꢀDay_alarm - day alarm register (address 11h) bit description

Bits labeled as T are unused and return 0 when readBits labeled as X are undefined at power-on and unchanged by

subsequent resets.

Bit

Symbol

Value

0

Place value Description

7

AE_D

-

day alarm is enabled

1

day alarm is disabled

unused

6

T

0

5 to 4

3 to 0

DAY_ALARM

0 to 3

0 to 9

ten’s place day alarm information coded in BCD format

unit place

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7.10.5 Register Weekday_alarm

Table 53.ꢀWeekday_alarm - weekday alarm register (address 12h) bit allocation

Bits labeled as T are unused and return 0 when read.Bits labeled as X are undefined at power-on and unchanged by

subsequent resets.

Bit

7

AE_W

1

6

T

0

5

T

0

4

T

0

3

T

0

2

1

0

Symbol

WEEKDAY_ALARM (0 to 6)

Reset

value

0

Table 54.ꢀWeekday_alarm - weekday alarm register (address 12h) bit description

Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and

unchanged by subsequent resets.

Bit

Symbol

Value

Description

7

AE_W

0

weekday alarm is enabled

weekday alarm is disabled

unused

1

6 to 3

2 to 0

T

0

WEEKDAY_ALARM

0 to 6

weekday alarm information

7.10.6 Alarm flag

When all enabled comparisons first match, the alarm flag AF (register Control_2) is set.

AF remains set until cleared by command. Once AF has been cleared, it will only be set

again when the time increments to match the alarm condition once more. For clearing the

flags, see Section 7.11.5

Alarm registers which have their alarm enable bit AE_x at logic 1 are ignored.

minutes counter

minute alarm

AF

44

45

46

INT when AIE = 1

001aaf903

Example where only the minute alarm is used and no other interrupts are enabled.

Figure 15.ꢀAlarm flag timing diagram

7.11 Watchdog timer functions

The PCA2131 has a watchdog timer function. The timer can be switched on and off by

using the control bit WD_CD in the register Watchdg_tim_ctl.

The watchdog timer has four selectable source clocks. It can, for example, be used to

detect a micro-controller with interrupt and reset capability which is out of control (see

Section 7.11.3)

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To control the timer function and timer output, the registers Control_2, Watchdg_tim_ctl,

and Watchdg_tim_val are used.

7.11.1 Register Watchdg_tim_ctl

Table 55.ꢀWatchdg_tim_ctl - watchdog timer control register (address 35h) bit allocation

Bits labeled as T are unused and return 0 when read.

Bit

7

WD_CD

0

6

T

0

5

TI_TP

0

4

T

0

3

T

0

2

T

0

1

0

Symbol

TF[1:0]

Reset

value

1

Table 56.ꢀWatchdg_tim_ctl - watchdog timer control register (address 35h) bit description

Bits labeled as T are unused and return 0 when read.

Bit

Symbol

Value

Description

7

WD_CD

0

1

watchdog timer interrupt disabled

watchdog timer interrupt enabled;

the interrupt pin INTA/B is activated when timed

out

6

5

T

0

unused

TI_TP

the interrupt pin INTA/B is configured to generate a

permanent active signal when MSF is set

1

the interrupt pin INTA/B is configured to generate a

pulsed signal when MSF flag is set (see Figure 17)

4 to 2

1 to 0

T

000

unused

TF[1:0]

timer source clock for watchdog timer

00

01

10

11

64 Hz

4 Hz

¹⁄₄Hz

1

⁄₆₄Hz

7.11.2 Register Watchdg_tim_val

Table 57.ꢀWatchdg_tim_val - watchdog timer value register (address 36h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

WATCHDG_TIM_VAL[7:0]

Reset

value

0

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Table 58.ꢀWatchdg_tim_val - watchdog timer value register (address 36h) bit description

Bits labeled as X are undefined at power-on and unchanged by subsequent resets.

Bit

Symbol

Value

Description

7 to 0

WATCHDG_TIM_

VAL[7:0]

00 to FF

timer period in seconds:

where n is the timer value (n > 1)

Write Only

Table 59.ꢀProgrammable watchdog timer

TF[1:0] Timer source

clock frequency

Units

Minimum timer

period (n = 2)

Units

Maximum timer

period (n = 255)

Units

00

01

10

11

64

Hz

15.625

250

4

ms

s

3.984

s

4

63.744

1

⁄

4

1020

1

⁄

64

s

16320

64

7.11.3 Watchdog timer function

The watchdog timer interrupt function is enabled or disabled by the WD_CD bit of the

register Watchdg_tim_ctl (see Table 56).

The 2 bits TF[1:0] in register Watchdg_tim_ctl determine one of the four source clock

frequencies for the watchdog timer: 64 Hz, 4 Hz, ¹⁄₄Hz or ¹⁄₆₄Hz (see Table 59).

When the watchdog timer function is enabled, the 8-bit timer in register Watchdg_tim_val

determines the watchdog timer period (see Table 59).

The watchdog timer counts down from the software programmed 8-bit binary value n in

register Watchdg_tim_val. When the counter reaches 1, the watchdog timer flag WDTF

(register Control_2) is set logic 1 and an interrupt is generated. The period accuracy

corresponds to n +/- 0.5.

The register Watchdg_tim_val is write only and not readable after set.

The counter does not automatically reload.

When WD_CD is logic 1/0 (watchdog timer interrupt enabled/disabled) and the Micro-

controller Unit (MCU) loads a watchdog timer value n:

• the flag WDTF is reset

• INTA/B is cleared

• the watchdog timer starts again

Loading the counter with 0 or 1 will:

• reset the flag WDTF

• clear INTA/B

• stop the watchdog timer

Remark: WDTF can be cleared by:

• loading a value in register Watchdg_tim_val

• writing a logic 0 to WDTF

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Writing a logic 1 to WDTF has no effect.

MCU

watchdog

timer value

n = 1

n

WDTF

INT

001aag062

Counter reached 1, WDTF is logic 1, and an interrupt is generated.

Figure 16.ꢀWD_CD set logic 1: watchdog activates an interrupt when timed out

• When the watchdog timer counter reaches 1, the watchdog timer flag WDTF is set logic

1

• When a minute or second interrupt occurs, the minute/second flag MSF is set logic 1

(see Section 7.13.1).

7.11.4 Pre-defined timers: second and minute interrupt

PCA2131 has two pre-defined timers which are used to generate an interrupt either

once per second or once per minute (see Section 7.13.1). The pulse generator for the

minute or second interrupt operates from an internal 64 Hz clock. It is independent of the

watchdog timer. Each of these timers can be enabled by the bits SI (second interrupt)

and MI (minute interrupt) in register Control_1.

7.11.5 Clearing flags

The flags MSF and AF can be cleared by command. To prevent one flag being

overwritten while clearing another, a logic AND is performed during the write access. A

flag is cleared by writing logic 0 while a flag is not cleared by writing logic 1. Writing logic

1 results in the flag value remaining unchanged.

Two examples are given for clearing the flags. Clearing a flag is made by a write

command:

• Bits labeled with - must be written with their previous values

• Bits labeled with T have to be written with logic 0

• WDTF is read only and has to be written with logic 0

Repeatedly rewriting these bits has no influence on the functional behavior.

Table 60.ꢀFlag location in register Control_2

Register

Bit

7

6

5

4

3

2

1

0

Control_2

MSF

WDTF

T

AF

T

-

T

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Table 61.ꢀExample values in register Control_2

Register

Bit

7

6

5

4

3

2

1

0

Control_2

1

0

1

0

The following tables show what instruction must be sent to clear the appropriate flag.

Table 62.ꢀExample to clear only AF (bit 4)

Register

Bit

7

6

5

4

3

2

1

0

Control_2

1

0

1

0

0^[1]

0

[1] The bits labeled as - have to be rewritten with the previous values.

Table 63.ꢀExample to clear only MSF (bit 7)

Register

Bit

7

6

5

4

3

2

1

0

Control_2

0

1

0

0^[1]

0

[1] The bits labeled as - have to be rewritten with the previous values.

7.12 Timestamp function

The PCA2131 has four active LOW timestamp input pins TS1, TS2, TS3 and TS4,

internally pulled with on-chip pull-up resistors to V_oper(int). It also has a timestamp

detection circuit which can detect the event when inputs on pin TS1/2/3/4 are driven to

ground.

The timestamp function is enabled by default after power-on and it can be switched off by

setting the control bit TSOFF (register Timestp_ctl1/2/3/4).

The time recorded in the time stamps, when in 100 Hz disable mode (1 Hz mode), will be

at least two 16 Hz clocks behind the timestamp event and no more than 3 clocks behind.

If the exact time of the timestamp event is required then subtract 2 subseconds from the

timestamp value and the result will have -0 subseconds to +1 subseconds of uncertainty.

A most common application of the timestamp function is described in [1].

See Section 7.13.5 for a description of interrupt generation from the timestamp function.

7.12.1 Timestamp flag

1. When the TS1/2/3/4 input pin are driven to ground, the following sequence occurs:

a. The actual date and time are stored in the timestamp registers.

b. The timestamp flag TSF1/2/3/4 flag is set.

c. If the TSIE1/2/3/4 bit is active, and corresponding interrupt mask is disabled, an

interrupt on the INTA/B pin is generated.

The TSF1/2/3/4 and TSF1/2/3/4_2 flags can be cleared by command; clearing the flag

clears the interrupt. Once TSF1/2/3/4 is cleared, it will only be set again when TS1/2/3/4

pin is driven to ground once again.

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7.12.2 Timestamp mode

The timestamp function has two different modes selected by the control bit TSM

(timestamp mode) in register Timestp_ctl:

• If TSM is logic 0 (default): in subsequent trigger events without clearing the timestamp

flags, the last timestamp event is stored

• If TSM is logic 1: in subsequent trigger events without clearing the timestamp flags, the

first timestamp event is stored

The timestamp function also depends on the control bit BTSE in register Control_3, see

Section 7.12.4.

7.12.3 Timestamp registers

7.12.3.1 Register Timestp_ctl1/2/3/4

Table 64.ꢀTimestp_ctl1/2/3/4 - timestamp control register (address 14h/1Bh/22h/29h) bit allocation

Bits labeled as T are unused and return 0 when read

Bit

7

TSM

0

6

TSOFF

0

5

T

0

4

3

2

1

0

Symbol

SUBSEC_TIMESTP[4:0]

0

Reset

value

0

Table 65.ꢀTimestp_ctl1/2/3/4 - timestamp control register (address 14h/1Bh/22h/29h) bit description

Bits labeled as T are unused and return 0 when read

Bit

Symbol

Value

Description

7

TSM

0

in subsequent events without clearing the timestamp

flags, the last event is stored

1

in subsequent events without clearing the timestamp

flags, the first event is stored

6

TSOFF

0

1

-

timestamp function active

timestamp function disabled

5

-

unused

1

4 to 0

SUBSEC_TIMESTP[4:0]

⁄₁₆second timestamp information coded in BCD

format when 100TH_S_DIS = ‘1’^[1], ¹⁄₂₀second

timestamp information coded in BCD format when

100TH_S_DIS = ‘0’;

[1] The time recorded in the time stamps, when in 100 Hz disable mode (1 Hz mode), will be at least two 16 Hz clocks behind the timestamp event and no

more than 3 clocks behind. If the exact time of the timestamp event is required then subtract 2 subseconds from the timestamp value and the result will

have -0 subseconds to +1 subseconds of uncertainty.

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7.12.3.2 Register Sec_timestp

Table 66.ꢀSec_timestp1/2/3/4 - second timestamp register (address 15h/1Ch/23h/2Ah) bit allocation

Bits labeled as T are unused and return 0 when read

Bit

7

T

0

6

5

4

3

2

1

0

Symbol

SECOND_TIMESTP (0 to 59)

Reset

value

0

Table 67.ꢀSec_timestp1/2/3/4 - second timestamp register (address 15h/1Ch/23h/2Ah) bit description

Bits labeled as T are unused and return 0 when read

Bit

Symbol

Value

0

Place value Description

- unused

7

T

6 to 4

3 to 0

SECOND_TIMESTP

0 to 5

0 to 9

ten’s place second timestamp information coded in BCD format

unit place

7.12.3.3 Register Min_timestp

Table 68.ꢀMin_timestp1/2/3/4 - minute timestamp register (address 16h/1Dh/24h/2Bh) bit allocation

Bits labeled as T are unused and return 0 when read.

Bit

7

T

0

6

5

4

3

2

1

0

Symbol

MINUTE_TIMESTP (0 to 59)

Reset

value

0

Table 69.ꢀMin_timestp1/2/3/4 - minute timestamp register (address 16h/1Dh/24h/2Bh) bit description

Bits labeled as T are unused and return 0 when read.

Bit

Symbol

Value

0

Place value Description

- unused

7

T

6 to 4

3 to 0

MINUTE_TIMESTP

0 to 5

0 to 9

ten’s place minute timestamp information coded in BCD format

unit place

7.12.3.4 Register Hour_timestp

Table 70.ꢀHour_timestp1/2/3/4 - hour timestamp register (address 17h/1Eh/25h/2Ch) bit allocation

Bits labeled as T are unused and return 0 when read.

Bit

7

6

5

4

3

2

1

0

Symbol

T

AMPM

HOUR_TIMESTP (1 to 12) in 12-hour mode

HOUR_TIMESTP (0 to 23) in 24-hour mode

Reset

value

0

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Table 71.ꢀHour_timestp1/2/3/4 - hour timestamp register (address 17h/1Eh/25h/2Ch) bit description

Bits labeled as T are unused and return 0 when read.

Bit

Symbol

Value

Place value Description

7 to 6

-

unused

12-hour mode^[1]

5

AMPM

0

-

indicates AM

indicates PM

1

4

HOUR_TIMESTP

0 to 1

0 to 9

ten’s place hour timestamp information coded in BCD format

when in 12-hour mode

3 to 0

unit place

24-hour mode^[1]

5 to 4

3 to 0

HOUR_TIMESTP

0 to 2

0 to 9

ten’s place hour timestamp information coded in BCD format

when in 24-hour mode

unit place

[1] Hour mode is set by the bit 12_24 in register Control_1.

7.12.3.5 Register Day_timestp

Table 72.ꢀDay_timestp1/2/3/4 - day timestamp register (address 18h/1Fh/26h/2Dh) bit allocation

Bits labeled as T are unused and return 0 when read.

Bit

7

T

0

6

T

0

5

4

3

2

1

0

Symbol

DAY_TIMESTP (1 to 31)

Reset

value

0

Table 73.ꢀDay_timestp1/2/3/4 - day timestamp register (address 18h/1Fh/26h/2Dh) bit description

Bits labeled as T are unused and return 0 when read.

Bit

Symbol

Value

00

Place value Description

- unused

7 to 6

5 to 4

3 to 0

T

DAY_TIMESTP

0 to 3

0 to 9

ten’s place day timestamp information coded in BCD format

unit place

7.12.3.6 Register Mon_timestp

Table 74.ꢀMon_timestp1/2/3/4 - month timestamp register (address 19h/20h/27h/2Eh) bit allocation

Bits labeled as T are unused and return 0 when read.

Bit

7

T

0

6

T

0

5

T

0

4

3

2

1

0

Symbol

MONTH_TIMESTP (1 to 12)

Reset

value

0

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Table 75.ꢀMon_timestp1/2/3/4 - month timestamp register (address 19h/20h/27h/2Eh) bit description

Bits labeled as T are unused and return 0 when read.

Bit

Symbol

Value

000

Place value Description

- unused

7 to 5

4

T

MONTH_TIMESTP

0 to 1

0 to 9

ten’s place month timestamp information coded in BCD format

unit place

3 to 0

7.12.3.7 Register Year_timestp

Table 76.ꢀYear_timestp1/2/3/4 - year timestamp register (address 1Ah/21h/28h/2Fh) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

YEAR_TIMESTP (0 to 99)

Reset

value

0

1

Table 77.ꢀYear_timestp1/2/3/4 - year timestamp register (address 1Ah/21h/28h/2Fh) bit description

Bit

Symbol

Value

0 to 9

Place value Description

7 to 4

3 to 0

YEAR_TIMESTP

ten’s place year timestamp information coded in BCD format

unit place

7.12.4 Dependency between Battery switch-over and timestamp

The timestamp function depends on the control bit BTSE in register Control_3:

Table 78.ꢀBattery switch-over and timestamp

BTSE

BF

Description

[1]

0

-

the battery switch-over does not affect the

timestamp registers

1

If a battery switch-over event occurs:

[1]

0

1

the timestamp 4 group registers store the

time and date when the switch-over occurs;

after this event occurred BF is set logic 1

the timestamp 4 group registers are not

modified;

in this condition subsequent battery switch-

over events or falling edges on pin TS4 are

not registered

[1] Default value.

7.13 Interrupt output, INTA/INTB

PCA2131 has two interrupt output pins INTA and INTB which are open-drain, active LOW

(requiring a pull-up resistor if used). Interrupts may be sourced from different places:

• second or minute timer

• watchdog timer

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• alarm

• timestamp1/2/3/4

• battery switch-over

• battery low detection

The control bit TI_TP (register Watchdg_tim_ctl) is used to configure whether the

interrupts generated from the second/minute timer (flag MSF in register Control_2) are

pulsed signals or a permanently active signal. All the other interrupt sources generate a

permanently active interrupt signal which follows the status of the corresponding flags.

When the interrupt sources are all disabled, INTA/B remains high-impedance.

• The flags MSF, AF, TSFx, and BF can be cleared by command.

• The flag WDTF is read only. How it can be cleared is explained in Section 7.11.5.

• The flag BLF is read only. It is cleared automatically from the battery low detection

circuit when the battery is replaced.

SI

MSF:

MINUTE

SECOND FLAG

SIA/MIA

to interface:

read MSF

SECONDS COUNTER

MINUTES COUNTER

SI/MI

0

1

MI

SIB/MIB

SET

CLEAR

PULSE

GENERATOR 1

TRIGGER

CLEAR

INTA pin

INTB pin

TI_TP

from interface:

clear MSF

WD_CDA

WDTF:

WATCHDOG

TIMER FLAG

to interface:

read WD_CD

WD_CD

WD_CDB

WATCHDOG

COUNTER

SET

CLEAR

MCU loading

watchdog counter

AIEA

to interface:

read AF

AIE

AF: ALARM

FLAG

AIEB

set alarm

flag, AF

SET

CLEAR

from interface:

clear AF

TSIE1/2/3/4A

to interface:

read TSF1/2/3/4_x

TSIE1/2/3/4

TSF1/2/3/4:

TIMESTAMP FLAGS

TSIE1/2/3/4B

set timestamp

flag, TSF1/2/3/4

SET

CLEAR

from interface:

clear TSF

BIEA

to interface:

read BF

BIE

BF: BATTERY

FLAG

BIEB

set battery

flag, BF

SET

CLEAR

from interface:

clear BF

BLIEA

to interface:

read BLF

BLIE

BLF: BATTERY

LOW FLAG

BLIEB

set battery

low flag, BLF

SET

CLEAR

from battery

low detection

circuit: clear BF

aaa-041571

When SI, MI, WD_CD, AIE, TSIE1/2/3/4, BIE, BLIE are all disabled, INTA/INTB remains high-impedance.

Figure 17.ꢀInterrupt block diagram

7.13.1 Minute and second interrupts

Minute and second interrupts are generated by predefined timers. The timers

can be enabled independently from one another by the bits MI and SI in register

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Control_1. However, a minute interrupt enabled on top of a second interrupt cannot be

distinguishable since it occurs at the same time.

The minute/second flag MSF (register Control_2) is set logic 1 when either the seconds

or the minutes counter increments according to the enabled interrupt (see Table 79). The

MSF flag can be cleared by command.

Table 79.ꢀEffect of bits MI and SI on pin INTA/B and bit MSF

MI

0

SI

0

Result on INTA/B

Result on MSF

no interrupt generated

an interrupt once per minute

MSF never set

1

0

MSF set when minutes

counter increments

0

1

an interrupt once per second

MSF set when seconds

counter increments

MSF set when seconds

counter increments

When MSF is set logic 1:

• If TI_TP is logic 1, the interrupt is generated as a pulsed signal if not masked.

• If TI_TP is logic 0, the interrupt is permanently active signal that remains until MSF is

cleared.

seconds counter

minutes counter

58

59

11

00

12

00

01

INTA/B when SI enabled

MSF when SI enabled

INTA/B when only MI enabled

MSF when only MI enabled

aaa-041610

In this example, bit TI_TP is logic 1 and the MSF flag is not cleared after an interrupt.

Figure 18.ꢀINTA/B example for SI and MI when TI_TP is logic 1

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seconds counter

minutes counter

58 59

59 00

11 12

00 01

INTA/B when SI enable

MSF when SI enable

INTA/B when only MI enabled

MSF when only MI enabled

aaa-041572

In this example, bit TI_TP is logic 0 and the MSF flag is cleared after an interrupt.

Figure 19.ꢀINTA/B example for SI and MI when TI_TP is logic 0

The pulse generator for the minute/second interrupt operates from an internal 64 Hz

clock and generates a pulse of ¹⁄₆₄seconds in duration.

7.13.2 INTA/B pulse shortening

If the MSF flag (register Control_2) is cleared before the end of the INTA/B pulse,

then the INTA/B pulse is shortened. This allows the source of a system interrupt to be

cleared immediately when it is serviced, that is, the system does not have to wait for the

completion of the pulse before continuing; see Figure 20. Instructions for clearing the bit

MSF can be found in Section 7.11.5.

seconds counter

MSF

58

59

INTA/B

(1)

SCL

8th clock

instruction

CLEAR INSTRUCTION

aaa-041573

1. Indicates normal duration of INTA/B pulse.

The timing shown for clearing bit MSF is also valid for the non-pulsed interrupt mode, that is,

when TI_TP is logic 0, where the INTA/B pulse may be shortened by setting both bits MI and SI

logic 0.

Figure 20.ꢀExample of shortening the INTA/B pulse by clearing the MSF flag

7.13.3 Watchdog timer interrupts

The generation of interrupts from the watchdog timer is controlled using the WD_CD bit

(register Watchdg_tim_ctl). The interrupt is generated as an active signal which follows

the status of the watchdog timer flag WDTF (register Control_2) if not masked. No pulse

generation is possible for watchdog timer interrupts.

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The interrupt is cleared when the flag WDTF is reset. Instructions for clearing it can be

found in Section 7.11.5.

7.13.4 Alarm interrupts

Generation of interrupts from the alarm function is controlled by the bit AIE (register

Control_2). If AIE is enabled, the INTA/B pin follows the status of bit AF (register

Control_2) if not masked. Clearing AF immediately clears INTA/B. No pulse generation is

possible for alarm interrupts.

minute counter

minute alarm

AF

44

45

INTA/B

SCL

8th clock

instruction

CLEAR INSTRUCTION

aaa-041574

Example where only the minute alarm is used and no other interrupts are enabled.

Figure 21.ꢀAF timing diagram

7.13.5 Timestamp interrupts

Interrupt generation from the timestamp function is controlled using the TSIE1-4 bit

(register Control_5). If TSIE1-4 is enabled, the INTA/B pin follows the status of the flags

TSF1/2/3/4, if not masked. Clearing the flags TSFx immediately clears INTA/B. No pulse

generation is possible for timestamp interrupts.

7.13.6 Battery switch-over interrupts

Generation of interrupts from the battery switch-over is controlled by the BIE bit (register

Control_3). If BIE is enabled, the INTA/B pin follows the status of bit BF in register

Control_3 if not masked(see Table 78). Clearing BF immediately clears INTA/B. No pulse

generation is possible for battery switch-over interrupts.

7.13.7 Battery low detection interrupts

Generation of interrupts from the battery low detection is controlled by the BLIE bit

(register Control_3). If BLIE is enabled, the INTA/B pin follows the status of bit BLF

(register Control_3) if not masked. The interrupt is cleared when the battery is replaced

(BLF is logic 0) or when bit BLIE is disabled (BLIE is logic 0). BLF is read only and

therefore cannot be cleared by command.

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7.13.8 Interrupt masks

Table 80.ꢀINT_A/B_MASK1 - interrupt mask 1 register (address 31h/33h) bit allocation

Bits labeled as T are unused and return 0 when read.

Bit

7

6

5

4

3

2

1

0

Symbol

INT_A/B_MASK1

Reset

value

-

1

Table 81.ꢀINT_A/B_MASK1 - interrupt mask 1 register (address 31h/33h) bit description

Bits labeled as T are unused and return 0 when read.

Bit

Symbol

T

Value

Description

7 to 6

00

1

unused

5

4

3

2

1

0

MIA/B

minute interrupt mask

second interrupt mask

watchdog interrupt mask

alarm interrupt mask

battery flag interrupt mask

battery low flag interrupt mask

SIA/B

1

WD_CDA/B

AIEA/B

BIEA/B

BLIEA/B

1

Table 82.ꢀINT_A/B_MASK2 - interrupt mask 2 register (address 32h/34h) bit allocation

Bits labeled as T are unused and return 0 when read.

Bit

7

6

5

4

3

2

1

0

Symbol

INT_A/B_MASK2

Reset

value

T

1

Table 83.ꢀINT_A/B_MASK2 - interrupt mask 2 register (address 32h/34h) bit description

Bits labeled as T are unused and return 0 when read.

Bit

Symbol

T

Value

Description

7 to 4

0000

unused

3

2

1

0

TSIE1A/B

TSIE2A/B

TSIE3A/B

TSIE4A/B

1

time stamp 1 interrupt mask

time stamp 2 interrupt mask

time stamp 3 interrupt mask

time stamp 4 interrupt mask

The registers at addresses 31h to 32h are used to configure interrupt source for INTA

pin, and the registers at addresses 33h to 34h are for INTB pin.

All of above interrupts could be masked from either INTA or INTB, with corresponding bit

set to ‘1’, as shown in Figure 17.

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7.14 External clock test mode

A test mode is available which allows on-board testing. In this mode, it is possible to set

up test conditions and control the operation of the RTC.

The test mode is entered by setting bits COF[2:0] logic 111 (register CLKOUT_ctl) and bit

EXT_TEST logic 1 (register Control_1). Then pin CLKOUT becomes an input. The test

mode replaces the internal clock signal (8192 Hz) with the signal applied to pin CLKOUT.

Every 8192 positive edges applied to pin CLKOUT generate an increment of one second.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a

minimum period of 1ꢀ000 ns. The internal clock, now sourced from CLKOUT, is divided

down by a divider chain called prescaler. The prescaler can be set into a known state by

using bit STOP and CPR. When bit STOP and CPR are logic 1, the prescaler is reset to

0. STOP and CPR must be cleared before the prescaler can operate again.

From a stop condition, the first 1 second increment will take place after 8192 positive

edges on pin CLKOUT. Thereafter, every 8192 positive edges cause a 1 second

increment. In 100 Hz mode, the first 100th of a second increment will take place after

80 pulses on pin CLKOUT, and the first 1 second increment will take place after 8176

pulses on pin CLKOUT. Thereafter, every 8192 pulses cause a 1 second increment. The

100 Hz clock is generated from a dithered state machine which runs on the 256 Hz clock,

so the number of pulses for each subsequent 100ths change is not constant. After the

first 1 second increment the 25-bit dither pattern proceeds as follows from left to right:

1101010101101010110101010

Where 1 == 96 CLKOUT pulses, and 0 == 64 CLKOUT pulses. This pattern repeats

4 times every second.In the first second, after 80 clock pulses trigger the first

100th,the left pattern is 101010101101010110101010, 1101010101101010110101010,

1101010101101010110101010, 1101010101101010110101010, which means 96 pulses

for 100ths == 2, then 64 pulses for 100ths == 3, 96 for 100ths == 4, and so on.

Remark: Entry into test mode is not synchronized to the internal 8192 Hz clock. When

entering the test mode, no assumption as to the state of the prescaler can be made.

Operating example:

1. Set CLKOUT = high-Z (register CLKOUT_ctl, COF[2:0] = 111).

2. Set EXT_TEST test mode (register Control_1, EXT_TEST is logic 1).

3. Set bit STOP (register Control_1, STOP is logic 1).

4. Set bit CPR (register SR_RESET, CPR is logic 1).

5. Set time registers to desired value.

6. Clear STOP (register Control_1, STOP is logic 0).

7. Apply 8192 clock pulses to CLKOUT.

8. Read time registers to see the first change.

9. Apply 8192 clock pulses to CLKOUT.

10.Read time registers to see the second change.

Repeat 7 and 8 for additional increments.

Operating example (100 Hz mode):

1. Set CLKOUT = high-Z (register CLKOUT_ctl, COF[2:0] = 111.

2. Set EXT_TEST test mode (register Control_1, EXT_TEST is logic 1).

3. Set bit STOP (register Control_1, STOP is logic 1).

4. Set bit CPR (register SR_RESET, CPR is logic 1).

5. Set time registers to desired value.

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6. Clear STOP (register Control_1, STOP is logic 0).

7. Apply 80 clock pulses to CLKOUT.

8. Read hundredths registers to see the first change.

9. Apply 8096 clock pulses to CLKOUT (8096 + 80 = 8176 total pulses).

10.Read seconds registers to see the first change.

11.Apply the number of pulses needed for the current dither value.

12.Read the hundredths register to see subsequent changes.

13.Read the seconds register every 8192 pulses to see subsequent changes.

7.15 STOP bit function

The STOP bit stops the time from counting in both RTC mode and external clock test

mode. STOP must be set to unlock the time and date registers to set the time.

OSCILLATOR STOP

setting the OS flag

DETECTOR

100 Hz tick

1 Hz tick

0

1

32768 Hz

8192 Hz

PRESCALER

RESET

div 4

OSCILLATOR

CPR

stop

aaa-041575

Figure 22.ꢀCPR and STOP bit functional diagram

The stop signal blocks the 8.192 kHz clock from generating system clocks and freezes

the time. In this state, the prescaler can be cleared with the CPR command in the Resets

register.

Remark: The CLKOUT output of clock frequencies is not affected.

The time circuits can then be set and do not increment until the STOP bit is released.

There is a slight chance that STOP is set during a carry over of multiple time registers,

which may have been executed incomplete. Therefore time must be set before clearing

STOP to maintain time integrity.

The stop acts on the 8.192 kHz signal. Because the I²C-bus or TS pin input is

asynchronous to the crystal oscillator, the accuracy of restarting the time circuits is

between zero and one 8.192 kHz cycle (see Figure 23).

8192 Hz

stop released

0 µs to 122 µs

aaa-004417

Figure 23.ꢀSTOP release timing

The first increment of the time circuits is between 0 s and 122 µs after STOP is released.

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7.16 Interfaces

The PCA2131 has an I²C-bus or SPI-bus interface using the same pins. The selection is

done using the interface selection pin IFS (see Table 84).

Table 84.ꢀInterface selection input pin IFS

Connection

V_SS

Bus interface

SPI-bus

I²C-bus

Reference

IFS

Section 7.16.1

Section 7.16.2

V_DD

V

DD

SCL

SDI

R

PU

R

PU

SCL

SDA

SDO

CE

V

SCL

DD

V

DD

SCL

SDI

SDO

BBS

SDO

BBS

SDA/CE

IFS

SDA/CE

IFS

PCA2131

V

SS

V

SS

V

SS

aaa-041576

aaa-041577

To select the SPI-bus interface, pin IFS has to be connected To select the I²C-bus interface, pin IFS has to be connected

to pin V_SSto pin V_DD

b. I²C-bus interface selection

.

a. SPI-bus interface selection

Figure 24.ꢀInterface selection

7.16.1 SPI-bus interface

Data transfer to and from the device is made by a 4-line SPI-bus (see Table 85). The

data lines for input and output are split. The SPI-bus is initialized whenever the chip

enable line pin SDA/CE is inactive.

SDI

SDO

two-wire mode

aaa-041578

Figure 25.ꢀSDI, SDO configurations

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Table 85.ꢀSerial interface

Symbol

Function

Description

[1]

SDA/CE chip enable input;

active LOW

when HIGH, the interface is reset;

input may be higher than V_DD

SCL

serial clock input

when SDA/CE is HIGH, input may float;

input may be higher than V_DD

SDI

serial data input

when SDA/CE is HIGH, input may float;

input may be higher than V_DD

;

input data is sampled on the rising edge of

SCL

SDO

serial data output

push-pull output;

drives from V_SSto V_oper(int)(V_BBS);

output data is changed on the falling edge of

SCL

[1] The chip enable must not be wired permanently LOW.

7.16.1.1 Data transmission

The chip enable signal is used to identify the transmitted data. Each data transfer is a

whole byte, with the Most Significant Bit (MSB) sent first.

The transmission is controlled by the active LOW chip enable signal SDA/CE. The first

byte transmitted is the command byte. Subsequent bytes are either data to be written or

data to be read (see Figure 26).

SDI

SDO

COMMAND

DATA

SDA/CE

aaa-041579

Figure 26.ꢀData transfer overview

The command byte defines the address of the first register to be accessed and the read/

write mode. The address counter will auto increment after every access and will reset to

zero after the last valid register is accessed. The R/W bit defines if the following bytes are

read or write information.

Table 86.ꢀCommand byte definition

Bit

Symbol

Value

Description

7

R/W

data read or write selection

write data

0

1

read data

6 to 0

RA

00h to 36h

register address

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R/W

addr 07h

seconds data 45

BCD

minutes data 10

BCD

b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

0

1

0

1

0

1

0

1

0

1

0

SCL

SDI

SDA/CE

address

counter

xx

07

08

09

aaa-041580

In this example, the Seconds register is set to 45 seconds and the Minutes register to 10 minutes.

Figure 27.ꢀSPI-bus write example

R/W

addr 0Ch

months data 11

BCD

years data 06

BCD

b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

1

0

1

0

1

0

1

0

1

0

SCL

SDI

SDO

SDA/CE

address

counter

xx

0C

0D

0E

aaa-041581

In this example, the registers Months and Years are read. The pins SDI and SDO are not connected together. For this

configuration, it is important that pin SDI is never left floating. It must always be driven either HIGH or LOW. If pin SDI is

left open, high I_DDcurrents may result.

Figure 28.ꢀSPI-bus read example

7.16.2 I²C-bus interface

The I²C-bus is for bidirectional, two-line communication between different ICs or

modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both

lines are connected to a positive supply by a pull-up resistor. Data transfer is initiated

only when the bus is not busy.

7.16.2.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line remains

stable during the HIGH period of the clock pulse as changes in the data line at this time

are interpreted as control signals (see Figure 29).

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SDA

SCL

data line

stable;

data valid

change

of data

allowed

mbc621

Figure 29.ꢀBit transfer

7.16.2.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH, is defined as the START condition S. A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition P (see Figure 30).

SDA

SCL

SDA

SCL

S

P

START condition

STOP condition

mbc622

Figure 30.ꢀDefinition of START and STOP conditions

7.16.2.3 System configuration

A device generating a message is a transmitter; a device receiving a message is the

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves.

The PCA2131 can act as a slave transmitter and a slave receiver.

SDA

SCL

MASTER

TRANSMITTER

RECEIVER

SLAVE

TRANSMITTER

RECEIVER

MASTER

TRANSMITTER

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

mba605

Figure 31.ꢀSystem configuration

7.16.2.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge

cycle.

• A slave receiver which is addressed must generate an acknowledge after the reception

of each byte.

• Also a master receiver must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

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• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be considered).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgment on the I²C-bus is illustrated in Figure 32.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from

master

1

2

8

9

S

clock pulse for

acknowledgement

START

condition

mbc602

Figure 32.ꢀAcknowledgment on the I²C-bus

7.16.2.5 I²C-bus protocol

After a start condition, a valid hardware address has to be sent to a PCA2131 device.

The appropriate I²C-bus slave address is 1010ꢀ011. The entire I²C-bus slave address

byte is shown in Table 87.

Table 87.ꢀI²C slave address byte

Slave address

Bit

7

6

5

4

3

2

1

0

MSB

LSB

R/W

1

0

1

0

1

The R/W bit defines the direction of the following single or multiple byte data transfer

(read is logic 1, write is logic 0).

For the format and the timing of the START condition (S), the STOP condition (P), and

the acknowledge (A) refer to the I²C-bus specification [3] and the characteristics table

(Table 92). In the write mode, a data transfer is terminated by sending a STOP condition.

acknowledge

from PCA2131

S

1

0

1

0

1

0

A

P

S

slave address

register address

00h to 36h

0 to n (data bytes

plus ACK)

write bit

STOP

START

aaa-041582

Figure 33.ꢀBus protocol, writing to registers

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acknowledge

from PCA2131

set register

address

S

1

0

1

0

1

0

A

P

slave address

register address

00h to 36h

write bit

STOP

acknowledge

from PCA2131

acknowledge

from master

no acknowledge

LAST DATA BYTE

read register

data

S

1

0

1

0

1

A

DATA BYTE

A

P

slave address

0 to n (data bytes

plus ACK)

read bit

aaa-041583

Figure 34.ꢀBus protocol, reading from registers

7.16.3 Bus communication and battery backup operation

To save power during battery backup operation (see Section 7.5.1), the bus interfaces

are inactive. Therefore the communication via I²C- or SPI-bus should be terminated

before the supply of the PCA2131 is switched from V_DDto V_BAT

.

With I2C interface, PCA2131 will terminate transaction before switching from V_DDto

V_BAT, with SPI interface, PCA2131 will corrupt SPI write and read data when battery

switchover occurs.

Remark: If the I²C-bus communication was terminated uncontrolled, the I²C-bus has to

be reinitialized by sending a STOP followed by a START after the device switched back

from battery backup operation to V_DDsupply operation.

7.17 Internal circuitry

PCA2131

IFS

SCL

VBAT

VDD

BBS

SDI

SDO

SDA/CE

CLKOUT

INTA/B

VSS

TS1/2/3/4

aaa-041584

Figure 35.ꢀDevice diode protection diagram of PCA2131

PCA2131

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7.18 Safety notes

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe

precautions for handling electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5,

JESD625-A or equivalent standards.

8 Limiting values

Table 88.ꢀLimiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

-0.5

-50

-0.5

-10

-0.5

-10

-0.5

-

Max

+6.5

+50

Unit

V

V_DD

I_DD

V_i

supply voltage

supply current

input voltage

input current

output voltage

output current

mA

V

+6.5

+10

I_I

mA

V

V_O

I_O

+6.5

+10

mA

V

at pin SDA/CE

+20

V_BAT

P_tot

battery supply voltage

total power dissipation

+6.5

300

mW

V

[1]

[2]

[3]

[4]

V_ESD

electrostatic discharge

voltage

HBM

CDM

-

±2ꢀ000

±500

1ꢀ00

+125

-

V

I_lu

latch-up current

-

mA

°C

T_stg

T_amb

storage temperature

ambient temperature

-55

-40

operating device

[1] Pass level; Human Body Model (HBM) according to AEC Q100-002.

[2] Pass level (750 V for corner pins); Charged-Device Model (CDM), according to AEC Q100-011.

[3] Pass level; latch-up testing according to AEC Q100-004 at maximum ambient temperature (T_amb(max)).

[4] According to the store and transport requirements (see [4]) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to

75 %.

Note: The PCA2131 part is not guaranteed (nor characterized) above the operating

range as denoted in the data sheet. NXP recommends not to bias the PCA2131 device

during reflow (e.g. if utilizing a 'coin' type battery in the assembly). If customer so

chooses to use this assembly method, there must be the allowance for a full \Q0 V' level

Power supply \Qreset' to re-enable the device. Without a proper POR, the device may

remain in an indeterminate state.

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9 Static characteristics

Table 89.ꢀStatic characteristics

V_DD= 1.2 V to 5.5 V; V_SS= 0 V; T_amb= -40 °C to +105 °C, unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

85 °C 105 °C

Supplies

[1]

V_DD

supply voltage

1.2

-

5.5

V

V_BAT

battery supply

voltage

V_low

I_DD

low voltage

-

1.15

-

V

interface active; supplied by V_DD

supply current ^[2]

SPI-bus (f_SCL= 6.5

MHz)

I²C-bus (f_SCL= 400

kHz)

-

800

200

800

200

µA

-

interface inactive (f_SCL= 0 Hz) ^[3]; TCR[1:0] = 00 (see Table 16)

PWRMNG[2:0] = 111 (see Table 22);

COF[2:0] = 111 (see Table 18)

TC_DIS = 1 (see Table 5); 100TH_S_DIS = 1 (see Table 5)

V_DD= 1.2 V

V_DD= 3.3 V

V_DD= 5.5 V

-

93

420

365 ^[4]655

465 850

735

nA

106

137

PWRMNG[2:0] = 111 (see Table 22);

COF[2:0] = 111 (see Table 18)

TC_DIS = 0 (see Table 5); 100TH_S_DIS = 1 (see Table 5)

V_DD= 1.2 V

V_DD= 3.3 V

V_DD= 5.5 V

-

98

520

500

600

925

nA

112

141

855

1080

PWRMNG[2:0] = 111 (see Table 22);

COF[2:0] = 000 (see Table 18)

TC_DIS = 0 (see Table 5); 100TH_S_DIS = 0 (see Table 5);

[5]

460

770

1325

1925

2835

V_DD= 1.2 V

V_DD= 3.3 V

V_DD= 5.5 V

-

nA

[6]

1075

1735

1435

2210

PWRMNG[2:0] = 000 (see Table 22);

COF[2:0] = 111 (see Table 18)

TC_DIS = 0 (see Table 5); 100TH_S_DIS = 0 (see Table 5)

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Table 89.ꢀStatic characteristics...continued

V_DD= 1.2 V to 5.5 V; V_SS= 0 V; T_amb= -40 °C to +105 °C, unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

85 °C 105 °C

Max

Unit

nA

113

550

650

1220

920

V_DD= 1.8 V, V_BAT

1.5 V

=

-

133

169

V_DD= 3.3 V, V_BAT

3.3 V

nA

1290

V_DD= 5.5 V, V_BAT

3.3 V

nA

[7]

112

125

154

580

530

680

970

830

1130

V_BAT= 1.2 V, I_BAT

-

nA

V_BAT= 3.3 V, I_BAT

:

V_BAT= 5.5 V, I_BAT

:

I_DD

PWRMNG[2:0] = 000 (see Table 22);

COF[2:0] = 000 (see Table 18)

supply current ^[2]

TC_DIS = 0 (see Table 5); 100TH_S_DIS = 0

(see Table 5)

[5]

650

965

1495

1970

2890

V_DD= 1.8 V, V_BAT

1.5 V

=

-

nA

[5]

1100

1770

1450

2260

V_DD= 3.3 V, V_BAT

3.3 V

V_DD= 5.5 V, V_BAT

3.3 V

[7]

130

185

280

395

435

580

905

880

1135

V_BAT= 1.2 V, I_BAT

V_BAT= 3.3 V, I_BAT

V_BAT= 5.5 V, I_BAT

-

nA

I_L(bat)

battery leakage

current

V_DDis active supply;

V_BAT= 3.0 V

0.1

-

Power management

V_th(sw)batbattery switch

threshold voltage

2.3

2.5

2.7

V

V_th(bat)lowlow battery threshold

voltage

Inputs ^[8]

V_I

input voltage

-0.5

-

V_DD

0.5

+

V

V_IL

LOW-level input

voltage

-

0.25V_DD

0.3V_DD

V

T_amb= -40 °C to +85 °C;

V_DD> 2.0 V

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Table 89.ꢀStatic characteristics...continued

V_DD= 1.2 V to 5.5 V; V_SS= 0 V; T_amb= -40 °C to +105 °C, unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

85 °C 105 °C

V_IH

I_LI

HIGH-level input

voltage

0.7V_DD

-

V

input leakage current V_I= V_DDor V_SS

post ESD event

-

0

-

µA

pF

-1

-

+1

7

[9]

C_i

input capacitance

-

Outputs

V_O

output voltage

on pins INTA/B, referring

to external pull-up

-0.5

-

5.5

V

[10]

on pin BBS

1.2

-

5.5

V

V_OH

V_OL

HIGH output voltage on pin SDO, CLKOUT at

1 mA source current

0.8V_DD

V_DD

LOW output voltage on pins CLKOUT, INTA/

B and SDO at 1 mA sink

current

V_SS

-

0.2V_DD

0.4

V

on pin SDA, V_DD

> 2.0 V, 3 mA sink

current

-

on pin SDA, V_DD

< 2.0 V, 2 mA sink

current

0.2V_DD

I_OL

LOW-level output

current

output sink current;

V_OL= 0.4 V

[11]

on pin SDA/CE

3

-

mA

on all other outputs

1.0

I_OH

HIGH-level output

current

output source current; on

pin SDO, CLKOUT; V_OH

= 0.8 * V_DD

I_LO

output leakage

current

V_O= V_DDor V_SS

post ESD event

-

0

-

µA

-1

+1

[1] For reliable oscillator start-up and OTP refresh at power-on: V_DDneeds to be above 1.8 V.

[2] MAX I_DDand I_BATdetermined by characterization.

[3] Timer source clock = ¹

⁄

₆₀Hz, level of pins SDA/CE, SDI, and SCL is V_DDor V_SS

.

[4] Production tested I_DDparameter.

[5] Any load in the application driven by CLKOUT adds to this value, e.g. 10 pF, Vdd = 3v3 will add 32768 Hz * 10 pF * 3.3 V = 1.1 µA.

[6] Any load in the application driven by CLKOUT adds to this value, e.g. 10 pF, Vdd = 3v3 will add 32768 Hz * 10 pF * 3.3 V = 1.1 µA.

[7] When the device is supplied by the V_BATpin instead of the V_DDpin, V_DD= 0 V. The device can only start up from V_DD

[8] The I²C-bus and SPI-bus interfaces of PCA2131 are 5 V tolerant.

[9] Tested on sample basis.

.

[10] Pin BBS is internally connected to either V_DDor V_BAT, see section Section 7.5.3.

[11] For further information, see Figure 36.

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9.1 Current consumption characteristics, typical

aaa-041586

60

I

DD

(mA)

50

40

30

20

10

0

1

2

3

4

5

6

V

DD

(V)

Typical value; V_OL= 0.4 V.

Figure 36.ꢀI_OLon pin SDA/CE

aaa-043184

1200

Current

(nA)

1000

800

VDD = 1.8 V

VDD = 3.3 V

600

400

200

0

(1)

-40

0

40

80

105 120

Temperature (C)

160

CLKOUT disabled; PWRMNG[2:0] = 111; TSOFF = 1; TS input floating.

1. Above maximum guaranteed operating temperature of +105 °C, the typical I_DDis based on

the bench result.

Figure 37.ꢀI_DDas a function of temperature

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aaa-042113

2000

I

DD

(nA)

1600

1200

800

400

0

CLKOUT enabled at 32 kHz

CLKOUT off

1

2

3

4

5

6

V

DD

(V)

a. PWRMNG[2:0] = 111; TSOFF = 1; T_amb= 25 °C; TS input floating

aaa-042114

2000

I

DD

(nA)

1600

1200

800

400

0

CLKOUT enabled at 32 kHz

CLKOUT off

1

2

3

4

5

6

V

DD

(V)

b. PWRMNG[2:0] = 000; TSOFF = 0; T_amb= 25 °C; TS input floating

Figure 38.ꢀI_DDas a function of V_DD

9.2 Frequency characteristics

Table 90.ꢀFrequency characteristics

V_DD= 1.2 V to 5.5 V; V_SS= 0 V; T_amb= +25 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f_o

output frequency

on pin CLKOUT;

V_DD= 3.3 V;

-

32.768

-

kHz

COF[2:0] = 000;

AO[3:0] = 1000

Δf/f

time accuracy

V_DDor V_BAT= 3.3 V, T_amb

-40 °C to +85 °C

=

[1] [2]

TC_DIS = 0

TC_DIS = 1

-8

±3

+8

+4

ppm

-200

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Table 90.ꢀFrequency characteristics...continued

V_DD= 1.2 V to 5.5 V; V_SS= 0 V; T_amb= +25 °C, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_DDor V_BAT= 3.3 V, T_amb

+85 °C to +105 °C

=

[1] [2]

TC_DIS = 0

TC_DIS = 1

-15

-320

-3

±8

+15

-50

+3

ppm

TC_DIS = 1, T_amb= 25 °C

crystal aging

Δf_xtal/f_xtal

relative crystal

frequency variation

PCA2131

[3]

first year;

-3

-

+3

ppm

V_DDor V_BAT= 3.3 V

Δf/ΔV

Jitter

frequency variation

with voltage

on pin CLKOUT

-

±1

50

-

ppm/V

ns

Output clock peak to on pin CLKOUT

peak jitter

[1] ±1 ppm corresponds to a time deviation of ±0.0864 seconds per day.

[2] Only valid if CLKOUT frequencies are not equal to 32.768 kHz or if CLKOUT is disabled.

[3] Not production tested. Effects of reflow soldering are included (see application note AN13202).

aaa-042794

50

± 3 ppm

± 8 ppm

Frequency

stability

(ppm)

(1)

(2)

(3)

-50

-150

-250

-350

120 125

100 105

Temperature (°C)

-40

-20

0

20

40

60

80

1. Typical temperature compensated RTC time accuracy response (TC_DIS = 0).

2. Typical CLKOUT frequency Y [ppm] = -0.035*(T-25C)²(TC_DIS = 0 or 1).

3. Above maximum guaranteed operating temperature of +105 °C, the typical time accuracy is

based on the bench result.

Figure 39.ꢀTypical characteristic of frequency with respect to temperature of PCA2131

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10 Dynamic characteristics

10.1 SPI-bus timing characteristics

Table 91.ꢀSPI-bus characteristics

V_DD= 1.2 V to 5.5 V; V_SS= 0 V; T_amb= -40 °C to +105 °C, unless otherwise specified. All timing values are valid within the

operating supply voltage at ambient temperature and referenced to V_ILand V_IHwith an input voltage swing of V_SSto V_DD

(see Figure 40).

Symbol

Parameter

Conditions

V_DD= 1.2 V to 3.3 V

V_DD= 3.3 V to

5.5 V

Unit

Min

Max

Min

Max

Pin SCL

f_clk(SCL)

t_clk(H)

t_clk(L)

t_r

SCL clock frequency

clock HIGH time

clock LOW time

rise time

-

0.5

-

6.5

-

MHz

ns

1000

70

-

1000

-

ns

for SCL signal

-

100

ns

t_f

fall time

-

ns

Pin SDA/CE

t_{su(CE_N)}CE_N set-up time

t_{h(CE_N)}CE_N hold time

t_{rec(CE_N)}CE_N recovery time

300

325

1500

-

30

25

1500

-

ns

s

-

t_{w(CE_N)}

Pin SDI

t_su

CE_N pulse width

0.99

set-up time

hold time

set-up time for SDI data

hold time for SDI data

250

-

20

-

ns

t_h

Pin SDO

t_d(R)SDO

t_dis(SDO)

SDO read delay time C_L= 50 pF

SDO disable time

-

550

150

-

55

25

ns

[1]

[1] No load value; bus is held up by bus capacitance; use RC time constant with application values.

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t

w(CE_N)

CE

t

rec(CE_N)

t

r

su(CE_N)

t

h(CE_N)

f

clk(SCL)

80%

SCL

20%

t

clk(L)

t

clk(H)

WRITE

t

su

t

h

SDI

R/W

SA2

RA0

b7

b6

b0

high-Z

SDO

READ

SDI

b7

b6

b0

t(SDI-SDO)

t

d(R)SDO

t

dis(SDO)

high-Z

SDO

b7

b6

b0

013aaa152

Figure 40.ꢀSPI-bus timing

10.2 I²C-bus timing characteristics

Table 92.ꢀI²C-bus characteristics

All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 %

and 70 % with an input voltage swing of V_SSto V_DD(see Figure 41).

Symbol

Parameter

Standard mode

Fast-mode (Fm)

Unit

Min

Max

Min

Max

Pin SCL

f_SCL

[1]

SCL clock frequency

10

100

10

400

kHz

µs

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

4.7

4.0

-

1.3

0.6

-

t_HIGH

µs

Pin SDA/CE

t_SU;DAT

t_HD;DAT

data set-up time

data hold time

250

0

-

100

0

-

ns

Pins SCL and SDA/CE

t_BUF

bus free time between a STOP

and START condition

4.7

-

1.5

-

µs

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Table 92.ꢀI²C-bus characteristics...continued

All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 %

and 70 % with an input voltage swing of V_SSto V_DD(see Figure 41).

Symbol

Parameter

Standard mode

Fast-mode (Fm)

Unit

Min

4.0

Max

Min

0.6

Max

t_SU;STO

t_HD;STA

set-up time for STOP condition

-

µs

hold time (repeated) START

condition

t_SU;STA

set-up time for a repeated START

condition

4.7

-

0.6

-

µs

ns

[2][3][4]

t_r

t_f

rise time of both SDA and SCL

signals

-

1ꢀ000

300

20 + 0.1C_b

300

fall time of both SDA and SCL

signals

[5]

[6]

[7]

t_VD;ACK

t_VD;DAT

t_SP

data valid acknowledge time

data valid time

-

3.45

50

-

0.9

50

µs

ns

pulse width of spikes that must

be suppressed by the input filter

[1] The minimum SCL clock frequency is limited by the bus time-out feature which resets the serial bus interface if either the SDA or SCL is held LOW for a

minimum of 25 ms. The bus time-out feature must be disabled for DC operation.

[2] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_ILof the SCL signal) in order to bridge the

undefined region of the falling edge of SCL.

[3] C_bis the total capacitance of one bus line in pF.

[4] The maximum t_ffor the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, t_fis 250 ns. This allows series protection

resistors to be connected between the SDA/CE pin, the SCL pin, and the SDA/SCL bus lines without exceeding the maximum t_f.

[5] t_VD;ACKis the time of the acknowledgment signal from SCL LOW to SDA (out) LOW.

[6] t_VD;DATis the minimum time for valid SDA (out) data following SCL LOW.

[7] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.

START

CONDITION

(S)

BIT 7

MSB

(A7)

BIT 6

(A6)

BIT 0

LSB

(R/W)

ACKNOWLEDGE

(A)

STOP

CONDITION

(P)

PROTOCOL

t

SU;STA

LOW

HIGH

1 / f

SCL

SDA

t

BUF

r

f

t

HD;STA

SU;DAT

HD;DAT

VD;DAT

SU;STO

mbd820

Figure 41.ꢀI²C-bus timing diagram; rise and fall times refer to 30 % and 70 %

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11 Application information

The PCA2131TF/Q900 is AEC-Q100 compliant for automotive applications. The

operating temperature range is from -40 °C to +105 °C and the time accuracy with

temperature compensation is:

• ±3 ppm typical with ±8 ppm min/max from -40 °C to +85 °C

• ±8 ppm typical with ±15 ppm min/max from +85 °C to +105 °C

Above the maximum guaranteed operating temperature of +105 °C to the maximum

ambient temperature of +125 °C the PCA2131TF/Q900 TCXO, RTC and digital

interfaces (I²C and SPI) functions continue to be operational with the supply current

increasing proportionally to temperature (see Figure 37 for the trend). The temperature

compensation circuity also continues to function and typical time accuracy of ±8 ppm has

been measured on the bench.

The general application diagram is shown in Figure 42.

100 nF

Csup

V

SCL

SDI

DD

Rsup

V

DD(in)

Interface

SDO

100 nF

V

BAT

SDA/CE

V

2

DD

BBS

IFS

I C

BBS

INTA

SPI

1 to 100 nF

PCA2131

TS1

TS2

TS3

TS4

INTA

INTB

R

PU

V

DD

INTB

R

PU

V

DD

CLKOUT

V

SS

CLKOUT

aaa-041588

R_PU: 10 kΩ is recommended.

R_SUPand C_SUP: An appropriate RC filter needs to be added to guarantee the chip will only see

<0.35 V/ms ramp down rate on supply, even if Vdd_in ramp rate is very high.

Figure 42.ꢀGeneral application diagram

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12 Package outline

Figure 43.ꢀPackage outline SOT1992-1 (HLSON16)

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Figure 44.ꢀPackage outline SOT1992-1 (HLSON16); detail G

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Figure 45.ꢀPackage outline SOT1992-1 (HLSON16); notes

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13 Packing information

13.1 Tape and reel information

For tape and reel packing information, see [2]

14 Soldering

For information about soldering, see [1].

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14.1 Footprint information

Figure 46.ꢀFootprint information part 1 for reflow soldering of SOT1992-1 (HLSON16)

PCA2131

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Figure 47.ꢀFootprint information part 2 for reflow soldering of SOT1992-1 (HLSON16)

PCA2131

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Figure 48.ꢀFootprint information part 3 for reflow soldering of SOT1992-1 (HLSON16)

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16 Abbreviations

Table 94.ꢀAbbreviations

Acronym

AM

Description

Ante Meridiem

BCD

CDM

CMOS

DC

Binary Coded Decimal

Charged Device Model

Complementary Metal-Oxide Semiconductor

Direct Current

GPS

HBM

I²C

Global Positioning System

Human Body Model

Inter-Integrated Circuit

Integrated Circuit

IC

LSB

Least Significant Bit

Microcontroller Unit

Machine Model

MCU

MM

MSB

PM

Most Significant Bit

Post Meridiem

POR

PORO

PPM

RC

Power-On Reset

Power-On Reset Override

Parts Per Million

Resistance-Capacitance

Real-Time Clock

RTC

SCL

SDA

SPI

Serial CLock line

Serial DAta line

Serial Peripheral Interface

Static Random Access Memory

Temperature Compensated Xtal Oscillator

crystal

SRAM

TCXO

Xtal

17 References

[1] AN13203 Application and soldering information for the PCF2131 and PCA2131

RTC

[2] SOT1992-1_518 HLSON16; Reel pack; SMD, 13", packing information

[3] UM10204 I²C-bus specification and user manual

[4] UM10569 Store and transport requirements

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18 Revision history

Table 95.ꢀRevision history

Document ID

Release date

Data sheet status

Change

notice

Supersedes

PCA2131 v.1.0

20210726

Product data sheet

-

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19 Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product

development.

Preliminary [short] data sheet

Product [short] data sheet

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

19.2 Definitions

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Draft — A draft status on a document indicates that the content is still

under internal review and subject to formal approval, which may result

in modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included in a draft version of a document and shall have no

liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

19.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

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to result in personal injury, death or severe property or environmental

open and/or proprietary technologies supported by NXP products for use

in customer’s applications. NXP accepts no liability for any vulnerability.

Customer should regularly check security updates from NXP and follow up

appropriately. Customer shall select products with security features that best

meet rules, regulations, and standards of the intended application and make

the ultimate design decisions regarding its products and is solely responsible

for compliance with all legal, regulatory, and security related requirements

concerning its products, regardless of any information or support that may

be provided by NXP. NXP has a Product Security Incident Response Team

(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,

reporting, and solution release to security vulnerabilities of NXP products.

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

19.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Security — Customer understands that all NXP products may be subject

to unidentified or documented vulnerabilities. Customer is responsible

for the design and operation of its applications and products throughout

their lifecycles to reduce the effect of these vulnerabilities on customer’s

applications and products. Customer’s responsibility also extends to other

I²C-bus — logo is a trademark of NXP B.V.

NXP — wordmark and logo are trademarks of NXP B.V.

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Tables

Tab. 1.

Tab. 2.

Tab. 3.

Tab. 4.

Tab. 5.

Ordering information ..........................................2

Ordering options ................................................2

Pin description ...................................................4

Register overview ..............................................7

Control_1 - control and status register 1

(address 00h) bit allocation .............................10

Control_1 - control and status register 1

(address 00h) bit description ...........................10

Control_2 - control and status register 2

(address 01h) bit allocation .............................11

Control_2 - control and status register 2

(address 01h) bit description ...........................11

Control_3 - control and status register 3

Tab. 34. Hours - hours register (address 09h) bit

description ....................................................... 28

Tab. 35. Days - days register (address 0Ah) bit

allocation ......................................................... 29

Tab. 36. Days - days register (address 0Ah) bit

description ....................................................... 29

Tab. 37. Weekdays - weekdays register (address

0Bh) bit allocation ........................................... 29

Tab. 38. Weekdays - weekdays register (address

0Bh) bit description ......................................... 29

Tab. 39. Weekday assignments .................................... 30

Tab. 40. Months - months register (address 0Ch) bit

allocation ......................................................... 30

Tab. 41. Months - months register (address 0Ch) bit

description ....................................................... 30

Tab. 42. Month assignments in BCD format ..................30

Tab. 43. Years - years register (address 0Dh) bit

allocation ......................................................... 31

Tab. 44. Years - years register (address 0Dh) bit

description ....................................................... 31

Tab. 45. Second_alarm - second alarm register

(address 0Eh) bit allocation .............................33

Tab. 46. Second_alarm - second alarm register

(address 0Eh) bit description .......................... 34

Tab. 47. Minute_alarm - minute alarm register

(address 0Fh) bit allocation .............................34

Tab. 48. Minute_alarm - minute alarm register

(address 0Fh) bit description ...........................34

Tab. 49. Hour_alarm - hour alarm register (address

10h) bit allocation ............................................34

Tab. 50. Hour_alarm - hour alarm register (address

10h) bit description ..........................................34

Tab. 51. Day_alarm - day alarm register (address

11h) bit allocation ............................................35

Tab. 52. Day_alarm - day alarm register (address

11h) bit description ..........................................35

Tab. 53. Weekday_alarm - weekday alarm register

(address 12h) bit allocation .............................36

Tab. 54. Weekday_alarm - weekday alarm register

(address 12h) bit description ...........................36

Tab. 55. Watchdg_tim_ctl - watchdog timer control

register (address 35h) bit allocation ................ 37

Tab. 56. Watchdg_tim_ctl - watchdog timer control

register (address 35h) bit description ..............37

Tab. 57. Watchdg_tim_val - watchdog timer value

register (address 36h) bit allocation ................ 37

Tab. 58. Watchdg_tim_val - watchdog timer value

register (address 36h) bit description ..............38

Tab. 59. Programmable watchdog timer ....................... 38

Tab. 60. Flag location in register Control_2 .................. 39

Tab. 61. Example values in register Control_2 ..............40

Tab. 62. Example to clear only AF (bit 4) ......................40

Tab. 63. Example to clear only MSF (bit 7) ...................40

Tab. 64. Timestp_ctl1/2/3/4 - timestamp control

register (address 14h/1Bh/22h/29h) bit

Tab. 6.

Tab. 7.

Tab. 8.

Tab. 9.

(address 02h) bit allocation .............................11

Tab. 10. Control_3 - control and status register 3

(address 02h) bit description ...........................12

Tab. 11. Control_4 - control and status register 4

(address 03h) bit allocation .............................12

Tab. 12. Control_4 - control and status register 4

(address 03h) bit description ...........................12

Tab. 13. Control_5 - control and status register 5

(address 04h) bit allocation .............................13

Tab. 14. Control_5 - control and status register 5

(address 04h) bit description ...........................13

Tab. 15. CLKOUT_ctl - CLKOUT control register

(address 13h) bit allocation .............................13

Tab. 16. CLKOUT_ctl - CLKOUT control register

(address 13h) bit description ...........................14

Tab. 17. Temperature measurement period .................. 15

Tab. 18. CLKOUT frequency selection ..........................16

Tab. 19. Aging_offset - crystal aging offset register

(address 30h) bit allocation .............................16

Tab. 20. Aging_offset - crystal aging offset register

(address 30h) bit description ...........................16

Tab. 21. Frequency correction at 25 °C, typical ............ 17

Tab. 22. Power management control bit description ......18

Tab. 23. Output pin BBS ............................................... 22

Tab. 24. Reset - software reset control (address

05h) bit description ..........................................25

Tab. 25. 100th Seconds - 100th seconds (address

06h) bit allocation ............................................26

Tab. 26. 100th Seconds - 100th seconds register

(address 06h) bit description ...........................26

Tab. 27. 100th Seconds coded in BCD format ..............27

Tab. 28. Seconds - seconds and clock integrity

register (address 07h) bit allocation ................ 27

Tab. 29. Seconds - seconds and clock integrity

register (address 07h) bit description ..............27

Tab. 30. Seconds coded in BCD format ........................27

Tab. 31. Minutes - minutes register (address 08h) bit

allocation ......................................................... 28

Tab. 32. Minutes - minutes register (address 08h) bit

description ....................................................... 28

Tab. 33. Hours - hours register (address 09h) bit

allocation ......................................................... 28

allocation ......................................................... 41

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Tab. 65. Timestp_ctl1/2/3/4 - timestamp control

Tab. 75. Mon_timestp1/2/3/4 - month timestamp

register (address 19h/20h/27h/2Eh) bit

description ....................................................... 44

Tab. 76. Year_timestp1/2/3/4 - year timestamp

register (address 1Ah/21h/28h/2Fh) bit

register (address 14h/1Bh/22h/29h) bit

description ....................................................... 41

Tab. 66. Sec_timestp1/2/3/4 - second timestamp

register (address 15h/1Ch/23h/2Ah) bit

allocation ......................................................... 42

Tab. 67. Sec_timestp1/2/3/4 - second timestamp

register (address 15h/1Ch/23h/2Ah) bit

allocation ......................................................... 44

Tab. 77. Year_timestp1/2/3/4 - year timestamp

register (address 1Ah/21h/28h/2Fh) bit

description ....................................................... 42

Tab. 68. Min_timestp1/2/3/4 - minute timestamp

register (address 16h/1Dh/24h/2Bh) bit

allocation ......................................................... 42

Tab. 69. Min_timestp1/2/3/4 - minute timestamp

register (address 16h/1Dh/24h/2Bh) bit

description ....................................................... 42

Tab. 70. Hour_timestp1/2/3/4 - hour timestamp

register (address 17h/1Eh/25h/2Ch) bit

description ....................................................... 44

Tab. 78. Battery switch-over and timestamp ................. 44

Tab. 79. Effect of bits MI and SI on pin INTA/B and

bit MSF ............................................................46

Tab. 80. INT_A/B_MASK1 - interrupt mask 1

register (address 31h/33h) bit allocation ......... 49

Tab. 81. INT_A/B_MASK1 - interrupt mask 1

register (address 31h/33h) bit description ....... 49

Tab. 82. INT_A/B_MASK2 - interrupt mask 2

allocation ......................................................... 42

Tab. 71. Hour_timestp1/2/3/4 - hour timestamp

register (address 17h/1Eh/25h/2Ch) bit

description ....................................................... 43

Tab. 72. Day_timestp1/2/3/4 - day timestamp

register (address 18h/1Fh/26h/2Dh) bit

allocation ......................................................... 43

Tab. 73. Day_timestp1/2/3/4 - day timestamp

register (address 18h/1Fh/26h/2Dh) bit

description ....................................................... 43

Tab. 74. Mon_timestp1/2/3/4 - month timestamp

register (address 19h/20h/27h/2Eh) bit

register (address 32h/34h) bit allocation ......... 49

Tab. 83. INT_A/B_MASK2 - interrupt mask 2

register (address 32h/34h) bit description ....... 49

Tab. 84. Interface selection input pin IFS ......................52

Tab. 85. Serial interface ................................................ 53

Tab. 86. Command byte definition ................................ 53

Tab. 87. I2C slave address byte ................................... 56

Tab. 88. Limiting values ................................................ 58

Tab. 89. Static characteristics ....................................... 59

Tab. 90. Frequency characteristics ............................... 63

Tab. 91. SPI-bus characteristics ....................................65

Tab. 92. I2C-bus characteristics ....................................66

Tab. 93. Selection of Real-Time Clocks ........................ 76

Tab. 94. Abbreviations ...................................................78

Tab. 95. Revision history ...............................................79

allocation ......................................................... 43

Figures

Fig. 1.

Fig. 2.

Block diagram of PCA2131 ...............................3

Pin configuration for PCA2131 (transparent

top view) ............................................................4

Handling address registers ............................... 5

Battery switch-over behavior in standard

mode with bit BIE set logic 1 (enabled) ...........19

Battery switch-over behavior in direct

switching mode with bit BIE set logic 1

Fig. 15. Alarm flag timing diagram ............................... 36

Fig. 16. WD_CD set logic 1: watchdog activates an

interrupt when timed out ................................. 39

Fig. 17. Interrupt block diagram ................................... 45

Fig. 18. INTA/B example for SI and MI when TI_TP

is logic 1 ..........................................................46

Fig. 3.

Fig. 4.

Fig. 5.

Fig. 19. INTA/B example for SI and MI when TI_TP

is logic 0 ..........................................................47

(enabled) ......................................................... 20

Battery switch-over circuit, simplified block

diagram ............................................................20

Battery low detection behavior with bit BLIE

set logic 1 (enabled) ....................................... 21

Power failure event due to battery

Fig. 20. Example of shortening the INTA/B pulse by

clearing the MSF flag ......................................47

Fig. 6.

Fig. 7.

Fig. 8.

Fig. 9.

Fig. 21. AF timing diagram ...........................................48

Fig. 22. CPR and STOP bit functional diagram ............51

Fig. 23. STOP release timing .......................................51

Fig. 24. Interface selection ........................................... 52

Fig. 25. SDI, SDO configurations .................................52

Fig. 26. Data transfer overview .................................... 53

Fig. 27. SPI-bus write example .................................... 54

Fig. 28. SPI-bus read example .....................................54

Fig. 29. Bit transfer .......................................................55

Fig. 30. Definition of START and STOP conditions ...... 55

Fig. 31. System configuration .......................................55

Fig. 32. Acknowledgment on the I2C-bus .................... 56

Fig. 33. Bus protocol, writing to registers .....................56

discharge: reset occurs ...................................23

Dependency between POR and oscillator .......24

Fig. 10. Power-On Reset (POR) system ...................... 24

Fig. 11.

Power-On Reset Override (PORO)

sequence, valid for both I2C-bus and SPI-

bus ...................................................................25

Fig. 12. Software reset command ................................ 26

Fig. 13. Data flow for the time function ........................ 32

Fig. 14. Alarm function block diagram ..........................33

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Fig. 34. Bus protocol, reading from registers ............... 57

Fig. 35. Device diode protection diagram of

Fig. 43. Package outline SOT1992-1 (HLSON16) ........69

Fig. 44. Package outline SOT1992-1 (HLSON16);

detail G ............................................................70

Fig. 45. Package outline SOT1992-1 (HLSON16);

notes ................................................................71

Fig. 46. Footprint information part 1 for reflow

soldering of SOT1992-1 (HLSON16) ...............73

Fig. 47. Footprint information part 2 for reflow

soldering of SOT1992-1 (HLSON16) ...............74

Fig. 48. Footprint information part 3 for reflow

soldering of SOT1992-1 (HLSON16) ...............75

PCA2131 ......................................................... 57

Fig. 36. IOL on pin SDA/CE .........................................62

Fig. 37. IDD as a function of temperature .................... 62

Fig. 38. IDD as a function of VDD ............................... 63

Fig. 39. Typical characteristic of frequency with

respect to temperature of PCA2131 ................64

Fig. 40. SPI-bus timing .................................................66

Fig. 41. I2C-bus timing diagram; rise and fall times

refer to 30 % and 70 % .................................. 67

Fig. 42. General application diagram ........................... 68

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Contents

1

2

3

4

4.1

5

6

6.1

6.2

7

7.1

7.2

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.3

7.3.1

General description ............................................ 1

7.10.4

7.10.5

7.10.6

7.11

7.11.1

7.11.2

7.11.3

7.11.4

Register Day_alarm .........................................35

Register Weekday_alarm .................................36

Alarm flag ........................................................ 36

Watchdog timer functions ................................ 36

Register Watchdg_tim_ctl ................................37

Register Watchdg_tim_val ...............................37

Watchdog timer function ..................................38

Pre-defined timers: second and minute

interrupt ............................................................39

Clearing flags ...................................................39

Timestamp function ......................................... 40

Timestamp flag ................................................ 40

Timestamp mode .............................................41

Timestamp registers ........................................ 41

Features and benefits .........................................1

Applications .........................................................2

Ordering information .......................................... 2

Ordering options ................................................ 2

Block diagram ..................................................... 3

Pinning information ............................................ 4

Pinning ...............................................................4

Pin description ...................................................4

Functional description ........................................5

Register overview .............................................. 5

Control registers .............................................. 10

Register Control_1 ...........................................10

Register Control_2 ...........................................11

Register Control_3 ...........................................11

Register Control_4 ...........................................12

Register Control_5 ...........................................13

Register CLKOUT_ctl ...................................... 13

Temperature compensated Real Time

Clock ................................................................14

Temperature measurement ..............................15

OTP refresh .....................................................15

Clock output .....................................................15

Register Aging_offset ...................................... 16

Crystal aging correction ...................................16

Power management functions ......................... 17

Battery switch-over function .............................18

Standard mode ................................................ 19

Direct switching mode ..................................... 19

Battery switch-over disabled: only one

power supply (VDD) ........................................ 20

Battery switch-over architecture ...................... 20

Battery low detection function ..........................20

Battery backup supply ..................................... 21

Oscillator stop detection function .....................22

Power-On Reset function ................................ 23

Power-On Reset (POR) ...................................23

Power-On Reset Override (PORO) ................. 24

Software Reset register ...................................25

SR - Software reset .........................................25

CPR: clear prescaler ....................................... 26

CTS: clear timestamp ......................................26

Time and date function ....................................26

Register 100th Seconds .................................. 26

Register Seconds ............................................ 27

Register Minutes ..............................................28

Register Hours .................................................28

Register Days ..................................................29

Register Weekdays ..........................................29

Register Months .............................................. 30

Register Years ................................................. 31

Setting and reading the time ........................... 31

Alarm function ..................................................33

Register Second_alarm ................................... 33

Register Minute_alarm .....................................34

Register Hour_alarm ........................................34

7.11.5

7.12

7.12.1

7.12.2

7.12.3

7.12.3.1 Register Timestp_ctl1/2/3/4 ............................. 41

7.12.3.2 Register Sec_timestp .......................................42

7.12.3.3 Register Min_timestp .......................................42

7.12.3.4 Register Hour_timestp .....................................42

7.12.3.5 Register Day_timestp ...................................... 43

7.12.3.6 Register Mon_timestp ......................................43

7.12.3.7 Register Year_timestp ......................................44

7.3.1.1

7.3.2

7.3.3

7.4

7.4.1

7.5

7.5.1

7.5.1.1

7.5.1.2

7.5.1.3

7.12.4

Dependency between Battery switch-over

and timestamp .................................................44

Interrupt output, INTA/INTB ............................. 44

Minute and second interrupts .......................... 45

INTA/B pulse shortening ..................................47

Watchdog timer interrupts ................................47

Alarm interrupts ............................................... 48

Timestamp interrupts ....................................... 48

Battery switch-over interrupts .......................... 48

Battery low detection interrupts ....................... 48

Interrupt masks ................................................49

External clock test mode ................................. 50

STOP bit function ............................................ 51

Interfaces ......................................................... 52

SPI-bus interface ............................................. 52

7.13

7.13.1

7.13.2

7.13.3

7.13.4

7.13.5

7.13.6

7.13.7

7.13.8

7.14

7.5.1.4

7.5.2

7.5.3

7.6

7.15

7.16

7.16.1

7.7

7.7.1

7.7.2

7.8

7.8.1

7.8.2

7.8.3

7.9

7.9.1

7.9.2

7.9.3

7.9.4

7.9.5

7.9.6

7.9.7

7.9.8

7.9.9

7.10

7.16.1.1 Data transmission ............................................53

7.16.2 I2C-bus interface ............................................. 54

7.16.2.1 Bit transfer ....................................................... 54

7.16.2.2 START and STOP conditions .......................... 55

7.16.2.3 System configuration ....................................... 55

7.16.2.4 Acknowledge ....................................................55

7.16.2.5 I2C-bus protocol .............................................. 56

7.16.3

Bus communication and battery backup

operation ..........................................................57

Internal circuitry ............................................... 57

Safety notes .....................................................58

Limiting values ..................................................58

Static characteristics ........................................59

Current consumption characteristics, typical ....62

Frequency characteristics ................................63

Dynamic characteristics ...................................65

SPI-bus timing characteristics ......................... 65

I2C-bus timing characteristics ..........................66

Application information ....................................68

Package outline .................................................69

7.17

7.18

8

9

9.1

9.2

10

10.1

10.2

11

7.10.1

7.10.2

7.10.3

12

PCA2131

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 26 July 2021

85 / 86

NXP Semiconductors

PCA2131

Nano-power highly accurate RTC with integrated quartz crystal for automotive applications

13

13.1

14

14.1

15

15.1

16

17

18

19

Packing information ..........................................72

Tape and reel information ................................72

Soldering ............................................................72

Footprint information ........................................73

Appendix ............................................................76

Real-time clock selection .................................76

Abbreviations .................................................... 78

References .........................................................78

Revision history ................................................ 79

Legal information ..............................................80

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 26 July 2021

Document identifier: PCA2131


型号：	PCA2129
厂家：	NXP
描述：	Nano-power highly accurate RTC with integrated quartz crystal for automotive applications
文件：	总86页 (文件大小：1031K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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