PCA8574TS,118_技术文档

PCA8574; PCA8574A

Remote 8-bit I/O expander for I²C-bus with interrupt

Rev. 3 — 3 June 2013

Product data sheet

1. General description

The PCA8574/74A provides general-purpose remote I/O expansion via the two-wire

bidirectional I²C-bus (serial clock (SCL), serial data (SDA)).

The devices consist of eight quasi-bidirectional ports, 400 kHz I²C-bus interface, three

hardware address inputs and interrupt output operating between 2.3 V and 5.5 V. The

quasi-bidirectional port can be independently assigned as an input to monitor interrupt

status or keypads, or as an output to activate indicator devices such as LEDs. The system

master can read from the input port or write to the output port through a single register.

The low current consumption of 4.5 A (typical, static) is great for mobile applications and

the latched output ports have 25 mA high current sink drive capability for directly driving

LEDs.

The PCA8574 and PCA8574A are identical, except for the different fixed portion of the

slave address. The three hardware address pins allow eight of each device to be on the

same I²C-bus, so there can be up to 16 of these I/O expanders PCA8574/74A together on

the same I²C-bus, supporting up to 128 I/Os (for example, 128 LEDs).

The active LOW open-drain interrupt output (INT) can be connected to the interrupt logic

of the microcontroller and is activated when any input state differs from its corresponding

input port register state. It is used to indicate to the microcontroller that an input state has

changed and the device needs to be interrogated without the microcontroller continuously

polling the input register via the I²C-bus.

The internal Power-On Reset (POR) initializes the I/Os as inputs with a weak internal

pull-up 100 A current source.

2. Features and benefits

 I²C-bus to parallel port expander

 400 kHz I²C-bus interface (Fast-mode I²C-bus)

 Operating supply voltage 2.3 V to 5.5 V with 5.5 V tolerant I/Os held to V_DDwith

100 A current source

 8-bit remote I/O pins that default to inputs at power-up

 Latched outputs with 25 mA sink capability for directly driving LEDs

 Total package sink capability of 200 mA

 Active LOW open-drain interrupt output

 Eight programmable slave addresses using three address pins

 Low standby current (4.5 A typical)

 40 C to +85 C operation

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

 Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA

 Packages offered: SO16, TSSOP16, SSOP20

3. Applications

 LED signs and displays

 Servers

 Key pads

 Industrial control

 Medical equipment

 PLCs

 Cellular telephones

 Mobile devices

 Gaming machines

 Instrumentation and test measurement

4. Ordering information

Table 1.

Ordering information

Type number

Topside mark Package

Name

Description

Version

PCA8574D^[1]

PCA8574AD^[2]

PCA8574PW

PCA8574APW

PCA8574TS^[3]

PCA8574D

PCA8574AD

PCA8574

PA8574A

SO16

plastic small outline package; 16 leads; body width 7.5 mm SOT162-1

TSSOP16

SSOP20

plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT403-1

SOT266-1

PCA8574

plastic shrink small outline package; 20 leads;

body width 4.4 mm

PCA8574ATS^[4]PA8574A

[1] PCA8574D drop-in replacement for PCF8574T/3.

[2] PCA8574AD drop-in replacement for PCF8574AT/3.

[3] PCA8574TS drop-in replacement for PCF8574TS/3.

[4] PCA8574ATS drop-in replacement for PCF8574ATS/3.

PCA8574_PCA8574A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 3 June 2013

2 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

4.1 Ordering options

Table 2.

Ordering options

Type number Orderable

part number

Package

Packing method

Minimum Temperature range

order

quantity

PCA8574D

PCA8574D,512

PCA8574D,518

SO16

Standard marking * tube dry pack 1920

T_amb= 40 C to +85 C

Reel 13” Q1/T1

1000

*standard mark SMD dry pack

PCA8574AD

PCA8574PW

PCA8574AD,512

PCA8574AD,518

SO16

Standard marking * tube dry pack 1920

T_amb= 40 C to +85 C

Reel 13” Q1/T1

1000

2400

2500

2400

2500

1350

2500

1350

2500

T_amb= 40 C to +85 C

*standard mark SMD dry pack

PCA8574PW,112

PCA8574PW,118

TSSOP16 Standard marking

* IC’s tube - DSC bulk pack

TSSOP16 Reel 13” Q1/T1

*standard mark SMD

PCA8574APW PCA8574APW,112 TSSOP16 Standard marking

* IC’s tube - DSC bulk pack

T_amb= 40 C to +85 C

PCA8574APW,118 TSSOP16 Reel 13” Q1/T1

*standard mark SMD

T_amb= 40 C to +85 C

PCA8574TS

PCA8574TS,112

SSOP20

Standard marking

* IC’s tube - DSC bulk pack

PCA8574TS,118

SSOP20

Reel 13” Q1/T1

*standard mark SMD

T

_amb= 40 C to +85 C

PCA8574ATS PCA8574ATS,112 SSOP20

PCA8574ATS,118 SSOP20

Standard marking

T_amb= 40 C to +85 C

* IC’s tube - DSC bulk pack

Reel 13” Q1/T1

T

_amb= 40 C to +85 C

*standard mark SMD

5. Block diagram

PCA8574

PCA8574A

INT

INTERRUPT

LOGIC

LP FILTER

A0

A1

A2

SCL

2

SHIFT

REGISTER

I/O

PORT

INPUT

FILTER

I C-BUS

8 BITS

P0 to P7

CONTROL

SDA

write pulse

read pulse

POWER-ON

RESET

V

DD

V

SS

002aac677

Fig 1. Block diagram

PCA8574_PCA8574A

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Product data sheet

Rev. 3 — 3 June 2013

3 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

V

DD

I

OH

OL

write pulse

100 µA

I

trt(pu)

D

Q

data from Shift Register

FF

S

P0 to P7

I

CI

power-on reset

V

SS

D

Q

FF

S

CI

read pulse

to interrupt logic

data to Shift Register

002aah521

Fig 2. Simplified schematic diagram of P0 to P7

6. Pinning information

6.1 Pinning

1

2

20

19

18

17

16

INT

SCL

n.c.

P7

P6

n.c.

P5

P4

3

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

A0

A1

A2

P0

P1

P2

P3

V

A0

A1

A2

P0

P1

P2

P3

V

DD

4

SDA

SCL

INT

P7

SDA

SCL

INT

P7

5

V

DD

PCA8574TS

PCA8574ATS

6

15

14

13

12

11

A0

A1

V

SS

PCA8574D

PCA8574AD

PCA8574PW

PCA8574APW

7

P3

n.c.

P2

P1

8

n.c.

A2

P6

9

P5

10

P0

V

SS

P4

V

SS

P4

002aac678

002aac941

002aac680

Fig 3. Pin configuration for SO16

Fig 4. Pin configuration for

TSSOP16

Fig 5. Pin configuration for

SSOP20

PCA8574_PCA8574A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 3 June 2013

4 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

6.2 Pin description

Table 3.

Symbol

Pin description

Description

DIP16, SO16 SSOP20

A0

1

6

address input 0

A1

2

7

address input 1

A2

3

9

address input 2

P0

4

10

11

12

14

15

16

17

19

20

1

quasi-bidirectional I/O 0

quasi-bidirectional I/O 1

quasi-bidirectional I/O 2

quasi-bidirectional I/O 3

supply ground

P1

5

P2

6

P3

7

V_SS

P4

8

9

quasi-bidirectional I/O 4

quasi-bidirectional I/O 5

quasi-bidirectional I/O 6

quasi-bidirectional I/O 7

interrupt output (active LOW)

serial clock line

P5

10

11

12

13

14

15

16

-

P6

P7

INT

SCL

SDA

V_DD

n.c.

2

4

serial data line

5

supply voltage

3, 8, 13, 18 not connected

7. Functional description

Refer to Figure 1 “Block diagram”.

7.1 Device address

Following a START condition, the bus master must send the address of the slave it is

accessing and the operation it wants to perform (read or write). The address format of the

PCA8574/74A is shown in Figure 6. Slave address pins A2, A1 and A0 are held HIGH or

LOW to choose one of eight slave addresses. To conserve power, no internal pull-up

resistors are incorporated on pins A2, A1, or A0 so they must be externally held HIGH or

LOW. The address pins (A2, A1, A0) can connect to V_DDor V_SSdirectly or through

resistors.

R/W

0

R/W

0

slave address

0

1

0

A2 A1 A0

0

1

A2 A1 A0

fixed

hardware

selectable

fixed

hardware

selectable

002aah469

002aah470

a. PCA8574

b. PCA8574A

Fig 6. PCA8574 and PCA8574A slave addresses

PCA8574_PCA8574A

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Product data sheet

Rev. 3 — 3 June 2013

5 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

The last bit of the first byte defines the operation to be performed. When set to logic 1 a

read is selected, while a logic 0 selects a write operation (write operation is shown in

Figure 6).

7.1.1 Address maps

The PCA8574 and PCA8574A are functionally the same, but have a different fixed portion

(A6 to A3) of the slave address. This allows eight of the PCA8574 and eight of the

PCA8574A to be on the same I²C-bus without address conflict.

Table 4.

Pin connectivity

A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W

PCA8574 address map

Address of PCA8574

Address byte value

7-bit

hexadecimal

address

Write

Read

without R/W

V_SSV_SSV_SS

V_SSV_SSV_DD

V_SSV_DDV_SS

V_SSV_DDV_DD

V_DDV_SSV_SS

V_DDV_SSV_DD

V_DDV_DDV_SS

V_DDV_DDV_DD

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

-

40h

42h

44h

46h

48h

4Ah

4Ch

4Eh

41h

43h

45h

47h

49h

4Bh

4Dh

4Fh

20h

21h

22h

23h

24h

25h

26h

27h

Table 5.

PCA8574A address map

Pin connectivity

Address of PCA8574A

Address byte value

7-bit

hexadecimal

address

A2

A1

A0 A6 A5 A4 A3 A2 A1 A0 R/W

Write

Read

without R/W

V_SSV_SSV_SS

V_SSV_SSV_DD

V_SSV_DDV_SS

V_SSV_DDV_DD

V_DDV_SSV_SS

V_DDV_SSV_DD

V_DDV_DDV_SS

V_DDV_DDV_DD

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

-

70h

72h

74h

76h

78h

7Ah

7Ch

7Eh

71h

73h

75h

77h

79h

7Bh

7Dh

7Fh

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

PCA8574_PCA8574A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 3 June 2013

6 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

8. I/O programming

8.1 Quasi-bidirectional I/Os

A quasi-bidirectional I/O is an input or output port without using a direction control register.

Whenever the master reads the register, the value returned to master depends on the

actual voltage or status of the pin. At power-on, all the ports are HIGH with a weak 100 A

internal pull-up to V_DD, but can be driven LOW by an internal transistor, or an external

signal. The I/O ports are entirely independent of each other, but each I/O octal is

controlled by the same read or write data byte.

Advantages of the quasi-bidirectional I/O over totem pole I/O include:

• Better for driving LEDs since the p-channel (transistor to V_DD) is small, which saves

die size and therefore cost. LED drive only requires an internal transistor to ground,

while the LED is connected to V_DDthrough a current-limiting resistor. Totem pole I/O

have both n-channel and p-channel transistors, which allow solid HIGH and LOW

output levels without a pull-up resistor — good for logic levels.

• Simpler architecture — only a single register and the I/O can be both input and output

at the same time. Totem pole I/O have a direction register that specifies the port pin

direction and it is always in that configuration unless the direction is explicitly

changed.

• Does not require a command byte. The simplicity of one register (no need for the

pointer register or, technically, the command byte) is an advantage in some

embedded systems where every byte counts because of memory or bandwidth

limitations.

There is only one register to control four possibilities of the port pin: Input HIGH, input

LOW, output HIGH, or output LOW.

Input HIGH: The master needs to write 1 to the register to set the port as an input mode

if the device is not in the default power-on condition. The master reads the register to

check the input status. If the external source pulls the port pin up to V_DDor drives

logic 1, then the master will read the value of 1.

Input LOW: The master needs to write 1 to the register to set the port to input mode if

the device is not in the default power-on condition. The master reads the register to

check the input status. If the external source pulls the port pin down to V_SSor drives

logic 0, which sinks the weak 100 A current source, then the master will read the value

of 0.

Output HIGH: The master writes 1 to the register. There is an additional ‘accelerator’ or

strong pull-up current when the master sets the port HIGH. The additional strong pull-up

is only active during the HIGH time of the acknowledge clock cycle. This accelerator

current helps the port’s 100 A current source make a faster rising edge into a heavily

loaded output, but only at the start of the acknowledge clock cycle to avoid bus

contention if an external signal is pulling the port LOW to V_SS/driving the port with

logic 0 at the same time. After the half clock cycle there is only the 100 A current

source to hold the port HIGH.

Output LOW: The master writes 0 to the register. There is a strong current sink

transistor that holds the port pin LOW. A large current may flow into the port, which

could potentially damage the part if the master writes a 0 to the register and an external

source is pulling the port HIGH at the same time.

PCA8574_PCA8574A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 3 June 2013

7 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

V

DD

input HIGH

pull-up with

weak 100 µA

current source

(inactive when

output LOW)

output HIGH

resistor to V

or

DD

external drive HIGH

accelerator

pull-up

P port

P7 - P0

pull-down with

output LOW

resistor to V or

SS

external drive LOW

input LOW

V

SS

002aah683

Fig 7. Simple quasi-bidirectional I/O

8.2 Writing to the port (Output mode)

The master (microcontroller) sends the START condition and slave address setting the

last bit of the address byte to logic 0 for the write mode. The PCA8574/74A acknowledges

and the master then sends the data byte for P7 to P0 to the port register. As the clock line

goes HIGH, the 8-bit data is presented on the port lines after it has been acknowledged by

the PCA8574/74A. If a LOW is written, the strong pull-down turns on and stays on. If a

HIGH is written, the strong pull-up turns on for ¹⁄₂of the clock cycle, then the line is held

HIGH by the weak current source. The master can then send a STOP or ReSTART

condition or continue sending data. The number of data bytes that can be sent

successively is not limited and the previous data is overwritten every time a data byte has

been sent and acknowledged.

Ensure a logic 1 is written for any port that is being used as an input to ensure the strong

external pull-down is turned off.

SCL

1

2

3

4

5

6

7

8

9

slave address

data 1

data 2

SDA

S

A6 A5 A4 A3 A2 A1 A0

0

A

P7 P6

1

P4 P3 P2 P1 P0

A

P7 P6

0

P4 P3 P2 P1 P0

A

P5

START condition

write to port

R/W

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

t

v(Q)

data output from port

P5 output voltage

DATA 1 VALID

DATA 2 VALID

I

trt(pu)

P5 pull-up output current

INT

I

OH

t

rst(INT)

002aah623

Fig 8. Write mode (output)

PCA8574_PCA8574A

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Product data sheet

Rev. 3 — 3 June 2013

8 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

Simple code WRITE mode:

<S> <slave address + write> <ACK> <data out> <ACK> <data out> <ACK> ...

Remark: Bold type = generated by slave device.

8.3 Reading from a port (Input mode)

The port must have been previously written to logic 1, which is the condition after

power-on reset. To enter the Read mode the master (microcontroller) addresses the slave

device and sets the last bit of the address byte to logic 1 (address byte read). The slave

will acknowledge and then send the data byte to the master. The master will NACK and

then send the STOP condition or ACK and read the input register again.

The read of any pin being used as an output will indicate HIGH or LOW depending on the

actual state of the input pin.

If the data on the input port changes faster than the master can read, this data may be

lost. The DATA 2 and DATA 3 are lost because these data did not meet the setup time and

hold time (see Figure 9).

no acknowledge

from master

slave address

data from port

DATA 1

data from port

DATA 4

SDA

S

A6 A5 A4 A3 A2 A1 A0

1

A

1

P

START condition

R/W acknowledge

from slave

acknowledge

from master

STOP

condition

read from

port

DATA 2

data at

port

DATA 1

DATA 3

DATA 4

t

su(D)

h(D)

INT

t

rst(INT)

v(INT)

rst(INT)

002aah383

A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at

any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input

data is lost.

Fig 9. Read mode (input)

Simple code for Read mode:

<NACK>

Remark: Bold type = generated by slave device.

PCA8574_PCA8574A

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Product data sheet

Rev. 3 — 3 June 2013

9 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

8.4 Power-on reset

When power is applied to V_DD, an internal Power-On Reset (POR) holds the PCA8574;

PCA8574A in a reset condition until V_DDhas reached V_POR. At that point, the reset

condition is released and the PCA8574; PCA8574A registers and I²C-bus/SMBus state

machine will initialize to their default states of all I/Os to inputs with weak current source to

V

_DD. Thereafter V_DDmust be lowered below V_PORand back up to the operation voltage for

power-on reset cycle.

8.5 Interrupt output (INT)

The PCA8574/74A provides an open-drain output (INT) which can be fed to a

corresponding input of the microcontroller (see Figure 10). As soon as a port input is

changed, the INT will be active (LOW) and notify the microcontroller.

An interrupt is generated at any rising or falling edge of the port inputs. After time t_v(Q), the

signal INT is valid.

The interrupt will reset to HIGH when data on the port is changed to the original setting or

data is read or written by the master.

In the Write mode, the interrupt may be reset (HIGH) on the rising edge of the

acknowledge bit of the data byte and also on the rising edge of the write to port pulse. The

interrupt will always be reset (HIGH) on the falling edge of the write to port pulse (see

Figure 8).

The interrupt is reset (HIGH) in the Read mode on the rising edge of the acknowledge of

slave address byte and on the rising edge of the read from port pulse (see Figure 9).

During the interrupt reset, any I/O change close to the read or write pulse may not

generate an interrupt, or the interrupt will have a very short pulse. After the interrupt is

reset, any change in I/Os will be detected and transmitted as an INT.

At power-on reset all ports are in Input mode and the initial state of the ports is HIGH,

therefore, for any port pin that is pulled LOW or driven LOW by external source, the

interrupt output will be active (output LOW).

V

DD

device 1

device 2

device 16

PCA8574

PCA8574A

MICROCONTROLLER

INT

002aac682

Fig 10. Application of multiple PCA8574/74As with interrupt

PCA8574_PCA8574A

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Product data sheet

Rev. 3 — 3 June 2013

10 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

9. Characteristics of the I²C-bus

The I²C-bus is for 2-way, 2-wire communication between different ICs or modules. The

two wires are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 11).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 11. Bit transfer

9.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P) (see Figure 12).

SDA

SCL

S

P

STOP condition

START condition

mba608

Fig 12. Definition of START and STOP conditions

9.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 13).

PCA8574_PCA8574A

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Product data sheet

Rev. 3 — 3 June 2013

11 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

SDA

SCL

SLAVE

TRANSMITTER/

RECEIVER

MASTER

2

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

I C-BUS

TRANSMITTER/

RECEIVER

MULTIPLEXER

SLAVE

002aaa966

Fig 13. System configuration

9.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit (see Figure 14). The acknowledge bit is an active LOW level (generated

by the receiving device) that indicates to the transmitter that the data transfer was

successful.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that wants to issue an

acknowledge bit has to pull down the SDA line during the acknowledge clock pulse, so

that the SDA line is stable LOW during the HIGH period of the acknowledge bit related

clock pulse; set-up and hold times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from master

1

2

8

9

S

clock pulse for

START

condition

acknowledgement

002aaa987

Fig 14. Acknowledgement on the I²C-bus

PCA8574_PCA8574A

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Product data sheet

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PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

10. Application design-in information

10.1 Bidirectional I/O expander applications

In the 8-bit I/O expander application shown in Figure 15, P0 and P1 are inputs, and

P2 to P7 are outputs. When used in this configuration, during a write, the input (P0 and

P1) must be written as HIGH so the external devices fully control the input ports.

The desired HIGH or LOW logic levels may be written to the ports used as outputs (P2 to

P7). If 10 A internal output HIGH is not enough current source, the port needs external

pull-up resistor. During a read, the logic levels of the external devices driving the input

ports (P0 and P1) and the previous written logic level to the output ports (P2 to P7) will be

read.

The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of

the microcontroller. By sending an interrupt signal on this line, the remote I/O informs the

microprocessor that there has been a change of data on its ports without having to

communicate via the I²C-bus.

V

DD

V

DD

V

DD

SDA

SCL

INT

P0

P1

P2

P3

P4

P5

P6

P7

temperature sensor

battery status

CORE

PROCESSOR

control for latch

control for switch

control for audio

control for camera

control for MP3

A0

A1

A2

002aah625

Fig 15. Bidirectional I/O expander application

10.2 How to read and write to I/O expander (example)

In the application example of PCA8574 shown in Figure 15, the microcontroller wants to

control the P3 switch ON and the P7 LED ON when the temperature sensor P0 changes.

1. When the system power on:

Core Processor needs to issue an initial command to set P0 and P1 as inputs and

P[7:2] as outputs with value 1010 00 (LED off, MP3 off, camera on, audio off,

switch off and latch off).

2. Operation:

When the temperature changes above the threshold, the temperature sensor signal

will toggle from HIGH to LOW. The INT will be activated and notifies the ‘core

processor’ that there have been changes on the input pins. Read the input register.

If P0 = 0 (temperature sensor has changed), then turn on LED and turn on switch.

3. Software code:

//System Power on

// write to PCA8574 with data 1010 0011b to set P[7:2] outputs and P[1:0] inputs

<S> <0100 0000> <ACK> <1010 0011> <ACK> //Initial setting for PCA8574

PCA8574_PCA8574A

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Product data sheet

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13 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

while (INT == 1); //Monitor the interrupt pin. If INT

//When INT then read input ports

= 1 do nothing

=

0

<S> <slave address read> <ACK> <1010 0010> <NACK> //Read PCA8574 data

If (P0 == 0) //Temperature sensor activated

{

// write to PCA8574 with data 0010 1011b to turn on LED (P7), on Switch (P3)

and keep P[1:0] as input ports.

<S> <0100 0000> <ACK> <0010 1011> <ACK> // Write to PCA8574

}

10.3 High current-drive load applications

The GPIO has a minimum guaranteed sinking current of 25 mA per bit at 4.5 V. In

applications requiring additional drive, two port pins may be connected together to sink up

to 50 mA current. Both bits must then always be turned on or off together. Up to 8 pins can

be connected together to drive 200 mA, which is the device recommended total limit.

Each pin needs its own limiting resistor as shown in Figure 16 to prevent damage to the

device should all ports not be turned on at the same time.

V

DD

V

DD

SDA

SCL

INT

P0

P1

P2

P3

P4

P5

P6

P7

CORE

PROCESSOR

LOAD

A0

A1

A2

002aah472

Fig 16. High current-drive load application

10.4 Migration path

NXP offers newer, more capable drop-in replacements for the PCF8574/74A in newer

space-saving packages.

Table 6.

Migration path

Type number

I²C-bus

frequency

Voltage range

Number of

addresses

per device

Interrupt

Reset

Total package

sink current

PCF8574/74A

PCA8574/74A

PCA9674/74A

PCA9670

100 kHz

2.5 V to 6 V

8

yes

no

80 mA

400 kHz

2.3 V to 5.5 V

8

no

200 mA

1 MHz Fm+

64

16

no

yes

PCA9672

yes

PCA9670 replaces the interrupt output of the PCA9674 with a hardware reset input to

retain the maximum number of addresses. The PCA9672 replaces address A2 of the

PCA9674 with a hardware reset input to retain the interrupt, but limit the number of

addresses.

PCA8574_PCA8574A

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Product data sheet

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14 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

11. Limiting values

Table 7.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

I_DD

Parameter

Conditions

Min

Max

+6

Unit

V

supply voltage

0.5

supply current

-

100

400

mA

V

I_SS

ground supply current

input voltage

V_I

V_SS 0.5 5.5

I_I

input current

-

20

50

400

100

125

+150

+85

mA

mW

C

[1]

I_O

output current

-

P_tot

total power dissipation

power dissipation per output

maximum junction temperature

storage temperature

ambient temperature

-

P/out

T_j(max)

T_stg

T_amb

-

65

40

C

operating

C

[1] Total package (maximum) output current is 400 mA.

12. Thermal characteristics

Table 8.

Thermal characteristics

Parameter

Symbol

Conditions

Typ

Unit

R_th(j-a)

thermal resistance from junction SO16 package

to ambient

115

160

136

C/W

TSSOP16 package

SSOP20 package

PCA8574_PCA8574A

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Product data sheet

Rev. 3 — 3 June 2013

15 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

13. Static characteristics

Table 9.

Static characteristics

V_DD= 2.3 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

supply voltage

supply current

2.3

-

5.5

V

I_DD

Operating mode; no load;

V_I= V_DDor V_SS; f_SCL= 400 kHz;

A0, A1, A2 = static H or L

200

500

A

I_stb

standby current

Standby mode; no load;

V_I= V_DDor V_SS; f_SCL= 0 kHz

-

4.5

1.8

10

A

[1]

V_POR

power-on reset voltage

2.0

V

Input SCL; input/output SDA

V_IL

V_IH

I_OL

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

0.5

0.7V_DD

20

-

+0.3V_DD

V

-

5.5

-

V

V_OL= 0.4 V; V_DD= 2.3 V

V_OL= 0.4 V; V_DD= 3.0 V

V_OL= 0.4 V; V_DD= 4.5 V

V_I= V_DDor V_SS

35

44

57

-

mA

A

pF

25

-

30

-

I_L

leakage current

1

+1

10

C_i

input capacitance

V_I= V_SS

-

5

I/Os; P0 to P7

V_IL

V_IH

I_OL

LOW-level input voltage

0.5

-

+0.3V_DD

V

HIGH-level input voltage

LOW-level output current

0.7V_DD

-

5.5

V

[2]

V_OL= 0.5 V; V_DD= 2.3 V

V_OL= 0.5 V; V_DD= 3.0 V

V_OL= 0.5 V; V_DD= 4.5 V

V_OH= V_SS

12

17

25

-

26

33

40

-

mA

A

mA

pF

-

I_OL(tot)

I_OH

I_trt(pu)

C_i

total LOW-level output current

HIGH-level output current

200

300

-

30

0.5

-

138

1.0

2.1

transient boosted pull-up current V_OH= V_SS; see Figure 8

input capacitance

[3]

10

C_o

output capacitance

-

Interrupt INT (see Figure 8 and Figure 9)

I_OL

C_o

LOW-level output current

output capacitance

V_OL= 0.4 V

3.0

-

mA

pF

3

5

Inputs A0, A1, A2

V_IL

V_IH

I_LI

LOW-level input voltage

0.5

0.7V_DD

1

-

+0.3V_DD

V

HIGH-level input voltage

input leakage current

input capacitance

-

5.5

+1

5

V

-

A

pF

C_i

-

3.5

[1] The power-on reset circuit resets the I²C-bus logic with V_DD< V_PORand sets all I/Os to logic 1 (with current source to V_DD).

[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits.

[3] The value is not tested, but verified on sampling basis.

PCA8574_PCA8574A

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Product data sheet

Rev. 3 — 3 June 2013

16 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

14. Dynamic characteristics

Table 10. Dynamic characteristics

V

_DD= 2.3 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; unless otherwise specified. Limits are for Fast-mode I²C-bus.

Symbol Parameter

Conditions

Min

0

Typ

Max

400

-

Unit

kHz

s

f_SCL

t_BUF

SCL clock frequency

-

bus free time between a STOP and START

condition

1.3

t_HD;STA

t_SU;STA

t_SU;STO

t_HD;DAT

t_VD;ACK

t_VD;DAT

t_SU;DAT

t_LOW

hold time (repeated) START condition

set-up time for a repeated START condition

set-up time for STOP condition

data hold time

0.6

-

s

ns

s

ns

s

ns

0.6

-

0.6

-

0

-

[1]

[2]

data valid acknowledge time

data valid time

0.1

0.9

50

-

data set-up time

100

-

LOW period of the SCL clock

HIGH period of the SCL clock

fall time of both SDA and SCL signals

rise time of both SDA and SCL signals

1.3

-

t_HIGH

t_f

0.6

-

[3][4]

[6]

[5]

20 + 0.1C_b

-

300

50

t_r

t_SP

pulse width of spikes that must be

suppressed by the input filter

Port timing; C_L 100 pF (see Figure 8 and Figure 9)

t_v(Q)

t_su(D)

t_h(D)

data output valid time

data input set-up time

data input hold time

-

4

-

s

0

4

-

Interrupt timing; C_L 100 pF (see Figure 8 and Figure 9)

t_v(INT)

valid time on pin INT

reset time on pin INT

from port to INT

from SCL to INT

-

4

s

t_rst(INT)

[1] t_VD;ACK= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[2] t_VD;DAT= minimum time for SDA data out to be valid following SCL LOW.

[3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_ILof the SCL signal) in order to

bridge the undefined region SCL’s falling edge.

[4] The maximum t_ffor the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t_fis specified at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum specified t_f.

[5] C_b= total capacitance of one bus line in pF.

[6] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

PCA8574_PCA8574A

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Product data sheet

Rev. 3 — 3 June 2013

17 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

START

condition

(S)

bit 7

MSB

(A7)

STOP

condition

(P)

bit 6

(A6)

bit 0

(R/W)

acknowledge

(A)

protocol

t

HIGH

SU;STA

LOW

1 / f

SCL

0.7 × V

0.3 × V

DD

SCL

SDA

DD

t

BUF

f

t

r

0.7 × V

0.3 × V

DD

t

HD;DAT

VD;DAT

VD;ACK

SU;STO

HD;STA

SU;DAT

002aab175

Rise and fall times refer to V_ILand V_IH.

Fig 17. I²C-bus timing diagram

PCA8574_PCA8574A

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Product data sheet

Rev. 3 — 3 June 2013

18 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

15. Package outline

SO16: plastic small outline package; 16 leads; body width 7.5 mm

SOT162-1

D

E

A

X

c

H

v

M

A

E

y

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

detail X

e

w

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

10.5

10.1

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25 0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.41

0.014 0.009 0.40

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT162-1

075E03

MS-013

Fig 18. Package outline SOT162-1 (SO16)

PCA8574_PCA8574A

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Product data sheet

Rev. 3 — 3 June 2013

19 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT403-1

MO-153

Fig 19. Package outline SOT403-1 (TSSOP16)

PCA8574_PCA8574A

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Product data sheet

Rev. 3 — 3 June 2013

20 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm

SOT266-1

D

E

A

X

c

y

H

v

M

A

E

Z

11

20

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

10^o

0^o

0.15

0

1.4

1.2

0.32

0.20

0.13

6.6

6.4

4.5

4.3

6.6

6.2

0.75

0.45

0.65

0.45

0.48

0.18

mm

1.5

0.65

1

0.2

0.25

0.13

0.1

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT266-1

MO-152

Fig 20. Package outline SOT266-1 (SSOP20)

PCA8574_PCA8574A

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Product data sheet

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21 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate precautions are taken as

described in JESD625-A or equivalent standards.

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

PCA8574_PCA8574A

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Product data sheet

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PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

17.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 21) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 11 and 12

Table 11. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 12. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 21.

PCA8574_PCA8574A

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Product data sheet

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23 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 21. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

PCA8574_PCA8574A

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Product data sheet

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24 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

18. Soldering: PCB footprints

Footprint information for reflow soldering of SO16 package

SOT162-1

Hx

Gx

P2

(0.125)

Hy Gy

By Ay

C

D2 (4x)

P1

D1

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ay

By

C

D1

D2

Gx

Gy

Hx

Hy

1.270 1.320 11.200 6.400 2.400 0.700 0.800 10.040 8.600 11.900 11.450

sot162-1_fr

Fig 22. PCB footprint for SOT162-1 (SO16); reflow soldering

PCA8574_PCA8574A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 3 June 2013

25 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

Footprint information for reflow soldering of TSSOP16 package

SOT403-1

Hx

Gx

P2

(0.125)

Hy Gy

By Ay

C

D2 (4x)

P1

D1

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ay

By

C

D1

D2

Gx

Gy

Hx

Hy

0.650 0.750 7.200 4.500 1.350 0.400 0.600 5.600 5.300 5.800 7.450

sot403-1_fr

Fig 23. PCB footprint for SOT403-1 (TSSOP16); reflow soldering

PCA8574_PCA8574A

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Product data sheet

Rev. 3 — 3 June 2013

26 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

Footprint information for reflow soldering of SSOP20 package

SOT266-1

Hx

Gx

(0.125)

P2

(0.125)

Hy

Gy

By

Ay

C

D2 (4x)

P1

D1

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ay

By

C

D1

D2

Gx

Gy

Hx

Hy

0.650 0.750 7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.300 7.450

sot266-1_fr

Fig 24. PCB footprint for SOT266-1 (SSOP20); reflow soldering

PCA8574_PCA8574A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 3 June 2013

27 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

19. Abbreviations

Table 13. Abbreviations

Acronym

CDM

CMOS

ESD

FF

Description

Charged-Device Model

Complementary Metal Oxide Semiconductor

ElectroStatic Discharge

Flip-Flop

GPIO

HBM

I/O

General Purpose Input/Output

Human Body Model

Input/Output

I²C-bus

Inter-Integrated Circuit bus

Integrated Circuit

IC

LED

Light Emitting Diode

Low-Pass

LP

LSB

Least Significant Bit

Most Significant Bit

MSB

PLC

Programmable Logic Controller

Power-On Reset

POR

SMBus

System Management Bus

20. Revision history

Table 14. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

PCA8574_PCA8574A v.3 20130603

Product data sheet

-

PCA8574_PCA8574A v.2

Modifications:

• Section 1 “General description” re-written

• Section 2 “Features and benefits”

–

added (new) first bullet item

appended “(Fast-mode I²C-bus)” to second bullet item

added (new) third bullet item

(new) fifth bullet item changed from “50 mA sink capability” to “25 mA sink capability”

deleted (old) eighth bullet item, “Readable device ID (manufacturer, device type, and

revision)”

–

12th bullet item: deleted phrase “200 V MM per JESD22-A115”

14th bullet item: deleted “DIP16”

• Table 1 “Ordering information”:

–

deleted discontinued DIP16 package option (PCA8574N, PCA8574AN)

Topside mark for PCA8574ATS corrected from “PCA8574A” to “PA8574A”

added Table note [1], Table note [2], Table note [3] and Table note [4]

• Added (new) Table 2 “Ordering options”

• Figure 1 “Block diagram” modified: switched positions of blocks “INTERRUPT LOGIC” and

“LP FILTER”

• Figure 2 “Simplified schematic diagram of P0 to P7” modified: removed diode between

“V_DD” and “P0 to P7” signal lines

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Product data sheet

Rev. 3 — 3 June 2013

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PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

Table 14. Revision history …continued

Document ID

Release date

Data sheet status

Change notice

Supersedes

Modifications: (continued)

• Section 6.1 “Pinning”:

–

deleted (old) Figure 3, “Pin configuration for DIP16”

pin names changed from “AD0, AD1, AD2” to “A0, A1, A2”, respectively

• Section 6.2 “Pin description”: (old) Table 3, “Pin description for SO16, TSSOP16” and (old)

Table 4, “Pin description for SSOP20” are merged in (new) Table 3 “Pin description”

• Section 7.1 “Device address” re-written

• Section 7.1.1 “Address maps” re-written

• Section 8.1 “Quasi-bidirectional I/Os” re-written

• Section 8.2 “Writing to the port (Output mode)” re-written

• Figure 8 “Write mode (output)”: timing measurement symbol corrected from “t_d(rst)” to

“t_rst(INT)

”

• Section 8.3 “Reading from a port (Input mode)” re-written

• Figure 9 “Read mode (input)”:

–

timing measurement symbol corrected from “t_v(D)” to “t_v(INT)

”

–

timing measurement symbol corrected from “t_d(rst)” to “t_rst(INT)

”

• Section 8.4 “Power-on reset”: second and third sentences re-written

• Figure 9 “Read mode (input)” modified: corrected label from “data into port” to “data at port”

• Section 8.5 “Interrupt output (INT)”, fourth, fifth and sixth paragraphs re-written; added new

seventh paragraph

• Figure 10 “Application of multiple PCA8574/74As with interrupt” updated

(changed from “device 8, PCA8574” to “device 16, PCA8574A”)

• Added (new) Section 10.2 “How to read and write to I/O expander (example)”

• Section 10.3 “High current-drive load applications”:

–

1st sentence changed from “maximum sinking current of 25 mA per bit”

to “minimum guaranteed sinking current of 25 mA per bit at 4.5 V”

–

4th sentence changed from “device total limit” to “device recommended total limit”

• Figure 16 “High current-drive load application” modified: added resistor on P6 and P7 signal

lines

• Added (new) Section 10.4 “Migration path”

• Table 7 “Limiting values”: added T_j(max)limits

• Added Section 12 “Thermal characteristics”

• Table 9 “Static characteristics”, sub-section “I/Os; P0 to P7”: added V_ILand V_IH

characteristics

• Table 10 “Dynamic characteristics”, sub-section “Interrupt timing”:

–

symbol/parameter corrected from “t_v(D), data input valid time”

to “t_v(INT), valid time on pin INT”

–

symbol/parameter corrected from “t_d(rst), reset delay time”

to “t_rst(INT), reset time on pin INT”

• Figure 17 “I²C-bus timing diagram” updated: added 0.3  V_DDand 0.7  V_DDreference lines

• Deleted (old) Figure 18, “Package outline SOT38-1 (DIP16)”

• Updated soldering information

• Added Section 18 “Soldering: PCB footprints”

PCA8574_PCA8574A v.2 20070514

Product data sheet

-

PCA8574_PCA8574A v.1

-

PCA8574_PCA8574A v.1 20070117

Product data sheet

-

PCA8574_PCA8574A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 3 June 2013

29 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

21. Legal information

21.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

21.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

21.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

PCA8574_PCA8574A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 3 June 2013

30 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

21.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP B.V.

22. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCA8574_PCA8574A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 3 June 2013

31 of 32

PCA8574; PCA8574A

NXP Semiconductors

Remote 8-bit I/O expander for I²C-bus with interrupt

23. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

21.1

21.2

21.3

21.4

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3

4

4.1

5

22

23

Contact information . . . . . . . . . . . . . . . . . . . . 31

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7

Functional description . . . . . . . . . . . . . . . . . . . 5

Device address. . . . . . . . . . . . . . . . . . . . . . . . . 5

Address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.1

7.1.1

8

I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 7

Quasi-bidirectional I/Os . . . . . . . . . . . . . . . . . . 7

Writing to the port (Output mode) . . . . . . . . . . . 8

Reading from a port (Input mode) . . . . . . . . . . 9

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10

Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 10

8.1

8.2

8.3

8.4

8.5

9

Characteristics of the I²C-bus . . . . . . . . . . . . 11

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

START and STOP conditions . . . . . . . . . . . . . 11

System configuration . . . . . . . . . . . . . . . . . . . 11

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 12

9.1

9.1.1

9.2

9.3

10

10.1

10.2

Application design-in information . . . . . . . . . 13

Bidirectional I/O expander applications . . . . . 13

How to read and write to I/O expander

(example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

High current-drive load applications . . . . . . . . 14

Migration path. . . . . . . . . . . . . . . . . . . . . . . . . 14

10.3

10.4

11

12

13

14

15

16

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15

Thermal characteristics . . . . . . . . . . . . . . . . . 15

Static characteristics. . . . . . . . . . . . . . . . . . . . 16

Dynamic characteristics . . . . . . . . . . . . . . . . . 17

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19

Handling information. . . . . . . . . . . . . . . . . . . . 22

17

Soldering of SMD packages . . . . . . . . . . . . . . 22

Introduction to soldering . . . . . . . . . . . . . . . . . 22

Wave and reflow soldering . . . . . . . . . . . . . . . 22

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 22

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 23

17.1

17.2

17.3

17.4

18

19

20

21

Soldering: PCB footprints. . . . . . . . . . . . . . . . 25

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 28

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 28

Legal information. . . . . . . . . . . . . . . . . . . . . . . 30

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 June 2013

Document identifier: PCA8574_PCA8574A


型号：	PCA8574TS,118
厂家：	NXP
描述：	PCA8574/74A - Remote 8-bit I/O expander for I²C-bus with interrupt SSOP2 20-Pin PC 光电二极管外围集成电路
文件：	总32页 (文件大小：1030K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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