PCA8575DK_技术文档

PCA8575

Remote 16-bit I/O expander for I²C-bus with interrupt

Rev. 01 — 30 November 2006

Objective data sheet

1. General description

The PCA8575 provides general purpose remote I/O expansion for most microcontroller

families via the two-line bidirectional I²C-bus (serial clock (SCL), serial data (SDA)).

The device consists of a 16-bit quasi-bidirectional port and an I²C-bus interface. The

PCA8575 has a low current consumption and includes latched outputs with high current

drive capability for directly driving LEDs.

The PCA8575 also possesses an interrupt line (INT) which can be connected to the

interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote

I/O can inform the microcontroller if there is incoming data on its ports without having to

communicate via the I²C-bus. The internal Power-On Reset (POR) initializes the I/Os as

inputs.

2. Features

I 400 kHz I²C-bus interface

I 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os

I 16-bit remote I/O pins that default to inputs at power-up

I Latched outputs with 25 mA sink capability for directly driving LEDs

I Total package sink capability of 400 mA

I Active LOW open-drain interrupt output

I 8 programmable slave addresses using 3 address pins

I Readable device ID (manufacturer, device type, and revision)

I Low standby current (10 µA max.)

I −40 °C to +85 °C operation

I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

I Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA

I Packages offered: SO24, SSOP24 (QSOP24), TSSOP24, HVQFN24, DHVQFN24

3. Applications

I LED signs and displays

I Servers

I Industrial control

I Medical equipment

I PLCs

I Cellular telephones

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

I Gaming machines

I Instrumentation and test measurement

4. Ordering information

Table 1.

Ordering information

Type number Topside

mark

Package

Name

Description

Version

PCA8575D

PCA8575DB

PCA8575DK

PCA8575D

SO24

plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

PCA8575DB SSOP24

plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1

PCA8575

SSOP24^[1]plastic shrink small outline package; 24 leads;

SOT556-1

SOT355-1

SOT815-1

body width 3.9 mm; lead pitch 0.635 mm

PCA8575PW PCA8575PW TSSOP24

plastic thin shrink small outline package; 24 leads;

body width 4.4 mm

PCA8575BQ 8575

PCA8575BS 8575

DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad

ﬂat package; no leads; 24 terminals; body 3.5 × 5.5 × 0.85 mm

HVQFN24 plastic thermal enhanced very thin quad ﬂat package; no leads; SOT616-1

24 terminals; body 4 × 4 × 0.85 mm

[1] Also known as QSOP24.

5. Block diagram

PCA8575

INTERRUPT

LOGIC

LP FILTER

INT

AD0

AD1

AD2

P00 to P07

P10 to P17

SCL

SDA

2

SHIFT

REGISTER

I/O

PORT

INPUT

FILTER

I C-BUS

CONTROL

16 BITS

write pulse

read pulse

POWER-ON

RESET

V

DD

V

SS

002aac669

Fig 1. Block diagram of PCA8575

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

2 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

V

DD

I

OH

OL

write pulse

100 µA

I

trt(pu)

D

Q

data from Shift Register

P00 to P07

P10 to P17

FF

S

I

CI

power-on reset

V

SS

D

Q

FF

S

CI

read pulse

to interrupt logic

data to Shift Register

002aab631

Fig 2. Simpliﬁed schematic diagram of P00 to P17

6. Pinning information

6.1 Pinning

1

2

24

23

22

21

20

19

18

17

16

15

14

13

1

24

23

22

21

20

19

18

17

16

15

14

13

INT

AD1

AD2

P00

P01

P02

P03

P04

P05

P06

P07

V

INT

AD1

AD2

P00

P01

P02

P03

P04

P05

P06

P07

V

DD

2

3

SDA

SCL

AD0

P17

P16

P15

P14

P13

P12

P11

P10

SDA

SCL

AD0

P17

P16

P15

P14

P13

P12

P11

P10

3

4

5

6

PCA8575D

PCA8575PW

7

8

9

10

11

12

10

11

12

V

SS

V

SS

002aac670

002aac671

Fig 3. Pin conﬁguration for SO24

Fig 4. Pin conﬁguration for TSSOP24

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

3 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

24

23

22

21

20

19

18

17

16

15

14

13

1

2

24

23

22

21

20

19

18

17

16

15

14

13

INT

AD1

AD2

P00

P01

P02

P03

P04

P05

P06

P07

1

2

V

INT

AD1

AD2

P00

P01

P02

P03

P04

P05

P06

P07

V

DD

SDA

SCL

AD0

P17

P16

P15

P14

P13

P12

P11

P10

SDA

SCL

AD0

P17

P16

P15

P14

P13

P12

P11

P10

3

4

5

6

PCA8575DK

PCA8575DB

7

8

9

10

11

12

10

11

12

V

SS

V

SS

002aac672

002aac673

Fig 5. Pin conﬁguration for SSOP24

(QSOP24)

Fig 6. Pin conﬁguration for SSOP24

terminal 1

index area

2

3

23

22

21

20

19

18

17

16

15

14

AD1

AD2

P00

P01

P02

P03

P04

P05

P06

P07

SDA

SCL

AD0

P17

P16

P15

P14

P13

P12

P11

terminal 1

index area

4

5

1

2

3

4

5

6

18

17

16

15

14

13

P00

P01

P02

P03

P04

P05

AD0

P17

P16

P15

P14

P13

6

PCA8575BQ

7

8

PCA8575BS

9

10

11

002aac675

002aac674

Transparent top view

Fig 7. Pin conﬁguration for HVQFN24

Fig 8. Pin conﬁguration for DHVQFN24

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

4 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

6.2 Pin description

Table 2.

Symbol

Pin description

Description

HVQFN24

SO24, SSOP24,

TSSOP24, DHVQFN24

INT

1

22

23

24

1

interrupt output (active LOW)

address input 1

AD1

AD2

P00

P01

P02

P03

P04

P05

P06

P07

V_SS

P10

P11

P12

P13

P14

P15

P16

P17

AD0

SCL

SDA

V_DD

2

3

address input 2

4

quasi-bidirectional I/O 00

quasi-bidirectional I/O 01

quasi-bidirectional I/O 02

quasi-bidirectional I/O 03

quasi-bidirectional I/O 04

quasi-bidirectional I/O 05

quasi-bidirectional I/O 06

quasi-bidirectional I/O 07

supply ground

5

2

6

3

7

4

8

5

9

6

10

11

12^[1]

13

14

15

16

17

18

19

20

21

22

23

24

7

8

9^[1]

10

11

12

13

14

15

16

17

18

19

20

21

quasi-bidirectional I/O 10

quasi-bidirectional I/O 11

quasi-bidirectional I/O 12

quasi-bidirectional I/O 13

quasi-bidirectional I/O 14

quasi-bidirectional I/O 15

quasi-bidirectional I/O 16

quasi-bidirectional I/O 17

address input 0

serial clock line input

serial data line input/output

supply voltage

[1] HVQFN and DHVQFN package die supply ground is connected to both the V_SSpin and the exposed center

pad. The V_SSpin must be connected to supply ground for proper device operation. For enhanced thermal,

electrical, and board-level performance, the exposed pad needs to be soldered to the board using a

corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias

need to be incorporated in the PCB in the thermal pad region.

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

5 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

7. Functional description

Refer to Figure 1 “Block diagram of PCA8575”.

7.1 Device address

Following a START condition, the bus master must send the address of the slave it is

accessing and the operation it wants to perform (read or write). The address of the

PCA8575 is shown in Figure 9. Slave address pins AD2, AD1, and AD0 choose 1 of

8 slave addresses. To conserve power, no internal pull-up resistors are incorporated on

AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in

Table 3 “PCA8575 address map”.

Remark: The General Call address (0000 0000b) and the Device ID address

(1111 100Xb) are reserved and cannot be used as device address. Failure to follow this

requirement will cause the PCA8575 not to acknowledge.

slave address

A6 A5 A4 A3 A2 A1 A0 R/W

programmable

002aab636

Fig 9. PCA8575 address

The last bit of the ﬁrst byte deﬁnes the operation to be performed. When set to logic 1 a

read is selected, while a logic 0 selects a write operation.

When AD2, AD1 and AD0 are held to V_DDor V_SS, the same address as the PCF8575 is

applied.

7.1.1 Address map

Table 3.

A6

PCA8575 address map

A5

1

A4

0

A3

0

A2

0

A1

0

A0

0

Address (hex)

0

20h

21h

22h

23h

24h

25h

26h

27h

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

6 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

8. I/O programming

8.1 Quasi-bidirectional I/O architecture

The PCA8575’s 16 ports (see Figure 2) are entirely independent and can be used either

as input or output ports. Input data is transferred from the ports to the microcontroller in

the Read mode (see Figure 12). Output data is transmitted to the ports in the Write mode

(see Figure 11).

Every data transmission from the PCA8575 must consist of an even number of bytes, the

ﬁrst byte will be referred to as P07 to P00, and the second byte as P17 to P10. The third

will be referred to as P07 to P00, and so on.

This quasi-bidirectional I/O can be used as an input or output without the use of a control

signal for data directions. At power-on the I/Os are HIGH. In this mode only a current

source (I_OH) to V_DDis active. An additional strong pull-up to V_DD(I_trt(pu)) allows fast rising

edges into heavily loaded outputs. These devices turn on when an output is written HIGH,

and are switched off by the negative edge of SCL. The I/Os should be HIGH before being

used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as

inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the

write mode.

Remark: If a HIGH is applied to an I/O which has been written earlier to LOW, a large

current (I_OL) will ﬂow to V_SS

.

8.2 Writing to the port (Output mode)

To write, the master (microcontroller) ﬁrst addresses the slave device. By setting the last

bit of the byte containing the slave address to logic 0 the Write mode is entered. The

PCA8575 acknowledges and the master sends the ﬁrst data byte for P07 to P00. After the

ﬁrst data byte is acknowledged by the PCA8575, the second data byte P17 to P10 is sent

by the master. Once again, the PCA8575 acknowledges the receipt of the data. Each 8-bit

data is presented on the port lines after it has been acknowledged by the PCA8575.

The number of data bytes that can be sent successively is not limited. After every two

bytes, the previous data is overwritten.

The ﬁrst data byte in every pair refers to Port 0 (P07 to P00), whereas the second data

byte in every pair refers to Port 1 (P17 to P10). See Figure 10.

first byte

second byte

07 06 05 04 03 02 01 00

P07 P06 P05 P04 P03 P02 P01 P00

A

17 16 15 14 13 12 11 10

P17 P16 P15 P14 P13 P12 P11 P10

A

002aab634

Fig 10. Correlation between bits and ports

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

7 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

SCL

1

2

3

4

5

6

7

8

9

slave address

A6 A5 A4 A3 A2 A1 A0

data to port 0

data to port 1

P

SDA

S

0

A

1

A

1

A

07 06

04 03 02 01 00

17

15 14 13 12 11 10

P05

acknowledge

from slave

P16

acknowledge

from slave

START condition

write to port

R/W

acknowledge

from slave

t

v(Q)

data output from port

P05 output voltage

data A0 and B0 valid

I

trt(pu)

P05 pull-up output current

P16 output voltage

I

OH

I

trt(pu)

P16 pull-up output current

INT

I

OH

t

d(rst)

002aab632

Fig 11. Write mode (output)

8.3 Reading from a port (Input mode)

All ports programmed as input should be set to logic 1. To read, the master

(microcontroller) ﬁrst addresses the slave device after it receives the interrupt. By setting

the last bit of the byte containing the slave address to logic 1 the Read mode is entered.

The data bytes that follow on the SDA are the values on the ports.

If the data on the input port changes faster than the master can read, this data may be

lost.

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

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PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

8.4 Power-on reset

When power is applied to V_DD, an internal Power-On Reset (POR) holds the PCA8575 in

a reset condition until V_DDhas reached V_POR. At that point, the reset condition is released

and the PCA8575 registers and I²C-bus/SMBus state machine will initialize to their default

states. Thereafter V_DDmust be lowered below 0.2 V to reset the device.

8.5 Interrupt output (INT)

The PCA8575 provides an open-drain interrupt (INT) which can be fed to a corresponding

input of the microcontroller (see Figure 12, Figure 13, and Figure 14). This gives these

chips a kind of master function which can initiate an action elsewhere in the system.

An interrupt is generated by any rising or falling edge of the port inputs. After time t_v(D)the

signal INT is valid.

The interrupt disappears when data on the port is changed to the original setting or data is

read from or written to the device which has generated the interrupt.

In the write mode, the interrupt may become deactivated (HIGH) on the rising edge of the

write to port pulse. On the falling edge of the write to port pulse the interrupt is deﬁnitely

deactivated (HIGH).

The interrupt is reset in the read mode on the rising edge of the read from port pulse.

During the resetting of the interrupt itself, any changes on the I/Os may not generate an

interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as

an INT.

V

DD

device 1

device 2

device 8

PCA8575

MICROCOMPUTER

INT

002aac676

Fig 14. Application of multiple PCA8575s with interrupt

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

11 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

9. Characteristics of the I²C-bus

The I²C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 15).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 15. Bit transfer

9.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P) (see Figure 16.)

SDA

SCL

SDA

SCL

S

P

STOP condition

START condition

mba608

Fig 16. Deﬁnition of START and STOP conditions

9.2 System conﬁguration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 17).

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

12 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

SDA

SCL

SLAVE

TRANSMITTER/

RECEIVER

MASTER

2

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

I C-BUS

TRANSMITTER/

RECEIVER

MULTIPLEXER

SLAVE

002aaa966

Fig 17. System conﬁguration

9.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from master

1

2

8

9

S

clock pulse for

START

condition

acknowledgement

002aaa987

Fig 18. Acknowledgement on the I²C-bus

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

13 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

10. Application design-in information

10.1 Bidirectional I/O expander applications

In the 8-bit I/O expander application shown in Figure 19, P00 and P01 are inputs, and P02

to P07 are outputs. When used in this conﬁguration, during a write, the input (P00 and

P01) must be written as HIGH so the external devices fully control the input ports. The

desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P02 to

P07). During a read, the logic levels of the external devices driving the input ports (P00

and P01) and the previous written logic level to the output ports (P02 to P07) will be read.

The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of

the microprocessor. By sending an interrupt signal on this line, the remote I/O informs the

microprocessor that there is incoming data or a change of data on its ports without having

to communicate via the I²C-bus.

V

DD

V

DD

V

DD

SDA

SCL

INT

P00

P01

P02

P03

P04

P05

P06

P07

temperature sensor

battery status

CORE

PROCESSOR

control for latch

control for switch

control for audio

control for camera

control for MP3

AD0

AD1

AD2

002aab812

Fig 19. Bidirectional I/O expander application

10.2 High current-drive load applications

The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring

additional drive, two port pins in the same octal may be connected together to sink up to

50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one

octal) can be connected together to drive 200 mA.

V

DD

V

DD

SDA

SCL

INT

P00

P01

P02

P03

P04

P05

P06

P07

CORE

PROCESSOR

LOAD

AD0

AD1

AD2

002aab813

Fig 20. High current-drive load application

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

14 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

10.3 Differences between the PCA8575 and the PCF8575

The PCA8575 is a drop in replacement for the PCF8575 and can used without electrical

or software modiﬁcations, but there is a difference in interrupt output release timing during

the read operation.

Write operations are identical. At the completion of each 8-bit write sequence the data is

stored in its associated 8-bit write register at ACK or NACK. The ﬁrst byte goes to P0n

while the second goes to P1n. Subsequent writes without a STOP wrap around to P0n

then P1n again. Any write will update both read registers and clear interrupts.

Read operations are identical. Both devices update the byte register with the pin data as

each 8-bit read is initiated, the very ﬁrst read after an address cycle corresponds to ports

P0n while the second (even byte) corresponds to P1n and subsequent reads without a

STOP wrap around to P0n then P1n again.

During read operations, the PCA8575 interrupt output will be cleared in a byte-wise

fashion as each byte is read. Reading the ﬁrst byte will clear any interrupts associated

with the P0n pins. This ﬁrst byte read operation will have no effect on interrupts associated

with changes of state on the P1n pins. Interrupts associated with the P1n pins will be

cleared when the second byte is read. Reading the second byte has no effect on

interrupts associated with the changes of state on the P0x pins. The PCF8575 interrupt

output will clear after reading both bytes of data regardless of whether data was changed

in the ﬁrst byte or the second byte or both bytes.

11. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

I_DD

Parameter

Conditions

Min

Max

+6

Unit

V

supply voltage

−0.5

supply current

-

±100

±600

5.5

mA

V

I_SS

ground supply current

input voltage

V_I

V

_SS− 0.5

I_I

input current

-

±20

±50^[1]

mA

mW

°C

I_O

output current

-

P_tot

P/out

T_stg

T_amb

total power dissipation

power dissipation per output

storage temperature

ambient temperature

-

600

-

200

−65

−40

+150

+85

operating

°C

[1] Total package (maximum) output current is 600 mA.

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

15 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

12. Static characteristics

Table 5.

Static characteristics

V_DD= 2.3 V to 5.5 V; V_SS= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Supplies

Conditions

Min

Typ

Max

Unit

V_DD

I_DD

supply voltage

supply current

2.3

-

5.5

V

Operating mode; no load;

100

200

µA

V_I= V_DDor V_SS; f_SCL= 400 kHz

I_stb

standby current

Standby mode; no load;

V_I= V_DDor V_SS

-

2.5

1.8

10

µA

[1]

V_POR

power-on reset voltage

2.0

V

Input SCL; input/output SDA

V_IL

V_IH

I_OL

I_L

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

leakage current

−0.5

0.7V_DD

20

-

+0.3V_DD

V

-

5.5

-

V

V_OL= 0.4 V

V_I= V_DDor V_SS

V_I= V_SS

-

mA

µA

pF

−1

-

+1

10

C_i

input capacitance

-

5

I/Os; P00 to P07 and P10 to P17

I_OL

LOW-level output current^[2]

V_OL= 0.5 V; V_DD= 2.3 V

V_OL= 0.5 V; V_DD= 3.0 V

V_OL= 0.5 V; V_DD= 4.5 V

12

17

25

-

<tbd>

-

mA

µA

-

I_OL(tot)

I_OH

I_trt(pu)

C_i

total LOW-level output current^[2]V_OL= 0.5 V; V_DD= 4.5 V

400

−300

-

HIGH-level output current V_OH= V_SS

−30

−0.5

-

<tbd>

−1.0

transient boosted pull-up current V_OH= V_SS; see Figure 11

input capacitance

mA

pF

[3]

<tbd>

10

C_o

output capacitance

-

pF

Interrupt INT

I_OL

C_o

LOW-level output current

output capacitance

V_OL= 0.4 V

6

-

mA

pF

3

5

Inputs AD0, AD1, AD2

V_IL

V_IH

I_LI

LOW-level input voltage

−0.5

0.7V_DD

−1

-

+0.3V_DD

V

HIGH-level input voltage

input leakage current

input capacitance

-

5.5

+1

5

V

-

µA

pF

C_i

-

3.5

[1] The power-on reset circuit resets the I²C-bus logic with V_DD< V_PORand set all I/Os to logic 1 (with current source to V_DD).

[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal busing limits.

[3] The value is not tested, but veriﬁed on sampling basis.

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

16 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

13. Dynamic characteristics

Table 6.

Dynamic characteristics

V_DD= 2.3 V to 5.5 V; V_SS= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter Conditions

Fast mode I²C-bus

Unit

Min

Typ

Max

400

f_SCL

t_BUF

SCL clock frequency

0

-

kHz

bus free time between a STOP and START

condition

1.3

-

µs

t_HD;STA

t_SU;STA

t_SU;STO

t_HD;DAT

t_VD;ACK

t_VD;DAT

t_SU;DAT

t_LOW

hold time (repeated) START condition

set-up time for a repeated START condition

set-up time for STOP condition

data hold time

0.6

-

µs

ns

µs

ns

µs

ns

0.6

-

0.6

-

0

-

[1]

[2]

data valid acknowledge time

data valid time

0.1

0.9

50

-

data set-up time

100

-

LOW period of the SCL clock

HIGH period of the SCL clock

fall time of both SDA and SCL signals

rise time of both SDA and SCL signals

1.3

-

t_HIGH

t_f

0.6

-

[3][4]

[6]

[5]

20 + 0.1C_b

-

300

50

t_r

t_SP

pulse width of spikes that must be suppressed

by the input ﬁlter

Port timing; C_L≤ 100 pF (see Figure 11 and Figure 12)

t_v(Q)

t_su(D)

t_h(D)

data output valid time

data input set-up time

data input hold time

-

4

-

µs

0

4

-

Interrupt timing; C_L≤ 100 pF (see Figure 11 and Figure 12)

t_v(D)

data input valid time

reset delay time

-

4

µs

t_d(rst)

[1] t_VD;ACK= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[2] t_VD;DAT= minimum time for SDA data out to be valid following SCL LOW.

[3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_ILof the SCL signal) in order to

bridge the undeﬁned region SCL’s falling edge.

[4] The maximum t_ffor the SDA and SCL bus lines is speciﬁed at 300 ns. The maximum fall time for the SDA output stage t_fis speciﬁed at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum speciﬁed t_f.

[5] C_b= total capacitance of one bus line in pF.

[6] Input ﬁlters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

17 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

START

condition

(S)

bit 7

MSB

(A7)

STOP

bit 0 acknowledge

condition

bit 6

(A6)

protocol

(R/W)

(A)

(P)

t

HIGH

SU;STA

LOW

1

/f

SCL

SDA

t

BUF

f

t

r

t

HD;DAT

VD;DAT

VD;ACK

SU;STO

002aab175

HD;STA

SU;DAT

Rise and fall times refer to V_ILand V_IH

.

Fig 21. I²C-bus timing diagram

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

18 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

14. Package outline

SO24: plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

D

E

A

X

c

H

v

M

A

E

y

Z

24

13

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

12

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

15.6

15.2

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.61

0.014 0.009 0.60

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT137-1

075E05

MS-013

Fig 22. Package outline SOT137-1 (SO24)

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

19 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm

SOT340-1

D

E

A

X

v

c

H

M

A

y

E

Z

24

13

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

12

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

8.4

8.0

5.4

5.2

7.9

7.6

1.03

0.63

0.9

0.7

0.8

0.4

mm

2

0.65

1.25

0.25

0.2

0.13

0.1

Note

1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT340-1

MO-150

Fig 23. Package outline SOT340-1 (SSOP24)

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

20 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

SSOP24: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635 mm

SOT556-1

D

E

A

X

c

y

H

v

M

A

E

Z

13

24

A

2

A

(A )

3

A

1

θ

L

p

L

12

1

detail X

w

M

e

b

p

0

2.5

5 mm

scale

DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

1

L

p

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.25

0.10

1.55

1.40

0.31

0.20

0.25

0.18

8.8

8.6

4.0

3.8

6.2

5.8

0.89

0.41

1.05

0.66

mm

1.73

0.25

0.01

0.635

0.025

0.25

0.18

0.1

0.0098 0.061

0.0040 0.055

0.012 0.0098 0.344 0.157

0.008 0.0075 0.337 0.150

0.244

0.228

0.035

0.016

0.040

0.026

8^o

0^o

inches

0.068

0.041

0.01 0.007 0.004

Note

1. Plastic or metal protrusions of 0.2 mm (0.008 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT556-1

MO-137

Fig 24. Package outline SOT556-1 (SSOP24)

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

21 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm

SOT355-1

D

E

A

X

c

H

v

M

A

y

E

Z

13

24

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

1

12

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

7.9

7.7

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT355-1

MO-153

Fig 25. Package outline SOT355-1 (TSSOP24)

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

22 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;

no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm

SOT815-1

D

B

A

E

1

c

detail X

terminal 1

index area

C

e

1

terminal 1

index area

y

v

M

C

A B

C

1

e

b

w

M

2

11

L

12

13

1

e

E

h

2

24

23

14

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

D

E

h

e

L

v

w

y

1

2

1

h

max.

0.05 0.30

0.00 0.18

5.6

5.4

4.25

3.95

3.6

3.4

2.25

1.95

0.5

0.3

mm

1

0.2

0.5

4.5

1.5

0.1

0.05 0.05

0.1

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

03-04-29

SOT815-1

- - -

Fig 26. Package outline SOT815-1 (DHVQFN24)

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

23 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.85 mm

SOT616-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

e

1

C

1/2 e

y

C

1

e

v

M

C

A

B

b

7

12

w

L

13

6

e

E

h

2

1/2 e

1

18

terminal 1

index area

24

19

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

mm

A

b

c

E

e

2

y

D

E

L

v

w

y

1

h

1

h

max.

0.05 0.30

0.00 0.18

4.1

3.9

2.25

1.95

4.1

3.9

2.25

1.95

0.5

0.3

0.05

0.1

1

0.2

0.5

2.5

0.1 0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-22

SOT616-1

- - -

MO-220

- - -

Fig 27. Package outline SOT616-1 (HVQFN24)

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

24 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

15. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.

However, to be completely safe you must take normal precautions appropriate to handling

integrated circuits.

16. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

25 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

16.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 28) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 7 and 8

Table 7.

SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

≥ 350

220

< 2.5

235

220

≥ 2.5

220

Table 8.

Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 28.

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

26 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 28. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

17. Abbreviations

Table 9.

Abbreviations

Description

Acronym

CDM

CMOS

ESD

GPIO

HBM

I/O

Charged Device Model

Complementary Metal Oxide Semiconductor

ElectroStatic Discharge

General Purpose Input/Output

Human Body Model

Input/Output

I²C-bus

Inter-Integrated Circuit bus

Integrated Circuit

IC

ID

Identiﬁcation

LED

Light Emitting Diode

LSB

Least Signiﬁcant Bit

MM

Machine Model

MSB

PLC

Most Signiﬁcant Bit

Programmable Logic Controller

Redundant Array of Independent Disks

System Management Bus

RAID

SMBus

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

27 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

18. Revision history

Table 10. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

PCA8575_1

20061130

Objective data sheet

-

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

28 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

result in personal injury, death or severe property or environmental damage.

19.2 Deﬁnitions

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

19.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

19.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

I²C-bus — logo is a trademark of NXP B.V.

20. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

PCA8575_1

Objective data sheet

Rev. 01 — 30 November 2006

29 of 30

PCA8575

NXP Semiconductors

Remote 16-bit I/O expander for I²C-bus with interrupt

21. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

20

21

Contact information . . . . . . . . . . . . . . . . . . . . 29

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7

7.1

7.1.1

Functional description . . . . . . . . . . . . . . . . . . . 6

Device address. . . . . . . . . . . . . . . . . . . . . . . . . 6

Address map. . . . . . . . . . . . . . . . . . . . . . . . . . . 6

8

I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 7

Quasi-bidirectional I/O architecture . . . . . . . . . 7

Writing to the port (Output mode). . . . . . . . . . . 7

Reading from a port (Input mode) . . . . . . . . . . 8

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 11

Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 11

8.1

8.2

8.3

8.4

8.5

9

Characteristics of the I²C-bus. . . . . . . . . . . . . 12

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

START and STOP conditions . . . . . . . . . . . . . 12

System conﬁguration . . . . . . . . . . . . . . . . . . . 12

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 13

9.1

9.1.1

9.2

9.3

10

Application design-in information . . . . . . . . . 14

Bidirectional I/O expander applications . . . . . 14

High current-drive load applications . . . . . . . . 14

Differences between the PCA8575 and the

10.1

10.2

10.3

PCF8575. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

11

12

13

14

15

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15

Static characteristics. . . . . . . . . . . . . . . . . . . . 16

Dynamic characteristics . . . . . . . . . . . . . . . . . 17

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19

Handling information. . . . . . . . . . . . . . . . . . . . 25

16

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Introduction to soldering . . . . . . . . . . . . . . . . . 25

Wave and reﬂow soldering . . . . . . . . . . . . . . . 25

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 26

16.1

16.2

16.3

16.4

17

18

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 27

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 28

19

Legal information. . . . . . . . . . . . . . . . . . . . . . . 29

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 29

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

19.1

19.2

19.3

19.4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 30 November 2006

Document identifier: PCA8575_1


型号：	PCA8575DK
厂家：	NXP
描述：	Remote 16-bit I/O expander for I2C-bus with interrupt 远程16位I / O扩展器I2C总线与中断并行IO端口微控制器和处理器外围集成电路光电二极管
文件：	总30页 (文件大小：180K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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