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PCA8576D [NXP]

Automotive 40 x 4 LCD segment driver for low multiplex rates up to 1:4; 汽车40 ×4的LCD段驱动器的低复用率高达1 ： 4
PCA8576D
型号： PCA8576D
厂家： NXP    NXP
描述：

Automotive 40 x 4 LCD segment driver for low multiplex rates up to 1:4
汽车40 ×4的LCD段驱动器的低复用率高达1 ： 4

驱动器 CD
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PCA8576D  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
up to 1:4  
Rev. 1 — 4 April 2011  
Product data sheet  
1. General description  
The PCA8576D is a peripheral device which interfaces to almost any Liquid Crystal  
Display (LCD) with low multiplex rates. It generates the drive signals for any static or  
multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily  
cascaded for larger LCD applications. The PCA8576D is compatible with most  
microcontrollers and communicates via the two-line bidirectional I2C-bus. Communication  
overheads are minimized by a display RAM with auto-incremented addressing, by  
hardware subaddressing and by display memory switching (static and duplex drive  
modes).  
2. Features and benefits  
AEC-Q100 compliant for automotive applications  
Single chip LCD controller and driver  
Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing  
Selectable display bias configuration: static, 12 or 13  
Internal LCD bias generation with voltage-follower buffers  
40 segment drives:  
Up to 20 7-segment numeric characters  
Up to 10 14-segment alphanumeric characters  
Any graphics of up to 160 elements  
40 4-bit RAM for display data storage  
Auto-incremented display data loading across device subaddress boundaries  
Display memory bank switching in static and duplex drive modes  
Versatile blinking modes  
Independent supplies possible for LCD and logic voltages  
Wide power supply range: from 1.8 V to 5.5 V  
Wide logic LCD supply range:  
From 2.5 V for low-threshold LCDs  
Up to 6.5 V for high-threshold twisted nematic LCDs  
Low power consumption  
400 kHz I2C-bus interface  
May be cascaded for large LCD applications (up to 2560 elements possible)  
No external components required  
Compatible with chip-on-glass and chip-on-board technology  
Manufactured in silicon gate CMOS process  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
3. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Name  
Description  
Version  
PCA8576DU/2DA/Q2 bare die 59 bumps[1]  
PCA8576DU/2DA  
[1] Chips with bumps in tray.  
4. Marking  
Table 2.  
Marking codes  
Type number  
Marking code  
PCA8576DU/2DA/Q2  
PC8576D-2  
5. Block diagram  
BP0 BP2 BP1 BP3  
S0 to S39  
40  
V
LCD  
BACKPLANE  
OUTPUTS  
DISPLAY SEGMENT  
OUTPUTS  
LCD  
VOLTAGE  
SELECTOR  
DISPLAY  
REGISTER  
DISPLAY  
CONTROLLER  
OUTPUT BANK SELECT  
AND BLINK CONTROL  
LCD BIAS  
GENERATOR  
V
SS  
CLK  
DISPLAY RAM  
40 × 4-BIT  
CLOCK SELECT  
AND TIMING  
BLINKER  
TIMEBASE  
PCA8576D  
SYNC  
POWER-ON  
RESET  
COMMAND  
DECODER  
WRITE DATA  
CONTROL  
DATA POINTER AND  
AUTO INCREMENT  
OSC  
OSCILLATOR  
V
DD  
SCL  
SDA  
2
INPUT  
FILTERS  
I C-BUS  
SUBADDRESS  
COUNTER  
CONTROLLER  
SA0  
A0  
A1  
A2  
013aaa467  
Fig 1. Block diagram of PCA8576D  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
2 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
6. Pinning information  
6.1 Pinning  
S3  
S2  
S1  
S0  
21  
20  
19  
18  
S18  
S19  
S20  
S21  
S22  
S23  
S24  
S25  
S26  
S27  
S28  
S29  
S30  
S31  
S32  
S33  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
BP3  
BP1  
BP2  
BP0  
17  
16  
15  
14  
PCA8576DU  
V
13  
LCD  
V
SS  
12  
11  
SA0  
A2  
A1  
10  
9
013aaa468  
Viewed from active side. C1 and C2 are alignment marks. For mechanical details, see Figure 23.  
Fig 2. Pinning diagram for PCA8576DU (bare die)  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
3 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
6.2 Pin description  
Table 3.  
Symbol  
Pin description  
Description  
Pin  
PCA8576DU  
SDA  
SCL  
1, 58, 59  
I2C-bus serial data input and output  
I2C-bus serial clock input  
external clock input or output  
supply voltage  
2, 3  
CLK  
5
VDD  
6
SYNC  
OSC  
A0 to A2  
SA0  
4
cascade synchronization input or output  
internal oscillator enable input  
subaddress inputs  
7
8 to 10  
11  
I2C-bus address input; bit 0  
VSS  
12[1]  
13  
ground supply voltage  
VLCD  
LCD supply voltage  
BP0, BP2, BP1, 14 to 17  
BP3  
LCD backplane outputs  
S0 to S39  
18 to 57  
LCD segment outputs  
[1] The substrate (rear side of the die) is connected to VSS and should be electrically isolated.  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
4 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
7. Functional description  
The PCA8576D is a versatile peripheral device designed to interface any microcontroller  
with a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing  
up to four backplanes and up to 40 segments.  
The possible display configurations of the PCA8576D depend on the number of active  
backplane outputs required. A selection of display configurations is shown in Table 4. All  
of these configurations can be implemented in the typical system shown in Figure 3.  
Table 4.  
Selection of possible display configurations  
Number of  
Backplanes  
Icons  
Digits/Characters  
Dot matrix/  
Elements  
7-segment  
14-segment  
4
3
2
1
160  
120  
80  
20  
15  
10  
5
10  
7
160 (4 40)  
120 (3 40)  
80 (2 40)  
40 (1 40)  
5
40  
2
V
DD  
t
r
R ≤  
2C  
B
V
V
LCD  
DD  
40 segment drives  
4 backplanes  
SDA  
SCL  
OSC  
HOST  
MICRO-  
LCD PANEL  
PROCESSOR/  
MICRO-  
PCA8576D  
(up to 160  
elements)  
CONTROLLER  
A0 A1 A2 SA0  
V
SS  
V
SS  
013aaa469  
The resistance of the power lines must be kept to a minimum.  
For chip-on-glass applications, due to the Indium Tin Oxide (ITO) track resistance, each supply line  
must be routed separately between the chip and the connector.  
Fig 3. Typical system configuration  
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication  
channel with the PCA8576D. The internal oscillator is enabled by connecting  
pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms  
are generated internally. The only other connections required to complete the system are  
to the power supplies (VDD, VSS and VLCD) and the LCD panel chosen for the application.  
7.1 Power-on reset  
At power-on the PCA8576D resets to the following starting conditions:  
• All backplane outputs are set to VLCD  
• All segment outputs are set to VLCD  
• The selected drive mode is: 1:4 multiplex with 13 bias  
• Blinking is switched off  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
5 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
• Input and output bank selectors are reset  
• The I2C-bus interface is initialized  
• The data pointer and the subaddress counter are cleared (set to logic 0)  
• Display is disabled  
Data transfers on the I2C-bus must be avoided for 1 ms following power-on to allow the  
reset action to complete.  
7.2 LCD bias generator  
Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of  
three impedances connected in series between VLCD and VSS. The middle resistor can be  
bypassed to provide a 12 bias voltage level for the 1:2 multiplex configuration. The LCD  
voltage can be temperature compensated externally using the supply to pin VLCD  
.
7.3 LCD voltage selector  
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the  
selected LCD drive configuration. The operation of the voltage selector is controlled by the  
mode-set command (see Table 10) from the command decoder. The biasing  
configurations that apply to the preferred modes of operation, together with the biasing  
characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in  
Table 5.  
Table 5.  
Discrimination ratios  
Number of:  
LCD drive  
mode  
LCD bias  
configuration  
VoffRMSVonRMS  
------------------------ ----------------------- D = ------------------------  
VLCD VLCD VoffRMS  
VonRMS  
Backplanes Levels  
static  
1
2
2
3
4
2
3
4
4
4
static  
12  
13  
13  
13  
0
1
1:2 multiplex  
1:2 multiplex  
1:3 multiplex  
1:4 multiplex  
0.354  
0.333  
0.333  
0.333  
0.791  
0.745  
0.638  
0.577  
2.236  
2.236  
1.915  
1.732  
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD  
threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In  
the static drive mode a suitable choice is VLCD > 3Vth.  
Multiplex drive modes of 1:3 and 1:4 with 12 bias are possible but the discrimination and  
hence the contrast ratios are smaller.  
1
Bias is calculated by ------------ , where the values for a are  
1 + a  
a = 1 for 12 bias  
a = 2 for 13 bias  
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1  
a2 + 2a + n  
n  1 + a2  
VonRMS  
=
-----------------------------  
(1)  
V
LCD  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
6 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
where the values for n are  
n = 1 for static mode  
n = 2 for 1:2 multiplex  
n = 3 for 1:3 multiplex  
n = 4 for 1:4 multiplex  
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:  
a2 – 2a + n  
n  1 + a2  
VoffRMS  
=
-----------------------------  
(2)  
(3)  
V
LCD  
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:  
a + 12 + n – 1  
VonRMS  
D =  
=
-------------------------------------------  
----------------------  
a – 12 + n – 1  
VoffRMS  
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with  
12 bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with  
21  
12 bias is ---------- = 1.528 .  
3
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD  
as follows:  
• 1:3 multiplex (12 bias): VLCD  
=
6 VoffRMS= 2.449VoffRMS  
4 3  
• 1:4 multiplex (12 bias): VLCD  
=
= 2.309VoffRMS  
---------------------  
3
These compare with VLCD = 3VoffRMSwhen 13 bias is used.  
It should be noted that VLCD is sometimes referred as the LCD operating voltage.  
7.3.1 Electro-optical performance  
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The  
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of  
the pixel.  
For any given liquid, there are two threshold values defined. One point is at 10 % relative  
transmission (at Vlow) and the other at 90 % relative transmission (at Vhigh), see Figure 4.  
For a good contrast performance, the following rules should be followed:  
V
V
onRMSVhigh  
offRMSVlow  
(4)  
(5)  
V
on(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection  
of a, n (see Equation 1 to Equation 3) and the VLCD voltage.  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
7 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
Vlow and Vhigh are properties of the LCD liquid and can be provided by the module  
manufacturer.  
It is important to match the module properties to those of the driver in order to achieve  
optimum performance.  
100 %  
90 %  
10 %  
V
[V]  
RMS  
V
low  
V
high  
OFF  
SEGMENT  
GREY  
SEGMENT  
ON  
SEGMENT  
001aam358  
Fig 4. Electro-optical characteristic: relative transmission curve of the liquid  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
8 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
7.4 LCD drive mode waveforms  
7.4.1 Static drive mode  
The static LCD drive mode is used when a single backplane is provided in the LCD. The  
backplane (BPn) and segment drive (Sn) waveforms for this mode are shown in Figure 5.  
T
fr  
LCD segments  
V
LCD  
BP0  
Sn  
V
SS  
state 1  
(on)  
state 2  
(off)  
V
LCD  
V
SS  
V
LCD  
Sn+1  
V
SS  
(a) Waveforms at driver.  
V
LCD  
state 1  
0 V  
−V  
LCD  
V
LCD  
state 2  
0 V  
−V  
LCD  
(b) Resultant waveforms  
at LCD segment.  
mgl745  
(1) Vstate1(t) = VSn(t) VBP0(t).  
(2) on(RMS) = VLCD  
V
.
(3) Vstate2(t) = VSn+1(t) VBP0(t).  
(4) Voff(RMS) = 0 V.  
Fig 5. Static drive mode waveforms  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
9 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
7.4.2 1:2 Multiplex drive mode  
The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This  
mode allows fractional LCD bias voltages of 12 bias or 13 bias as shown in Figure 6 and  
Figure 7.  
T
fr  
V
LCD  
LCD segments  
V
V
/ 2  
/ 2  
BP0  
BP1  
Sn  
LCD  
SS  
state 1  
V
LCD  
state 2  
V
V
LCD  
SS  
V
LCD  
V
V
SS  
LCD  
Sn+1  
V
SS  
(a) Waveforms at driver.  
V
V
LCD  
LCD  
/ 2  
0 V  
−V  
state 1  
/ 2  
LCD  
−V  
LCD  
V
V
LCD  
/ 2  
LCD  
0 V  
state 2  
−V  
/ 2  
LCD  
LCD  
−V  
(b) Resultant waveforms  
at LCD segment.  
mgl746  
(1) Vstate1(t) = VSn(t) VBP0(t).  
(2) Von(RMS) = 0.791VLCD  
(3) Vstate2(t) = VSn+1(t) VBP1(t).  
(4) off(RMS) = 0.354VLCD  
.
V
.
Fig 6. Waveforms for the 1:2 multiplex drive mode with 12 bias  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
10 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
T
fr  
V
LCD  
2V  
LCD segments  
/ 3  
LCD  
/ 3  
BP0  
BP1  
Sn  
V
V
LCD  
SS  
state 1  
V
LCD  
state 2  
2V  
/ 3  
/ 3  
LCD  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
Sn+1  
V
V
LCD  
SS  
(a) Waveforms at driver.  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
V
LCD  
0 V  
−V  
state 1  
/ 3  
LCD  
−2V  
−V  
/ 3  
LCD  
LCD  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
V
LCD  
0 V  
−V  
state 2  
/ 3  
LCD  
−2V  
−V  
/ 3  
LCD  
LCD  
(b) Resultant waveforms  
at LCD segment.  
mgl747  
(1) Vstate1(t) = VSn(t) VBP0(t).  
(2) Von(RMS) = 0.745VLCD  
(3) Vstate2(t) = VSn+1(t) VBP1(t).  
(4) off(RMS) = 0.333VLCD  
.
V
.
Fig 7. Waveforms for the 1:2 multiplex drive mode with 13 bias  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
11 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
7.4.3 1:3 Multiplex drive mode  
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies  
(see Figure 8).  
T
fr  
V
LCD  
2V  
LCD segments  
/ 3  
LCD  
/ 3  
BP0  
BP1  
BP2  
Sn  
V
V
LCD  
SS  
state 1  
state 2  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
Sn+1  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
Sn+2  
V
V
LCD  
SS  
(a) Waveforms at driver.  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
V
LCD  
0 V  
−V  
state 1  
/ 3  
LCD  
−2V  
−V  
/ 3  
LCD  
LCD  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
V
LCD  
0 V  
−V  
state 2  
/ 3  
LCD  
−2V  
−V  
/ 3  
LCD  
LCD  
(b) Resultant waveforms  
at LCD segment.  
mgl748  
(1) Vstate1(t) = VSn(t) VBP0(t).  
(2) on(RMS) = 0.638VLCD  
(3) Vstate2(t) = VSn+1(t) VBP1(t).  
(4) Voff(RMS) = 0.333VLCD  
V
.
.
Fig 8. Waveforms for the 1:3 multiplex drive mode with 13 bias  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
12 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
7.4.4 1:4 Multiplex drive mode  
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies (see  
Figure 9).  
T
fr  
V
LCD segments  
LCD  
2V  
/ 3  
LCD  
/ 3  
BP0  
BP1  
BP2  
V
V
LCD  
SS  
state 1  
state 2  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
BP3  
Sn  
V
V
LCD  
SS  
V
LCD  
2V  
LCD  
/ 3  
/ 3  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
Sn+1  
V
V
LCD  
SS  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
Sn+2  
Sn+3  
V
V
LCD  
SS  
V
LCD  
2V  
LCD  
/ 3  
/ 3  
V
V
LCD  
SS  
(a) Waveforms at driver.  
V
LCD  
2V  
/ 3  
/ 3  
LCD  
V
LCD  
0 V  
−V  
state 1  
/ 3  
LCD  
−2V  
−V  
/ 3  
LCD  
LCD  
V
LCD  
2V  
/ 3  
LCD  
/ 3  
V
LCD  
0 V  
−V  
state 2  
/ 3  
LCD  
−2V  
−V  
/ 3  
LCD  
LCD  
(b) Resultant waveforms  
at LCD segment.  
mgl749  
(1) Vstate1(t) = VSn(t) VBP0(t).  
(2) on(RMS) = 0.577VLCD  
(3) Vstate2(t) = VSn+1(t) VBP1(t).  
(4) Voff(RMS) = 0.333VLCD  
V
.
.
Fig 9. Waveforms for the 1:4 multiplex drive mode with 13 bias  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
13 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
7.5 Oscillator  
7.5.1 Internal clock  
The internal logic of the PCA8576D and its LCD drive signals are timed either by its  
internal oscillator or by an external clock. The internal oscillator is enabled by connecting  
pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used  
as the clock signal for several PCA8576D in the system that are connected in cascade.  
7.5.2 External clock  
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD  
.
The LCD frame signal frequency is determined by the clock frequency (fclk).  
Remark: A clock signal must always be supplied to the device; removing the clock may  
freeze the LCD in a DC state, which is not suitable for the liquid crystal.  
7.6 Timing  
The PCA8576D timing controls the internal data flow of the device. This includes the  
transfer of display data from the display RAM to the display segment outputs. In cascaded  
applications, the correct timing relationship between each PCA8576D in the system is  
maintained by the synchronization signal at pin SYNC. The timing also generates the LCD  
frame signal whose frequency is derived from the clock frequency. The frame signal  
frequency is a fixed division of the clock frequency from either the internal or an external  
fclk  
clock: ffr  
=
.
-------  
24  
7.7 Display register  
The display register holds the display data while the corresponding multiplex signals are  
generated. There is a one-to-one relationship between the data in the display register, the  
LCD segment outputs, and one column of the display RAM.  
7.8 Segment outputs  
The LCD drive section includes 40 segment outputs S0 to S39 which should be  
connected directly to the LCD. The segment output signals are generated in accordance  
with the multiplexed backplane signals and with data residing in the display register. When  
less than 40 segment outputs are required, the unused segment outputs should be left  
open-circuit.  
7.9 Backplane outputs  
The LCD drive section includes four backplane outputs BP0 to BP3 which must be  
connected directly to the LCD. The backplane output signals are generated in accordance  
with the selected LCD drive mode. If less than four backplane outputs are required, the  
unused outputs can be left open-circuit.  
In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two  
adjacent outputs can be tied together to give enhanced drive capabilities.  
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In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals  
and may also be paired to increase the drive capabilities.  
In the static drive mode the same signal is carried by all four backplane outputs and they  
can be connected in parallel for very high drive requirements.  
7.10 Display RAM  
The display RAM is a static 40 4-bit RAM which stores LCD data. A logic 1 in the RAM  
bit-map indicates the on-state of the corresponding LCD element; similarly, a logic 0  
indicates the off-state. There is a one-to-one correspondence between the RAM  
addresses and the segment outputs, and between the individual bits of a RAM word and  
the backplane outputs. The display RAM bit map Figure 10 shows the rows 0 to 3 which  
correspond with the backplane outputs BP0 to BP3, and the columns 0 to 39 which  
correspond with the segment outputs S0 to S39. In multiplexed LCD applications the  
segment data of the first, second, third and fourth row of the display RAM are  
time-multiplexed with BP0, BP1, BP2 and BP3 respectively.  
display RAM addresses (columns)/segment outputs (S)  
0
1
2
3
4
35 36 37 38 39  
0
1
2
3
display RAM bits  
(rows)/  
backplane outputs  
(BP)  
mbe525  
Display RAM bit map showing direct relationship between RAM addresses and segment outputs;  
also between bits in a RAM word and the backplane outputs.  
Fig 10. Display RAM bit map  
When display data is transmitted to the PCA8576D, the display bytes received are stored  
in the display RAM in accordance with the selected LCD drive mode. The data is stored as  
it arrives and does not wait for an acknowledge cycle as with the commands. Depending  
on the current multiplex drive mode, data is stored singularly, in pairs, triplets or  
quadruplets. To illustrate the filling order, an example of a 7-segment numeric display  
showing all drive modes is given in Figure 11; the RAM filling organization depicted  
applies equally to other LCD types.  
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx  
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
drive mode  
LCD segments  
LCD backplanes  
display RAM filling order  
transmitted display byte  
columns  
display RAM address/segment outputs (s)  
byte1  
S
S
S
S
S
a
n+2  
n+3  
n+4  
n+5  
n+6  
b
BP0  
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7  
S
f
n+1  
rows  
static  
display RAM  
rows/backplane  
outputs (BP)  
MSB  
LSB  
g
0
1
2
3
c
x
x
x
b
x
x
x
a
x
x
x
f
g
x
x
x
e
x
x
x
d
x
x
x
DP  
x
S
S
n
x
x
x
e
n+7  
c
b
a
f
g
e
d
DP  
c
x
d
DP  
x
columns  
display RAM address/segment outputs (s)  
byte1 byte2  
BP0  
a
S
S
n
1:2  
b
n
n + 1 n + 2 n + 3  
f
n+1  
rows  
MSB  
LSB  
DP  
display RAM  
rows/backplane  
outputs (BP)  
g
0
1
2
3
a
b
x
x
f
e
c
x
x
d
DP  
x
multiplex  
g
x
x
BP1  
a
b
f
g
e c d  
e
S
S
n+2  
n+3  
c
d
DP  
x
columns  
display RAM address/segment outputs (s)  
BP0  
BP1  
byte1  
byte2  
byte3  
S
S
n+1  
n+2  
a
1:3  
b
n
n + 1 n + 2  
S
n
f
rows  
MSB  
LSB  
e
display RAM  
rows/backplane  
outputs (BP)  
0
1
2
3
b
DP  
c
a
d
g
x
f
g
multiplex  
b
DP  
c
a
d
g
f
e
x
x
BP2  
e
c
d
DP  
x
columns  
display RAM address/segment outputs (s)  
byte2 byte3 byte4  
byte1  
byte5  
a
S
S
n
1:4  
b
BP2  
BP3  
n
n + 1  
BP0  
BP1  
f
rows  
display RAM  
rows/backplane  
outputs (BP)  
g
0
1
2
3
a
c
f
MSB  
LSB  
d
multiplex  
e
g
d
e
c
b
a
c
b
DP  
f
e
g
d
DP  
DP  
n+1  
001aaj646  
x = data bit unchanged.  
Fig 11. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus  
PCA8576D  
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Automotive 40 x 4 LCD segment driver for low multiplex rates  
The following applies to Figure 11:  
• In the static drive mode, the eight transmitted data bits are placed in row 0 of eight  
successive 4-bit RAM words.  
• In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into  
row 0 and 1 of four successive 4-bit RAM words.  
• In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1 and 2 to  
three successive 4-bit RAM words, with row 2 of the third address left unchanged. It is  
not recommended to use this bit in a display because of the difficult addressing. This  
last bit may, if necessary, be controlled by an additional transfer to this address but  
care should be taken to avoid overwriting adjacent data because always full bytes are  
transmitted.  
• In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into  
row 0, 1, 2 and 3 of two successive 4-bit RAM words.  
7.11 Data pointer  
The addressing mechanism for the display RAM is realized using the data pointer.  
This allows the loading of an individual display data byte, or a series of display data bytes,  
into any location of the display RAM. The sequence commences with the initialization of  
the data pointer by the load-data-pointer command (see Section 7.17).  
Following this command, an arriving data byte is stored at the display RAM address  
indicated by the data pointer. The filling order is shown in Figure 11.  
After each byte is stored, the content of the data pointer is automatically incremented by a  
value dependent on the selected LCD drive mode:  
After each byte is stored, the contents of the data pointer is automatically incremented by  
a value dependent on the selected LCD drive mode:  
• In static drive mode by eight  
• In 1:2 multiplex drive mode by four  
• In 1:3 multiplex drive mode by three  
• In 1:4 multiplex drive mode by two  
If an I2C-bus data access is terminated early then the state of the data pointer is unknown.  
The data pointer should be re-written prior to further RAM accesses.  
7.12 Subaddress counter  
The storage of display data is determined by the contents of the subaddress counter.  
Storage is allowed to take place only when the contents of the subaddress counter match  
with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is  
defined by the device-select command (see Section 7.17). If the contents of the  
subaddress counter and the hardware subaddress do not match then data storage is  
inhibited but the data pointer is incremented as if data storage had taken place. The  
subaddress counter is also incremented when the data pointer overflows.  
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The storage arrangements described lead to extremely efficient data loading in cascaded  
applications. When a series of display bytes are sent to the display RAM, automatic  
wrap-over to the next PCA8576D occurs when the last RAM address is exceeded.  
Subaddressing across device boundaries is successful even if the change to the next  
device in the cascade occurs within a transmitted character (such as during the 14th  
display data byte transmitted in 1:3 multiplex mode).  
The hardware subaddress must not be changed while the device is being accessed on the  
I2C-bus interface.  
7.13 Output bank selector  
The output bank selector (see Table 13) selects one of the four rows per display RAM  
address for transfer to the display register. The actual row selected depends on the  
particular LCD drive mode in operation and on the instant in the multiplex sequence.  
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by  
the contents of row 1, 2, and then 3  
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially  
• In 1:2 multiplex mode, rows 0 and 1 are selected  
• In static mode, row 0 is selected  
The SYNC signal resets these sequences to the following starting points: row 3 for  
1:4 multiplex, row 2 for 1:3 multiplex, row 1 for 1:2 multiplex and row 0 for static mode.  
The PCA8576D includes a RAM bank switching feature in the static and 1:2 multiplex  
drive modes. In the static drive mode, the bank-select command may request the contents  
of row 2 to be selected for display instead of the contents of row 0. In the 1:2 mode, the  
contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the  
provision for preparing display information in an alternative bank and to be able to switch  
to it, once it is assembled.  
7.14 Input bank selector  
The input bank selector loads display data into the display RAM in accordance with the  
selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode  
or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command. The  
input bank selector functions independently to the output bank selector.  
7.15 Blinking  
The PCA8576D has a very versatile display blinking capability. The whole display can  
blink at a frequency selected by the blink-select command (see Table 14). Each blink  
frequency is a fraction of the clock frequency; the ratio between the clock frequency and  
blink frequency depends on the blink mode selected (see Table 6).  
An additional feature allows an arbitrary selection of LCD segments to blink in the static  
and 1:2 drive modes. This is implemented without any communication overheads by the  
output bank selector which alternates the displayed data between the data in the display  
RAM bank and the data in an alternative RAM bank at the blink frequency. This mode can  
also be implemented by the blink-select command (see Table 14).  
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In the 1:3 and 1:4 drive modes, where no alternative RAM bank is available, groups of  
LCD segments can blink selectively by changing the display RAM data at fixed time  
intervals.  
The entire display can blink at a frequency other than the nominal blink frequency by  
sequentially resetting and setting the display enable bit E at the required rate using the  
mode-set command (see Table 10).  
Table 6.  
Blinking frequencies[1]  
Blink mode  
Normal operating mode ratio  
Nominal blink frequency  
off  
1
-
blinking off  
2 Hz  
fclk  
---------  
768  
2
3
1 Hz  
fclk  
------------  
1536  
0.5 Hz  
fclk  
------------  
3072  
[1] Blink modes 1, 2 and 3 and the nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz correspond to an oscillator  
frequency (fclk) of 1536 Hz (see Section 11).  
7.16 Characteristics of the I2C-bus  
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.  
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must  
be connected to a positive supply via a pull-up resistor when connected to the output  
stages of a device. Data transfer may be initiated only when the bus is not busy.  
7.16.1 Bit transfer  
One data bit is transferred during each clock pulse. The data on the SDA line must remain  
stable during the HIGH period of the clock pulse as changes in the data line at this time  
will be interpreted as a control signal (see Figure 12).  
SDA  
SCL  
data line  
stable;  
data valid  
change  
of data  
allowed  
mba607  
Fig 12. Bit transfer  
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7.16.2 START and STOP conditions  
Both data and clock lines remain HIGH when the bus is not busy.  
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START  
condition - S.  
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP  
condition - P (see Figure 13).  
SDA  
SCL  
SDA  
SCL  
S
P
START condition  
STOP condition  
mbc622  
Fig 13. Definition of START and STOP conditions  
7.16.3 System configuration  
A device generating a message is a transmitter, a device receiving a message is the  
receiver. The device that controls the message is the master and the devices which are  
controlled by the master are the slaves (see Figure 14).  
MASTER  
TRANSMITTER/  
RECEIVER  
MASTER  
TRANSMITTER/  
RECEIVER  
SLAVE  
TRANSMITTER/  
RECEIVER  
SLAVE  
RECEIVER  
MASTER  
TRANSMITTER  
SDA  
SCL  
mga807  
Fig 14. System configuration  
7.16.4 Acknowledge  
The number of data bytes transferred between the START and STOP conditions from  
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge  
cycle.  
• A slave receiver which is addressed must generate an acknowledge after the  
reception of each byte.  
• Also a master receiver must generate an acknowledge after the reception of each  
byte that has been clocked out of the slave transmitter.  
• The device that acknowledges must pull-down the SDA line during the acknowledge  
clock pulse, so that the SDA line is stable LOW during the HIGH period of the  
acknowledge related clock pulse (set-up and hold times must be taken into  
consideration).  
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• A master receiver must signal an end of data to the transmitter by not generating an  
acknowledge on the last byte that has been clocked out of the slave. In this event the  
transmitter must leave the data line HIGH to enable the master to generate a STOP  
condition.  
Acknowledgement on the I2C-bus is shown in Figure 15.  
data output  
by transmitter  
not acknowledge  
data output  
by receiver  
acknowledge  
SCL from  
master  
1
2
8
9
S
clock pulse for  
acknowledgement  
START  
condition  
mbc602  
Fig 15. Acknowledgement of the I2C-bus  
7.16.5 I2C-bus controller  
The PCA8576D acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or  
transmit data to an I2C-bus master receiver. The only data output from the PCA8576D are  
the acknowledge signals of the selected devices. Device selection depends on the  
I2C-bus slave address, on the transferred command data and on the hardware  
subaddress.  
In single device applications, the hardware subaddress inputs A0, A1 and A2 are normally  
tied to VSS which defines the hardware subaddress 0. In multiple device  
applications A0, A1 and A2 are tied to VSS or VDD in accordance with a binary coding  
scheme such that no two devices with a common I2C-bus slave address have the same  
hardware subaddress.  
7.16.6 Input filters  
To enhance noise immunity in electrically adverse environments, RC low-pass filters are  
provided on the SDA and SCL lines.  
7.16.7 I2C-bus protocol  
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCA8576D.  
The PCA8576D slave address is illustrated in Table 7.  
Table 7.  
Bit  
I2C slave address byte  
Slave address  
7
6
5
4
3
2
1
0
MSB  
LSB  
R/W  
0
1
1
1
0
0
SA0  
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The least significant bit of the slave address that a PCA8576D will respond to is defined  
by the level tied to its SA0 input. The PCA8576D is a write-only device and will not  
respond to a read access. Having two reserved slave addresses allows the following on  
the same I2C-bus:  
• Up to 16 PCA8576D for very large LCD applications  
• The use of two types of LCD multiplex drive modes.  
The I2C-bus protocol is shown in Figure 16. The sequence is initiated with a START  
condition (S) from the I2C-bus master which is followed by one of two possible PCA8576D  
slave addresses available. All PCA8576D whose SA0 inputs correspond to bit 0 of the  
slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is  
ignored by all PCA8576D whose SA0 inputs are set to the alternative level.  
acknowledge  
acknowledge by  
by A0, A1 and A2  
all addressed  
selected  
PCA8576D only  
PCA8576D  
R/W  
0
slave address  
S
A
0
0
1
1
1
0
0
A
C
COMMAND  
n ≥ 1 byte(s)  
A
DISPLAY DATA  
n ≥ 0 byte(s)  
A
P
S
1 byte  
update data pointers  
and if necessary,  
subaddress counter  
013aaa470  
Fig 16. I2C-bus protocol  
After an acknowledgement, one or more command bytes follow, that define the status of  
each addressed PCA8576D.  
The last command byte sent is identified by resetting its most significant bit, continuation  
bit C, (see Figure 17). The command bytes are also acknowledged by all addressed  
PCA8576D on the bus.  
MSB  
LSB  
C
REST OF OPCODE  
msa833  
Fig 17. Format of command byte  
After the last command byte, one or more display data bytes may follow. Display data  
bytes are stored in the display RAM at the address specified by the data pointer and the  
subaddress counter. Both data pointer and subaddress counter are automatically updated  
and the data directed to the intended PCA8576D device.  
An acknowledgement after each byte is asserted only by the PCA8576D that are  
addressed via address lines A0, A1 and A2. After the last display byte, the I2C-bus master  
asserts a STOP condition (P). Alternately a START may be asserted to restart an I2C-bus  
access.  
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7.17 Command decoder  
The command decoder identifies command bytes that arrive on the I2C-bus. The  
commands available to the PCA8576D are defined in Table 8.  
Table 8.  
Definition of PCA8576D commands  
Operation Code  
Command  
Bit  
Reference  
7
6
1
0
1
1
1
5
4
3
2
1
0
[1]  
mode-set  
C
C
C
C
C
0
E
B
M[1:0]  
Table 10  
Table 11  
Table 12  
Table 13  
Table 14  
load-data-pointer  
device-select  
bank-select  
blink-select  
P[5:0]  
1
1
1
0
1
1
0
1
0
A[2:0]  
0
I
O
AB  
BF[1:0]  
[1] Not used.  
All available commands carry a continuation bit C in their most significant bit position as  
shown in Figure 17. When this bit is set, it indicates that the next byte of the transfer to  
arrive will also represent a command. If this bit is reset, it indicates that the command byte  
is the last in the transfer. Further bytes will be regarded as display data (see Table 9).  
Table 9.  
C bit description  
Bit  
Symbol Value  
Description  
continue bit  
7
C
0
last control byte in the transfer; next byte will be regarded  
as display data  
1
control bytes continue; next byte will be a command too  
Table 10. Mode-set command bit description  
Bit  
Symbol Value  
Description  
7
C
-
0, 1  
10  
-
see Table 9  
6 to 5  
fixed value  
4
3
-
unused  
E
display status  
0
1
disabled (blank)[1]  
enabled  
2
B
LCD bias configuration[2]  
13 bias  
12 bias  
0
1
1 to 0  
M[1:0]  
LCD drive mode selection  
static; BP0  
01  
10  
11  
00  
1:2 multiplex; BP0, BP1  
1:3 multiplex; BP0, BP1, BP2  
1:4 multiplex; BP0, BP1, BP2, BP3  
[1] The possibility to disable the display allows implementation of blinking under external control.  
[2] Not applicable for static drive mode.  
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Table 11. Load-data-pointer command bit description  
Bit  
7
Symbol Value  
Description  
see Table 9  
fixed value  
C
0, 1  
0
6
-
5 to 0  
P[5:0]  
000000 to  
100111  
6 bit binary value, 0 to 39; transferred to the data pointer to  
define one of forty display RAM addresses  
Table 12. Device-select command bit description  
Bit  
Symbol Value  
Description  
see Table 9  
fixed value  
7
C
0, 1  
6 to 3  
2 to 0  
-
1100  
A[2:0]  
000 to 111  
3 bit binary value, 0 to 7; transferred to the subaddress  
counter to define one of eight hardware subaddresses  
Table 13. Bank-select command bit description  
Bit  
Symbol Value  
Description  
Static  
1:2 multiplex[1]  
7
C
-
0, 1  
see Table 9  
fixed value  
6 to 2  
1
11110  
I
input bank selection; storage of arriving display data  
0
1
RAM bit 0  
RAM bit 2  
RAM bits 0 and 1  
RAM bits 2 and 3  
0
O
output bank selection; retrieval of LCD display data  
0
1
RAM bit 0  
RAM bit 2  
RAM bits 0 and 1  
RAM bits 2 and 3  
[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.  
Table 14. Blink-select command bit description  
Bit  
7
Symbol Value  
Description  
C
0, 1  
see Table 9  
6 to 3  
2
-
1110  
fixed value  
AB  
blink mode selection  
0
1
normal blinking[1]  
alternate RAM bank blinking[2]  
1 to 0  
BF[1:0]  
blink frequency selection  
00  
01  
10  
11  
off  
1
2
3
[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.  
[2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.  
PCA8576D  
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Automotive 40 x 4 LCD segment driver for low multiplex rates  
7.18 Display controller  
The display controller executes the commands identified by the command decoder. It  
contains the device’s status registers and coordinates their effects. The display controller  
is also responsible for loading display data into the display RAM in the correct filling order.  
8. Internal circuitry  
V
V
DD  
DD  
SA0  
CLK  
V
V
V
SS  
DD  
SS  
SCL  
V
V
SS  
DD  
V
SS  
OSC  
V
V
SS  
DD  
SDA  
SYNC  
V
V
V
SS  
SS  
DD  
A0, A1 A2  
V
V
SS  
LCD  
BP0, BP1,  
BP2, BP3  
V
V
SS  
V
LCD  
LCD  
S0 to S39  
V
V
SS  
SS  
mdb076  
Fig 18. Device protection circuits  
PCA8576D  
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PCA8576D  
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Automotive 40 x 4 LCD segment driver for low multiplex rates  
9. Limiting values  
CAUTION  
Static voltages across the liquid crystal display can build up when the LCD supply voltage  
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted  
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.  
Table 15. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol Parameter  
Conditions  
Min  
0.5  
0.5  
0.5  
Max  
+6.5  
+7.5  
+6.5  
Unit  
V
VDD  
VLCD  
VI  
supply voltage  
LCD supply voltage  
input voltage  
V
on each of the pins CLK,  
SDA, SCL, SYNC, SA0,  
OSC, A0 to A2  
V
VO  
output voltage  
on each of the pins S0 to  
S39, BP0 to BP3  
0.5  
+7.5  
V
II  
input current  
output current  
supply current  
10  
10  
50  
50  
50  
-
+10  
mA  
mA  
mA  
mA  
mA  
mW  
mW  
V
IO  
IDD  
+10  
+50  
IDD(LCD) LCD supply current  
+50  
ISS  
ground supply current  
total power dissipation  
output power  
+50  
Ptot  
Po  
400  
-
100  
[1]  
[2]  
[3]  
[4]  
VESD  
electrostatic discharge  
voltage  
HBM  
MM  
-
5000  
200  
100  
-
V
Ilu  
latch-up current  
-
mA  
C  
Tstg  
Tamb  
storage temperature  
ambient temperature  
65  
40  
+150  
+85  
operating device  
C  
[1] Pass level; Human Body Model (HBM) according to Ref. 6 “JESD22-A114”.  
[2] Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”.  
[3] Pass level; latch-up testing according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max)).  
[4] According to the NXP store and transport requirements (see Ref. 10 “NX3-00092”) the devices have to be  
stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. For long-term storage products,  
divergent conditions are described in that document.  
PCA8576D  
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PCA8576D  
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Automotive 40 x 4 LCD segment driver for low multiplex rates  
10. Static characteristics  
Table 16. Static characteristics  
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Supplies  
VDD  
supply voltage  
1.8  
2.5  
-
-
5.5  
6.5  
20  
-
V
[1]  
[2]  
VLCD  
IDD  
LCD supply voltage  
supply current  
-
V
fclk(ext) = 1536 Hz  
6
A  
A  
VDD = 3.0 V;  
-
2.7  
Tamb = 25 C  
[2]  
IDD(LCD)  
LCD supply current  
fclk(ext) = 1536 Hz  
-
-
18  
30  
-
A  
A  
VLCD = 3.0 V;  
17.5  
Tamb = 25 C  
Logic[3]  
VP(POR)  
VIL  
power-on reset supply voltage  
LOW-level input voltage  
1.0  
1.3  
-
1.6  
V
V
on pins CLK, SYNC,  
OSC, A0 to A2, SA0,  
SCL, SDA  
VSS  
0.3VDD  
[4][5]  
VIH  
HIGH-level input voltage  
LOW-level output current  
on pins CLK, SYNC,  
OSC, A0 to A2, SA0,  
SCL, SDA  
0.7VDD  
-
VDD  
V
IOL  
output sink current;  
VOL = 0.4 V; VDD = 5 V  
on pins CLK and SYNC  
on pin SDA  
1
3
1
-
-
-
-
-
-
mA  
mA  
mA  
IOH(CLK)  
IL  
HIGH-level output current on pin CLK output source current;  
VOH = 4.6 V; VDD = 5 V  
leakage current  
VI = VDD or VSS  
;
1  
-
+1  
A  
on pins CLK, SCL, SDA,  
A0 to A2 and SA0  
IL(OSC)  
leakage current on pin OSC  
input capacitance  
VI = VDD  
1  
-
-
+1  
7
A  
[6]  
[7]  
CI  
-
pF  
LCD outputs  
VO  
output voltage variation  
on pins BP0 to BP3 and  
S0 to S39  
100  
-
+100  
mV  
RO  
output resistance  
VLCD = 5 V  
on pins BP0 to BP3  
on pins S0 to S39  
-
-
1.5  
6.0  
-
-
k  
k  
[1] VLCD > 3 V for 13 bias.  
[2] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.  
[3] The I2C-bus interface of PCA8576D is 5 V tolerant.  
[4] When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 15.  
[5] Propagation delay of driver between clock (CLK) and LCD driving signals.  
[6] Periodically sampled, not 100 % tested.  
[7] Outputs measured one at a time.  
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Automotive 40 x 4 LCD segment driver for low multiplex rates  
11. Dynamic characteristics  
Table 17. Dynamic characteristics  
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Clock  
fclk(int)  
fclk(ext)  
tclk(H)  
tclk(L)  
[1]  
internal clock frequency  
external clock frequency  
HIGH-level clock time  
LOW-level clock time  
1440  
960  
60  
1850  
2640  
Hz  
Hz  
s  
s  
-
-
-
2640  
-
-
60  
Synchronization  
tPD(SYNC_N) SYNC propagation delay  
-
30  
-
-
ns  
s  
s  
tSYNC_NL  
tPD(drv)  
I2C-bus[3]  
Pin SCL  
fSCL  
SYNC LOW time  
1
-
-
[2]  
driver propagation delay  
VLCD = 5 V  
-
30  
SCL clock frequency  
-
-
-
-
400  
kHz  
s  
tLOW  
LOW period of the SCL clock  
HIGH period of the SCL clock  
1.3  
0.6  
-
-
tHIGH  
s  
Pin SDA  
tSU;DAT  
tHD;DAT  
data set-up time  
data hold time  
100  
0
-
-
-
-
ns  
ns  
Pins SCL and SDA  
tBUF  
bus free time between a STOP and  
1.3  
-
-
s  
START condition  
tSU;STO  
tHD;STA  
tSU;STA  
set-up time for STOP condition  
hold time (repeated) START condition  
0.6  
0.6  
0.6  
-
-
-
-
-
-
s  
s  
s  
set-up time for a repeated START  
condition  
tr  
rise time of both SDA and SCL signals fSCL = 400 kHz  
fSCL < 125 kHz  
-
-
-
-
-
-
-
-
-
-
0.3  
1.0  
0.3  
400  
50  
s  
s  
s  
pF  
ns  
tf  
fall time of both SDA and SCL signals  
capacitive load for each bus line  
Cb  
tw(spike)  
spike pulse width  
on the I2C-bus  
[1] Typical output duty factor: 50 % measured at the CLK output pin.  
[2] Not tested in production.  
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an  
input voltage swing of VSS to VDD  
.
PCA8576D  
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Automotive 40 x 4 LCD segment driver for low multiplex rates  
1 / f  
CLK  
t
t
clk(L)  
clk(H)  
0.7 V  
0.3 V  
DD  
DD  
CLK  
0.7 V  
0.3 V  
DD  
DD  
SYNC  
t
PD(SYNC_N)  
t
SYNC_NL  
0.5 V  
BP0 to BP3,  
and S0 to S39  
(V  
DD  
= 5 V)  
0.5 V  
t
001aai163  
PD(drv)  
Fig 19. Driver timing waveforms  
SDA  
t
t
t
f
BUF  
LOW  
SCL  
SDA  
t
HD;STA  
t
t
t
SU;DAT  
r
HD;DAT  
t
HIGH  
t
SU;STA  
t
SU;STO  
mga728  
Fig 20. I2C-bus timing waveforms  
PCA8576D  
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Automotive 40 x 4 LCD segment driver for low multiplex rates  
12. Application information  
12.1 Cascaded operation  
In large display configurations, up to 16 PCA8576D can be differentiated on the same  
I2C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the  
programmable I2C-bus slave address (SA0).  
Table 18. Addressing cascaded PCA8576D  
Cluster  
Bit SA0  
Pin A2  
Pin A1  
Pin A0  
Device  
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
2
1
8
9
10  
11  
12  
13  
14  
15  
The PCA8576D connected in cascade are synchronized to allow the backplane signals  
from only one device in the cascade to be shared. This arrangement is cost-effective in  
large LCD applications since the backplane outputs of only one device need to be  
through-plated to the backplane electrodes of the display. The other cascaded PCA8576D  
contribute additional segment outputs but their backplane outputs are left open-circuit  
(see Figure 21).  
All PCA8576D connected in cascade are correctly synchronized by the SYNC signal. This  
synchronization is guaranteed after the power-on reset. The only time that SYNC is likely  
to be needed is if synchronization is lost accidentally, for example, by noise in adverse  
electrical environments, or if the LCD multiplex drive mode is changed in an application  
using several cascaded PCA8576D, as the drive mode cannot be changed on all of the  
cascaded devices simultaneously. SYNC can be either an input or an output signal; a  
SYNC output is implemented as an open-drain driver with an internal pull-up resistor.  
The PCA8576D asserts SYNC at the start of its last active backplane signal and monitors  
the SYNC line at all other times. If cascade synchronization is lost, it is restored by the first  
PCA8576D to assert SYNC. The timing relationship between the backplane waveforms  
and the SYNC signal for each LCD drive mode is shown in Figure 22.  
PCA8576D  
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Product data sheet  
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PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
The contact resistance between the SYNC on each cascaded device must be controlled.  
If the resistance is too high, the device is not able to synchronize properly; this is  
particularly applicable to chip-on-glass applications. The maximum SYNC contact  
resistance allowed for the number of devices in cascade is given in Table 19.  
Table 19. SYNC contact resistance  
Number of devices  
Maximum contact resistance  
2
6 k  
3 to 5  
6 to 10  
10 to 16  
2.2 k  
1.2 k  
700   
The PCA8576D can be cascaded with the PCA8534A. This allows optimal drive selection  
for a given number of pixels to display. Figure 19 and Figure 20 show the timing of the  
synchronization signals.  
V
V
LCD  
DD  
SDA  
SCL  
40 segment drives  
LCD PANEL  
SYNC  
CLK  
PCA8576D  
(up to 2560  
elements)  
OSC  
BP0 to BP3  
(open-circuit)  
A0 A1 A2 SA0 V  
SS  
V
V
LCD  
t
DD  
r
R ≤  
2C  
V
V
LCD  
B
DD  
40 segment drives  
SDA  
SCL  
HOST  
MICRO-  
PROCESSOR/  
MICRO-  
SYNC  
4 backplanes  
BP0 to BP3  
PCA8576D  
CONTROLLER  
CLK  
OSC  
013aaa471  
A0 A1 A2 SA0 V  
SS  
V
SS  
Fig 21. Cascaded PCA8576D configuration  
PCA8576D  
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Automotive 40 x 4 LCD segment driver for low multiplex rates  
1
T
=
fr  
f
fr  
BP0  
SYNC  
(a) static drive mode.  
BP0  
(1/2 bias)  
BP0  
(1/3 bias)  
SYNC  
(b) 1:2 multiplex drive mode.  
BP0  
(1/3 bias)  
SYNC  
(c) 1:3 multiplex drive mode.  
BP0  
(1/3 bias)  
SYNC  
(d) 1:4 multiplex drive mode.  
mgl755  
Fig 22. Synchronization of the cascade for the various PCA8576D drive modes  
12.2 RAM writing in 1:3 multiplex drive mode  
In 1:3 multiplex drive mode, the RAM is written as shown in Table 20 (see Figure 11 as  
well).  
Table 20. Standard RAM filling in 1:3 multiplex drive mode  
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.  
Display RAM  
bits (rows)/  
backplane  
Display RAM addresses (columns)/segment outputs (Sn)  
0
1
2
3
4
5
6
7
8
9
:
outputs (BPn)  
0
1
2
3
a7  
a6  
a5  
-
a4  
a3  
a2  
-
a1  
a0  
-
b7  
b6  
b5  
-
b4  
b3  
b2  
-
b1  
b0  
-
c7  
c6  
c5  
-
c4  
c3  
c2  
-
c1  
c0  
-
d7  
d6  
d5  
-
:
:
:
:
-
-
-
If the bit at position BP2/S2 would be written by a second byte transmitted, then the  
mapping of the segment bits would change as illustrated in Table 21.  
PCA8576D  
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Automotive 40 x 4 LCD segment driver for low multiplex rates  
Table 21. Continuos RAM filling by rewriting in 1:3 multiplex drive mode  
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.  
Display RAM  
bits (rows)/  
backplane  
Display RAM addresses (columns)/segment outputs (Sn)  
0
1
2
3
4
5
6
7
8
9
:
outputs (BPn)  
0
1
2
3
a7  
a6  
a5  
-
a4  
a3  
a2  
-
a1/b7 b4  
a0/b6 b3  
b1/c7 c4  
b0/c6 c3  
c1/d7 d4  
c0/d6 d3  
d1/e7 e4  
d0/e6 e3  
:
:
:
:
b5  
-
b2  
-
c5  
-
c2  
-
d5  
-
d2  
-
e5  
-
e2  
-
In the case described in Table 21 the RAM has to be written entirely and BP2/S2, BP2/S5,  
BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a  
combination of writing and rewriting the RAM like follows:  
• In the first write to the RAM, bits a7 to a0 are written.  
• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7  
and b6.  
• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and  
c6.  
Depending on the method of writing to the RAM (standard or continuous filling by  
rewriting), some elements remain unused or can be used, but it has to be considered in  
the module layout process as well as in the driver software design.  
13. Test information  
13.1 Quality information  
This product has been qualified in accordance with the Automotive Electronics Council  
(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated  
circuits, and is suitable for use in automotive applications.  
PCA8576D  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
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PCA8576D  
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Automotive 40 x 4 LCD segment driver for low multiplex rates  
14. Bare die outline  
Bare die; 59 bumps  
PCA8576DU/2DA  
D
(1)  
35  
22  
Y
21  
e
36  
x
E
0
0
y
51  
9
C2 52  
59 1  
8
C1  
X
L
A
A
b
2
detail X  
A
1
detail Y  
0
0.5  
1 mm  
scale  
Notes  
1. Marking code: PC8576D-2  
pca8576du_2da_do  
References  
Outline  
version  
European  
projection  
Issue date  
IEC  
JEDEC  
JEITA  
11-03-07  
11-03-10  
PCA8576DU/2DA  
Fig 23. Bare die outline PCA8576DU/2DA/2 (for dimensions see Table 22)  
PCA8576D  
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Automotive 40 x 4 LCD segment driver for low multiplex rates  
Table 22. Dimensions of PCA8576DU  
Original dimensions are in mm.  
Unit (mm)  
max  
A
A1  
A2  
b
D
-
E
-
e[1]  
L
-
-
-
-
-
-
nom  
0.40  
-
0.015  
-
0.381  
-
0.052  
-
2.2  
-
2.0  
-
-
0.077  
-
min  
0.072  
[1] Dimension not drawn to scale.  
Table 23. Bump location for PCA8576DU  
All x/y coordinates represent the position of the center of each bump with respect to the center  
(x/y = 0) of the chip (see Figure 2 and Figure 23).  
Symbol  
SDA  
SCL  
SCL  
SYNC  
CLK  
VDD  
OSC  
A0  
Bump  
1
X (m)  
34.38  
109.53  
181.53  
365.58  
469.08  
577.08  
740.88  
835.83  
1005.48  
1005.48  
1005.48  
1005.48  
1005.48  
1005.48  
1005.48  
1005.48  
1005.48  
1005.48  
1005.48  
1005.48  
1005.48  
347.22  
263.97  
180.72  
97.47  
Y (m)  
876.6  
876.6  
876.6  
876.6  
876.6  
876.6  
876.6  
876.6  
630.9  
513.9  
396.9  
221.4  
10.71  
Description  
I2C-bus serial data input/output  
I2C-bus serial clock input  
2
3
4
cascade synchronization input/output  
external clock input/output  
supply voltage  
5
6
7
internal oscillator enable input  
subaddress inputs  
8
A1  
9
A2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
SA0  
VSS  
VLCD  
BP0  
BP2  
BP1  
BP3  
S0  
I2C-bus address input; bit 0  
ground supply voltage  
LCD supply voltage  
156.51  
232.74  
308.97  
385.2  
LCD backplane outputs  
493.2  
LCD segment outputs  
LCD segment outputs  
S1  
565.2  
S2  
637.2  
S3  
709.2  
S4  
876.6  
S5  
876.6  
S6  
876.6  
S7  
876.6  
S8  
14.22  
876.6  
S9  
69.03  
152.28  
235.53  
318.78  
876.6  
S10  
S11  
S12  
876.6  
876.6  
876.6  
PCA8576D  
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© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
35 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
Table 23. Bump location for PCA8576DU …continued  
All x/y coordinates represent the position of the center of each bump with respect to the center  
(x/y = 0) of the chip (see Figure 2 and Figure 23).  
Symbol  
S13  
S14  
S15  
S16  
S17  
S18  
S19  
S20  
S21  
S22  
S23  
S24  
S25  
S26  
S27  
S28  
S29  
S30  
S31  
S32  
S33  
S34  
S35  
S36  
S37  
S38  
S39  
SDA  
SDA  
Bump  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
X (m)  
Y (m)  
876.6  
Description  
402.03  
485.28  
568.53  
651.78  
735.03  
1005.5  
1005.5  
1005.5  
1005.5  
1005.5  
1005.5  
1005.5  
1005.5  
1005.5  
1005.5  
1005.5  
1005.5  
1005.5  
1005.5  
1005.5  
1005.5  
735.03  
663.03  
591.03  
519.03  
447.03  
375.03  
196.38  
106.38  
876.6  
876.6  
876.6  
876.6  
625.59  
541.62  
458.19  
374.76  
291.33  
207.9  
124.47  
41.04  
42.39  
125.8  
209.3  
292.7  
376.1  
459.5  
543  
625.6  
876.6  
876.6  
876.6  
876.6  
876.6  
876.6  
876.6  
876.6  
LCD segment outputs  
I2C-bus serial data input/output  
Table 24. Alignment marks  
All x/y coordinates represent the position of the center of each alignment mark with respect to the  
center (x/y = 0) of the chip (see Figure 2 and Figure 23).  
Symbol  
C1  
X (m)  
930.42  
829.98  
Y (m)  
870.3  
870.3  
C2  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
36 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
15. Handling information  
All input and output pins are protected against ElectroStatic Discharge (ESD) under  
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that  
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent  
standards.  
16. Packing information  
16.1 Tray information  
x
G
A
C
H
y
1,1  
1,2  
2,1  
x,1  
D
B
F
x,y  
1,y  
E
mce404  
Fig 24. Tray details  
Table 25. Tray dimensions (see Figure 24)  
Symbol  
Description  
Value  
5.59  
6.35  
3.16  
3.16  
50.8  
50.8  
5.83  
6.35  
8
Unit  
mm  
mm  
mm  
mm  
mm  
mm  
mm  
mm  
-
A
B
C
D
E
F
G
H
x
pocket pitch in x direction  
pocket pitch in y direction  
pocket width in x direction  
pocket width in y direction  
tray width in x direction  
tray width in y direction  
cut corner to pocket 1.1 center  
cut corner to pocket 1.1 center  
number of pockets, x direction  
number of pockets, y direction  
y
7
-
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
37 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
PC8576D  
mdb080  
Fig 25. Tray alignment  
17. Abbreviations  
Table 26. Abbreviations  
Acronym  
CMOS  
HBM  
ITO  
Description  
Complementary Metal-Oxide Semiconductor  
Human Body Model  
Indium Tin Oxide  
LCD  
Liquid Crystal Display  
Least Significant Bit  
Machine Model  
LSB  
MM  
MSB  
PCB  
RAM  
RMS  
SCL  
Most Significant Bit  
Printed Circuit Board  
Random Access Memory  
Root Mean Square  
Serial CLock line  
SDA  
Serial DAta line  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
38 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
18. References  
[1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD  
drivers  
[2] AN10706 — Handling bare die  
[3] IEC 60134 — Rating systems for electronic tubes and valves and analogous  
semiconductor devices  
[4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena  
[5] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for  
Nonhermetic Solid State Surface Mount Devices  
[6] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body  
Model (HBM)  
[7] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model  
(MM)  
[8] JESD78 — IC Latch-Up Test  
[9] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive  
(ESDS) Devices  
[10] NX3-00092 — NXP store and transport requirements  
[11] UM10204 — I2C-bus specification and user manual  
19. Revision history  
Table 27. Revision history  
Document ID  
Release date  
20110404  
Data sheet status  
Change notice  
Supersedes  
PCA8576D v.1  
Product data sheet  
-
-
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
39 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
20. Legal information  
20.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
suitable for use in medical, military, aircraft, space or life support equipment,  
20.2 Definitions  
nor in applications where failure or malfunction of an NXP Semiconductors  
product can reasonably be expected to result in personal injury, death or  
severe property or environmental damage. NXP Semiconductors accepts no  
liability for inclusion and/or use of NXP Semiconductors products in such  
equipment or applications and therefore such inclusion and/or use is at the  
customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
20.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Suitability for use in automotive applications — This NXP  
Semiconductors product has been qualified for use in automotive  
applications. The product is not designed, authorized or warranted to be  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
40 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
systems after third party sawing, handling, packing or assembly of the die. It  
is the responsibility of the customer to test and qualify their application in  
which the die is used.  
All die sales are conditioned upon and subject to the customer entering into a  
written die sale agreement with NXP Semiconductors through its legal  
department.  
Bare die — All die are tested on compliance with their related technical  
specifications as stated in this data sheet up to the point of wafer sawing and  
are handled in accordance with the NXP Semiconductors storage and  
transportation conditions. If there are data sheet limits not guaranteed, these  
will be separately indicated in the data sheet. There are no post-packing tests  
performed on individual die or wafers.  
20.4 Trademarks  
NXP Semiconductors has no control of third party procedures in the sawing,  
handling, packing or assembly of the die. Accordingly, NXP Semiconductors  
assumes no liability for device functionality or performance of the die or  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
I2C-bus — logo is a trademark of NXP B.V.  
21. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
PCA8576D  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 1 — 4 April 2011  
41 of 42  
PCA8576D  
NXP Semiconductors  
Automotive 40 x 4 LCD segment driver for low multiplex rates  
22. Contents  
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1  
12.1  
12.2  
Cascaded operation. . . . . . . . . . . . . . . . . . . . 30  
RAM writing in 1:3 multiplex drive mode . . . . 32  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
13  
13.1  
14  
Test information . . . . . . . . . . . . . . . . . . . . . . . 33  
Quality information. . . . . . . . . . . . . . . . . . . . . 33  
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 34  
Handling information . . . . . . . . . . . . . . . . . . . 37  
Packing information . . . . . . . . . . . . . . . . . . . . 37  
Tray information . . . . . . . . . . . . . . . . . . . . . . . 37  
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38  
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Revision history . . . . . . . . . . . . . . . . . . . . . . . 39  
15  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4  
16  
16.1  
17  
7
7.1  
7.2  
7.3  
7.3.1  
7.4  
7.4.1  
7.4.2  
7.4.3  
7.4.4  
7.5  
7.5.1  
7.5.2  
7.6  
Functional description . . . . . . . . . . . . . . . . . . . 5  
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 5  
LCD bias generator . . . . . . . . . . . . . . . . . . . . . 6  
LCD voltage selector . . . . . . . . . . . . . . . . . . . . 6  
Electro-optical performance . . . . . . . . . . . . . . . 7  
LCD drive mode waveforms . . . . . . . . . . . . . . . 9  
Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9  
1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 10  
1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 12  
1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 13  
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 14  
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Display register. . . . . . . . . . . . . . . . . . . . . . . . 14  
Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14  
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 14  
Display RAM. . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Subaddress counter . . . . . . . . . . . . . . . . . . . . 17  
Output bank selector . . . . . . . . . . . . . . . . . . . 18  
Input bank selector . . . . . . . . . . . . . . . . . . . . . 18  
Blinking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Characteristics of the I2C-bus. . . . . . . . . . . . . 19  
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
START and STOP conditions . . . . . . . . . . . . . 20  
System configuration . . . . . . . . . . . . . . . . . . . 20  
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20  
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 21  
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21  
Command decoder. . . . . . . . . . . . . . . . . . . . . 23  
Display controller . . . . . . . . . . . . . . . . . . . . . . 25  
18  
19  
20  
Legal information . . . . . . . . . . . . . . . . . . . . . . 40  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 40  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
20.1  
20.2  
20.3  
20.4  
21  
22  
Contact information . . . . . . . . . . . . . . . . . . . . 41  
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
7.7  
7.8  
7.9  
7.10  
7.11  
7.12  
7.13  
7.14  
7.15  
7.16  
7.16.1  
7.16.2  
7.16.3  
7.16.4  
7.16.5  
7.16.6  
7.16.7  
7.17  
7.18  
8
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 25  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26  
Static characteristics. . . . . . . . . . . . . . . . . . . . 27  
Dynamic characteristics . . . . . . . . . . . . . . . . . 28  
Application information. . . . . . . . . . . . . . . . . . 30  
9
10  
11  
12  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2011.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 4 April 2011  
Document identifier: PCA8576D  

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