PCA9420 [NXP]
Power management IC for low-power microcontroller applications;
| 型号： | PCA9420 |
| 厂家： | 
NXP |
| 描述： | Power management IC for low-power microcontroller applications |
| 文件： | 总82页 (文件大小：1167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9420
Power management IC for low-power microcontroller
applications
Rev. 2 — 26 January 2021
Product data sheet
1 General description
The PCA9420 is a highly-integrated Power Management IC (PMIC), targeted to provide
a full power management solution for low power microcontroller applications or other
similar applications.
The device consists of a linear battery charger capable of charging up to 315 mA current.
It has an I2C programmable Constant Current (CC) and Constant Voltage (CV) values
for flexible configuration. Various built-in protection features such as input overvoltage
protection, overcurrent protection, thermal protection, etc. are also provided for safe
battery charging. It also features JEITA compliant charging.
The device also integrates two step-down (buck) DC/DC converters which have I2C
programmable output voltage. Both buck regulators have integrated high-side and low-
side switches and related control circuitry, to minimize the external component counts;
a Pulse-Frequency Modulation (PFM) approach is utilized to achieve better efficiency
under light load condition. Other protection features such as overcurrent protection,
under-voltage lockout (UVLO), etc. are also provided. By default, the input for these
regulators is powered by either VIN or VBAT, whichever is greater.
In addition, two on-chip LDO regulators are provided to power up various voltage rails in
the system.
Other features such as FM+ I2C-bus interface, chip enable, interrupt signal, etc. are also
provided.
The chip is offered in 2.09 mm x 2.09 mm, 5 x 5 bump, 0.4 mm pitch WLCSP package;
and 3 mm x 3 mm, 24-pin QFN package.
2 Features and Benefits
• Linear battery charger for charging single cell li-ion battery
– 20 V tolerance on VIN pin
– Programmable input OVP (5.5 V or 6 V)
– Programmable constant current (up to 315 mA) and pre-charge low voltage current
threshold
– Programmable constant voltage regulation
– Programmable automatic recharge voltage and termination current threshold
– Built-in protection features such as input OVP, battery SCP, thermal protection
– JEITA compliant
– Battery attached detection
– Over-temperature protection
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
• Two step-down DC/DC converters
– Very low quiescent current
– Programmable output voltage
– SW1: core buck converter, 0.5 V~1.5 V output, 25 mV/step, and a fixed 1.8 V, up to
250 mA
– SW2: system buck converter, 1.5 V~2.1 V/2.7 V~3.3 V output, 25 mV/step, up to
500 mA
– Low power mode for extra power saving
• Two LDOs
– Programmable output voltage regulation
– LDO1: always-on LDO, 1.70 V~1.90 V output, 25 mV/step, up to 1 mA
– LDO2: system LDO, 1.5 V~2.1 V/2.7 V~3.3 V output, 25 mV/step, up to 250 mA
• 1 MHz I2C-bus slave interface
• -40 °C ~ +85 °C ambient temperature range
• Offered in 5 x 5 bump-array WLCSP and 24-pin QFN package
3 Applications
• Low power microcontroller application
4 Ordering information
Table 1.ꢀOrdering information
Type number
Topside Package
marking
Name
Description
Version
PCA9420BS
PCA9420UK
420
HVQFN24
plastic thermal enhanced very thin quad flat package; no SOT905-1
leads; 24 terminals; body 3 x 3 x 0.85 mm
9420
WLCSP25
wafer level chip-scale package, 25 terminals, 0.4 mm
pitch, 2.09 mm x 2.09 mm x 0.525 mm body
SOT1401-4
4.1 Ordering options
Table 2.ꢀOrdering options
Type number Orderable part Package
number
Packing method
Minimum order
quantity
Temperature range
PCA9420BS
PCA9420BSAZ HVQFN24
REEL 7" Q2 NDP
1400
3000
-40°C to +85°C
-40°C to +85°C
PCA9420UK PCA9420UKZ
WLCSP25
REEL 7" Q1 DP CHIPS
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
2 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
5 Simplified block diagram
Reverse
Blocking
VIN
VIN ≤ 6V
2.2µF/
ASYS
4.7µF/
10V
OVP
Detection
10V
Thermal
Max 315mA
If VIN is greater than 6V, the
voltage rating on the capacitor of
2.2µF/10V shall be changed to a
higher voltage than a maximum
voltage in applications.
Regulation (5.5V default or
6V over I2C)
VBAT
Linear Charger
(80°C to
EN
115°C)
1µF/
10V
1
2
A programmed
ICHG_CC
X
I2
C
Battery
absence
detection
+ (VBAT)
1-Cell
Li-Ion
Battery
Watchdog
(disable, 16s,
32s, 64s)
ASYS_
Pre-
warning
+
-
100mV
- (GND)
+
VIN_
UVLO
200mV
Input Current Limit (typical): 85mA, 255mA, 425mA, 595mA, 765mA, 935mA,
1105mA, or disable
-
3.3V,3.4V,
3.5V (default),3.6V
Linear charger: 0mA to 315mA in 5mA steps for charge current
2.9V,3.1V(default),
3.3V,3.5V
*
: Regardless of mode setting
+
ASYS_
UVLO
Regulator
TDIE
+
Default (V)* Output Range
1.0
Resolution Max Current
100mV
Thermal
shutdown
-
20°C
-
BUCK1
BUCK2
0.5V to 1.5V and fixed 1.8V
25mV
250mA
500mA
(MTP)
1.8
(MTP)
1.8
1.5V to 2.1V or 2.7V to 3.3V 25mV
2.4V,2.5V, 2.6V,
2.7V (default)
3-bit
programmable
(95°C to 125°C
in 5°C steps)
25mV
25mV
LDO1
LDO2
1.7V to 1.9V
1mA
(MTP)
3.3
(MTP)
1.5V to 2.1V or 2.7V to 3.3V
250mA
TDIE
20°C
+
-
Thermal
warning
PSYS1
ASYS
1µF/
10V
2-bit
STEP-DOWN
CONVERTER 1
250mA
(0.5V-1.5V
in 25mV steps
& fixed 1.8V)
programmable
(75°C to 90°C
in 5°C steps)
PGND1
2.2µH
Default:1.0V
ENTER
SHIP_EN_x=1
VDDCORE
LX1
SHIP
MODE
EXIT
10µF/
6.3V
Valid VIN
2.5V
OR
or VBAT
SW1_OUT
I2
C
50Ω
EN
1MΩ
Debounce
Filter
Power-on
from off or
ship-mode
ON
OFF
(200µs)
On-Key
ON
PSYS2
Valid VIN
ASYS
2.2µF/
10V
STEP-DOWN
CONVERTER 2
500mA
SHIP_WKUP_CFG=0
PGND2
2.2µH
PCA9420
Long-Key
Debounce
Filter
(4s, 8s(default)
,12s,16s)
Default:1.8V
VDDIO_1,2,3,
and/or 4
(1.5V-2.1V in
25mV steps)
(or 2.7V-3.3V
in 25mV steps)
Recycle
Power rails
LX2
Main
Control
Blocks
10µF/
6.3V
VDD1V8 and
other 1.8V power
SW2_OUT
Add 1.2V
offset
I2
C
50Ω
Power-down
sequence
i.MXRT*
RT600
PWR_DN_EN=1
EN
VDDIO_1
+
-
VBAT_
BKUP_
UVLO
100mV
SCL
Option
Option: can be remove if an
PMIC_I2C_SCL
(VDDIO_1)
VBAT
1.9V
Up to 1MHz
VBAT_BKUP
internal pull-up is available
R
I2C Interface
on i.MXRT* device
SDA
INTB
PMIC_I2C_SDA
(VDDIO_1)
0.47µF/
6.3V
ASYS
VDD_AO1V8
Coin
battery
IN
R1
R2
PMIC_IRQN
(VDD_AO1V8)
LDO1
1mA
Interrupts
LDO1_OUT
VDD_AO1V8
Always-on
1.8V
(1.7V-1.9V
in 25mV steps)
1µF/
6.3V
50Ω
SYSRSTn
R1=R2=20kΩ to 220kΩ
RESETN
(VDD_AO1V8)
Power-Good
&
Reset
I2
C
EN
EN
ASYS
IN
I2
C
i.MXRT*
RT600
ASYS
LDO2
250mA
Default:
3.3V
LDO2_OUT
50µA
5µA
VDDIO_1,2,3,
and/or 4
(1.5V-2.1V in
25mV steps)
(or 2.7V-3.3V
in 25mV steps)
2.2µF/
6.3V
50Ω
USB1_VDD3V3
and other
3V power
TS
ADC
NTC
Control
Block
Add 1.2V
offset
I2
C
NTC
Can be connected to any ADC
β
selction
EN
I2C
MODESEL0
MODESEL1
PMIC_MODE0
(VDD_AO1V8)
3-bit programmable
From 3434k to 4750k
MODE
SELECTION
PMIC_MODE1
(VDD_AO1V8)
EN_MODE_SEL_BY_PIN_x=1 (x can be 0, 1, 2 or 3)
25-Bump WLCSP, 0.4mm pitch,
2.09mm x 2.09mm
Note: All directions for the arrows in the schematic are
made from the PCA9420 perspective.
MODESEL1
MODESEL0 Output Voltage Setting
LOW (0)
LOW (0)
HIGH (1)
HIGH (1)
LOW (0)
HIGH (1)
LOW (0)
HIGH (1)
Mode Setting 0
Mode Setting 1
AGND1 AGND2
AGND3
Mode Setting 2
Mode Setting 3
Short on PCB
aaa-033067
Figure 1.ꢀSimplified block diagram
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
3 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
6 Pinning information
6.1 Pinning
terminal 1
index area
LX2
1
2
17 ASYS
16 VIN
PSYS2
PCA9420BS
SW2_OUT
3
15 LDO2_OUT
Exposed pad
ON
4
5
14 TS
SCL
13 VBAT_BKUP
aaa-033076
Transparent top view
Figure 2.ꢀPCA9420BS pinout (HVQFN24) – top view
pin A1
index area
1
3
5
2
4
PSYS
1
PGND
1
PGND
2
VBAT
LX1
A
B
SW1_
OUT
AGND
1
SW2_
OUT
ASYS
VIN
LX2
AGND
2
PSYS
2
TS
ON
C
D
E
LDO2
_OUT
VBAT_
BKUP
SYS
RSTn
INTB
SCL
LDO1
_OUT
AGND
3
MODE
SEL1
MODE
SEL0
SDA
aaa-033077
Figure 3.ꢀPCA9420UK pinout (WLCSP25) – top view
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
4 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
6.2 Pin description
Table 3.ꢀPin Description
Symbol
Pin
Pin Type
Description
HVQFN24
WLCSP25
INPUT SUPPLY
VIN
16
C1
P
Input supply voltage. Bypass with a 2.2µF/10V ceramic
capacitor. If VIN is greater than 6V, the voltage rating shall
be changed to a higher voltage than the maximum voltage
in applications.
ASYS
17
13
B1
D2
P
P
Bypass output of VIN and input supply voltage for LDO2,
connect with a typical 4.7µF or 10µF/10V decoupling
capacitor.
VBAT_BKUP
Backup battery input voltage. LDO1 is powered by the
greater of ASYS or VAT_BKUP. If a back-up battery with a
coin cell is not connected, connect the pin to VBAT power
domain. Connect with a typical 0.47µF/6.3V decoupling
capacitor.
LINEAR CHARGER
VBAT
18
A1
C2
P
I
Battery (+) connection point. A typical 1µF/10V decoupling
capacitor should be connected between VBAT to system
ground.
TS
14
Battery temperature sensing pin. An external thermistor is
connected between TS pin and system ground.
BUCK1 STEP_DOWN CONVERTER (SW1)
PSYS1
20
A2
P
Input supply for SW1. Bypass with a typical 1µF/10V
ceramic capacitor. Connect to ASYS power domain as short
as possible in the system.
LX1
22
19
23
A3
B2
A4
P
I
Switching node for SW1. Connect to a 2.2µH inductor.
Feedback pin. Bypass with a 10µF/6.3V ceramic capacitor.
SW1_OUT
PGND1
P
Power ground for buck 1 (SW1). Connect ground nodes of
two bypass capacitors for PSYS1 and SW1_OUT as close
to PGND1 pin as possible in the system.
BUCK2 STEP_DOWN CONVERTER (SW2)
PSYS2
2
C5
P
Input supply for SW2. Bypass with a typical 2.2µF/10V
ceramic capacitor. Connect to ASYS power domain as short
as possible in the system.
LX2
1
B5
B4
A5
P
I
Switching node for SW2. Connect to a 2.2µH inductor.
Feedback pin. Bypass with a 10µF/6.3V ceramic capacitor.
SW2_OUT
PGND2
3
24
P
Power ground for buck 2 (SW2). Connect ground nodes of
two bypass capacitors for PSYS2 and SW2_OUT as close
to PGND2 pin as possible in the system.
LOW_DROPOUT REGULATORS (LDO1 and LDO2)
LDO1_OUT
12
E1
P
LDO1 output. It is always-ON supply. The input supply is a
higher voltage between ASYS and VBAT_BKUP. Bypass
with a 1µF/6.3V ceramic capacitor.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
5 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 3.ꢀPin Description...continued
Symbol
Pin
Pin Type
Description
HVQFN24
15
WLCSP25
LDO2_OUT
D1
P
LDO2 output. The input supply is ASYS. Bypass with a
2.2µF/6.3V ceramic capacitor.
LOGIC INPUTS
ON Pin with an internal pull-up resistor, 1MΩ typ, to either
2.5V or VBAT. Refer to Section 8.3 for more details.
ON
4
C4
I
MODESEL0
7
8
E4
E3
I
I
Mode selection input pin #1
Mode selection input pin #2
MODESEL1
LOGIC OUTPUTS
Interrupt output, Open-drain type. Place a pull-up resistor
from 20kΩ to 220kΩ to a system I/O supply rail.
INTB
10
11
D4
D3
O
O
Reset output for external MCU, Open-drain type. Place a
pull-up resistor from 20kΩ to 220kΩ to a system I/O supply
rail.
SYSRSTn
SERIAL I2C INTERFACE
I2C Interface clock pin. Place a pull-up resistor between
2.2kΩ and 10kΩ to a system I/O supply rail.
I2C Interface data pin. Place a pull-up resistor between
2.2kΩ and 10kΩ to a system I/O supply rail.
SCL
SDA
5
6
D5
E5
I
I/O
DEVICE GROUND
AGND1
AGND2
AGND3
9
B3
C3
E2
P
P
P
Analog ground. It shall be connected to system ground
through a via. Do not connect AGND1 and AGND2 to
PGND1 or PGND2 on the top PCB layer in the system.
21
Exposed
Pad
Exposed pad. Connect to system ground
P = Power, I = Input, I/O = input/output
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
6 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
7 System configuration diagram
If VIN is greater than 6V, the voltage
rating on the capacitor of 2.2µF/10V
shall be changed to a higher
voltage than a maximum voltage
in applications.
A1
VBAT
1µF/
10V
Input Current Limit (typical): 85mA, 255mA, 425mA, 595mA, 765mA, 935mA,
1105mA, or disable
Linearcharger: 0mA to 315mA in 5mA steps for charge current
+ (VBAT)
1-Cell
Li-Ion
Battery
Input Supply
* : Regardless of mode setting
VIN ≤ 6V C1
VBUS
VIN
Default (V)*
2.2µF/
10V
Regulator
Output Range
Resolution Max Current
1.0
(MTP)
1.8
(MTP)
1.8
(MTP)
3.3
(MTP)
BUCK1
BUCK2
0.5V to 1.5V and fixed 1.8V
25mV
250mA
500mA
- (GND)
1.5V to 2.1V or 2.7V to 3.3V 25mV
GND
B1
ASYS
25mV
25mV
LDO1
LDO2
1.7V to 1.9V
1mA
4.7µF/
10V
1.5V to 2.1V or 2.7V to 3.3V
250mA
C4
ON
OFF
On-Key
button
A2
A4
ON
If the pin is not used,
leave the pin open
PSYS1
PGND1
1µF/
10V
2.2µH
Default:1.0V
A3
B2
VBAT
LX1
VDDCORE
10µF/
6.3V
D2
VBAT_BKUP
0.47µF/
6.3V
SW1_OUT
If a coil cell is not used, tie
with the VBAT power domain
Coin
battery
E1
C5
A5
VDD_AO1V8
LDO1_OUT
ASYS
2.2µF/
10V
PSYS2
PGND2
Always-on
1.8V
1µF/
6.3V
PCA9420
i.MXRT
RT5xx
RT6xx
2.2µH
Default:1.8V
B5
B4
VDDIO_1,2,3,
and/or 4
LX2
10µF/
6.3V
VDD1V8 and
other 1.8V power
SW2_OUT
Default:
3.3V
D1
VDDIO_1,2,3,
and/or 4
i.MXRT
RT5xx
RT6xx
LDO2_OUT
2.2µF/
6.3V
VDDIO_1
Option
USB1_VDD3V3
and other
3V.3V power
D5
E5
PMIC_I2C_SCL
(VDDIO_1)
SCL
Option: can be removed if an
internal pull-up R is available
on i.MXRT* device
If the pin is not used,
leave the pin open
E4
E3
PMIC_MODE0
(VDD_AO1V8)
PMIC_I2C_SDA
(VDDIO_1)
MODESEL0
SDA
INTB
VDD_AO1V8
PMIC_MODE1
(VDD_AO1V8)
MODESEL1
R1
R2
D4
D3
PMIC_IRQN
(VDD_AO1V8)
(x can be 0, 1, 2 or 3)
EN_MODE_SEL_BY_PIN_x=1
MODESEL1
MODESEL0 Output Voltage Setting
LOW (0)
LOW (0)
HIGH (1)
HIGH (1)
LOW (0)
HIGH (1)
LOW (0)
HIGH (1)
Mode Setting 0
RESETN
(VDD_AO1V8)
SYSRSTn
Mode Setting 1
Mode Setting 2
Mode Setting 3
R1=R2=100-220kΩ
C2
If the pin is not used,
leave the pin open
Note: All directions for the arrows in the
schematic are made from the PCA9420
perspective.
ADC
TS
Can be connected to any ADC
NTC
25-Bump WLCSP, 0.4mm pitch,
2.1mm x 2.1mm
AGND1 AGND2
AGND3
E2
B3
C3
aaa-033078
Short on PCB
Figure 4.ꢀSystem configuration diagram; i.MXRT series
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
7 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
VIN
LDO1_OUT
(AO_LDO)
VDD_BAT
VDD_IO
ASYS
PSYS1
PSYS2
LDO2_OUT
(System LDO)
PGND
VBAT_BKUP
LX1
VDD_CORE
SW1_OUT
(Core Buck)
K4 Family MCU
PCA9420
VBAT
TS
VDD_SYS
LX2
Battery
Pack
SW2_OUT
(SYS Buck)
T
SYSRSTn
MODESEL0
MODESEL1
ON
RESET_n
SPM_LPREQ
RTC_WAKEUP_n
LPI2Cn_SCL
SCL
AGND1/2/3
LPI2Cn_SDA
SDA
INTB
GPIO_n
aaa-033079
Figure 5.ꢀSystem configuration diagram; K4-family MCU
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
8 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
8 Functional description
8.1 ASYS
The ASYS pin serves as the input power pin for SW1, SW2 and LDO2. Internally by
default it’s powered by either VIN or VBAT, whichever is greater. The internal ASYS input
selection circuit ensures a seamless transition when its input source changes from VIN to
VBAT, or vice versa.
Through I2C register setting selection (SYS_INPUT_SEL [1:0]), the user also has the
option to choose the ASYS input source. However, upon power cycling and/or chip reset,
the ASYS input source goes back to the default setting (option 1 below).
SYS_INPUT_SEL [1:0]
1. 2b’00: From either VBAT or VIN, whichever is greater (default setting);
2. 2b’01: From VBAT only;
3. 2b’10: From VIN only;
4. 2b’11: Disconnect from VBAT or VIN (not a normal operation condition, for test
purposes only).
An I2C programmable pre-warning ASYS voltage threshold (ASYS_PRE_WARNING
[1:0]) can also be used to indicate when ASYS voltage drops below the ASYS pre-
warning threshold voltage, which triggers an interrupt event.
If any peripheral regulators are connected to ASYS node, the ASYS node follows a VIN
voltage up to a programmed OVP threshold (either 5.5V or 6V) with a various voltage
difference depending on a load current.
8.2 VBAT_BKUP (back-up battery input)
Internally, the input power source for LDO1 is provided by either VBAT_BKUP or ASYS,
whichever is greater. When a coin cell battery (or similar battery) is used in the system
as a backup battery, it can be connected to VBAT_BKUP; thus the LDO1 is powered
by either ASYS or the backup battery. When no such backup battery is used, the
VBAT_BKUP pin should always be connected to VBAT.
8.3 ON
The ON pin has the following functions implemented:
1. ON pin has internal 1MΩ pull-up resistor to either 2.5V or VBAT depending on VBAT
voltage. If VBAT is less than 3V, ON is pulled up to 2.5V and if VBAT is greater than
3V, it is pulled to VBAT.
Falling edge (filtered after deglitching time, 200µs typ), active-low signal enables the
chip. If the chip stays in ship mode before applying ON falling edge, upon the filtered
falling edge of the ON pin, the chip exits ship mode to start up into Mode Setting 0.
If the device is already in the middle of power-up or power-down sequence, the falling
edge applied on the ON pin is ignored by the chip.
1. Long press (duration time, 4s, 8s, 12s or 16s, is programmable via I2C,
ON_GLT_LONG [1:0]). If the logic low signal is applied continuously over a
programmed duration, the chip gets reset and recycles all power rails to their default
values
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
9 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
2. Also, in mode setting 0, 1, 2, or 3, an I2C bit “ON_CFG_x“ (x=0, 1, 2, or 3) is reserved;
by setting its value to either 0 or 1, the user can configure whether a mode setting
switches back to Mode Setting 0 or not, upon a valid falling edge detected from “ON”
pin. Refer to ON_CFG_x bit description in the relation registers for more details.
3. The filtered falling edge on the ON pin resets the bit of EN_MODE_SEL_BY_PIN_A to
the default value, 0, at 22h register.
8.4 TS
With the temperature sensing pin, the external thermistor (NTC) is connected between
the TS pin and ground. The thermistor may be included in the battery pack to monitor the
battery pack temperature, or it may be an additional component user chooses to have on
the board level to monitor the temperature at a chosen area.
The voltage at TS pin is monitored, and the user can enable the feature through I2C-bus
interface (NTC_EN) to implement JEITA compliant charging at a safe temperature. Per
JEITA standard, there are four temperature threshold settings:
1. Cold threshold (T1, 0°C as example)
2. Cool threshold (T2, 10°C as example)
3. Warm threshold (T3, 45°C as example)
4. Hot threshold (T4, 60°C as example)
Each of the above temperature thresholds represents a voltage threshold. When the
monitored temperature, T, falls into a different temperature zone, the charger should
adjust the charging method accordingly:
1. T > T4 or T < T1, i.e., when the temperature is in a “cold” or “hot” zone, charging is
suspended, as well as the safety timer;
2. T1 < T < T2, charging current is reduced by 50% of the programmed current level;
3. T2 < T < T3, normal charging;
4. T3 < T < T4, the CV mode regulating voltage should be set as VBAT_REG [5:0] –
ΔVBAT_REG(HOT), 140mV typical
To disable this function, set NTC_EN to “0”.
8.5 Mode setting
When the MCU operates in different modes such as overdrive run mode or low power
mode, it may require the power supply to operate in different settings accordingly (for
example, enable/disable of each rail, output voltage of each rail, etc.) to achieve a better
performance and efficiency.
On the PCA9420, there are four modes of registers representing Mode Setting A/B/C/
D to accommodate such requirements from MCU, where Mode Setting A is the default
mode setting (i.e., the initial mode setting upon initial power up). Depending on the user’s
preference, switching among different mode settings can be controlled by either the
external signal (ON pin), external pins (MODESEL0/1) or I2C.
Within each mode setting, the user can program the follow parameters providing great
flexibility to accommodate different MCU operation modes:
1. Enable/disable of the four output voltage rails
2. Voltage setting of the four output voltage rails
3. Ship mode enable/disable
4. Watchdog timer setting
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
10 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
5. Mode control selection (EN_MODE_SEL_BY_PIN_x, x=0, 1, 2, or 3)
EN_MODE_SEL_BY_PIN_x = 0: under current mode setting, mode setting switch is
controlled by internal I2C register bits MODE0_I2C and/or MODE1_I2C only; signal
applied on external MODESEL0/MODESEL1 pins is ignored.
EN_MODE_SEL_BY_PIN_x = 1: under current mode setting, mode setting switch is
controlled by signal applied on external MODESEL0 and/or MODESEL1 pins only, not by
internal I2C register bits MODE0_I2C and MODE1_I2C.
1. Mode setting switches back to Mode Setting A triggered by ON pin falling edge. Refer
to register description for “ON_CFG_x” bit for more details.
In the event of switching from one mode setting (initial mode setting) to another mode
setting (target mode setting):
1. If one output rail remains enabled in both initial mode setting and target mode setting
but with different output voltage in each setting, such voltage transition should happen
when the mode setting switch command (from either internal I2C setting or external
signal) is received;
2. If there are output rails which may be enabled or disabled from initial mode setting to
target mode setting, then always make sure these rails which change from disabled
to enabled take higher priority over rails which change from enabled to disabled, i.e.,
make sure all the rails change from disabled status to enabled status (reaches 90% of
its target value) first, and then start to disable these rails, changing from enable status
to disable status.
8.6 Mode selection by external pins (MODESEL0, MODESEL1)
Up on initial power-up, PCA9420 enters its default setting (Mode Setting
0). While operating under Mode Setting 0, by default the I2C register bit,
EN_MODE_SEL_BY_PINEN_MODE_SEL_BY_PIN_0, is set to “0”, and the external
signal applied on the MODESEL0 and MODESEL1 pins are ignored. Only when the user
sets EN_MODE_SEL_BY_PINEN_MODE_SEL_BY_PIN_0 to “1”, can the mode control
on the chip be programmed via MODESEL0 and MODESEL1 pin signal settings.
Table 4.ꢀMode Selection by external pins (MODESEL0, MODESEL1)
MODESEL1 pin voltage level
MODESEL0 pin voltage level
All Settings from
Mode Setting 0
Mode Setting 1
Mode Setting 2
Mode Setting 3
LOW (0)
LOW (0)
HIGH (1)
HIGH (1)
LOW (0)
HIGH (1)
LOW (0)
HIGH (1)
8.7 SYSRSTn
The SYSRSTn is implemented as an open-drain output signal. It is used as an output of
“power-good” indication as well as to reset the microcontroller system.
The SYSRSTn signal is held from high to low under one of following conditions:
1. When any of the enabled voltage rail output voltage drops below 90% (typ) of its
target value.
2. When any of the enabled voltage rail output voltage goes above 110% (typ) of its
target value
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
11 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
If any of the voltage rail is disabled by the user (by setting the corresponding enable
bit in I2C register in each mode setting, i.e., LDO1_EN_x, LDO2_EN_x, SW1_EN_x,
SW2_EN_x), the SYSRSTn signal should NOT assert (stays high) under such scenario.
This also applies during the power-up/power-down sequence events, i.e., during power-
up or power-down event, the SYSRSTn signal should assert when any of the enabled rail
has not reaches the 90% ~ 110% of its target value. In other words, the SYSRSTn = 0
(low) needs to remain at such state until all enabled rails reach 90% of the target values.
1. When a programmed watchdog timer expires (only when watchdog timer is enabled)
Once the condition that caused the SYSRSTn signal to go low is removed, then the
SYSRSTn should refresh accordingly.
Meanwhile, during the voltage change on-the-fly, this could be caused by:
1. Mode setting remains the same, but the user chooses to change one or some of the
enabled output rail voltage by programming its output voltage I2C register setting
2. Mode setting changes by setting different values on MODESEL0/MODESEL1 pins or
MODE0_I2C/MODE1_I2C bits, and it causes one or some of the output rail voltage
change
In such case, the SYSRSTn signal does NOT assert when any of the enabled voltage
rail output voltage is in the middle of the transition from initial output voltage level to
target level.
8.8 SHIP mode
PCA9420 features a “SHIP mode”, in which the chip provides the lowest quiescent
consumption.
To enter the SHIP mode, set the bit of SHIP_EN_x (x can be 0, 1, 2 or 3) in each Mode
register to 1. Once the bit is set to 1, the ship mode immediately takes place regardless
of any operation under any mode setting. It means that the SHIP mode has a higher
priority over any conditions and operations.
Upon request to enter the ship mode while the device is running in active mode, a power-
down sequence should take place first and then enter the ship mode. Once the device
enters ship mode, all the I2C register values are reset to their default setting.
To exit ship mode, one of the following conditions must be satisfied:
1. ON pin falling edge (filtered) applied, less than the long-press duration of time
2. A valid VIN attached. For the VIN attached plugin event, depending on
OPERATION_SEL_FROM_SHIPMODE bit setting, there are two possible operations
as described below:
a. OPERATION_SEL_FROM_SHIPMODE=0, upon VIN attached, the chip enables
the charging process, as well as start the power-up sequence for LDO1/LDO2/
SW1/SW2 per the setting
b. OPERATION_SEL_FROM_SHIPMODE=1, upon VIN attached, the chip enables
the charging process, LDO1/LDO2/SW1/SW2 remains in shutdown mode and the
chip will only enable the power-up sequence upon ON pin falling edge signal.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
12 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
8.9 Watchdog timer
PCA9420 provides an on-chip watchdog timer, the duration of this watchdog can be
programmed via I2C register setting (WD_TIMER_x [1:0] in each mode configuration
registers), or disabled if needed in each mode setting.
Upon initial enable, the watchdog timer starts counting. If the watchdog timer expires
before reset, an interrupt signal is issued (WD_TIMER). Depending on the I2C register
setting (nEN_CHG_IN_WATCHDOG), the following action is also taken:
1. nEN_CHG_IN_WATCHDOG = 0: when the watchdog timer expires, the following
operations are expected.
• The SYSRSTn signal asserted (high to low)
• Charging is continued based on battery condition
• All settings for LDO1/LDO2/SW1/SW2 set to Mode 0 settings
2. nEN_CHG_IN_WATCHDOG=1: when the watchdog timer expires, the following
operations are expected.
• The SYSRSTn signal asserted (high to low)
• Charging is suspended
• All settings for LDO1/LDO2/SW1/SW2 set to Mode 0 settings
The following events reset the watchdog timer:
1. When WD_TIMER_CLR bit is set to 3b’001 at 0Dh register
2. When the device changes the mode settings
8.10 Regulators
There are four regulators on PCA9420, which include two buck regulators and two LDOs.
Table 5 shows the outline for each regulator:
Table 5.ꢀ Regulator summary
Regulator name
SW1 (Core Buck)
SW2 (System Buck)
Output regulation voltage range
0.5V ~ 1.5V and a fixed 1.8V
1.5V ~ 2.1V or 2.7V~3.3V
Adjustable resolution
25mV/step
Max output current
Up to 250mA
Up to 500mA
Up to 1mA
25mV/step
LDO1 (Always-on LDO) 1.7V ~ 1.9V
LDO2 (System LDO) 1.5V ~ 2.1V or 2.7V~3.3V
25mV/step
25mV/step
Up to 250mA
For each rail, its output target voltage can be set independently in mode setting 0, 1, 2 or
3. User can also choose to switch among any of the mode settings.
8.10.1 Enable/disable and active discharge
Enable/disable: Each rail can be enabled/disabled via I2C register setting independently
in each mode setting.
Active discharge: Additionally, there is an active discharge resistor on each rail, and
the user can choose to enable/disable such feature through I2C register setting, so that
when the output rail is disabled, it can quickly discharge the output voltage to ground.
In addition, the active discharge is also enabled during voltage step down. This can be
disabled by MTP bit.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
13 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
8.10.2 Power-good indication
There is an output voltage comparator for each rail, comparing the actual output voltage
against 90% and 110% of its target value; when the actual voltage is between 90% and
110% of its target value, the read-only related bits in I2C register, Regulator Status_1
(address: 20h) are updated accordingly to report the output voltage status (Power-good
Indication). These comparators can be enabled/disabled by setting I2C register bit,
PG_EN. A corresponding interrupt is triggered if unmasked. During steady state, only
90% threshold is monitored.
The power-good indication is shown as “not good”, and refreshes upon the completion of
any of the following events:
1. During the power-up sequence stage
2. During power-down sequence stage
3. During the on-the-fly change of output voltage
8.10.3 Power-up/down sequence and on-the-fly voltage change
Power-up sequence
The device initiates the default power-up sequence in three different conditions.
Condition 1) The device is off with no any power supply (No valid VIN and No battery
with 2.7V or above attached). In this condition, two signals below are able to start the
default power-up sequence.
• A valid VIN supply on VIN pin
• A voltage on ASYS higher than ASYS_UVLO, a 2.8V typical
Condition 2) The device stays off by enabling SHIPMODE or in SHIP mode with a
battery ≥ 2.8V attached. In this condition, two signals are able to start the default power-
up sequence.
• A valid VIN supply on VIN pin
• A falling edge on ON key over a 200µs
Condition 3) The device stays off by enabling PWR_DN_EN bit setting to 1 with a
battery ≥ 2.8V attached. In this condition, only one signal is able to start the default
power-up sequence.
• A falling edge on ON key over a 200µs
Condition 4) The device stays at VIN OVP condition with no any valid supply attached
at VBAT. In result, all enabled power rails have been off. The following condition re-
initiates the power-up sequence.
• The VIN goes below its VIN OVP hysteresis (typ 100mV)
The power-up sequence by ON key=Low over the debounce time is described as shown
in Figure 6.
For the power-up sequence, the chip can set the default sequence per the customer
requirement at factory setting (i.e. MTP option), from one of the 64 options. Once the chip
enters the power-down stage, the power-down sequence is implemented as the reverse
of the power-up sequence (i.e., first up, last down).
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
14 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
The ON Key shall be pulled high
t
ON_LONG_PRESS
to avoid power recycle initiated
by a programmed ON long-Press
timer expired
(ON Long-Press Timer, 4s,8s,12s or 16s)
TON_DEBOUNCE
=200µs
ON Key
TPWDOWN_DLY_INTERVAL
=2ms
PWR_DN_EN bit=1
OR
Position 1
90%
2
3
4 (NOTE)
SHIP_EN_x bit=1
Default-On Rails
Position 4
3
2
1
TPWUP_DLY_INTERVAL
=1ms
SYSRSTn
CONTROL BY PROCESSOR
POWER-UP SEQUENCE
POWER-DOWN SEQUENCE
POWER-OFF STATE
NOTE: BUCK1, BUCK2, LDO1 and LDO2 can be assigned to any of position 1-4
Figure 6.ꢀPower-up/down sequence
aaa-033080
On-the-fly output voltage change sequence
On-the-fly output voltage change is defined as the following: for any output rail, its
output voltage changes from one level (initial level) to another level (target level). Note
this assumes the output rail is always enabled before and after the on-the-fly change
transition. It does not include the case when any output rail is changed from disabled
state to enabled state, or vice versa.
If a user prefers to change any rail voltage on-the-fly, depending on the scenarios listed
below, the chip behavior is described as the following:
1. While the chip remains in its current operation mode, and the user programs the
output voltage setting I2C register value or enables/disables any or some of output
voltage rail(s), the chip simply executes the I2C command
2. While the user chooses to switch modes, i.e. change mode between any of the two
mode settings among Mode 0/1/2/3, and if this involves on-the-fly voltage change for
one or some output rails, such change should occur simultaneously when the chip
switches from initial mode to the target mode.
CAUTION: The user should not send an I2C command related to changing the setting of
the output rails during the power up/down or mode setting change process.
8.10.4 BUCK1 (SW1, core buck regulator)
The SW1 supplies the core power.
Its output voltage can be programmed via I2C from 0.5V to 1.5V at 25mV step and a fixed
1.8V, which is capable of providing up to 250mA loading. The application circuit uses
typical 2.2µH inductor and 10µF/6.3V output capacitor.
8.10.5 BUCK2 (SW2, system buck regulator)
The SW2 output voltage can be programmed via I2C register from 1.5V to 2.1V, or from
2.7V to 3.3V in both at 25mV/step and is capable of providing up to 500mA loading. The
application circuit uses a 2.2µH inductor and 10µF output capacitor.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
15 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
In SW2, a pass-through mode is implemented. When its input (ASYS) is close to the
output voltage (within typical 200mV), the SW2 enters the pass-through mode operation;
the high-side switch is fully turned on and the low-side switch is turned off, and the output
voltage can be calculated as input voltage – (RDSON*ILOAD), where RDSON is the on-
resistance of the high-side switch, and the ILOAD refers to the load current. When the
input voltage rises again, so that the voltage different between input and output crosses
the typical 250mV threshold, the SW2 exits the pass-through mode and re- enters the
normal switching mode operation.
While SW2 operates in pass-through mode, protection features such as over-current
protection are also implemented as well.
VPSYS2
50mV
(VPSYS2 - VSW2_Regulation)=200mV
Delta V
VSW2_Regulation
Delta V=RRDS_ON_High_side x ILOAD
SW2 in pass-through mode
SW2 in regulation mode
SW2 in regulation mode
aaa-033081
Figure 7.ꢀPass-Through mode of BUCK2 (SW2)
8.10.6 LDO1 (always-on LDO)
The LDO1 (Always-on LDO) output can be programmed from 1.7V to 1.9V at 25mV step,
depending on the system requirements (selectable through I2C register). Typically, a
1µF/6.3V MLCC output capacitor providing at least 1mA loading capability is needed.
8.10.7 LDO2 (system LDO)
The LDO2 (system LDO) output can be programmed via the I2C register from 1.5V
to 2.1V, or 2.7V to 3.3V at 25mV/step. Typically, a 2.2µF/6.3V MLCC output capacitor
providing at least 250mA loading current is needed.
8.11 Linear battery charger
The battery charger is a linear charger. Its charging is done through a linear switch with
the following output protections:
• Reverse current protection
– (triggers when VIN < VBAT+ VIN2BAT_HEADROOM*)
• Charging current limiting
– (a function of programmed threshold and battery temperature)
• VBAT short circuit protection
– short circuit output voltage threshold: (typ 0.8V with 80mV hysteresis)
– Maximum output sourcing current during “short circuit” detection ~ 13mA
(VIN2BAT_HEADROOM = 100mV, typical)
If the battery voltage is below the VBAT_LOW threshold, the battery is considered
discharged and a preconditioning cycle begins. The amount of pre-charge current
(ICHG_LOW) can be programmed through I2C register setting. This feature is useful
when there is a load connected directly across the battery (at VBAT pin) “stealing” the
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
16 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
battery current. The pre-charge current can be set higher to account for the system
loading while allowing the battery to be properly conditioned. Once the battery voltage
has charged to the VBAT_LOW threshold, fast charge is initiated and a programmed fast
charge current (ICHG_CC) is applied. The fast charge constant current is programmed
using I2C register. The constant current provides the bulk of the charge. Power
dissipation in the device is greatest in fast charge with a lower battery voltage.
If the device reaches a programmed thermal regulation threshold temperature from 85°C
to 115°C in 5°C steps, the device enters thermal regulation. Thermal regulation increases
the safe-charging-timer period by 2x and reduces the charge current in half (if the initial
current is 5mA, it will remain unchanged) to keep the temperature from rising any further
when battery charger works in constant current charging mode, or at a reduced regulated
voltage when battery charger works in constant voltage charging mode.
Figure 8 shows the charging profile with a dead battery condition. Once the cell has
charged to the regulation voltage (VBAT_REG) the voltage loop takes control and holds
the battery at the regulation voltage until the current tapers to the termination threshold
(ICHG_TOPOFF).
8.11.1 Battery charging management
Battery charging management supports typical constant current/constant voltage
charging profile for single cell Li-Ion battery, as well as pre-qualification (dead battery, low
battery), top-off mode, etc.; JEITA and thermal regulation compliant.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
17 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
VBAT
3.6V to 4.6V, 20mV steps, 4.2V Default
BAT_REG
V
VBAT_RESTART
(=VBAT_REG-140mV or 240mVtyp)
VBAT
tDGL_BAT_RESTART=50ms
2.5V
(2.3V,2.4V,2.6V by MTP)
VBAT_LOW
1.9V
(1.7V,1.8V,2V by MTP)
VBAT_DEAD
0V
Time
Recharge Mode
(Fast Charge Mode)
Trickle Charge
(Dead Battery)
Mode
Pre-charge
(Low-Voltage)
Mode
Top-OFF
Mode
Fast Charge Mode
Fast Charge Mode
Charging Done Mode
Input & Charge Current
85mA to 1105mA programmable
IVIN__LIM
5mA to 315mA programmable in 5mA steps
I
CHG_CC
Shall be updated with 1mA to 20mA Programmable
in 1mA steps due to top-off problem
1mA to 63mA programmable
in 1mA steps
CHG_LOW
di/dt=3mA/µs
I
tDGL_BAT_LOW2CC=50µs
1mA to 63mA programmable
in 1mA steps
Current to battery
I
CHG_TOPOFF
ICHG_TOPOFF
1mA to 63mA programmable
in 1mA steps
t
DGL_BAT_CC2TOPOFF=20ms
I
CHG_DEAD
ICHG=0mA
0mA
OFF
t
DGL_BAT_DEAD2LOW=50µs
T
CHG_TOPOFF
Time
T
CHG_TOPOFF started
T
CHG_TOPOFF expired
15, 30, 45,
or 60min
T
CHG_PREQ
ON
reset
3, 5, 7, or 9 hours
ON
OFF
OFF
T
CHG_FAST
reset
0, 6.4, 12.8, or 19.2min
T
CHG_TOPOFF
ON
reset
aaa-033082
Figure 8.ꢀTypical Charging Profile Example
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
18 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Device in non-charging mode
- VIN < VINUVLO
- CHG_EN=0 or 1
- TJ < TJ(OFF), 150°C
Charging Stopped
VIN has been validated
&&
A programmed watchdog timer expired in
nEN_CHG_IN_WATCHDOG=1
&& WD_TIMER_A/B/C/D=2b01, 10, or 11
or
Battery attached
&&
CHG_EN=1
TJ ≥ a programmed TSHDN
or
One of the safety timers (TCHG_PREQ & TCHG_FAST) expired
Device in Dead Battery Charging
- Charge current=ICHG_DEAD
- TCHG_PREQ started counting
VBAT ≤ VBAT_DEAD
Any Charging State
VBAT > VBAT_DEAD
&&
tDGL_BAT_DEAD2LOW, 50µs
Charging in Thermal Regulation
_1
2
- ICHG= (A programmed ICHG_CC) x
VBAT ≤> VBAT_LOW
&&
tDGL_BAT_CC2LOW, 50ms
Device in Pre-Charge
(Low Voltage) Mode
- Charge current=ICHG_LOW
TJ = A programmed TTHEM_REGULATION
Any Charging State
VBAT > VBAT_LOW
&&
tDGL_BAT_LOW2CC, 50µs
Device in Fast Charge Mode
- Charge current=ICHG_CC
- TCHG_PREQ reset
- TCHG_FAST started counting
ICHG > 2x ICHG_TOPOFF or
20mA, whichever is lower
ICHG < ICHG_TOPOFF for
tDGL_BAT_CC2TOPOFF, 20ms
VBAT-VBAT_REG ≤ VBAT_RESTART, 140mV typ
(240mV by MTP)
&&
Device in Top-Off Mode
- TCHG_FAST reset
- TCHG_TOPOFF started counting
t
DGL_BAT_RESTART, 50ms
TCHG_TOPOFF expired
Device in DONE Mode
- TCHG_TOPOFF reset
- ICHG=0mA
aaa-033083
Figure 9.ꢀCharger State Diagram
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
19 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
8.11.2 Battery temperature sensing and JEITA-compliant charging profile
45°C
10°C
0°C
Programmed VBAT_REG
Hot fault
No operation
charge disable
during cold fault
Programmed ICHG
(100%)
50%
1.0
Cold fault
1.4
0
0.2
0.4
0.6
0.8
1.2
VCOLD
1.6
1.8
VHOT VWARM
VCOOL
Termination
disable
TS voltage-V
aaa-033084
Figure 10.ꢀOperation over TS bias voltage for JEITA
8.11.3 Low-battery/dead-battery (pre-qualification) charging
If the battery is detected and VBAT < VBAT_LOW, the charger initiates pre-charging
using a predefined (I2C register) current.
When it is under the dead-battery condition, the charging current ICHG_DEAD is
programmed by ICHG_DEAD [5:0]; and when it is under the low-battery condition, the
charging current ICHG_LOW is programmed by ICHG_LOW [5:0]. When VBAT ≥ VBAT_LOW
the charger moves to the next state, fast charging mode.
,
8.11.4 Constant current charging/constant voltage charging (fast charging) and
termination
When VBAT ≥ VBAT_LOW, the charger enters Fast Charge Mode (Constant Current). In this
state, the battery voltage VBAT continues to rise, while the battery is being charged with
the current set by ICHG_CC [5:0], until VBAT reaches the maximum allowable voltage
set by VBAT_REG [5:0].
At this time, the charger enters the Constant Voltage (CV) mode. While operating in
the CV mode, the voltage is still regulated at the level set by VBAT_REG [5:0], and the
charging current continues to decrease.
When the charging current drops below the top-off current threshold, set by
ICHG_TOPOFF [5:0], the charger enters TOPOFF mode, and upon expiration of
TOPOFF timer (set by T_TOPOFF [1:0]), the charger enters DONE mode.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
20 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
8.11.5 Charger safety timers
Two sets of charging safety timers are implemented on PCA9420. These timers
ensure the charging is terminated if the charging time is longer than its predefined limit
(programmed via I2C registers) at given states:
• Pre-qualification timer, set by ICHG_PREQ_TIMER [1:0], 15min ~ 60min
• Fast charge timer, set by ICHG_FAST_TIMER [1:0], 3hr ~ 9hr
8.11.6 Recharging
While in DONE mode, if the voltage of VBAT stays below (a programmed VBAT_REG –
140mV or 240mV) over the deglitch time (tDGL_BAT_RESTART), 50ms the battery charger
resumes back to Constant Current (CC) Mode.
8.11.7 Starting a new charge cycle
When a VIN plug in, VBAT attached, or CHG_EN are set to “1”, the device initializes a
new charging process.
8.11.8 Battery attach detection
The device has a unique battery detection scheme with two comparators, 1.9V and 3.4V.
when the detection scheme is executed, a 5mA current sink is activated to determine
battery presence by detection the fall threshold, VBAT_DET_LOW, 1.9V typ. In addition,
a 5mA current source is used to detect battery voltage whether it stays above the
threshold, VBAT_DET_UP, 3.4V. if both conditions are met, absence of battery is declared.
8.12 Hardware and software reset
Please refer to description for ON pin for the hardware reset function by a long time
ON key pressed. The "software reset” is achieved by setting “1” to SW_RST bit in I2C
register. If the user writes a “1” to this bit, it resets all other I2C register bits to their default
setting; this bit is cleared and reset back to “0” as well.
9 I2C-bus interface and register
The PCA9420 implements an I2C-bus slave interface to communicate with the host
system. The interface supports Fast Mode plus Fm+ with up to 1 Mbit/s. A detailed
description of the I2C-bus specification is given in UM10204, Rev. 06, 4 April 2014 ,“ I2C-
bus specification and user manual”.
Features such as clock-stretching and 10-bit slave address are not supported; general
call is supported by default but can be disabled via metal option. Auto increment with
address wrap-around is supported as well.
9.1 I2C slave address
Following a START condition, the bus master must send the target slave address
followed by a read or write operation. The slave address of the PCA9420 is shown below:
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
21 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 6.ꢀI2C Slave Address
Bit 7
1
Bit 6
1
Bit 5
0
Bit 4
Bit 3
0
Bit 2
0
Bit 1
1
Bit 0
0/1
0
Fixed
Fixed
Fixed
MTP option
Fixed
Fixed
Fixed
R/W
Bit 4 should be reserved as MTP option, with its default value set as “0” but can be
trimmed to “1” when needed.
9.2 General call and device ID addresses
The device implements two different addresses for general call and device ID.
9.3 Register type
There are four register types used on the device:
• Read and Write (R/W)
• Read Only (R)
• Write Only (W)
• Write and Clear (W/C)
For Write and Clear (W/C), a write to a register with a bit-mask specifies which interrupts
to clear.
For example, if the status register shows 8’b0000_1001 as an interrupt status (i.e.
interrupt [0] and interrupt [3] are both set), user may write 8’b0000_1000, meaning the
intent is to only clear interrupt [3] (but interrupt [0] should NOT be “cleared”). If the intent
is to clear both interrupts, then the user could write back 8’b0000_1001.
9.4 Register map
Table 7.ꢀRegister map
Address
(Hex)
Register Name
Description
Type
Reset
Value
(Binary)
System Control Registers
00
01
02
03
Device Information, DEV_INFO
Device ID, revision
R
0000 0000
0000 0000
0000 0000
0011 1111
Top Level Interrupt Status, TOP_INT Top level interrupt event status
R/C
W/C
R/W
Sub Level Interrupt_0, SUB_INT0
Sub-level interrupt indication_0
Sub Level Interrupt_0 Mask, SUB_
INT0_MASK
Sub-level interrupt mask for SUB_
INT0
04
05
Sub Level Interrupt_1, SUB_INT1
Sub-level interrupt indication_1
W/C
R/W
0000 0000
0111 1111
Sub Level Interrupt_1 Mask, SUB_
INT1_MASK
Sub-level interrupt mask for SUB_
INT1
06
07
Sub Level Interrupt_2, SUB_INT2
Sub-level interrupt indication_2
W/C
R/W
0000 0000
1111 1111
Sub Level Interrupt_2 Mask, SUB_
INT2_MASK
Sub-level interrupt mask for SUB_
INT2
08
09
RSVD
Reserved
R/W
R/W
0000 0000
0100 0001
Top Level Control_0, TOP_CNTL0
Top level system control_0
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
22 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 7.ꢀRegister map...continued
Address
(Hex)
Register Name
Description
Type
Reset
Value
(Binary)
0A
Top Level Control_1, TOP_CNTL1
Top Level Control_2, TOP_CNTL2
Top Level Control_3, TOP_CNTL3
Top Level Control_4, TOP_CNTL4
RSVD
Top level system control_1
Top level system control_2
Top level system control_3
Top level system control_4
Reserved
R/W
R/W
R/W
W
1000 1001
1100 1110
0000 0001
0000 0000
0B
0C
0D
0E – 0F
Battery Charger Control
Battery Charger Control_0, CHG_
10
11
12
13
14
15
16
17
18
Battery charger control register_0
Battery charger control register_1
Battery charger control register_2
Battery charger control register_3
Battery charger control register_4
Battery charger control register_5
Battery charger control register_6
Battery charger control register_7
Battery charger status indication_0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0000 0011
0000 1000
0000 0100
0000 1000
0000 0100
0001 1110
1001 0101
0010 0100
0001 0000
CNTL0
Battery Charger Control_1, CHG_
CNTL1
Battery Charger Control_2, CHG_
CNTL2
Battery Charger Control_3, CHG_
CNTL3
Battery Charger Control_4, CHG_
CNTL4
Battery Charger Control_5, CHG_
CNTL5
Battery Charger Control_6, CHG_
CNTL6
Battery Charger Control_7, CHG_
CNTL7
Battery Charger Status_0, CHG_
STATUS_0
Battery Charger Status_1, CHG_
STATUS_1
19
1A
Battery charger status indication_1
Battery charger status indication_2
R
R
R
0000 0000
0111 1000
0000 0000
Battery Charger Status_2, CHG_
STATUS_2
Battery Charger Status_3, CHG_
STATUS_3
1B
Battery charger status indication_3
Reserved
1C – 1F
RSVD
Regulator Control
20
21
Regulator Status, REG_STATUS
Regulators status indication
R
0000 0000
0000 0000
Active Discharge Control, ACT_
DISCHARGE_CNTL_1
Active Discharge control register
R/W
Mode Configuration Mode Setting 0_ Mode configuration settings for
0, MODECFG_0_0 Mode 0_0
22
23
R/W
R/W
R/W
0001 0100
0000 1100
0100 1111
Mode Configuration Mode Setting 0_ Mode configuration settings for
1, MODECFG_0_1 Mode 0_1
Mode Configuration Mode Setting 0_ Mode configuration settings for
24
2, MODECFG_0_2
Mode 0_2
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
23 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 7.ꢀRegister map...continued
Address
(Hex)
Register Name
Description
Type
Reset
Value
(Binary)
Mode Configuration Mode Setting 0_ Mode configuration settings for
3, MODECFG_0_3 Mode 0_3
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0011 1001
0001 1100
0100 1100
0100 1111
0000 1100
0001 1100
0100 1100
0100 1111
0000 1100
0001 1100
0100 1100
0100 1111
0000 1100
Mode Configuration Mode Setting 1_ Mode configuration settings for
0, MODECFG_1_0 Mode 1_0
Mode Configuration Mode Setting 1_ Mode configuration settings for
1, MODECFG_1_1 Mode 1_1
Mode Configuration Mode Setting 1_ Mode configuration settings for
2, MODECFG_1_2 Mode 1_2
Mode Configuration Mode Setting 1_ Mode configuration settings for
3, MODECFG_1_3 Mode 1_3
Mode Configuration Mode Setting 2_ Mode configuration settings for
0, MODECFG_2_0 Mode 2_0
Mode Configuration Mode Setting 2_ Mode configuration settings for
1, MODECFG_2_1 Mode 2_1
Mode Configuration Mode Setting 2_ Mode configuration settings for
2, MODECFG_2_2 Mode 2_2
Mode Configuration Mode Setting 2_ Mode configuration settings for
3, MODECFG_2_3 Mode 2_3
Mode Configuration Mode Setting 3_ Mode configuration settings for
0, MODECFG_3_0 Mode 3_0
Mode Configuration Mode Setting 3_ Mode configuration settings for
1, MODECFG_3_1 Mode 3_1
Mode Configuration Mode Setting 3_ Mode configuration settings for
2, MODECFG_3_2 Mode 3_2
Mode Configuration Mode Setting 3_ Mode configuration settings for
3, MODECFG_3_3
Mode 3_3
9.5 Register description
9.5.1 Device information (DEV_INFO, address 00h)
The device identification code stores a unique identifier for each version and/or revision
of device, so that the connected MCU recognizes it automatically.
This is a READ ONLY register.
Table 8.ꢀDEV_INFO register bit description
Bit
7
Symbol
Default value Type
Function
DEV_ID [4]
DEV_ID [3]
DEV_ID [2]
DEV_ID [1]
0
0
0
0
R
R
R
R
Device ID
6
5
4
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
24 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 8.ꢀDEV_INFO register bit description...continued
Bit
3
Symbol
Default value Type
Function
DEV_ID [0]
DEV_REV [2]
DEV_REV [1]
DEV_REV [0]
0
0
0
0
R
R
R
R
2
Device revision
1
0
9.5.2 Top level interrupt status (TOP_INT, address 01h)
The top-level interrupt register contains flags indicating various top level interrupt events
as indicated below. An event will be latched and only its first occurrence triggers the
interrupt signal INTB (if it is not being masked). Reoccurring events will not change the
flag's status or trigger an additional interrupt. If multiple interrupt events happen, its
corresponding interrupt bits in the related registers will be “triggered”, however, the INTB
signal will be only triggered upon the first interrupt event.
The interrupt event reporting on the device is structured in a two-layer configuration. The
interrupt events are grouped as (1) system level; (2) charger block; (3) buck regulator
block; (4) LDO block. When any interrupt event is triggered, based on which mode it
falls into, the related bit for that mode in TOP_INT flags “1”. Any of the related bits in
TOP_INT will only change back to 0 when all the interrupt events in its affiliated mode
have been cleared.
This is READ Only register.
Table 9.ꢀTOP_INT register bit description
Bit
7
Symbol
RSVD
Default value
Type
R
Function
0
0
0
0
0
Reserved bit
Reserved bit
Reserved bit
Reserved bit
6
RSVD
R
5
RSVD
R
4
RSVD
R
3
SYS_INT
R
System level interrupt event trigger indication 0: no system level
interrupt event triggered 1: system level interrupt event triggered
2
1
0
CHG_INT
SW_INT
LDO_INT
0
0
0
R
R
R
Linear battery charger block interrupt event trigger indication 0: no
linear battery charger block interrupt event triggered
1: linear battery charger block interrupt event triggered
Buck regulator blocks (SW1, SW2) interrupt event trigger indication 0:
no interrupt event on SW1 and/or SW2 blocks triggered
1: interrupt event on SW1 and/or SW2 blocks triggered
LDO block (LDO1, LDO2) interrupt event trigger indication 0: no
interrupt event on LDO1 and/or LDO2 blocks triggered 1: interrupt
event on LDO1 and/or LDO2 blocks triggered
9.5.3 Sub level interrupt_0 (SUB_INT0, address 02h)
The sub-level interrupt register contains flags indicating the second-tier interrupt event.
For this register, it contains system level related interrupt events.
This is WRITE AND CLEAR register.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
25 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 10.ꢀSub_INT0 register bit description
Bit
7
Symbol
Default value Type
Function
RSVD
0
0
0
0
W/C
W/C
W/C
W/C
Reserved bit
6
RSVD
Reserved bit
5
ON_PUSH_INT
ON falling edge longer than 5ms happened
Die temperature pre-warning interrupt
4
TEMP_
PREWARNING
1: die temp ≥ TWARNING; 0: die temp < TWARNING TWARNING
threshold is configured by T_WARNING [1:0]
3
2
THEM_SHDN
0
0
W/C
W/C
Thermal shutdown interrupt
0: thermal shutdown is not triggered
1: die temp ≥ TSHDN (set in THEM_SHDN [2:0], thermal shutdown is
triggered
ASYS_
ASYS Pre-Warning Voltage Interrupt:
PREWARNING
0: ASYS voltage does NOT fall below the threshold set in ASYS_
PREWARNING [1:0]
1: ASYS voltage falls below the threshold set in ASYS_PREWARNING
[1:0]
1
0
WD_TIMER
0
0
W/C
W/C
Watchdog Timer Expiration Interrupt:
0: The watchdog timer expiration has not happened since the last time
this bit was cleared.
1: The watchdog timer expiration has happened since the last time this
bit was cleared.
VIN
Input Voltage Interrupt
0: The VIN_OK bit has not changed since the last time this bit was
cleared.
1: The VIN _OK bit has changed since the last time this bit was
cleared.
9.5.4 Sub level interrupt_0 mask (Sub_INT0_Mask, address 03h)
This is a READ AND WRITE register.
Table 11.ꢀSub_INT0_Mask bit description
Bit
Symbol
Default
value
Type
Function
7
6
5
RSVD
0
0
1
R/W
R/W
R/W
Reserved bit
Reserved bit
RSVD
ON_PUSH_INT_MASK
ON Key falling interrupt mask bit
0: Not Masked
1: Masked
4
3
TEMP_PREWARNING_MASK
THEM_SHDN_MASK
1
1
R/W
R/W
Die temp pre-warning interrupt mask bit
0: Not Masked
1: Masked
Thermal shutdown interrupt mask bit
0: Not Masked
1: Masked
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
26 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 11.ꢀSub_INT0_Mask bit description...continued
Bit
Symbol
Default
value
Type
Function
2
ASYS_PREWARNING_MASK
1
1
1
R/W
ASYS Pre-Warning Voltage Interrupt Mask bit
0: Not Masked
1: Masked
1
0
WD_TIMER_MASK
VIN_MASK
R/W
R/W
Watchdog Timer Expiration Interrupt Mask bit
0: Not Masked
1: Masked
Input Voltage Interrupt Mask bit
0: Not Masked
1: Masked
9.5.5 Sub level interrupt_1 (Sub_INT1, address 04h)
The sub-level interrupt register contains flags indicating the second-tier interrupt event.
For this register, it contains battery charger related interrupt events.
This is WRITE AND CLEAR register.
Table 12.ꢀSub_INT1 register bit description
Bit
7
Symbol
RSVD
Default value Type
Function
0
0
0
W/C
W/C
W/C
Reserved bit
6
RSVD
Reserved bit
5
VIN_ILIM
Input Current Limit Interrupt:
0: no Input current limit has been triggered since the last
time this bit is cleared;
1: input current limit event is triggered since last time this bit
is cleared.
4
3
2
1
ICHG_FAST_TIMER
ICHG_PREQ_TIMER
BATTERY_DETECTION
VBAT
0
0
0
0
W/C
W/C
W/C
W/C
Fast Charging Timer Expiration Interrupt:
0: The fast charging timer expiration has not happened
since the last time this bit was cleared.
1: The fast charging timer expiration has happened since
the last time this bit was cleared.
Pre-qualification Charging Timer Expiration Interrupt:
0: The pre-qual charging timer expiration has not happened
since the last time this bit was cleared.
1: The pre-qual charging timer expiration has happened
since the last time this bit was cleared.
Battery presence Interrupt
0: The VBAT_DET_OK bit has not changed since the last
time this bit was cleared.
1: The VBAT_DET_OK bit has changed since the last time
this bit was cleared.
Battery Interrupt
0: The VBAT_OK bit has not changed since the last time
this bit was cleared.
1: The VBAT_OK bit has changed since the last time this bit
was cleared.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
27 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 12.ꢀSub_INT1 register bit description...continued
Bit
Symbol
Default value Type
W/C
Function
0
CHG_OK
0
Charger Status Interrupt
0: The CHG_OK bit has not changed since the last time this
bit was cleared.
1: The CHG_OK bit has changed since the last time this bit
was cleared
9.5.6 Sub level interrupt_1 mask (Sub_INT1_Mask, address 05h)
This is a READ AND WRITE register.
Table 13.ꢀSub_INT1_Mask register bit description
Bit Symbol
Default
value
Type Function
7
6
5
RSVD
0
1
1
R/W
R/W
R/W
Reserved bit
Reserved bit
RSVD
VIN_ILIM_MASK
Input Current Limit Interrupt Mask bit
0: Not Masked
1: Masked
4
3
2
1
0
ICHG_FAST_TIMER_MASK
ICHG_PREQ_TIMER_MASK
BATTERY_DETECTION_MASK
VBAT_MASK
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
Fast Charging Timer Expiration Interrupt Mask bit
0: Not Masked
1: Masked
Pre-qual Charging Timer Expiration Interrupt Mask bit
0: Not Masked
1: Masked
Battery presence Interrupt Mask bit
0: Not Masked
1: Masked
Battery Interrupt Mask bit
0: Not Masked
1: Masked
CHG_OK_MASK
Charger Interrupt Mask bit
0: Not Masked
1: Masked
9.5.7 Sub level interrupt_2 (Sub_INT2, address 06h)
The sub-level interrupt register contains flags indicating the second-tier interrupt event.
For this register, it contains LDO1/LDO2, SW1/SW2 related interrupt events.
This is WRITE AND CLEAR register.
Table 14.ꢀSub_INT2 register bit description
Bit
7
Symbol
RSVD
RSVD
RSVD
Default value Type
Function
0
0
0
W/C
W/C
W/C
Reserved bit
Reserved bit
Reserved bit
6
5
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
28 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 14.ꢀSub_INT2 register bit description...continued
Bit
4
Symbol
RSVD
Default value Type
Function
0
0
W/C
W/C
Reserved bit
3
VOUTSW1
SW1 Output Voltage Interrupt
0: The VOUTSW1_OK bit has not changed since the last time this bit
was cleared.
1: The VOUTSW1_OK bit has changed since the last time this bit was
cleared.
2
1
0
VOUTSW2
VOUTLDO1
VOUTLDO2
0
0
0
W/C
W/C
W/C
SW2 Output Voltage Interrupt
0: The VOUTSW2_OK bit has not changed since the last time this bit
was cleared.
1: The VOUTSW2_OK bit has changed since the last time this bit was
cleared.
LDO1 Output Voltage Interrupt
0: The VOUTLDO1_OK bit has not changed since the last time this bit
was cleared.
1: The VOUTLDO1_OK bit has changed since the last time this bit was
cleared.
LDO2 Output Voltage Interrupt
0: The VOUTLDO2_OK bit has not changed since the last time this bit
was cleared.
1: The VOUTLDO2_OK bit has changed since the last time this bit was
cleared.
9.5.8 Sub level interrupt_2 mask (Sub_INT2_Mask, address 07h)
This is a READ AND WRITE register.
Table 15.ꢀSub_INT2_Mask register bit description
Bit
7
Symbol
RSVD
Default value Type
Function
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
Reserved bit
Reserved bit
Reserved bit
Reserved bit
6
RSVD
5
RSVD
4
RSVD
3
VOUTSW1 _MASK
VOUTSW1 Voltage Interrupt Mask bit
0: Not Masked
1: Masked
2
1
0
VOUTSW2 _MASK
VOUTLDO1 _MASK
VOUTLDO2_MASK
1
1
1
R/W
R/W
R/W
VOUTSW2 Voltage Interrupt Mask bit
0: Not Masked
1: Masked
VOUTLDO1 Voltage Interrupt Mask bit
0: Not Masked
1: Masked
VOUTLDO2 Voltage Interrupt Mask bit
0: Not Masked
1: Masked
08h register: Reserved
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
29 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
9.5.9 Top level control_0 (TOP_CTL0, address 09h)
This register contains various configuration bits for top level related functions, part 0. This
is a READ AND WRITE register.
Table 16.ꢀTOP_CNTL0 register bit description
Bit
7
Symbol
Default value Type
010 R/W
Function
VIN_ILIM_SEL
[2:0]
VIN input current limit selection: (min/typ/max)
000: 74mA/85mA/98mA, (another default setting by MTP)
001: 222mA/255mA/293mA
6
5
010: 370mA/425mA/489mA (default setting)
011: 517mA/595mA/684mA
100: 665mA/765mA/880mA
101: 813mA/935mA/1075mA
110: 961mA/1105mA/1271mA
111: Input current limit disabled
[Note] 1-bit MTP, VIN_ILIM_SEL [1], should be reserved to
change the default value for this function
4
OPERATION_SEL_
FROM_SHIPMODE
0
R/W
Ship mode wakeup configuration setting
0: upon VIN plug in, the chip will enable the battery charging
process, AND start the power-up sequence for LDO1/LDO2/
SW1/SW2 per the setting
1: upon VIN plug in, the chip will enable the charging process,
LDO1/LDO2/SW1/SW2 remain in shutdown mode and the chip
will only enable the power-up sequence upon ON pin falling
edge
[Note] 1-bit MTP should be reserved to change the default value
for this function
3
2
PWR_DN_EN[1]
0
0
R/W
R/W
Power-down Sequence Enable
0: Do not start power-down sequence
1: Start power-down sequence
nEN_CHG_IN_
WATCHDOG
Configure operations in a programmed watchdog timer expired
0: When the programmed watchdog timer expires, the following
operations take place.
• SYSRSTn signal asserts (high to low)
• Charging is continued
• LDO1/LDO2/SW1/SW2 enters the mode 0 setting
1: When the programmed watchdog timer expires, the following
operations take place.
• SYSRSTn signal asserts (high to low)
• Charging is disabled
• LDO1/LDO2/SW1/SW2 enters the mode 0 setting
1
0
RSVD
0
1
R/W
R/W
Reserved bit
PGood_EN
LDO1, LDO2, SW1, SW2 Output Voltage Status Indication
0: Output voltage power-good comparators are disabled.
This will also set “VOUTSW1 _OK”, “VOUTSW2 _OK”,
“VOUTLDO1_OK” and “VOUTLDO2 _OK” bits to 0
1: Output voltage power-good comparators are enabled
[1] A valid VIN does not generate the initial power-up sequence if all power rails have been turned off by setting PWR_DN_EN to 1. The use of PWR_DN_EN
bit is prohibited to be used in any application that requires power-up sequence by both VIN and ON key.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
30 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
The use of SHIP_EN_x (x can be 0, 1, 2 &3) is recommended for the application.
9.5.10 Top level control_1 (TOP_CTL1, address 0Ah)
This register contains various configuration bits for top level related functions, part 1. This
is a READ AND WRITE register.
Table 17.ꢀTOP_CNTL1 register bit description
Bit
Symbol
Default
value
Type
Function
7
6
ASYS_PREWARNING
[1:0]
10
00
R/W
ASYS Program a pre-warning voltage threshold on ASYS
00: 3.3V
01: 3.4V
10: 3.5V
11: 3.6V
5
4
ASYS_INPUT_SEL
[1:0]
R/W
ASYS input source selection
00: ASYS is power by either VBAT or VIN (VIN has higher
priority over VBAT if both are presented)
01: ASYS is powered by VBAT only
10: ASYS is powered by VIN only
11: ASYS is disconnected to either VBAT or VIN (for internal
testing purpose only)
3
2
RSVD
1
0
R/W
R/W
Reserved bit
VIN_OVP_SEL
VIN over-voltage protection threshold (rising) selection
0: 5.50V
1: 6.0V
Note: The current default value for VIN_OVP_SEL is set
at 5.5V, but it should be MTP programmable
1
0
VIN_UVLO_SEL
[1:0]
01
R/W
Program an under-voltage lockout threshold (falling) on VIN
00: 2.9V
01: 3.1V
10: 3.3V
11: 3.5V
9.5.11 Top level control_2 (TOP_CTL2, address 0Bh)
This register contains various configuration bits for top level related functions, part 2. This
is a READ AND WRITE register.
Table 18.ꢀTOP_CNTL2 register bit description
Bit
7
Symbol
Default value Type
Function
ASYS_UVLO_SEL
[1:0]
11
R/W
Program a UVLO threshold on ASYS
00: 2.4V
01: 2.5V
10: 2.6V
11: 2.7V
6
5
TERM_DIS
0
R/W
Enable/Disable the charge termination control. In this mode,
the fast charge timer is reset.
0: Enable charge termination mode
1: Disable charge termination mode
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
31 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 18.ꢀTOP_CNTL2 register bit description...continued
Bit
4
Symbol
Default value Type
011 R/W
Function
THEM_SHDN
[2:0]
Program a thermal shutdown threshold, TSHDN, in
rising(hysteresis with 20°C)
3
000: 95°C
2
001: 100°C
010: 105°C
011: 110°C
100: 115°C
101: 120°C
110: 125°C
111: reserved
1
0
DIE_TEMP_WARNING 10
[1:0]
R/W
Program a Die temperature warning threshold
00: 75°C
01: 80°C
10: 85°C
11: 90°C
9.5.12 Top level control_3 (TOP_CTL3, address 0Ch)
This register contains various configuration bits for top level related functions, part 3. This
is a READ AND WRITE register.
Table 19.ꢀTOP_CNTL3 register bit description
Bit
7
Symbol
RSVD
Default value Type
Function
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Reserved bit
Reserved bit
Reserved bit
6
RSVD
5
RSVD
4
MODE1_I2C
MODE0_I2C
Depending on EN_MODE_SEL_BY_PIN_x (x=”0”, or “1”, or “2”,
or “3”) bit setting, the chip mode control is set by either the I2C bit
MODE1_I2C/ MODE0_I2C value, or the signal applied on external
MODESEL1/ MODESEL1 pins. Refer to EN_MODE_SEL_BY_PIN
description for more details.
3
With EN_MODE_SEL_BY_PIN=0, the mode selection is determined
by the following:
[MODE1_I2C: MODE0_I2C] = 00, mode 0 setting
[MODE1_I2C: MODE0_I2C] = 01, mode 1 setting
[MODE1_I2C: MODE0_I2C] = 10, mode 2 setting
[MODE1_I2C: MODE0_I2C] = 11, mode 3 setting
2
SW_RST
0
W/C
R/W
Chip software reset bit. If user write “1” to this bit, it will reset all other
I2C register bit to its default setting and cycle the regulator outputs,
and meanwhile, this bit will be clear and reset back to “0” as well.
1
0
ON_GLT_LONG 01
[1:0]
Program a long glitch timer on ON key
00: 4s
01: 8s
10: 12s
11: 16s
Note: 2-bit MTP should be reserved to change the default setting
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
32 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
9.5.13 Top level control_4 (TOP_CTL4, address 0Dh)
This register contains various configuration bits for top level related functions, part 4. This
is a WRITE ONLY register.
Table 20.ꢀTOP_CNTL4 register bit description
Bit
7
Symbol
Default value Type
Function
RSVD
00000
W
Reserved bit
6
5
4
3
2
WD_TIMER_CLR 000
[2:0]
W
Watchdog Timer Reset.
001: When written 001 to WD_TIMER_CLR [2:0], the watchdog timer
is reset.
1
0
All other values: when written to WD_TIMER_CLR [2:0], watchdog
timer remains unaffected.
9.5.14 Battery charger control_0 (CHG_CTL0, address 10h)
This register stores the linear battery charge related control registers, part 0. This is a
READ AND WRITE register.
Table 21.ꢀCHG_CNTL0 register bit description
Bit
7
Symbol
Default value Type
Function
CHG_LOCK
[4:0]
00000
R/W
Critical charger related setting lock.
CHG_LOCK [4:0] = 10101, these registers which are labeled as
“locked by CHG_LOCK” can be accessed to perform I2C “write”
command.
6
5
CHGN_LOCK [4:0] ≠ 10101, these registers which are labeled as
“locked by CHG_LOCK” can NOT be accessed to perform I2C “write”
command. In such case when “write” command is performed on these
locked registers, it will keep the present register value.
4
3
2
1
0
NTC_EN
0
R/W
R/W
R/W
Enable TS pin external thermistor (NTC) control in charger
0: Disable Thermistor (NTC) control in charger
1: Enable Thermistor (NTC) control in charger
CHG_TIMER_EN 1
Enable the fast charge timer and pre-qual timer
0: Disable both fast charge timer and pre-qual timer
1: Enable both fast charge timer and pre-qual timer
CHG_EN
1
Enable the linear battery charger
0: Disable charger
1: Enable charger
Note: The default value for this bit should be MTP programmable
9.5.15 Battery charger control_1 (CHG_CTL1, address 11h)
This register stores the linear battery charge related control registers, part 1.
This is a READ AND WRITE register, and this register is locked by CHG_LOCK.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
33 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 22.ꢀCHG_CNTL1 register bit description
Bit
7
Symbol
RSVD
RSVD
Default value Type
Function
0
R/W
R/W
R/W
Reserved bit
6
0
Reserved bit
5
ICHG_CC
[5:0]
001000
Program a fast charge current
Note: The current default value for ICHG_CC [5:0] is set at 40mA,
but it should be MTP programmable.
4
3
2
1
0
Table 23.ꢀLinear battery charger constant current (CC) setting
00h: 0mA
10h: 80mA
11h: 85mA
20h: 160mA
21h: 165mA
22h: 170mA
23h: 175mA
24h: 180mA
25h: 185mA
26h: 190mA
27h: 195mA
28h: 200mA
29h: 205mA
2Ah: 210mA
2Bh: 215mA
2Ch: 220mA
2Dh: 225mA
2Eh: 230mA
2Fh: 235mA
30h: 240mA
31h: 245mA
32h: 250mA
33h: 255mA
34h: 260mA
35h: 265mA
36h: 270mA
37h: 275mA
38h: 280mA
39h: 285mA
3Ah: 290mA
3Bh: 295mA
3Ch: 300mA
3Dh: 305mA
3Eh: 310mA
3Fh: 315mA
01h: 5mA
02h: 10mA
03h: 15mA
04h: 20mA
05h: 25mA
06h: 30mA
07h: 35mA
08h: 40mA (default)
09h: 45mA
0Ah: 50mA
0Bh: 55mA
0Ch: 60mA
0Dh: 65mA
0Eh: 70mA
0Fh: 75mA
12h: 90mA
13h: 95mA
14h: 100mA
15h: 105mA
16h: 110mA
17h: 115mA
18h: 120mA
19h: 125mA
1Ah: 130mA
1Bh: 135mA
1Ch: 140mA
1Dh: 145mA
1Eh: 150mA
1Fh: 155mA
9.5.16 Battery charger control_2 (CHG_CTL2, address 12h)
This register stores the present status of chip, part 2, linear battery charger related
status. This is a READ AND WRITE register, and this register is locked by
CHG_LOCK.
Table 24.ꢀCHG_CNTL2 register bit description
Bit
7
Symbol
RSVD
RSVD
Default value Type
Function
0
0
R/W
R/W
Reserved bit
Reserved bit
6
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
34 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 24.ꢀCHG_CNTL2 register bit description...continued
Bit
5
Symbol
Default value Type
Function
ICHG_TOPOFF 000100b
[5:0]
R/W
Program a top-off current
Note: The current default value for ICHG_TOPOFF [5:0] is set at
4mA, but it should be MTP programmable.
4
3
2
1
0
Table 25.ꢀLinear battery charger top-off charge current setting
00h: 0mA
10h: 16mA
11h: 17mA
12h: 18mA
13h: 19mA
14h: 20mA
15h: 21mA
16h: 22mA
17h: 23mA
18h: 24mA
19h: 25mA
1Ah: 26mA
1Bh: 27mA
1Ch: 28mA
1Dh: 29mA
1Eh: 30mA
1Fh: 31mA
20h: 32mA
21h: 33mA
22h: 34mA
23h: 35mA
24h: 36mA
25h: 37mA
26h: 38mA
27h: 39mA
28h: 40mA
29h: 41mA
2Ah: 42mA
2Bh: 43mA
2Ch: 44mA
2Dh: 45mA
2Eh: 46mA
2Fh: 47mA
30h: 48mA
31h: 49mA
32h: 50mA
33h: 51mA
34h: 52mA
35h: 53mA
36h: 54mA
37h: 55mA
38h: 56mA
39h: 57mA
3Ah: 58mA
3Bh: 59mA
3Ch: 60mA
3Dh: 61mA
3Eh: 62mA
3Fh: 63mA
01h: 1mA
02h: 2mA
03h: 3mA
04h: 4mA (default)
05h: 5mA
06h: 6mA
07h: 7mA
08h: 8mA
09h: 9mA
0Ah: 10mA
0Bh: 11mA
0Ch: 12mA
0Dh: 13mA
0Eh: 14mA
0Fh: 15mA
9.5.17 Battery charger control_3 (CHG_CTL3, address 13h)
This register stores the present status of chip, part 3, linear battery charger related
status. This is a READ AND WRITE register, and this register is locked by
CHG_LOCK.
Table 26.ꢀCHG_CNTL3 register bit description
Bit
7
Symbol
RSVD
RSVD
Default value Type
Function
0
0
R/W
R/W
Reserved bit
Reserved bit
6
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
35 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 26.ꢀCHG_CNTL3 register bit description...continued
Bit
5
Symbol
Default value Type
R/W
Function
ICHG_LOW [5:0] 001000
Program a pre-charge (Low battery charge current)
Note: Current value set in ICHG_LOW [5:0] should NOT be higher
than the value set in ICHG_LOW [5:0].
4
3
Note: The current default value for ICHG_LOW [5:0] is set at 8mA,
ICHG_LOW [4:3] should be MTP programmable.
2
1
0
Table 27.ꢀLow battery charge current setting
00h: 0mA
10h: 16mA
20h: 32mA
21h: 33mA
22h: 34mA
23h: 35mA
24h: 36mA
25h: 37mA
26h: 38mA
27h: 39mA
28h: 40mA
29h: 41mA
2Ah: 42mA
2Bh: 43mA
2Ch: 44mA
2Dh: 45mA
2Eh: 46mA
2Fh: 47mA
30h: 48mA
31h: 49mA
32h: 50mA
33h: 51mA
34h: 52mA
35h: 53mA
36h: 54mA
37h: 55mA
38h: 56mA
39h: 57mA
3Ah: 58mA
3Bh: 59mA
3Ch: 60mA
3Dh: 61mA
3Eh: 62mA
3Fh: 63mA
01h: 1mA
11h: 17mA
12h: 18mA
13h: 19mA
14h: 20mA
15h: 21mA
16h: 22mA
17h: 23mA
18h: 24mA
19h: 25mA
1Ah: 26mA
1Bh: 27mA
1Ch: 28mA
1Dh: 29mA
1Eh: 30mA
1Fh: 31mA
02h: 2mA
03h: 3mA
04h: 4mA
05h: 5mA
06h: 6mA
07h: 7mA
08h: 8mA (default)
09h: 9mA
0Ah: 10mA
0Bh: 11mA
0Ch: 12mA
0Dh: 13mA
0Eh: 14mA
0Fh: 15mA
9.5.18 Battery charger control_4 (CHG_CTL4, address 14h)
This register stores the present status of chip, part 4, linear battery charger related
status. This is a READ AND WRITE register, and this register is locked by
CHG_LOCK.
Table 28.ꢀCHG_CNTL4 register bit description
Bit
7
Symbol
RSVD
RSVD
Default value Type
Function
0
0
R/W
R/W
Reserved bit
Reserved bit
6
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
36 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 28.ꢀCHG_CNTL4 register bit description...continued
Bit
5
Symbol
Default value Type
000100 R/W
Function
ICHG_DEAD
[5:0]
Program a Dead battery charge current
Note: Current value set in ICHG_DEAD [5:0] should NOT be greater
than the value set in ICHG_LOW [5:0].
4
3
Note: The current default value for ICHG_DEAD [5:0] is set
at 4mA, ICHG_DEAD [2] and ICHG_DEAD [4] should be MTP
programmable.
2
1
0
Table 29.ꢀDead battery charge current setting
00h: 0mA
10h: 16mA
20h: 32mA
21h: 33mA
22h: 34mA
23h: 35mA
24h: 36mA
25h: 37mA
26h: 38mA
27h: 39mA
28h: 40mA
29h: 41mA
2Ah: 42mA
2Bh: 43mA
2Ch: 44mA
2Dh: 45mA
2Eh: 46mA
2Fh: 47mA
30h: 48mA
31h: 49mA
32h: 50mA
33h: 51mA
34h: 52mA
35h: 53mA
36h: 54mA
37h: 55mA
38h: 56mA
39h: 57mA
3Ah: 58mA
3Bh: 59mA
3Ch: 60mA
3Dh: 61mA
3Eh: 62mA
3Fh: 63mA
01h: 1mA
11h: 17mA
12h: 18mA
13h: 19mA
14h: 20mA
15h: 21mA
16h: 22mA
17h: 23mA
18h: 24mA
19h: 25mA
1Ah: 26mA
1Bh: 27mA
1Ch: 28mA
1Dh: 29mA
1Eh: 30mA
1Fh: 31mA
02h: 2mA
03h: 3mA
04h: 4mA (default)
05h: 5mA
06h: 6mA
07h: 7mA
08h: 8mA
09h: 9mA
0Ah: 10mA
0Bh: 11mA
0Ch: 12mA
0Dh: 13mA
0Eh: 14mA
0Fh: 15mA
9.5.19 Battery charger control_5 (CHG_CTL5, address 15h)
This register stores the present status of chip, part 5, linear battery charger related
status. This is a READ AND WRITE register, and this register is locked by
CHG_LOCK.
Table 30.ꢀCHG_CNTL5 register bit description
Bit
7
Symbol
Default value Type
Function
RSVD
0
R/W
R/W
Reserved bit
6
VBAT_RESTART 0
Program a threshold for recharge
0: 140mV below a programmed VBAT_REG
1: 240mV below a programmed VBAT_REG
Note: The default value should be 1-bit MTP programmable.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
37 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 30.ꢀCHG_CNTL5 register bit description...continued
Bit
5
Symbol
Default value Type
011110 R/W
Function
VBAT_REG
[5:0]
Program a battery regulation voltage, VBAT_REG
Note: The current default value for VBAT_REG [5:0] is set at
4.20V, but it should be MTP programmable.
4
3
2
1
0
Table 31.ꢀVBATREG, linear battery charger regulated battery voltage setting
00h: 3.60V
01h: 3.62V
02h: 3.64V
03h: 3.66V
04h: 3.68V
05h: 3.70V
06h: 3.72V
07h: 3.74V
08h: 3.76V
09h: 3.78V
0Ah: 3.80V
0Bh: 3.82V
0Ch: 3.84V
0Dh: 3.86V
0Eh: 3.88V
0Fh: 3.90V
10h: 3.92V
11h: 3.94V
12h: 3.96V
13h: 3.98V
14h: 4.00V
15h: 4.02V
16h: 4.04V
17h: 4.06V
18h: 4.08V
19h: 4.10V
1Ah: 4.12V
1Bh: 4.14V
1Ch: 4.16V
1Dh: 4.18V
1Eh: 4.20V
1Fh: 4.22V
20h: 4.24V
21h: 4.26V
22h: 4.28V
23h: 4.30V
24h: 4.32V
25h: 4.34V
26h: 4.36V
27h: 4.38V
28h: 4.40V
29h: 4.42V
2Ah: 4.44V
2Bh: 4.46V
2Ch: 4.48V
2Dh: 4.50V
2Eh: 4.52V
2Fh: 4.54V
30h: 4.56V
31h: 4.58V
32h: 4.60V
33~3Fh: 4.60V
9.5.20 Battery charger control_6 (CHG_CTL6, address 16h)
This register stores the present status of chip, part 7, linear battery charger related
status. This is a READ AND WRITE register, and this register is locked by
CHG_LOCK.
Table 32.ꢀCHG_CNTL6 register bit description
Bit
Symbol
Default value Type
Function
7
NTC_RES_SEL
1
R/W
External thermistor typical resistance selection: 0: 100kΩ
1: 10kΩ
6
TIMER_2X
0
R/W
Charging Safety Timer Extension:
0: Both pre-qual and fast charge timer duration keeps as the values set
in ICHG_PREQ_TIMER [1:0] and ICHG_FAST_TIMER [1:0]
1: Both pre-qual and fast charge timer duration is extended to 2x of the
values set in ICHG_PREQ_TIMER [1:0] and ICHG_FAST_TIMER [1:0]
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
38 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 32.ꢀCHG_CNTL6 register bit description...continued
Bit
5
Symbol
Default value Type
Function
ICHG_FAST_
TIMER [1:0]
01
01
R/W
R/W
R/W
Linear battery charger fast charge timer setting: 00: 3hr; 01: 5hr; 10:
7hr; 11: 9hr
4
3
ICHG_PREQ_
TIMER [1:0]
Linear battery charger pre-qualification charge timer setting: 00: 15
min; 01: 30 min; 10: 45 min; 11: 60 min
2
1
T_TOPOFF [1:0] 01
TOPOFF Timer setting:
00: 0min; 01: 6.4min; 10: 12.8min; 11: 19.2min
0
9.5.21 Battery charger control_7 (CHG_CTL7, address 17h)
This register stores the present status of chip, part 7, linear battery charger related
status. This is a READ AND WRITE register.
Table 33.ꢀCHG_CNTL7 register bit description
Bit
Symbol
Default value Type
Function
7:5
NTC_BETA_SEL 001
[2:0]
R/W
Set the thermistor beta value selection (see below)
4
3
2
1
0
RSVD
RSVD
0
R/W
R/W
R/W
Reserved bit
0
Reserved bit
THM_REG
[2:0]
100
Thermal regulation threshold setting (see below)
Table 34.ꢀSet the thermistor beta value selection
000: 3434k
001: 3610k
010: 3934k
011: 3950k
100: 4100k
101: 4311k
110: 4543k
111: 4750k
Table 35.ꢀThermal regulation threshold setting
000: 80°C
001: 85°C
010: 90°C
011: 95°C
100: 100°C
101: 105°C
110: 110°C
111: 115°C
9.5.22 Battery charger status_0 (CHG_STATUS_0, address 18h)
This register stores the present status of the linear battery charger, part 0. This is a
READ ONLY register.
Table 36.ꢀCHG_STATUS_0 register bit description
Bit
Symbol
Default value Type
Function
7
VBAT_DET_OK
0
R
VBAT Detection Status:
0: No valid battery attachment detected. 1: Battery attachment
detected.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
39 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 36.ꢀCHG_STATUS_0 register bit description...continued
Bit
Symbol
Default value Type
Function
6
VBAT_OK
0
R
(Only valid with VBAT_DET_OK = 1)
VBAT status, refer to BAT_DETAIL_STATUS [2:0] for more details
0: the battery is invalid/missing, or charger reset is active, i.e.
BAT_DETAIL_STATUS [2:0] = 0b000, 0b111
1: the battery is OK. i.e. BAT_DETAIL_STATUS [2:0] = 0b001, 0b010,
0b011, 0b100, 0b101
5
4
VIN_OK
0
1
R
R
VIN status, refer to VIN_STATUS [1:0] for more details
0: VIN voltage is invalid. i.e. VIN_STATUS [1:0] ≠ 0b11
1: VIN voltage is valid. i.e. VIN_STATUS [1:0] = 0b11
CHG_OK
Charger status
0: The charger has suspended due to the following conditions: TS_
DETAIL_STATUS [2:0] = 001’b or 100’b; or SFTY_TIMER_STATUS
[1:0] ≠ 00’b
1: The charger is OK
3
2
1
0
RSVD
RSVD
RSVD
RSVD
0
0
0
0
R
R
R
R
Reserved bit
Reserved bit
Reserved bit
Reserved bit
9.5.23 Battery charger status_1 (CHG_STATUS_1, address 19h)
This register stores the present status of the linear battery charger, part 1. This is a
READ ONLY register.
Table 37.ꢀCHG_STATUS_1 register bit description
Bit
7
Symbol
Default value Type
Function
VIN_STATUS
00
R
VIN Status
00: VIN is invalid. VIN<VIN_UVLO
01: VIN is invalid. VIN< VBAT+VIN_HEADROOM and VIN>VIN_UVLO
10: VIN is invalid. VIN>VIN_OVP
6
11: VIN is valid. VIN>VIN_UVLO, VIN>VBAT+VIN2BAT_HEADROOM,
VIN<VIN_OVP
1
4
RSVD
0
0
R
R
Reserved bit
TREG_STATUS
Temperature Regulation Loop Status
0: Die junction temperature is less than the threshold set by THM_
REG and the full charge current limit is available.
1: Die junction temperature is greater than the threshold set by THEM_
REG, and the charge current limit may be folding back to reduce
power dissipation.
3
2
1
0
RSVD
RSVD
RSVD
RSVD
0
0
0
0
R
R
R
R
Reserved bit
Reserved bit
Reserved bit
Reserved bit
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
40 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
9.5.24 Battery charger status_2 (CHG_STATUS_2, address 1Ah)
This register stores the present status of the linear battery charger, part 2.
This is a READ ONLY register. The status of this register is only valid when VIN_OK = 1
Table 38.ꢀCHG_STATUS_2 register bit description
Bit
7
Symbol
Default value Type
Function
RSVD
0
R
R
Reserved bit
6
BAT_DETAIL_
STATUS
[2:0]
111
Battery conditions in details
000: Battery missing, not attached
5
001: Battery detection in-progress 010: VBAT < VBAT_DEAD
011: VBAT_DEAD < VBAT < VBAT_LOW
4
100: VBAT_LOW < VBAT < (VBAT_REG – VBAT_RESTART
)
101: VBAT > (VBAT_REG – VBAT_RESTART
)
110: reserved
111: battery charger is in reset
3
2
1
0
RSVD
0
R
R
Reserved bit
BAT_CHG_
STATUS
[2:0]
000
Charge conditions in details:
000: Charger in Idle State
001: Charger in Dead-Battery State
010: Charger in Low-Battery State
011-100: Charger in Fast Charging state in either CC or CV
101: Charger in Top-off State
110: Charger in Done State
111: Reserved
9.5.25 Battery charger status_3 (CHG_STATUS_3, address 1Bh)
This register stores the present status of the linear battery charger, part 3. This is a
READ ONLY register.
Table 39.ꢀCHG_STATUS_3 register bit description
Bit
Symbol
Default value Type
Function
7
TS_STATUS
0
R
0: TS_DETAIL_STATUS [2:0] = 000. Battery temp is normal, no impact
on normal charging.
1: TS_DETAIL_STATUS [2:0] ≠ 000.
6
5
4
TS_DETAIL_
STATUS
[2:0]
000
R
000: Battery Temperature Nominal, T2 ≤ T ≤ T3
001: Battery Temperature is Cold, T < T1
010: Battery Temperature is Cool, T1 ≤ T < T2
011: Battery Temperature is Warm, T3 < T ≤ T4
100: Battery Temperature is Hot, T > T4
3
2
RSVD
0
0
R
R
Reserved bit
CHIP_TEMP_
STATUS
Chip Temp Status:
0: Thermal regulation not activated
1: Thermal regulation activated
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
41 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 39.ꢀCHG_STATUS_3 register bit description...continued
Bit
1
Symbol
Default value Type
Function
SFTY_TIMER_S 00
TATUS
R
00: Safety Timers having No Effect on Battery Charging
01: Pre-qual Timer expires, battery charging suspended
10: Fast Timer expires, battery Charging suspended
11: Battery short test fails, battery charging suspended
0
[1:0]
1Ch ~ 1Fh registers: Reserved
9.5.26 Regulator status (REG_STATUS, address 20h)
This register stores the present status of the SW1, SW2, LDO1, LDO2. This is a READ
ONLY register.
Table 40.ꢀREG_STATUS register bit description
Bit
Symbol
Default value Type
Function
7
VOUTSW1 _OK
0
R
R
R
R
SW1 VOUT “Power-good” Status
0: VOUT_SW1 is not OK, i.e., VOUTSW1 / VOUTSW1(nominal) ≤
90% or VOUTSW1 / VOUTSW1(nominal) ≥ 110%
1: VOUT_SW1 is OK, i.e., 110% > VOUTSW1 / VOUTSW1(nominal) >
90%
6
5
4
VOUTSW2 _OK
0
SW2 VOUT “Power-good” Status
0: VOUT_SW2 is not OK, i.e., VOUTSW2 / VOUTSW2(nominal) ≤
90% or VOUTSW2 / VOUTSW2(nominal) ≥ 110%
1: VOUT_SW2 is OK, i.e., 110% > VOUTSW2 / VOUTSW2(nominal) >
90%
VOUTLDO1 _OK 0
LDO1VOUT “Power-good” Status
0: VOUTLDO1 is not OK, i.e., VOUTLDO1 / VOUTLDO1 (nominal) ≤
90% or VOUT LDO1 / VOUT LDO1 (nominal) ≥ 110%
1: VOUTLDO1 is OK, i.e., 110% > VOUTLDO1 / VOUTLDO1 (nominal)
> 90%
VOUTLDO2_OK
0
LDO2VOUT “Power-good” Status
0: VOUTLDO2 is not OK, i.e., VOUTLDO2 / VOUTLDO2 (nominal) ≤
90% or VOUTLDO2 / VOUTLDO2 (nominal) ≥ 110%
1: VOUTLDO2 is OK, i.e., 110% > VOUTLDO2 / VOUTLDO2 (nominal)
> 90%
3
2
1
0
RSVD
RSVD
RSVD
RSVD
0
0
0
0
R
R
R
R
Reserved bit
Reserved bit
Reserved bit
Reserved bit
9.5.27 Active Discharge Regulator control (ACT_DISCHARGE_CNTL, address 21h)
This register stores the control functions of the SW1, SW2, LDO1, LDO2. This is a READ
AND WRITE register.
Table 41.ꢀACT_DISCHARGE_CNTL register bit description
Bit
Symbol
Default value Type Function
7
RSVD
0
R/W Reserved bit
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
42 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 41.ꢀACT_DISCHARGE_CNTL register bit description...continued
Bit
6
Symbol
RSVD
RSVD
RSVD
Default value Type Function
0
0
0
R/W Reserved bit
R/W Reserved bit
R/W Reserved bit
5
4
3
nEN_SW1_BLEED 0
R/W SW1 Output Active Discharge Turn-on Control in the regulator disabled
0: Enable output discharge bleeding resistor disabled
1: Disable Output discharge bleeding resistor
2
1
nEN_SW2_BLEED 0
R/W SW2 Output Active Discharge Turn-on Control in the regulator disabled
0: Enable output discharge bleeding resistor disabled
1: Disable Output discharge bleeding resistor
nEN_LDO1_
BLEED
0
0
R/W LDO1 Output Active Discharge Turn-on Control in the regulator
disabled
0: Enable output discharge bleeding resistor disabled
1: Disable Output discharge bleeding resistor
0
nEN_LDO2_
BLEED
R/W LDO2 Output Active Discharge Turn-on Control in the regulator
disabled
0: Enable output discharge bleeding resistor disabled
1: Disable Output discharge bleeding resistor
9.5.28 Mode configuration mode setting 0_0 (MODECFG_0_0, address 22h)
This register contains mode setting 0, part 0 configuration register. This is a READ AND
WRITE register.
Table 42.ꢀMODECFG_0_0 register bit description
Bit
Symbol
Default value Type
Function
7
SHIP_EN_0
0
R/W
Ship mode enable/disable in mode setting 0
0: Device is NOT set in ship mode
1: Device is set in ship mode
6
EN_MODE_
SEL_BY_PIN_0
0
R/W
MODESEL0/MODESEL1 Control Selection in mode setting 0:
0: mode control by internal I2C register bits, MODE0_I2C and/or
MODE1_I2C only; signal applied on external MODESEL0/MODESEL1
pins is ignored.
1: mode control by signal applied on external MODESEL0 and/or
MODESEL1 pins only, not by internal I2C register bits, MODE0_I2C
and MODE1_I2C
[1-bit MTP to set default value]
5
4
3
2
1
0
SW1_OUT_0
[5:0]
010100
R/W
SW1 output voltage for mode setting 0 (see below).
[Note: The default value for SW1 _OUT_0[5:0] is set at 1.00V, but it
should be MTP programmable.]
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
43 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 43.ꢀSW1 output voltage for Mode Setting 0
001110=0.850V
000000=0.500V
000001=0.525V
000010=0.550V
000011=0.575V
000100=0.600V
000101=0.625V
000110=0.650V
000111=0.675V
001000=0.700V
001001=0.725V
001010=0.750V
001011=0.775V
001100=0.800V
001101=0.825V
011100=1.200V
011101=1.225V
011110=1.250V
011111=1.275V
100000=1.300V
100001=1.325V
100010=1.350V
100011=1.375V
100100=1.400V
100101=1.425V
100110=1.450V
100111=1.475V
101000=1.500V
101001~111110=1.5V
111111 = 1.8V
001111=0.875V
010000=0.900V
010001=0.925V
010010=0.950V
010011=0.975V
010100=1.000V
010101=1.025V
010110=1.050V
010111=1.075V
011000=1.100V
011001=1.125V
011010=1.150V
011011=1.175V
9.5.29 Mode configuration mode setting 0_1 (MODECFG_0_1, address 23h)
This register contains mode setting A, part 1 configuration register. This is a READ AND
WRITE register.
Table 44.ꢀMODECFG_0_1 register bit description
Bit
7
Symbol
RSVD
Default value Type
Function
0
0
R/W
R/W
Reserved bit
6
ON_CFG_0
Mode configuration upon falling edge applied on “ON” pin in
Mode Setting 0:
0: upon valid falling edge applied on “ON” pin, the device
will switch back to mode 0 setting (if the device is currently
operating in mode 0 setting, then no mode switch)
1: upon valid falling edge applied on “ON” pin, no mode
switch, the device stays in its current mode setting operation
5
SW2_OUT_0_OFFSET
0
R/W
R/W
SW2 output voltage offset selection in mode setting 0
0: SW2 Output Voltage = SW2_OUT_0_LSB [4:0] + 0V
1: SW2 Output Voltage = SW2_OUT_0_LSB [4:0] + 1.2V
4
3
2
1
0
SW2_OUT_0_LSB
[4:0]
01100
SW2 default output voltage for mode setting 0 (see below).
Note: The default value for SW2_OUT_A_LSB [4:0] is set
at 1.8V, but it should be MTP programmable.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
44 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 45.ꢀSW2 default output voltage for mode setting 0
00000=1.500V
00001=1.525V
00010=1.550V
00011=1.575V
00100=1.600V
00101=1.625V
00110=1.650V
00111=1.675V
01000=1.700V
01001=1.725V
01010=1.750V
01011=1.775V
01100=1.800V
01101=1.825V
01110=1.850V
01111=1.875V
10000=1.900V
10001=1.925V
10010=1.950V
10011=1.975V
10100=2.000V
10101=2.025V
10110=2.050V
10111=2.075V
11000=2.100V
11001-11111=2.1V
9.5.30 Mode configuration mode setting 0_2 (MODECFG_0_2, address 24h)
This register contains mode setting 0, part 2 configuration register. This is a READ AND
WRITE register.
Table 46.ꢀMODECFG_0_2 register bit description
Bit
7
Symbol
Default value Type
Function
LDO1_ OUT_0
[3:0]
0100
R/W
LDO1 default output voltage for mode setting 0 (see below).
Note: The default value for LDO1_OUT_0 [3:0] is set at 1.8V, but it
should be MTP programmable.
6
5
4
3
SW1_EN_0
SW2_EN_0
LDO1_EN_0
LDO2_EN_0
1
1
1
1
R/W
R/W
R/W
R/W
SW1 Enable Control in mode setting 0:
0: SW1 disabled
1: SW1 enabled
[Note] reserve 1-bit MTP to set its default value
2
1
0
SW2 Enable Control in mode setting 0:
0: SW2 disabled
1: SW2 enabled
[Note] reserve 1-bit MTP to set its default value
LDO1 Enable Control in mode setting 0:
0: LDO1 disabled
1: LDO1 enabled
[Note] reserve 1-bit MTP to set its default value
LDO2 Enable Control in mode setting 0:
0: LDO2 disabled
1: LDO2 enabled
[Note] reserve 1-bit MTP to set its default value
Table 47.ꢀLDO1 default output voltage for mode setting 0
0000: 1.700V
0001: 1.725V
0010: 1.750V
0011: 1.775V
0100: 1.800V
0101: 1.825V
0110: 1.850V
0111: 1.875V
1000: 1.900V
1001~1111:1.9V
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
45 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
9.5.31 Mode configuration mode setting 0_3 (MODECFG_0_3, address 25h)
This register contains mode setting 0, part 3 configuration register. This is a READ AND
WRITE register.
Table 48.ꢀMODECFG_0_3 register bit description
Bit
7
Symbol
Default value Type
Function
WD_TIMER_0
[1:0]
00
R/W
Watchdog timer setting in mode setting 0:
00: Watchdog Timer Disabled
01: Watchdog Timer = 16s
6
10: Watchdog Timer = 32s
11: Watchdog Timer = 64s
[2-bit MTP to set default value]
5
LDO2_OUT_0_
OFFSET
1
R/W
R/W
LDO2 output voltage offset selection in mode setting 0:
0: LDO2 Output Voltage = LDO2_OUT_0_LSB[4:0] + 0V
1: LDO2 Output Voltage = LDO2_OUT_0_LSB[4:0] + 1.2V
[1-bit MTP to set default value]
4
3
2
1
0
LDO2_OUT_0_
11001
LDO2 default output voltage for mode setting 0 (see below).
LSB
[4:0]
Note: The default value for LDO2_OUT_0_LSB [4:0] is set at 3.3V,
but it should be MTP programmable.
Table 49.ꢀLDO2 default output voltage for mode setting 0
00000=1.500V
00001=1.525V
00010=1.550V
00011=1.575V
00100=1.600V
00101=1.625V
00110=1.650V
00111=1.675V
01000=1.700V
01001=1.725V
01010=1.750V
01011=1.775V
01100=1.800V
01101=1.825V
01110=1.850V
01111=1.875V
10000=1.900V
10001=1.925V
10010=1.950V
10011=1.975V
10100=2.000V
10101=2.025V
10110=2.050V
10111=2.075V
11000=2.100V
11001-11111=2.1V
9.5.32 Mode configuration mode setting 1_0 (MODECFG_1_0, address 26h)
This register contains mode setting 1, part 0 configuration register. This is a READ AND
WRITE register.
Table 50.ꢀMODECFG_1_0 register bit description
Bit
Symbol
Default value Type
R/W
Function
7
SHIP_EN_1
0
Ship mode enable/disable in mode setting 1 0: Device is NOT set in
ship mode
1: Device is set in ship mode
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
46 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 50.ꢀMODECFG_1_0 register bit description...continued
Bit
Symbol
Default value Type
Function
6
EN_MODE_
SEL_BY_PIN_1
0
R/W
MODESEL0/MODESEL1 Control Selection in mode setting 1:
0: mode control by internal I2C register bits, MODE0_I2C and/or
MODE1_I2C only; signal applied on external MODESEL0/MODESEL1
pins is ignored.
1: mode control by signal applied on external MODESEL0 and/or
MODESEL1 pins only, not by internal I2C register bits, MODE0_I2C
and MODE1_I2C
5
4
3
2
1
0
SW1_OUT_1
[5:0]
011100
R/W
SW1 output voltage for mode setting 1 (see below).
Table 51.ꢀSW1 output voltage for Mode Setting 1
001110=0.850V
000000=0.500V
000001=0.525V
000010=0.550V
000011=0.575V
000100=0.600V
000101=0.625V
000110=0.650V
000111=0.675V
001000=0.700V
001001=0.725V
001010=0.750V
001011=0.775V
001100=0.800V
001101=0.825V
011100=1.200V
011101=1.225V
011110=1.250V
011111=1.275V
100000=1.300V
100001=1.325V
100010=1.350V
100011=1.375V
100100=1.400V
100101=1.425V
100110=1.450V
100111=1.475V
101000=1.500V
101001~111110=1.5V
111111 = 1.8V
001111=0.875V
010000=0.900V
010001=0.925V
010010=0.950V
010011=0.975V
010100=1.000V
010101=1.025V
010110=1.050V
010111=1.075V
011000=1.100V
011001=1.125V
011010=1.150V
011011=1.175V
9.5.33 Mode configuration mode setting 1_1 (MODECFG_1_1, address 27h)
This register contains mode setting 1, part 1 configuration register. This is a READ AND
WRITE register.
Table 52.ꢀMODECFG_1_1 register bit description
Bit
Symbol
Default value Type
R/W
Function
7
RSVD
0
Reserved bit
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
47 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 52.ꢀMODECFG_1_1 register bit description...continued
Bit
Symbol
Default value Type
Function
6
ON_CFG_1
1
R/W
Mode configuration upon falling edge applied on “ON” pin in Mode
Setting B:
0: upon valid falling edge applied on “ON” pin, the device will switch
back to mode 0 setting (if the device is currently operating in mode 0
setting, then no mode switch)
1: upon valid falling edge applied on “ON” pin, no mode switch, the
device stays in its current mode setting operation
5
SW2_OUT_1_
OFFSET
0
R/W
R/W
SW2 output voltage offset selection in mode setting 1
0: SW2 Output Voltage = SW2_OUT_1_LSB[4:0] + 0V
1: SW2 Output Voltage = SW2_OUT_1_LSB[4:0] + 1.2V
4
3
2
1
0
SW2_OUT_1_
LSB
01100
SW2 default output voltage for mode setting 1 (see below).
[4:0]
Table 53.ꢀSW2 default output voltage for mode setting 1
00000=1.500V
00001=1.525V
00010=1.550V
00011=1.575V
00100=1.600V
00101=1.625V
00110=1.650V
00111=1.675V
01000=1.700V
01001=1.725V
01010=1.750V
01011=1.775V
01100=1.800V
01101=1.825V
01110=1.850V
01111=1.875V
10000=1.900V
10001=1.925V
10010=1.950V
10011=1.975V
10100=2.000V
10101=2.025V
10110=2.050V
10111=2.075V
11000=2.100V
11001-11111=2.1V
9.5.34 Mode configuration mode setting 1_2 (MODECFG_1_2, address 28h)
This register contains mode setting 1, part 2 configuration register. This is a READ AND
WRITE register.
Table 54.ꢀMODECFG_1_2 register bit description
Bit
7
Symbol
Default value Type
Function
LDO1_ OUT_1
[3:0]
0100
R/W
LDO1 default output voltage for mode setting 1 (see below).
6
5
4
3
SW1_EN_1
1
R/W
SW1 Enable Control in mode setting 1:
0: SW1 disabled
1: SW1 enabled
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
48 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 54.ꢀMODECFG_1_2 register bit description...continued
Bit
Symbol
Default value Type
Function
2
SW2_EN_1
1
1
1
R/W
R/W
R/W
SW2 Enable Control in mode setting 1:
0: SW2 disabled
1: SW2 enabled
1
0
LDO1_EN_1
LDO2_EN_1
LDO1 Enable Control in mode setting 1:
0: LDO1 disabled
1: LDO1 enabled
LDO2 Enable Control in mode setting 1:
0: LDO2 disabled
1: LDO2 enabled
Table 55.ꢀLDO1 default output voltage for mode setting 1
0000: 1.700V
0001: 1.725V
0010: 1.750V
0011: 1.775V
0100: 1.800V
0101: 1.825V
0110: 1.850V
0111: 1.875V
1000: 1.900V
1001~1111:1.9V
9.5.35 Mode configuration mode setting 1_3 (MODECFG_1_3, address 29h)
This register contains mode setting 1, part 3 configuration register. This is a READ AND
WRITE register.
Table 56.ꢀMODECFG_1_3 register bit description
Bit
7
Symbol
Default value Type
Function
WD_TIMER_1
[1:0]
00
R/W
Watchdog timer setting in mode setting 1:
00: Watchdog Timer Disabled
01: Watchdog Timer = 16s
6
10: Watchdog Timer = 32s
11: Watchdog Timer = 64s
5
LDO2_OUT_1_OFFSET
0
R/W
R/W
LDO2 output voltage offset selection in mode setting 1:
0: LDO2 Output Voltage = LDO2_OUT_1_LSB[4:0] + 0V
1: LDO2 Output Voltage = LDO2_OUT_1_LSB[4:0] + 1.2V
4
3
2
1
0
LDO2_OUT_1_LSB
[4:0]
01100
LDO2 default output voltage for mode setting 1 (see below)
Table 57.ꢀLDO2 default output voltage for mode setting 1
00000=1.500V
00001=1.525V
00010=1.550V
00011=1.575V
01001=1.725V
01010=1.750V
01011=1.775V
01100=1.800V
10010=1.950V
10011=1.975V
10100=2.000V
10101=2.025V
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
49 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 57.ꢀLDO2 default output voltage for mode setting 1...continued
00100=1.600V
00101=1.625V
00110=1.650V
00111=1.675V
01000=1.700V
01101=1.825V
01110=1.850V
01111=1.875V
10000=1.900V
10001=1.925V
10110=2.050V
10111=2.075V
11000=2.100V
11001-11111=2.1V
9.5.36 Mode configuration mode setting 2_0 (MODECFG_2_0, address 2Ah)
This register contains mode setting 2, part 0 configuration register. This is a READ AND
WRITE register.
Table 58.ꢀMODECFG_2_0 register bit description
Bit
Symbol
Default value Type
Function
7
SHIP_EN_2
0
R/W
Ship mode enable/disable in mode setting 2
0: Device is NOT set in ship mode
1: Device is set in ship mode
6
EN_MODE_
SEL_BY_PIN_2
0
R/W
MODESEL0/MODESEL1 Control Selection in mode setting 2
0: mode control by internal I2C register bits, MODE0_I2C and/or
MODE1_I2C only; signal applied on external MODESEL0/MODESEL1
pins is ignored.
1: mode control by signal applied on external MODESEL0 and/or
MODESEL1 pins only, not by internal I2C register bits, MODE0_I2C
and MODE1_I2C
5
4
3
2
1
0
SW1_OUT_2
[5:0]
011100
R/W
SW1 output voltage for mode setting 2 (see below).
Table 59.ꢀSW1 output voltage for Mode Setting 2
000000=0.500V
001110=0.850V
001111=0.875V
011100=1.200V
011101=1.225V
011110=1.250V
011111=1.275V
100000=1.300V
100001=1.325V
100010=1.350V
100011=1.375V
100100=1.400V
100101=1.425V
000001=0.525V
000010=0.550V
000011=0.575V
000100=0.600V
000101=0.625V
000110=0.650V
000111=0.675V
001000=0.700V
001001=0.725V
010000=0.900V
010001=0.925V
010010=0.950V
010011=0.975V
010100=1.000V
010101=1.025V
010110=1.050V
010111=1.075V
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
50 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 59.ꢀSW1 output voltage for Mode Setting 2...continued
001010=0.750V
001011=0.775V
001100=0.800V
001101=0.825V
011000=1.100V
011001=1.125V
011010=1.150V
011011=1.175V
100110=1.450V
100111=1.475V
101000=1.500V
101001~111110=1.5V
111111 = 1.8V
9.5.37 Mode configuration mode setting 2_1 (MODECFG_2_1, address 2Bh)
This register contains mode setting 2, part 1 configuration register. This is a READ AND
WRITE register.
Table 60.ꢀMODECFG_2_1 register bit description
Bit
Symbol
Default
value
Type
Function
7
6
RSVD
0
1
R/W
R/W
Reserved bit
ON_CFG_2
Mode configuration upon falling edge applied on “ON” pin in
Mode setting 2
0: upon valid falling edge applied on “ON” pin, the device
will switch back to mode 0 setting (if the device is currently
operating in mode 0 setting, then no mode switch)
1: upon valid falling edge applied on “ON” pin, no mode
switch, the device stays in its current mode setting operation
5
SW2_OUT_2_OFFSET
0
R/W
R/W
SW2 output voltage offset selection in mode setting 2
0: SW2 Output Voltage = SW2_OUT_2_LSB[4:0] + 0V
1: SW2 Output Voltage = SW2_OUT_2_LSB[4:0] + 1.2V
4
3
2
1
0
SW2_OUT_2_LSB
[4:0]
01100
SW2 default output voltage for mode setting 2 (see below)
Table 61.ꢀSW2 default output voltage for mode setting 2
00000=1.500V
00001=1.525V
00010=1.550V
00011=1.575V
00100=1.600V
00101=1.625V
00110=1.650V
00111=1.675V
01000=1.700V
01001=1.725V
01010=1.750V
01011=1.775V
01100=1.800V
01101=1.825V
01110=1.850V
01111=1.875V
10000=1.900V
10001=1.925V
10010=1.950V
10011=1.975V
10100=2.000V
10101=2.025V
10110=2.050V
10111=2.075V
11000=2.100V
11001-11111=2.1V
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
51 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
9.5.38 Mode configuration mode setting 2_2 (MODECFG_2_2, address 2Ch)
This register contains mode setting 2, part 2 configuration register. This is a READ AND
WRITE register.
Table 62.ꢀMODECFG_2_2 register bit description
Bit
7
Symbol
Default value Type
Function
LDO1_ OUT_2
[3:0]
0100
R/W
LDO1 default output voltage for mode setting 2 (see below).
6
5
4
3
SW1_EN_2
SW2_EN_2
LDO1_EN_2
LDO2_EN_2
1
1
1
1
R/W
R/W
R/W
R/W
SW1 Enable Control in mode setting 2
0: SW1 disabled
1: SW1 enabled
2
1
0
SW2 Enable Control in mode setting 2
0: SW2 disabled
1: SW2 enabled
LDO1 Enable Control in mode setting 2
0: LDO1 disabled
1: LDO1 enabled
LDO2 Enable Control in mode setting 2
0: LDO2 disabled
1: LDO2 enabled
Table 63.ꢀLDO1 default output voltage for mode setting 2
0000: 1.700V
0001: 1.725V
0010: 1.750V
0011: 1.775V
0100: 1.800V
0101: 1.825V
0110: 1.850V
0111: 1.875V
1000: 1.900V
1001~1111:1.9V
9.5.39 Mode configuration mode setting 2_3 (MODECFG_2_3, address 2Dh)
This register contains mode setting 2, part 3 configuration register. This is a READ AND
WRITE register.
Table 64.ꢀMODECFG_2_3 register bit description
Bit
7
Symbol
Default value Type
Function
WD_TIMER_2
[1:0]
00
R/W
Watchdog timer setting in mode setting 2
00: Watchdog Timer Disabled
01: Watchdog Timer = 16s
6
10: Watchdog Timer = 32s
11: Watchdog Timer = 64s
5
LDO2_OUT_2_
OFFSET
0
R/W
LDO2 output voltage offset selection in mode setting 2
0: LDO2 Output Voltage = LDO2_OUT_2_LSB[4:0] + 0V
1: LDO2 Output Voltage = LDO2_OUT_2_LSB[4:0] + 1.2V
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
52 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 64.ꢀMODECFG_2_3 register bit description...continued
Bit
4
Symbol
Default value Type
01100 R/W
Function
LDO2_OUT_2_
LDO2 default output voltage for mode setting 2 (see below).
LSB
[4:0]
3
2
1
0
Table 65.ꢀLDO2 default output voltage for mode setting 2
00000=1.500V
00001=1.525V
00010=1.550V
00011=1.575V
00100=1.600V
00101=1.625V
00110=1.650V
00111=1.675V
01000=1.700V
01001=1.725V
01010=1.750V
01011=1.775V
01100=1.800V
01101=1.825V
01110=1.850V
01111=1.875V
10000=1.900V
10001=1.925V
10010=1.950V
10011=1.975V
10100=2.000V
10101=2.025V
10110=2.050V
10111=2.075V
11000=2.100V
11001-11111=2.1V
9.5.40 Mode configuration mode setting 3_0 (MODECFG_3_0, address 2Eh)
This register contains mode setting 3, part 0 configuration register. This is a READ AND
WRITE register.
Table 66.ꢀMODECFG_3_0 register bit description
Bit
Symbol
Default value Type
Function
7
SHIP_EN_3
0
R/W
Ship mode enable/disable in mode setting 3
0: Device is NOT set in ship mode
1: Device is set in ship mode
6
EN_MODE_
SEL_BY_PIN_3
0
R/W
MODESEL0/MODESEL1 Control Selection in mode setting 3
0: mode control by internal I2C register bits, MODE0_I2C and/or
MODE1_I2C only; signal applied on external MODESEL0/MODESEL1
pins is ignored.
1: mode control by signal applied on external MODESEL0 and/or
MODESEL1 pins only, not by internal I2C register bits, MODE0_I2C
and MODE1_I2C
5
4
3
2
1
0
SW1_OUT_3
[5:0]
011100
R/W
SW1 output voltage for mode setting 3 (see below).
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
53 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 67.ꢀSW1 output voltage for mode setting 3
001110=0.850V
000000=0.500V
000001=0.525V
000010=0.550V
000011=0.575V
000100=0.600V
000101=0.625V
000110=0.650V
000111=0.675V
001000=0.700V
001001=0.725V
001010=0.750V
001011=0.775V
001100=0.800V
001101=0.825V
011100=1.200V
011101=1.225V
011110=1.250V
011111=1.275V
100000=1.300V
100001=1.325V
100010=1.350V
100011=1.375V
100100=1.400V
100101=1.425V
100110=1.450V
100111=1.475V
101000=1.500V
101001~111110=1.5V
111111 = 1.8V
001111=0.875V
010000=0.900V
010001=0.925V
010010=0.950V
010011=0.975V
010100=1.000V
010101=1.025V
010110=1.050V
010111=1.075V
011000=1.100V
011001=1.125V
011010=1.150V
011011=1.175V
9.5.41 Mode configuration mode setting 3_1 (MODECFG_3_1, address 2Fh)
This register contains mode setting 3, part 1 configuration register. This is a READ AND
WRITE register.
Table 68.ꢀMODECFG_3_1 register bit description
Bit
7
Symbol
RSVD
Default value Type
Function
0
1
R/W
R/W
Reserved bit
6
ON_CFG_3
Mode configuration upon falling edge applied on “ON” pin in
mode setting 3
0: upon valid falling edge applied on “ON” pin, the device
will switch back to mode 0 setting (if the device is currently
operating in mode 0 setting, then no mode switch)
1: upon valid falling edge applied on “ON” pin, no mode
switch, the device stays in its current mode setting operation
5
SW2_OUT_3_OFFSET
0
R/W
R/W
SW2 output voltage offset selection in mode setting 3
0: SW2 Output Voltage = SW2_OUT_3_LSB[4:0] + 0V
1: SW2 Output Voltage = SW2_OUT_3_LSB[4:0] + 1.2V
4
3
2
1
0
SW2_OUT_3_LSB
[4:0]
01100
SW2 default output voltage for mode setting 3 (see below).
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
54 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 69.ꢀSW2 default output voltage for mode setting 3
00000=1.500V
00001=1.525V
00010=1.550V
00011=1.575V
00100=1.600V
00101=1.625V
00110=1.650V
00111=1.675V
01000=1.700V
01001=1.725V
01010=1.750V
01011=1.775V
01100=1.800V
01101=1.825V
01110=1.850V
01111=1.875V
10000=1.900V
10001=1.925V
10010=1.950V
10011=1.975V
10100=2.000V
10101=2.025V
10110=2.050V
10111=2.075V
11000=2.100V
11001-11111=2.1V
9.5.42 Mode configuration mode setting 3_2 (MODECFG_3_2, address 30h)
This register contains mode setting 3, part 2 configuration register. This is a READ AND
WRITE register.
Table 70.ꢀMODECFG_3_2 register bit description
Bit
7
Symbol
Default value Type
Function
LDO1_ OUT_3
[3:0]
0100
R/W
LDO1 default output voltage for mode setting 3 (see below).
6
5
4
3
SW1_EN_3
SW2_EN_3
LDO1_EN_3
LDO2_EN_3
1
1
1
1
R/W
R/W
R/W
R/W
SW1 Enable Control in mode setting 3
0: SW1 disabled
1: SW1 enabled
2
1
0
SW2 Enable Control in mode setting 3
0: SW2 disabled
1: SW2 enabled
LDO1 Enable Control in mode setting 3
0: LDO1 disabled
1: LDO1 enabled
LDO2 Enable Control in mode setting 3
0: LDO2 disabled
1: LDO2 enabled
Table 71.ꢀLDO1 default output voltage for mode setting 3
0000: 1.700V
0001: 1.725V
0010: 1.750V
0011: 1.775V
0100: 1.800V
0101: 1.825V
0110: 1.850V
0111: 1.875V
1000: 1.900V
1001~1111:1.9V
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
55 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
9.5.43 Mode configuration mode setting 3_3 (MODECFG_3_3, address 31h)
This register contains mode setting 3, part 3 configuration register. This is a READ AND
WRITE register.
Table 72.ꢀMODECFG_3_3 register bit description
Bit
Symbol
Default
value
Type
Function
7
6
WD_TIMER_3 [1:0]
00
R/W
Watchdog timer setting in mode setting 3
00: Watchdog Timer Disabled
01: Watchdog Timer = 16s
10: Watchdog Timer = 32s
11: Watchdog Timer = 64s
5
LDO2_OUT_3_OFFSET
0
R/W
R/W
LDO2 output voltage offset selection in mode setting D
0: LDO2 Output Voltage = LDO2_OUT_3_LSB[4:0] + 0V
1: LDO2 Output Voltage = LDO2_OUT_3_LSB[4:0] + 1.2V
4
3
2
1
0
LDO2_OUT_3_LSB
[4:0]
01100
LDO2 default output voltage for mode setting 3 (see below)
Table 73.ꢀLDO2 default output voltage for mode setting 3
00000=1.500V
00001=1.525V
00010=1.550V
00011=1.575V
00100=1.600V
00101=1.625V
00110=1.650V
00111=1.675V
01000=1.700V
01001=1.725V
01010=1.750V
01011=1.775V
01100=1.800V
01101=1.825V
01110=1.850V
01111=1.875V
10000=1.900V
10001=1.925V
10010=1.950V
10011=1.975V
10100=2.000V
10101=2.025V
10110=2.050V
10111=2.075V
11000=2.100V
11001-11111=2.1V
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
56 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
10 Limiting values
Table 74.ꢀLimiting values
Symbol
Parameter
Conditions
Min
-0.3
-0.3
-2
Max
20
6
Unit
V
Voltage range
VIN
(with respect to AGND)
ASYS, VBAT, VBAT_BKUP
LX1, LX2
V
6
V
SW1_OUT, SW2_OUT
LDO1, LDO2
-0.3
-0.3
-0.3
6
V
6
V
SDA, SCL, MODESEL0,
MODESEL1, ON, TS, SYSRSTn,
INTB
6
V
PGND to AGND
-0.3
–40
0.3
5
V
IO(sink)
Tj
Output sink current
on pins SYSRSTn,
INTB, SDA, SCL
mA
Junction temperature
125
°C
11 ESD ratings
Table 75.ꢀLimiting values
Symbol
Parameter
Conditions
Min
Max
Unit
V(ESD)
Electrostatic
discharge
Human body model (HBM)
Charged device model (CDM)
-
-
2000
500
V
V
12 Recommended operating conditions
Table 76.ꢀRecommended operating conditions
Symbol
VIN
Parameter
Conditions
Min
3.3
0
Max
Unit
V
Supply Voltage
Input/output voltage
VIN
5.5
3.6
VIO
SDA, SCL, MODESEL0,
MODESEL1, SYSRSTn
V
Tamb
Tj
Ambient Temperature
Junction Temperature
Storage Temperature
-40
-40
-55
85
°C
°C
°C
125
150
Tstg
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
57 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
13 Electrical characteristics
Unless otherwise specified, VVIN=5V, VVBAT=3.8V, LDO1_OUT=1.8V, LDO2_OUT=1.8V.
CVIN=2.2µF/10V, CASYS=4.7µF/10V, CVBAT=1µF/10V, CLDO1_OUT=1µF/6.3V,
CLDO2_OUT=2.2µF/6.3V, CSW1_OUT=10µF/6.3V, CSW2_OUT=10µF/6.3V, LSW1 =2.2µH, LSW2
=2.2µH, Tamb= -40°C ~ +85°C, Typical value at Tamb=25°C
13.1 Top level parameter
Table 77.ꢀEC table for Top level
Symbol Parameter
VBAT QUIESCENT CURRENT
IBAT_NOLOAD1 VBAT quiescent Current
Conditions
Min
Typ
Max
Unit
TJ = 25°C
TJ = 85°C[1]
2.9
4.5
4.5
8
µA
VBAT=4.5V
SW1, SW2, LDO1, LDO2
enabled, no load. No
switching on SW1, SW2.
VIN = open, charger disabled
[1]
IBAT_NOLOAD2
VBAT quiescent Current
TJ = 25°C
TJ = 85°C
3.5
5.5
5
µA
VBAT = 4.5V SW1, SW2,
LDO1, LDO2
11
enabled, no load.
Switching on SW1, SW2.
VIN = open, charger disabled
[1]
IBAT_DISABLE
VBAT quiescent Current
TJ = 25°C
TJ = 85°C
750
1200
3000
nA
nA
VBAT = 4.5V SW1, SW2,
LDO1, LDO2
1500
Disabled
VIN = open, charger disabled
IBAT_SHIP
VBAT quiescent current
VBAT=4.5V
100
150
VIN =open, Ship
Mode activated at TJ
= 25°C
VIN
VINUVLO
VIN Under voltage
lock-out
I2C programmable
in 200mV steps, VIN
Falling
2.9
3.5
V
VINUVLO Accuracy
VINUVLO_HYS
VINOVP
-5
+5
%
Hysteresis on VINUVLO
200
mV
V
I2C programmable
at 5.5V or 6V, VIN
Rising
5.5
6.0
VINOVP Accuracy
Input over- voltage protection
threshold
-3.5
+3.5
%
VINOVP Hysteresis
tDGL(VINOVP)
VIN Falling
100
20
mV
µs
Input over-voltage blanking
time
VIN: 5 V → 7V, 1V/
µs
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
58 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 77.ꢀEC table for Top level...continued
Symbol
Parameter
Conditions
Min
Typ
85
Max
98
Unit
VIN Current Limit
Input current limit
VIN_ILIM [2:0] = 000 74
VIN_ILIM [2:0] = 010 370
mA
425
489
ASYS
VASYS_UVLO_RISING
VASYS_UVLO_FALLING
ASYS in rising
ASYS in falling
By MTP
2.8
2.7
2.4
V
V
%VASYS_UVLO_FALLING
ASYS UVLO
Accuracy
-3.5
+3.5
%
VASYS_UVLO_HYS
ASYS UVLO
Hysteresis
400mV for 2.4V
falling threshold
100
mV
ms
or 400
TASYS_SW_DELAY
Time when ASYS
voltage is switched
between VIN and
VBAT
0.5
VASYS_PREWARNING
ASYS Pre-Warning Threshold ASYS falling, I2C
3.3
3.4
3.5
3.6
V
Accuracy
programmable
%VASYS_PREWARNING
ASYS Pre-Warning Threshold
Accuracy
-4
+4
%
VASYS_PREWARNING_HYS ASYS Pre-warning Threshold
Hysteresis
100
1.9
mV
VBAT_BKUP
VBAT_BKUP UVLO
VBAT_BKUP falling
edge
V
VBAT_BKUP
-5
5
%
UVLO Accuracy
VBAT_BKUP
100
mV
°C
UVLO Hysteresis
PROTECTION[1]
TWARNING
Pre-warning temperature
2-bit programmable,
T_WARNING [1:0]
75
80
85
90
TWARNING_HYS
TSHDN
Pre-warning threshold
Hysteresis
20
°C
°C
Thermal shutdown
3-bit
95
to
programmable,THEM_
SHDN [2:0], in 5°C
steps
125
TSHDN_HYS
Thermal shutdown Hysteresis
20
°C
WATCHDOG & SAFETY TIMER
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
59 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 77.ꢀEC table for Top level...continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TWD_TIMER Range
Watchdog Timer
When enabled via
I2C Programming
-15%
Disable +15%
s
16
32
64
TCHG_PREQ
Pre-qualification Charging
Safety Timer Range
I2C Programmable, -15%
15min/step [Note]
When under
thermal fold- back
status, the timer
will extend by 2x
automatically
15
30
45
60
+15%
+15%
min
hrs
TCHG_FAST
Fast (CC and CV) Charging
Safety Timer Range
I2C Programmable, -15%
2hr/step [Note]
3
5
7
9
When under
thermal fold- back
status, the timer
will extend by 2x
automatically
POWER UP/DOWN SEQUENCE TIMING[1]
TPWUP_DLY_INI
Power up Initial delay
Time from ON signal
asserts to the first
output rail reaches
90% of its nominal
value
2
ms
TPWDN_DLY_INTERVAL
TPWUP_DLY_INTERVAL
Power down interval delay
Power up interval delay
Delay between
power rail
2
1
ms
ms
For power-up: this
is the time from
previous voltage
rail reaches 90% of
its nominal value to
the time when the
following voltage
rail reaches its 90%
nominal value
For power-down:
this is the time
from the previous
voltage rail starts
falling to the time the
following rail starts
falling
[1] Guaranteed by design and characterization; not tested in production.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
60 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
13.2 Battery charger
Table 78.ꢀEC table for Linear Charger
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
LINEAR CHARGER
VBAT_REG
VBAT regulation
voltage range
I2C programmable,
20mV/step
3.60
-0.75
-1
4.60
0.75
1
V
%VBAT_REG
VBAT_REG Regulation IOUT=0 mA to 200 mA;
Voltage Accuracy
%
%
VIN= 5V, Tamb=25°C
IOUT=0 mA to 200 mA;
VIN= 5V, Tamb=-40°C~
+85°C
ICHG_CC
Constant charging
current value
I2C programmable,
5
315
mA
VBAT_REG > VBAT
>
VBAT_LOW; VIN = 5V
%ICHG_CC
ICHG_CC Accuracy
VBAT_REG > VBAT >
VBAT_LOW; VIN = 5V
ICHG_CC > 40mA
ICHG_CC ≤ 40mA
-6
+6
%
-12
120
+12
160
%
ΔVBAT_REG (HOT)
VBAT_REG reduction in T3 < VTS < T4 in TS
warm condition enabled
140
250
130
mV
[1]
RDS_ON_VIN_TO_ASYS
RDS_ON between VIN VIN = 5V at 50mA
and ASYS
360
175
mΩ
mΩ
[1]
RDS_ON_ASYS_TO_VBAT
RDS_ON between
ASYS and VBAT
VBAT = 3.8V at 50mA
DEAD BATTERY IN PRECHARGE MODE
VBAT_DEAD
Dead battery charge [Note: reserve 2-bit MTP
to low battery charge for programmability,
1.9
50
V
transition threshold
1.7V/1.8V/1.9V/2.0V]
%VBAT_DEAD Accuracy
tDGL_BAT_DEAD2LOW
-4.5
+4.5
%
Deglitch time from
dead battery charge
to low battery charge
transition
µs
ICHG_DEAD
I2C programmable,1mA/
step
1
63
mA
%
%ICHG_DEAD
ICHG_DEAD Accuracy
VBAT =1V, ICHG_DEAD
=4mA
-12
+12
LOW BATTERY IN PRECHARGE MODE
VBAT_LOW
Precharge to fast-
charge transition
threshold
[Note: reserve 2-bit MTP
for programmability,
2.3V/2.4V/2.5V/2.6V]
2.5
50
V
%VBAT_LOW
VBAT_LOW Accuracy
-3.5
+3.5
%
tDGL_BAT_LOW2CC
Deglitch time on pre-
charge to fast-charge
transition
µs
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
61 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 78.ꢀEC table for Linear Charger...continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ICHG_LOW
I2C programmable,1mA/
step
1
63
mA
%ICHG_LOW
ICHG_LOW Accuracy
VBAT =2V, ICHG_DEAD
=8mA
-10
+10
%
tDGL_BAT_CC2LOW
Deglitch time from
fast-charge to low
battery charge
transition
50
ms
TOP-OFF MODE
ICHG_TOPOFF
ICHG_TOPOFF
I2C programmable,1mA/
step
1
63
mA
programmed value
ICHG_TOPOFF Accuracy
ICHG_TOPOFF ≥ 8mA
-15
+15
+20
%
%
ICHG_TOPOFF < 8mA, test -20
4mA only in production
tDGL_BAT_CC2TOPOFF
ICHG_TOPOFF detection
deglitch time on fast
charging to top-off
charging transition
20
ms
RECHARGE MODE
VBAT_RESTART
Charging restart
threshold voltage
When below VBAT_
95
140
240
165
270
mV
ms
REG [Note: reserve 1-bit
MTP bit to set the typical
value, 140mV or 240mV]
185
tDGL_BAT_RESTART
Deglitch time,
recharge threshold
detected
50
BATTERY PRESENCE DETECTION
IBAT_DET_SINK
Sink current during
battery detection
VIN = 5V; Battery absent
VIN = 5V; Battery absent
5
mA
ms
mA
ms
V
tDGL(BAT_DET_SINK)
IBAT_DET_SOURCE
tDGL(BAT_DET_SOURCE)
VBAT_DET_LOW
Deglitch time, for
sinking current
300
5
Source current during VIN = 5V; Battery absent
battery detection
Deglitch time, for
sourcing current
VIN = 5V; Battery absent
300
1.9
Battery detection
lower threshold
VIN = 5V; Battery absent
[Note: reserve 2-bit MTP
for programmability,
1.7V/1.8V/1.9V/2.0V]
VBAT_DET_UP
Battery detection
upper threshold
VIN = 5V; Battery absent
[Note: reserve 2-bit MTP
for programmability,
3.4
V
3.2V/3.3V/3.4V/3.5V]
BATTERY-PACK NTC MONITOR (TS)
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
62 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 78.ꢀEC table for Linear Charger...continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
INTC-10k
NTC thermistor bias
current
VTS < ASYS-200mV
44
50
56
µA
(-12%)
(+12%)
INTC-DIS-10k
10k NTC bias current VTS < ASYS-200mV
4.4
5
5.6
µA
when charging is
disabled
(-12%)
(+12%)
VTS(0°C)
TS threshold voltage NTC_BETA_SEL [2:0] = 1.171
1.372
110
1.45
V
at 0°C
000
VTS(0°C)_HYS
VTS(0°C)
mV
Hysteresis Threshold
VTS(10°C)
TS threshold voltage NTC_BETA_SEL [2:0] = 0.813
0.900
70
0.999
0.303
0.187
V
at 10°C
000
VTS(10°C)_HYS
VTS(10°C)
mV
Hysteresis Threshold
VTS(45°C)
TS threshold voltage NTC_BETA_SEL [2:0] = 0.205
0.246
24
V
at 45°C
000
VTS(45°C)_HYS
VTS(45°C)
mV
Hysteresis Threshold
VTS(60°C)
TS threshold voltage NTC_BETA_SEL [2:0] = 0.128
0.151
20
V
at 60°C
000
VTS(60°C)_HYS
VTS(60°C)
mV
Hysteresis Threshold
TDGL (TS)
CTS
Deglitch time for TS
pin
50
10
ms
nF
Maximum Decoupling
Capacitor
THERMAL REGULATION[1]
TTHEM_REGULATION Thermal regulation
I2C Programmable, 5°C/ 80
step
115
°C
°C
(fold-back) range
TTHEM_REGULATION_HYS Thermal regulation
(fold-back) Hysteresis
20
[1] Guaranteed by design and characterization; not tested in production.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
63 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
13.3 BUCK1 (SW1)
Table 79.ꢀEC table for BUCK1 (SW1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIN(SW1)
Input voltage
range for CORE
BUCK
Input is PSYS1, guaranteed by design 2.5
5.5
V
IOUT(SW1) MAX
VSW1 Range
Max Output
Current
Over VPSYS1, guaranteed by design
250
0.5
-3
mA
V
Output range for I2C programmable from 0.5V to 1.5V
CORE BUCK in 25mV/step, a fixed 1.8V
1.5
+3
VSW1_OUT Accuracy CORE BUCK DC Over full VPSYS1, IOUT(SW1)
,
%
Output Accuracy -40°C ≤ Tamb ≤ +85°C, for all
VSW1_OUT except for 500mV and 1.8V
Over full VPSYS1, IOUT(SW1)
,
-3.5
-4
+3.5
+4
-40°C ≤ Tamb ≤ +85°C, for only
VSW1_OUT =1.8V
Over full VPSYS1, IOUT(SW1)
,
-40°C ≤ Tamb ≤ +85°C, for only
VSW1_OUT =0.5V
ΔVSW1 / Δ VPSYS1
DC Line
regulation
VSW1(NOM)+0.5V < VPSYS1 < 5.5V,
IOUT(SW1) = 250mA
0.15
%/V
ΔVSW1 / ΔIOUT(SW1) DC Load
regulation
0 mA < IOUT(SW1) < 250mA
-40°C ≤ Tamb ≤ +85°C[1]
0.008
%/mA
TON (SW1)
110
240
700
350
ns
[1]
IIN(SW1)
Quiescent current SW1 enabled, IOUT(SW1) = 0, no
switching
nA
Inductor value
L
2.2
µH
[1]
RDSON(SW1)
High Side P-FET VPSYS1=5V
RDSON
500
900
450
mΩ
Low Side N-FET VPSYS1=5V
RDSON
250
50
RSTDN(SW1)
SW1 Output
Active Discharge
Resistance
Ω
ILIM(SW1)
Internal Peak
Current Limit
Cycle by cycle peak current limit
700
950
50
1200
mA
ns
tONMIN(SW1)
tOFFMIN(SW1)
Minimum On-
Time
Minimum-Off
Time
10
ns
tSSTART(SW1)
Efficiency[1]
Soft-start time
VSW1OUT=1.2V
@IOUT=10µA
@IOUT=100µA
@IOUT=65mA
@IOUT=125mA
1.2
ms
%
%
%
%
VPSYS1=5V,
VSW1OUT=1.5V
> 76
> 84
> 86
> 86
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
64 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 79.ꢀEC table for BUCK1 (SW1)...continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
@IOUT=250mA
> 84
%
[1] Guaranteed by design and characterization; not tested in production.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
65 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
13.4 BUCK2 (SW2)
Table 80.ꢀEC table for BUCK2 (SW2)ꢀ
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIN(SW2)
Input voltage
Input is VPSYS2
2.5
5.5
V
range for SW2
IOUT(SW2)MAX
VSW2_RANGE
Maximum Output Over VPSYS2
Current
Output range for I2C programmable, 25mV/step
SW2
500
mA
V
1.5
2.7
-2
2.1
3.3
2
VSW2_Accuracy
SW2 DC Output Over full VPSYS2, IOUT(SW2)
,
%
%
Accuracy
Tamb=room temp
Over full VPSYS2, IOUT(SW2)
temperature range
,
-3
3
ΔVSW2 / Δ VPSYS2
DC Line
regulation
VSW2OUT(NOM)+0.5V < VPSYS2
5.5V, IOUT(SW1) = 500 mA
<
0.15
%/V
ΔVSW2 / ΔIOUT(SW2) DC Load
regulation
0 mA < IOUT(SW1) < 500 mA
0.008
%/mA
TON (SW2)
IIN(SW2)[1]
250
360
700
490
ns
Quiescent current SW2 enabled, IOUT(SW2) =0,
no switching
nA
Inductor value
L
2.2
µH
[1]
RDSON(SW2)
High Side P-FET VPSYS2=5V
RDSON
250
450
250
mΩ
Low Side N-FET VPSYS2=5V
RDSON
125
50
RSTDN(SW2)
SW2 Output
Active Discharge
Resistance
Ω
ILIM(SW2)
Peak Current
Limit
Cycle by cycle peak current limit
900
1300
1800
mA
tONMIN(SW2)
tOFFMIN(SW2)
tSSTART(SW2)
Efficiency[1]
Min. On Time
Max On Time
Softstart time
50
ns
ns
ms
%
10
VSW2OUT=1.8V
@IOUT=10µA
1.8
VPSYS25V
VSW2OUT=1.8V
> 78
> 87
> 88
> 88
> 86
@IOUT=100µA
@IOUT=125mA
@IOUT=250mA
@IOUT=500mA
[1] Guaranteed by design and characterization; not tested in production.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
66 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
13.5 LDO1 (Always-On LDO)
Table 81.ꢀEC table for LDO1
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIN_LDO1
Input voltage
Whichever is higher between VBAT_ 2.0
5.5
V
range for Always- BKUP and ASYS
On LDO
IOUT_LDO1_MAX
IOUT_LDO1_LIMIT
VLDO1_OUT Range
Maximum Output
DC Current
1
mA
mA
V
Internal Current
Limit
LDO1_OUT = GND
1.4
1.700
-3
3.3
7.0
LDO1 nominal
output voltage
I2C Programmable, 25mV/step
Over VIN_LDO1, I OUT= 0~1mA
1.900
+3
VLDO1_OUT
Accuracy
LDO1 Output
Voltage Accuracy
%
ΔVLDO1_OUT
(VLDO1_OUT(NOM)
ΔVIN_LDO1)
/
DC Line
regulation
VLDO1_OUT(NOM)+0.5V < VIN_LDO1
5V, I OUT= 1mA
<
1
%/V
x
x
ΔVLDO1_OUT
(VLDO1_OUT(NOM)
ΔV x ΔIOUT
/
DC Load
regulation
0 mA < I OUT < 1 mA
1
%/mA
dB
)
Power Supply
Rejection Ratio
(PSRR)[1]
40
IIN(LDO1)
Quiescent current I OUT =0mA
Dropout Voltage I OUT=1mA
94
50
nA
mV
Ω
[1][2]
VDROPOUT(LDO1)
RSTDN(LDO1)
200
LDO1 Output
Active Discharge
Resistance
[1] Guaranteed by design and characterization; not tested in production.
[2] Dropout voltage is defined as the input-to-output difference in the predefined load when the output is below 100mV to the nominal regulation voltage.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
67 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
13.6 LDO2 (System LDO)
Table 82.ꢀEC table for LDO2
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIN_LDO2
Input voltage
range
ASYS
2.5
5.5
V
IOUT_LDO2_MAX
Maximum Output
Current
250
300
mA
mA
V
[1]
IOUT_LDO2_LIMIT
Internal Current
Limit
LDO2_OUT = GND
450
600
VLDO2_OUT Range
LDO2 output
voltage range
programmable 25mV steps
1.5
2.7
-3.5
2.1
3.3
3.5
VLDO2_OUT
Accuracy
LDO2 Output
Accuracy
Over VIN_LDO2, IOUT
,
%
temperature
ΔVLDO2_OUT
(VLDO2_OUT(NOM)
ΔVIN_LDO2
/
DC Line
regulation
VLDO2_OUT(NOM)+0.5V < VIN_LDO2
5.5V, IOUT = 250 mA
<
0.35
%/V
x
x
)
ΔVLDO2_OUT
(VLDO2_OUT(NOM)
ΔIOUT
/
DC Load
regulation
0 mA < IOUT < 250 mA
0.0065
%/mA
dB
)
PSRR[1]
Power Supply
Rejection Ratio
40
IIN(LDO2)
Quiescent current IOUT =0mA
Dropout Voltage IOUT=100mA
450
nA
mV
Ω
[2]
VDROPOUT(LDO2)
150
RSTDN(LDO2)
LDO2 Output
Active Discharge
Resistance
150
[1] Guaranteed by design and characterization; not tested in production.
[2] Dropout voltage is defined as the input-to-output difference in the predefined load when the output is below 100mV to the nominal regulation voltage.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
68 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
13.7 I2C Interface and Logic I/O
Table 83.ꢀEC table for I2C and Logic
Symbol Parameter
SERIAL INTERFACE (SCL & SDA)
Conditions
Min
Typ
Max
Unit
VPULLUP
Range[1]
Pullup Voltage Range
1.5
3.6
V
FI2C
VIH
I2C Clock frequency
On SCL
0
1000
kHz
V
High-level Input voltage
Low-level Input voltage
1.5
VIL
0.5
0.4
V
Vhys
Hysteresis of Schmitt
trigger inputs
0.01
0
V
VOL
IOL
Low-level output voltage
at 3mA sink current
V
Low-level output current VOL =0.4 V; Standard and Fast
modes
3
mA
VOL =0.6 V; Fast mode
6
mA
µA
IIL
Low-level input current
Capacitance of IO pin
Pin voltage: 0.1xVpullup to 0.9x
Vpullup max
-10
10
10
CI
pF
µs
tHD,STA
Hold time (repeated)
START condition
Fast mode plus; After this period,
the first clock pulse is generated
0.26
tLOW
LOW period of I2C clock Fast mode plus
HIGH period of I2C clock Fast mode plus
0.5
µs
µs
µs
tHIGH
tSU,STA
0.26
0.26
Setup time (repeated)
START condition
Fast mode plus
tHD,DAT
tSU,DAT
tr
Data Hold time
Data Setup time
Fast mode plus
Fast mode plus
Fast mode plus
0
µs
ns
ns
50
Rise time of I2C_SCL
and
120
120
I2C_SDA signals
tf
Fall time of I2C_SCL and Fast mode plus
I2C_SDA signals
ns
µs
µs
tSU,STO
tBUF
Setup time for STOP
condition
Fast mode plus
0.26
0.5
Bus free time between
STOP and START
Fast mode plus
condition
tVD,DAT
tVD,ACK
Data valid time
Fast mode plus
0.45
0.45
µs
µs
Data valid acknowledge Fast mode plus
time
tSP
Pulse width of spikes that
must be suppressed by
input filter
0
50
ns
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
69 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Table 83.ꢀEC table for I2C and Logic...continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MODESEL0/MODESEL1
VIH1
Logic Input High
1.5
V
Threshold
VIL1
Logic Input Low
Threshold
0.4
1
V
ILK1
Logic Pin Leakage
Current
Pulled up to 5.0V
0.1
1
µA
µs
tdebounce_1
Debounce time
for MODESEL0,
MODESEL1
ON
VIH2
Logic Input High
Threshold
Note: ON pin internally pulled up, no 70% *
V
external pull-up voltage needed.
VBAT
VIL2
Logic Input Low
Threshold
0.4
V
tdebounce
Debounce time for ON
To initiate the default power-up
sequence
200
µs
SYSRSTn, INTB
VOL1
Low-level output voltage
at 1mA sink current
0.5
0.1
V
ILK2
Logic Pin Leakage
Current
Pulled up to 5.0V
0.01
µA
V
VPULLUP1
Minimum Supply Voltage
for valid Open-drain
signal
1.5
[1] Guaranteed by design and characterization; not tested in production.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
70 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
14 Package outline
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 3 x 3 x 0.85 mm
SOT905-1
D
B
A
terminal 1
index area
E
A
A
1
c
detail X
C
e
b
1
e
y
C
1
y
M
v
w
C A
C
B
1
b
M
6
7
11
12
L
13
5
e
e
b
1
E
h
2
17
1
LC
terminal 1
index area
24
23
19
18
X
D
h
L
1
LC
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
b
c
D
D
E
E
e
e
e
2
L
L
LC
v
w
y
y
1
1
1
h
h
1
1
max
0.05 0.25 0.45
0.00 0.15 0.35
3.1
2.9
2.05
1.75
3.1
2.9
2.05
1.75
0.35
0.15
0.1
0.0
0.3
0.2
mm
1
0.2
0.4
1.8
1.8
0.1
0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
06-03-13
06-03-31
SOT905-1
- - -
- - -
- - -
Figure 11.ꢀPackage outline SOT905-1 (HVQFN24)
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
71 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Figure 12.ꢀPackage outline SOT1397-7 (WLCSP25) (1 of 2)
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
72 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Figure 13.ꢀPackage outline SOT1397-7 (WLCSP25) (2 of 2)
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
73 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
15 Packing information
15.1 SOT905-1 HVQFN24; reel dry pack, SMD, 7" Q2 standard product
orientation ordering code (12NC) ending 547
15.1.1 Dimensions and quantities
Table 84.ꢀDimensions and quantities
Reel dimensions
d × w (mm) [1]
SPQ/PQ
(pcs) [2]
Reels
per box
178 × 12
1400
1
[1] d = reel diameter; w = tape width.
[2] Packing quantity dependent on specific product type. View ordering and availability details at NXP order portal, or contact
your local NXP representative.
15.1.2 Product orientation
pin 1
aaa-006538
Pin 1 is in quadrant 2.
Figure 14.ꢀProduct orientation in carrier tape
15.1.3 Carrier tape dimensions
4 mm
A
K
0
0
W
B
0
P
1
T
direction of feed
001aao148
Not drawn to scale.
Figure 15.ꢀCarrier tape dimensions
Table 85.ꢀCarrier tape dimensions
In accordance with IEC 60286-3/EIA-481.
A0 (mm)
B0 (mm)
K0 (mm)
T (mm)
0.30 ± 0.5
P1 (mm)
W (mm)
3.30 ± 0.1
3.30 ± 0.1
1.10 ± 0.1
8.0 ± 0.1
12 +.3/-.0
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
74 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
15.2 SOT1401-4 WLCSP25; reel dry pack, SMD, 7" Q1 standard product
orientation ordering code (12NC) ending 012
15.2.1 Dimensions and quantities
Table 86.ꢀDimensions and quantities
Reel dimensions
d × w (mm) [1]
SPQ/PQ
(pcs) [2]
Reels
per box
180 × 8
3000
1
[1] d = reel diameter; w = tape width.
[2] Packing quantity dependent on specific product type. View ordering and availability details at NXP order portal, or contact
your local NXP representative.
15.2.2 Product orientation
ball 1
aaa-017857
Ball 1 is in quadrant 1.
Figure 16.ꢀProduct orientation in carrier tape
15.2.3 Carrier tape dimensions
4 mm
A
K
0
0
W
B
0
P
1
T
direction of feed
001aao148
Not drawn to scale.
Figure 17.ꢀCarrier tape dimensions
Table 87.ꢀCarrier tape dimensions
In accordance with IEC 60286-3/EIA-481.
A0 (mm)
B0 (mm)
K0 (mm)
T (mm)
P1 (mm)
W (mm)
2.27 ± 0.05
2.27 ± 0.05
0.67 ± 0.05
0.25 ± 0.02
4.0 ± 0.10
8 +0.30/-0.10
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
75 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
16 Revision history
Table 88.ꢀRevision history
Document ID
PCA9420 v.2
Modifications:
Release date
20210126
Data sheet status
Change notice
Supersedes
Product data sheet
-
PCA9420 v.1.1
• Table 7: Corrected reset value for 03 SUB_INT0_MASK, 13 CHG_CNTL3, 23
MODECFG_0_1
• Table 11: Corrected default value for 5 ON_PUSH_INT_MASK
• Table 16: Removed text "(the default factory setting for the initial power up)"
• Table 26: Corrected default value for ICHG_LOW [5:0]
• Table 36 : Changed invalid to valid for VIN_OK
• Table 44 : Changed default value for ON_CFG_0; deleted "1-bit MTP to set default value"
• Added packing information for SOT905-1 and SOT1401-4
PCA9420 v.1.1
Modifications:
20191024
Product data sheet
-
PCA9420 v.1.0
• Table 10 and Table 11: Bit 5 updated from "reserved" to "ON_PUSH_INT".
• Changed orderable part number, packing method and minimum order quantity for
PCA9420BS.
PCA9420 v.1.0
20190601
Product data sheet
-
-
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
76 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
17 Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
17.2 Definitions
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
77 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
17.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
78 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Ordering information ..........................................2
Ordering options ................................................2
Pin Description ..................................................5
Mode Selection by external pins
Tab. 47. LDO1 default output voltage for mode
setting 0 ...........................................................45
Tab. 48. MODECFG_0_3 register bit description ..........46
Tab. 49. LDO2 default output voltage for mode
(MODESEL0, MODESEL1) .............................11
Regulator summary .........................................13
I2C Slave Address .......................................... 22
Register map ...................................................22
DEV_INFO register bit description .................. 24
TOP_INT register bit description .....................25
setting 0 ...........................................................46
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 50. MODECFG_1_0 register bit description ..........46
Tab. 51. SW1 output voltage for Mode Setting 1 ...........47
Tab. 52. MODECFG_1_1 register bit description ..........47
Tab. 53. SW2 default output voltage for mode
setting 1 ...........................................................48
Tab. 10. Sub_INT0 register bit description ....................26
Tab. 11. Sub_INT0_Mask bit description ...................... 26
Tab. 12. Sub_INT1 register bit description ....................27
Tab. 13. Sub_INT1_Mask register bit description ..........28
Tab. 14. Sub_INT2 register bit description ....................28
Tab. 15. Sub_INT2_Mask register bit description ..........29
Tab. 16. TOP_CNTL0 register bit description ................30
Tab. 17. TOP_CNTL1 register bit description ................31
Tab. 18. TOP_CNTL2 register bit description ................31
Tab. 19. TOP_CNTL3 register bit description ................32
Tab. 20. TOP_CNTL4 register bit description ................33
Tab. 21. CHG_CNTL0 register bit description ...............33
Tab. 22. CHG_CNTL1 register bit description ...............34
Tab. 23. Linear battery charger constant current
Tab. 54. MODECFG_1_2 register bit description ..........48
Tab. 55. LDO1 default output voltage for mode
setting 1 ...........................................................49
Tab. 56. MODECFG_1_3 register bit description ..........49
Tab. 57. LDO2 default output voltage for mode
setting 1 ...........................................................49
Tab. 58. MODECFG_2_0 register bit description ..........50
Tab. 59. SW1 output voltage for Mode Setting 2 ...........50
Tab. 60. MODECFG_2_1 register bit description ..........51
Tab. 61. SW2 default output voltage for mode
setting 2 ...........................................................51
Tab. 62. MODECFG_2_2 register bit description ..........52
Tab. 63. LDO1 default output voltage for mode
setting 2 ...........................................................52
(CC) setting .....................................................34
Tab. 24. CHG_CNTL2 register bit description ...............34
Tab. 25. Linear battery charger top-off charge
Tab. 64. MODECFG_2_3 register bit description ..........52
Tab. 65. LDO2 default output voltage for mode
setting 2 ...........................................................53
current setting ................................................. 35
Tab. 66. MODECFG_3_0 register bit description ..........53
Tab. 67. SW1 output voltage for mode setting 3 ........... 54
Tab. 68. MODECFG_3_1 register bit description ..........54
Tab. 69. SW2 default output voltage for mode
setting 3 ...........................................................55
Tab. 70. MODECFG_3_2 register bit description ..........55
Tab. 71. LDO1 default output voltage for mode
Tab. 26. CHG_CNTL3 register bit description ...............35
Tab. 27. Low battery charge current setting ..................36
Tab. 28. CHG_CNTL4 register bit description ...............36
Tab. 29. Dead battery charge current setting ................37
Tab. 30. CHG_CNTL5 register bit description ...............37
Tab. 31. VBATREG, linear battery charger regulated
battery voltage setting .....................................38
setting 3 ...........................................................55
Tab. 32. CHG_CNTL6 register bit description ...............38
Tab. 33. CHG_CNTL7 register bit description ...............39
Tab. 34. Set the thermistor beta value selection ........... 39
Tab. 35. Thermal regulation threshold setting ............... 39
Tab. 36. CHG_STATUS_0 register bit description .........39
Tab. 37. CHG_STATUS_1 register bit description .........40
Tab. 38. CHG_STATUS_2 register bit description .........41
Tab. 39. CHG_STATUS_3 register bit description .........41
Tab. 40. REG_STATUS register bit description .............42
Tab. 41. ACT_DISCHARGE_CNTL register bit
Tab. 72. MODECFG_3_3 register bit description ..........56
Tab. 73. LDO2 default output voltage for mode
setting 3 ...........................................................56
Tab. 74. Limiting values ................................................ 57
Tab. 75. Limiting values ................................................ 57
Tab. 76. Recommended operating conditions ...............57
Tab. 77. EC table for Top level ..................................... 58
Tab. 78. EC table for Linear Charger ............................61
Tab. 79. EC table for BUCK1 (SW1) .............................64
Tab. 80. EC table for BUCK2 (SW2)ꢀ ...........................66
Tab. 81. EC table for LDO1 .......................................... 67
Tab. 82. EC table for LDO2 .......................................... 68
Tab. 83. EC table for I2C and Logic ..............................69
Tab. 84. Dimensions and quantities .............................. 74
Tab. 85. Carrier tape dimensions ..................................74
Tab. 86. Dimensions and quantities .............................. 75
Tab. 87. Carrier tape dimensions ..................................75
Tab. 88. Revision history ...............................................76
description ....................................................... 42
Tab. 42. MODECFG_0_0 register bit description ..........43
Tab. 43. SW1 output voltage for Mode Setting 0 ...........44
Tab. 44. MODECFG_0_1 register bit description ..........44
Tab. 45. SW2 default output voltage for mode
setting 0 ...........................................................45
Tab. 46. MODECFG_0_2 register bit description ..........45
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
79 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Simplified block diagram ................................... 3
Fig. 10. Operation over TS bias voltage for JEITA ....... 20
PCA9420BS pinout (HVQFN24) – top view .......4
PCA9420UK pinout (WLCSP25) – top view ...... 4
System configuration diagram; i.MXRT
Fig. 11.
Package outline SOT905-1 (HVQFN24) ......... 71
Fig. 12. Package outline SOT1397-7 (WLCSP25)
(1 of 2) ............................................................ 72
series .................................................................7
System configuration diagram; K4-family
Fig. 13. Package outline SOT1397-7 (WLCSP25)
(2 of 2) ............................................................ 73
Fig. 5.
MCU .................................................................. 8
Power-up/down sequence ...............................15
Pass-Through mode of BUCK2 (SW2) ............16
Typical Charging Profile Example ................... 18
Charger State Diagram ................................... 19
Fig. 14. Product orientation in carrier tape ................... 74
Fig. 15. Carrier tape dimensions ..................................74
Fig. 16. Product orientation in carrier tape ................... 75
Fig. 17. Carrier tape dimensions ..................................75
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
80 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
Contents
1
General description ............................................ 1
9.5.4
Sub level interrupt_0 mask (Sub_INT0_
2
3
4
4.1
5
Features and Benefits ........................................ 1
Applications .........................................................2
Ordering information .......................................... 2
Ordering options ................................................ 2
Simplified block diagram ................................... 3
Pinning information ............................................ 4
Pinning ...............................................................4
Pin description ...................................................5
System configuration diagram .......................... 7
Functional description ........................................9
ASYS ................................................................. 9
VBAT_BKUP (back-up battery input) .................9
ON ..................................................................... 9
TS .................................................................... 10
Mode setting ....................................................10
Mode selection by external pins
(MODESEL0, MODESEL1) ............................. 11
SYSRSTn .........................................................11
SHIP mode ...................................................... 12
Watchdog timer ................................................13
Regulators ........................................................13
Enable/disable and active discharge ............... 13
Power-good indication ..................................... 14
Power-up/down sequence and on-the-fly
voltage change ................................................ 14
BUCK1 (SW1, core buck regulator) .................15
BUCK2 (SW2, system buck regulator) .............15
LDO1 (always-on LDO) ................................... 16
LDO2 (system LDO) ........................................16
Linear battery charger ..................................... 16
Battery charging management .........................17
Battery temperature sensing and JEITA-
compliant charging profile ................................20
Low-battery/dead-battery (pre-qualification)
charging ........................................................... 20
Constant current charging/constant voltage
Mask, address 03h) .........................................26
Sub level interrupt_1 (Sub_INT1, address
04h) ..................................................................27
Sub level interrupt_1 mask (Sub_INT1_
Mask, address 05h) .........................................28
Sub level interrupt_2 (Sub_INT2, address
06h) ..................................................................28
Sub level interrupt_2 mask (Sub_INT2_
Mask, address 07h) .........................................29
Top level control_0 (TOP_CTL0, address
09h) ..................................................................30
Top level control_1 (TOP_CTL1, address
0Ah) ................................................................. 31
Top level control_2 (TOP_CTL2, address
0Bh) ................................................................. 31
Top level control_3 (TOP_CTL3, address
0Ch) ................................................................. 32
Top level control_4 (TOP_CTL4, address
0Dh) ................................................................. 33
Battery charger control_0 (CHG_CTL0,
address 10h) ....................................................33
Battery charger control_1 (CHG_CTL1,
address 11h) ....................................................33
Battery charger control_2 (CHG_CTL2,
address 12h) ....................................................34
Battery charger control_3 (CHG_CTL3,
address 13h) ....................................................35
Battery charger control_4 (CHG_CTL4,
address 14h) ....................................................36
Battery charger control_5 (CHG_CTL5,
address 15h) ....................................................37
Battery charger control_6 (CHG_CTL6,
address 16h) ....................................................38
Battery charger control_7 (CHG_CTL7,
address 17h) ....................................................39
Battery charger status_0 (CHG_STATUS_
0, address 18h) ............................................... 39
Battery charger status_1 (CHG_STATUS_
1, address 19h) ............................................... 40
Battery charger status_2 (CHG_STATUS_
2, address 1Ah) ...............................................41
Battery charger status_3 (CHG_STATUS_
3, address 1Bh) ...............................................41
Regulator status (REG_STATUS, address
20h) ..................................................................42
Active Discharge Regulator control (ACT_
DISCHARGE_CNTL, address 21h) ................. 42
Mode configuration mode setting 0_0
(MODECFG_0_0, address 22h) ...................... 43
Mode configuration mode setting 0_1
(MODECFG_0_1, address 23h) ...................... 44
Mode configuration mode setting 0_2
(MODECFG_0_2, address 24h) ...................... 45
Mode configuration mode setting 0_3
9.5.5
9.5.6
6
9.5.7
6.1
6.2
7
9.5.8
8
9.5.9
8.1
8.2
8.3
8.4
8.5
8.6
9.5.10
9.5.11
9.5.12
9.5.13
9.5.14
9.5.15
9.5.16
9.5.17
9.5.18
9.5.19
9.5.20
9.5.21
9.5.22
9.5.23
9.5.24
9.5.25
9.5.26
9.5.27
9.5.28
9.5.29
9.5.30
9.5.31
8.7
8.8
8.9
8.10
8.10.1
8.10.2
8.10.3
8.10.4
8.10.5
8.10.6
8.10.7
8.11
8.11.1
8.11.2
8.11.3
8.11.4
charging (fast charging) and termination ......... 20
Charger safety timers ...................................... 21
Recharging .......................................................21
Starting a new charge cycle ............................ 21
Battery attach detection ...................................21
Hardware and software reset .......................... 21
I2C-bus interface and register ......................... 21
I2C slave address ............................................21
General call and device ID addresses .............22
Register type ................................................... 22
Register map ................................................... 22
Register description .........................................24
Device information (DEV_INFO, address
8.11.5
8.11.6
8.11.7
8.11.8
8.12
9
9.1
9.2
9.3
9.4
9.5
9.5.1
00h) ..................................................................24
Top level interrupt status (TOP_INT,
address 01h) ....................................................25
Sub level interrupt_0 (SUB_INT0, address
9.5.2
9.5.3
02h) ..................................................................25
(MODECFG_0_3, address 25h) ...................... 46
PCA9420
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 2 — 26 January 2021
81 / 82
NXP Semiconductors
PCA9420
Power management IC for low-power microcontroller applications
9.5.32
9.5.33
9.5.34
9.5.35
9.5.36
9.5.37
9.5.38
9.5.39
9.5.40
9.5.41
9.5.42
9.5.43
Mode configuration mode setting 1_0
(MODECFG_1_0, address 26h) ...................... 46
Mode configuration mode setting 1_1
(MODECFG_1_1, address 27h) ...................... 47
Mode configuration mode setting 1_2
(MODECFG_1_2, address 28h) ...................... 48
Mode configuration mode setting 1_3
(MODECFG_1_3, address 29h) ...................... 49
Mode configuration mode setting 2_0
(MODECFG_2_0, address 2Ah) ......................50
Mode configuration mode setting 2_1
(MODECFG_2_1, address 2Bh) ......................51
Mode configuration mode setting 2_2
(MODECFG_2_2, address 2Ch) ......................52
Mode configuration mode setting 2_3
(MODECFG_2_3, address 2Dh) ......................52
Mode configuration mode setting 3_0
(MODECFG_3_0, address 2Eh) ......................53
Mode configuration mode setting 3_1
(MODECFG_3_1, address 2Fh) ...................... 54
Mode configuration mode setting 3_2
(MODECFG_3_2, address 30h) ...................... 55
Mode configuration mode setting 3_3
(MODECFG_3_3, address 31h) ...................... 56
Limiting values ..................................................57
ESD ratings ........................................................57
Recommended operating conditions .............. 57
Electrical characteristics ..................................58
Top level parameter .........................................58
Battery charger ................................................ 61
BUCK1 (SW1) ................................................. 64
BUCK2 (SW2) ................................................. 66
LDO1 (Always-On LDO) ..................................67
LDO2 (System LDO) ....................................... 68
I2C Interface and Logic I/O ............................. 69
Package outline .................................................71
Packing information ..........................................74
SOT905-1 HVQFN24; reel dry pack, SMD,
7" Q2 standard product orientation ordering
code (12NC) ending 547 ................................. 74
Dimensions and quantities .............................. 74
Product orientation ...........................................74
Carrier tape dimensions .................................. 74
SOT1401-4 WLCSP25; reel dry pack,
10
11
12
13
13.1
13.2
13.3
13.4
13.5
13.6
13.7
14
15
15.1
15.1.1
15.1.2
15.1.3
15.2
SMD, 7" Q1 standard product orientation
ordering code (12NC) ending 012 ................... 75
Dimensions and quantities .............................. 75
Product orientation ...........................................75
Carrier tape dimensions .................................. 75
Revision history ................................................ 76
Legal information ..............................................77
15.2.1
15.2.2
15.2.3
16
17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 26 January 2021
Document identifier: PCA9420
相关型号：
©2020 ICPDF网 联系我们和版权申明