PCA9504ADGG [NXP]
Glue chip 4; 胶4片
| 型号： | PCA9504ADGG |
| 厂家： | 
NXP |
| 描述： | Glue chip 4 |
| 文件： | 总29页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PCA9504A
Glue chip 4
Product data
2004 May 11
Supersedes data of 2003 Nov 10
Philips
Semiconductors
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
platforms based on Intel processors and chipsets that require
additional external circuitry in order to function properly. It is used on
entry servers/workstations (840 and 860 chipsets), high-end
desktops (820 and 850 chipsets), as well as mid range (815, 830
and 845 chipsets) and low-end (810 chipset) motherboards. Some
of these functionalities include meeting timing specifications,
buffering signals, and switching between power wells.
The PCA9504A Glue Chip 4 integrates miscellaneous motherboard
logic and analog functions into a single, small footprint 56-pin
TSSOP device. The Glue Chip 4 typically resides on the
motherboard close to the I/O controller Hub (ICH) and is optimized
for the Intel 82801BA I/O controller hub (ICH2).
FEATURES
• Dual, Strapping, Selectable Feature Sets
• Audio-disable Circuit
PIN CONFIGURATION
• Mute Audio Circuit
• 5 V reference generation
VREF3IN
V_5P0_STBY
V_3P3_STBY
1
2
3
4
5
6
7
8
9
56 GP3_OUT
55 GP3_IN
• 5 V standby reference generation
• HD single color LED driver
54 STRAP
• IDE reset signal generation/PCIRST# buffers
• PWROK (PWRGD_3V) signal generation
• Power Sequencing / BACKFEED_CUT
• Power Supply turn on circuitry
• RMSRST# generation
53 VCCP_VREF
52 VSYNC_5V
51 HSYNC_5V
50 VSYNC_3V
GPO_FLUSH_CACHE/GP1_IN
A20M/GP1_INB
INIT/GP1_INA
FLUSH_OUT_CPU/GP1_OUT
INIT_OUT/GP2_OUT
CLK_IN
HSYNC_3V
49
48 REF5V_STBY
47 AUD_SHDN
46 MUTE_AUD
45 VREF5IN
• Voltage translation for DDC to VGA monitor
• HSYNCH / VSYNCH voltage translation to VGA monitor
• 3-state buffers for test
SEL_33_66 10
GND 11
PCIRST 12
PCRIST_OUT 13
AUD_EN 14
44 REF5V
• Extra GP Logic gates
43 GND
• Power LED Drivers
AUD_RST 15
42 RSMRST
• Flash FLUSH# / INIT# circuit
IDE_RSTDRV 16
3V_DDCSCL 17
5V_DDCSCL 18
3V_DDCSDA 19
5V_DDCSDA 20
CPU_PRESENT 21
SLP_S3 22
41 TEST_EN
2
• 5 V I C to 3.3 V SMBus conversion to 400 kHz
40 GRN_LED
39 YLW_LED
• Requires both 3.3 V and 5.0 V operating voltages
• 0 to +70 °C operating temperature range
38 YLW_BLNK
37 GRN_BLNK
36 SLP_S5
• ESD protection exceeds 1000 V HBM per JESD22-A114 and
750 V CDM per JESD22-C101
35 SCK_BJT_GATE
34 PWRGD_3V
33 FPRST
• Latch-up testing is done to JEDEC Standard JESD78 which
PS_ON 23
exceeds 100 mA
HD_LED 24
• Package offered: TSSOP56
PRIMARY_HD 25
SCSI 26
32 PWRGD_PS
31 FLUSH_OUT_FWH
30 LATCHED_BACKFED_CUT
29 GND
DESCRIPTION
SECONDARY_HD 27
BACKFEED_CUT 28
The PCA9504A Glue Chip 4 is a highly integrated and cost-efficient
custom ASIC that reduces logic part count, overall component cost,
and board space requirements for PC designers and manufacturers.
The Glue Chip 4 supports the latest generation of high-volume
SW00578
ORDERING INFORMATION
PACKAGE
TEMPERATURE RANGE
ORDER CODE
TOPSIDE MARK
PCA9504ADGG
DRAWING NUMBER
56-Pin Plastic TSSOP
0 °C to +70 °C
PCA9504ADGG
SOT364-1
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
2
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
PIN DESCRIPTION
PIN(S)
SYMBOL
FUNCTION
1
3I
VREF3IN
3.3 V input
2
P
V_5P0_STBY
V_3P3_STBY
5 V system standby power supply
3
P
3 V system standby power supply
4
3IU
GPO_FLUSH_CACHE / GP2_IN
A20M / GP1_INB
INIT / GP1_INA
FLUSH_OUT_CPU / GP1_OUT
INIT_OUT / GP2_OUT
CLK_IN
GPO from SIO / ICH2 / Buffer 2 input
A20M signal from ICH2 / NAND 1 input B
INIT signal from the ICH2 / Buffer 1 input A
5
REF
REF
5V OD
5V OD
3I
6
7
Open drain signal, goes to the CPU / NAND 1 output
Delayed INIT signal into the CPU / Buffer 2 output
Either 33MHz or 66MHz clock, based on SEL_33_66 pin
Strapping option for 33MHz or 66MHz CLK_IN
Ground
8
9
10
11, 29, 43
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
30
31
32
33
34
35
36
37
38
39
40
41
42
44
45
46
47
48
49
3IU
SEL_33_66
G
GND
3I
PCRIST
PCI reset signal
3O
PCRIST_OUT
AUD_EN
Copy of PCRIST, increased drive-strength
Audio enable input (GPO from ICH2 / SIO)
Audio reset output
3IU
3O
AUD_RST
5O
IDE_RSTDRV
3V_DDCSCL
5V_DDCSCL
3V_DDCSDA
5V_DDCSDA
CPU_PRESENT
SLP_S3
IDE reset output, 5 V push/pull
3IOD
5IOD
3IOD
5IOD
3IU
DDCSCL input/output 3.3 V side
DDCSCL input/output 5 V side
DDCSDA input/output 3.3 V side
DDCSDA input/output 5 V side
CPU present signal from the processor
Signal from ICH2 for transitioning to the S3 power state
Power supply turn-on signal
3I
5V OD
5V OD
5IU
PS_ON
HD_LED
Hard drive front panel LED output
IDE primary drive active input
PRIMARY_HD
SCSI
5IU
SCSI drive active input
5IU
SECONDARY_HD
BACKFEED_CUT
LATCHED_BACKFEED_CUT
FLUSH_OUT_FWH
PWRGD_PS
FPRST
IDE secondary drive active input
Signal used for STR circuitry
5V OD
5O
Signal used for STR circuitry
5V OD
5IU
Open drain signal, goes to the FWH
Power good signal from power supply
Reset signal from the front panel
3.3 V power good output
5IU
3O
PWRGD_3V
SCK_BJT_GATE
SLP_S5
5V OD
3I
Gate signal from the SCK BJT in suspend to RAM
Signal from the ICH2 for transitioning to the S5 power state
Power LED input, from SIO GPIO
Power LED input, from SIO GPIO
Power LED output
3IU
GRN_BLNK
3IU
YLW_BLNK
5V OD
5V OD
5ID
YLW_LED
GRN_LED
Power LED output
TEST_EN
Test enable, 100K internal pull-down to GND
Reset for the ICH2 resume well
3O
RSMRST
AO
REF5V
Highest system supply reference voltage
5V system primary supply input
5I
VREF5IN
3IU
MUTE_AUD
AUD_SHDN
REF5V_STBY
HSYNC_3V
Signal from SIO to mute audio on power up/down
Signal to audio amp to signal shutdown
Highest system standby voltage
HSYNCH input from chipset video
5O
AO
3I
3
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
PIN DESCRIPTION CONTINUED
PIN(S)
SYMBOL
FUNCTION
VSYNCH input from chipset video
50
51
52
53
3I
VSYNC_3V
HSYNC_5V
VSYNC_5V
5O
5O
AI
HSYNCH output to monitor
VSYNCH output to monitor
V
CCP
_VREF
Analog voltage reference for determining INIT/A20M input thresh-
olds
54
3IV/3O
STRAP
Strapping option for GP or FLUSH mode (internal pull-up resistor)
Note 1
55
5I
GP3_IN
Generic logic gate 3 input
Generic logic gate 3 output
56
5V OD
GP3_OUT
NOTE:
1. The pin is internally pulled up to default to FLUSH mode.
TYPE DESCRIPTION
3I
3.3 V input signal
3IU
5I
3.3 V input signal with internal pull-up
5 V input signal
5IU
5ID
P
5 V input signal with internal pull-up
5 V input signal with internal pull-down
Power (input)
G
Ground (input)
3O
3.3 V output signal
5O
5 V output signal
3V OD
5V OD
AO
3.3 V open-drain output signal
5 v open-drain output signal
Analog output
AI
Analog input
3IOD
5IOD
REFL
3.3 V input/output open-drain
5 V input/output open-drain
Input voltage levels referenced to V
_VREF
CCP
FUNCTION TABLES
Strapping Selection Pin
1
1
STRAP (pin 54)
MODE
PIN NAME & (PIN NUMBER)
1 No connect
1 No connect
1 No connect
1 No connect
1 No connect
0 GND
FLUSH
FLUSH
FLUSH
FLUSH
FLUSH
GP
GPO_FLUSH_CACHE (4)
A20M (5)
INIT (6)
FLUSH_OUT_CPU (7)
INIT_OUT (8)
GP2_IN (4)
0 GND
GP
GP1_INB (5)
GP1_INA (6)
GP1_OUT (7)
GP2_OUT (8)
0 GND
GP
0 GND
GP
0 GND
GP
NOTE:
1. The pin is internally pulled up to default to FLUSH mode.
4
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
TYPICAL APPLICATION
GLUE 4 INPUTS
PIN
1
2
FUNCTION
VREF3IN
5VSB
3
4
5
6
3VSB
GP2_IN
GP1_INB
GP1_INA
CLK_IN
V_3P3_STBY
VCC
VCC 3
IN
9
10
12
14
17
18
19
20
21
22
25
26
27
32
33
36
37
38
41
45
46
49
50
53
54
55
SEL_33_66
PCIRST*
AUD_EN
3V_DDCSCL
5V_DDCSCL
3V_DDCSD
5V_DDCSD
CPU_PRESENT*
SLP_S3*
PRIMAR Y_HD*
SC5I*
1 kΩ
10 kΩ
10 kΩ
A
A
GLUE CHIP 4
IN
GPO_FLUSH_CACHE_PU*
H_INIT_PU*
4
6
GPO_FLUSH_CACHE/GP2–IN
VREF5IN
VREF3IN
45
1
GLUE4_VREF5IN_R
GLUE4_VREF5IN_R
V_5P0_STBY
V_3P3_STBY
V_REF5V
IN
IN
IN
INIT/GP1_INA
PCIRST
V_3P3_STBY
SECOND AR Y_HD*
PWRGD_PS
FPRST*
IN
P_PCIRST*
12
17
8
V_5P0_STBY
2
TP_GLUE4_DDCSOL_3V
CK_66M_GLUE
CPU_PRESENT*
IDE_PRI_ACT*
NC
3V_DDC5CL
CLK_IN
V_3P3_STBY
3
SLP_S5*
GRN_BLNK
YL W_BLNK
TEST_EN
REF5V
44
24
OUT
IN
IN
IN
21
25
26
27
14
47
41
10
CPU_PRESENT
PRIMAR Y_HD
SCSI
HD_LED
HD_LED*
OUT
OUT
VREF5IN
PCIRST_OUT
13 P_RST_SLO TS_R*
MUTE_A UD*
HSYNCH_3V
VSYNCH_3V
VCCP_VREF
STRAP
AUD_RST
15
46
35
31
7
TP_A UD_RST*
IDE_SEC_ACT*
GPIO_A UD_EN
NC
SECOND ARY_HD
AUD_EN
MUTE_A UD
MUTE_A UD_PNI*
IN
IN
IN
SCK_BJT_GA TE
FLUSH_OUT_FWH
FLUSH_OUT_CPU/GP1_OUT
INIT_OUT/GP2_OUT
TP–SCK–BJT_GA TE_ENABLE
TP_GLUE4_FLUSH_OUT_FWH
TP_GLUE4_GP1_OUT
TP_GLUE4_8
GP3_IN
AUD_SHDN
TEST_EN
TP_GLUE4_TESTEN_41
GLUE4_SEL_33_66_R
SEL_33–66
8
TP_GLUE4_DDCSD A_5V 20
PWRGD_PS 32
TP_GLUE4_DDCSD A_3V 19
5V_DDCSD
PWRGD_PS
3V_DDC5D
FPRST
A
A
IDE_RSTDR V
16
28
30
34
23
42
39
40
51
52
54
56
11
29
43
IDE_RST*
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BACKFEED_OUT
LATCHED_BACKFEED_OUT
PWRGD–3V
PS_ON
BACKFEED_CUT
IN
IN
VREG_BACKFEED_U4
PWRGD_3V
GLUE_FP_RST_R*
TP_GLUE4_DDCSCL_5V
SLP_S5*
33
18
36
22
37
38
49
50
5
5V_DDCSCL
SLP_55
PS_ON*
1 kΩ
RSMRST
RSMRST*
IN
IN
IN
IN
SLP_S3*
SLP_S3
YLW_LED
GPIO_YL W_BLNK_HDR
GPIO_GRN_BLNK_HDR
TP_GLUE4_HSYNC5V
TP_GLUE4_VSYNC5V
GLUE4_STRAP
GPIO_GRN_BLNK
GPIO_YL W_BLNK
TP_GLUE4_HSYNC3V
TP_GLUE4_VSYNC3V
AUD_MIDI_OUT_B_PU
V5REF_SUS
GRN_BLNK
YLW_BLNK
HSYNC_3V
VSYNC_3V
GRN_LED
HSYNC_5V
VSYNC_5V
STRAP
A20M/GP1_INB
REF5V_STBY
VCCP_VREF
GP3_IN
GP3_OUT
PWRGD_PS_BUFF
IN
OUT
48
53
55
GND
V_383_STBY
OUT
VCCP_VREF
GND
IN
GND
100 Ω
PWRGD_PS HAS WEAK
INTERNAL PULL–UP
IC
49.9 kΩ
10 kΩ
SW01083
Figure 1. Typical application
5
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
1
ABSOLUTE MAXIMUM RATINGS
LIMITS
SYMBOL
PARAMETER
CONDITION
UNIT
MIN
MAX
V_5P0_STBY
V_3P3_STBY
DC 5.0V supply
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
+6.0
V
DC 3.3V supply
+6.0
V
V
V
V
V
DC input voltage (5 V pins)
Output voltage range (5 V pins)
DC input voltage (3.3 V pins)
Output voltage range (3.3 V pins)
Supply power dissipation
Static Discharge voltage
Note 2
V_5P0_STBY+0.5
V_5P0_STBY+0.5
V_3P3_STBY+0.5
V_3P3_STBY+0.5
100
V
I (5V)
Note 2
Note 2
Note 2
V
O (5V)
I (3.3V)
O (3.3V)
V
V
SPD
ESD
MW
V
2000
–55
0
T
T
Storage temperature range
Operating Temperature Range
+150
70
°C
°C
STG
OTR
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other condition beyond those indicated under “recommended operating condition” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage rating may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
MAX
3.6
5.25
V
DC 3.3 V supply voltage
3.0
V
DD3
DDL
I
V
V
DC 2.5 V supply voltage
DC input voltage
4.75
0
V
V
V
DD3
V
V
DDL
V
DC output voltage
0
0
V
O
DD3
T
A
Operating ambient temperature range in free air
+70
°C
6
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
DC CHARACTERISTICS
V_5P0_STBY = 5 V ± 5%; V_3P3_STBY = 3.3 V ± 10%
LIMITS
= 0 °C to +70 °C
TYP
T
amb
SYMBOL
STRAP
PARAMETER
TEST CONDITION
UNIT
MIN
MAX
V
V
HIGH-level input voltage
LOW-level input voltage
Input leakage HIGH
2.0
–1
V
IH
IL
0.8
1
V
I
IH
µA
V
V
V
LOW-level output voltage
HIGH-level output voltage
Input leakage LOW
I
I
= 6 mA
0.4
OL
OL
= –3 mA
2.4
V
OH
OH
I
IL
–88
–26
µA
AUD_EN
V
V
HIGH-level input voltage
LOW-level input voltage
Input leakage LOW
2.0
V
IH
IL
0.8
–26
1
V
I
IL
IH
V
IL
= 0 V
–88
–1
µA
µA
I
Input leakage HIGH
PCIRST
V
V
HIGH-level input voltage
LOW-level input voltage
Input leakage
2.2
V
IH
IL
0.8
1
V
I
L
–1
µA
mV
Hys
Input hysteresis
400
MUTE_AUD
V
V
HIGH-level input voltage
LOW-level input voltage
Input leakage HIGH
2.2
V
IH
IL
0.8
1
V
I
IH
I
IL
–1
µA
µA
Input leakage LOW
V
IL
= 0 V
–88
–26
VREF5IN
0.85*V5P
0_STBY
V
V
HIGH-level input voltage
V
IH
0.2*V5P
0_STBY
LOW-level input voltage
Input leakage
V
IL
I
L
–1
2.2
–1
1
µA
VREF3IN
V
IH
V
IL
HIGH-level input voltage
LOW-level input voltage
Input leakage
V
0.8
1
V
I
L
µA
PRIMARY_HD
V
V
HIGH-level input voltage
LOW-level input voltage
Input hysteresis
0.7*5VSB
V
IH
IL
0.2*5VSB
V
Hys
400
–88
–1
mV
µA
µA
I
I
Input leakage LOW
Input leakage HIGH
V
V
= 0 V
–26
1
IL
IL
= 5VSB
IH
IH
SECONDARY_HD
V
V
HIGH-level input voltage
LOW-level input voltage
Input hysteresis
0.7*5VSB
V
IH
IL
0.2*5VSB
–26
V
Hys
400
–88
mV
µA
I
IL
Input leakage LOW
V
IL
= 0 V
7
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
T
amb
= 0 °C to +70 °C
UNIT
MIN
TYP
MAX
I
IH
Input leakage HIGH
V
IH
= 5VSB
–1
1
µA
SCSI
V
V
HIGH-level input voltage
LOW-level input voltage
Input hysteresis
0.7*5VSB
V
IH
IL
0.2*5VSB
V
Hys
400
–88
–1
mV
µA
µA
I
I
Input leakage LOW
Input leakage HIGH
V
V
= 0 V
–26
1
IL
IL
= 5VSB
IH
IH
FPRST
V
V
HIGH-level input voltage
LOW-level input voltage
Input hysteresis
0.7*5VSB
V
IH
IL
0.2*5VSB
V
Hys
400
–88
–1
mV
µA
µA
I
I
Input leakage LOW
Input leakage HIGH
V
V
= 0 V
–26
1
IL
IL
= 5VSB
IH
IH
PWRGD_PS
V
V
HIGH-level input voltage
LOW-level input voltage
Input hysteresis
0.7*5VSB
V
IH
IL
0.2*5VSB
V
Hys
400
–88
–1
mV
µA
µA
I
I
Input leakage LOW
Input leakage HIGH
V
V
= 0 V
–26
1
IL
IL
= 5VSB
IH
IH
GPO_FLUSH_CACHE/GP2_IN
V
V
HIGH-level input voltage
LOW-level input voltage
Input leakage
2.2
V
IH
IL
0.8
–26
1
V
I
I
V
V
= 0 V
= 5 V
–88
–1
µA
µA
L
IL
Input leakage
IH
IH
INIT / GP1_INA (GP Mode)
V
HIGH-level input voltage
LOW-level input voltage
Input leakage
Part is strapped for GP
mode
2.4
V
IH
V
IL
Part is strapped for GP
mode
0.8
1
V
I
L
Part is strapped for GP
mode
–1
µA
V
VCCP_V
Bias voltage
GP mode
1.95
2.1
ref
INIT / GP1_INA (Flush Mode)
V
HIGH-level input voltage
LOW-level input voltage
Input leakage
FLUSH mode
FLUSH mode
FLUSH mode
FLUSH mode
1.5
V
IH
IL
V
0.4
1
V
I
IL
–1
µA
V
VCCP_V
Bias voltage
0.95
1.1
ref
8
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
LIMITS
= 0 °C to +70 °C
TYP
SYMBOL
PARAMETER
TEST CONDITION
T
amb
UNIT
MIN
MAX
A20M / GP1_INB
V
V
HIGH-level input voltage
LOW-level input voltage
Input leakage
FLUSH mode
FLUSH mode
FLUSH mode
FLUSH mode
GP mode
1.5
V
IH
IL
0.4
1
V
I
IL
–1
µA
V
VCCP_V
Bias voltage
0.95
2.4
1.1
ref
V
IH
V
IL
HIGH-level input voltage
LOW-level input voltage
Input leakage
V
GP mode
0.8
1
V
I
L
GP mode
–1
µA
V
VCCP_V
Bias voltage
GP mode
1.95
2.1
ref
CLK_IN
V
V
HIGH-level input voltage
LOW-level input voltage
Input hysteresis
2.2
V
IH
IL
0.8
1
V
Hys
250
–1
mV
µA
I
L
Input leakage
SEL_33_66
V
V
HIGH-level input voltage
LOW-level input voltage
Input hysteresis
2.0
V
IH
IL
0.8
V
Hys
400
–1
mV
µA
µA
I
IH
I
IL
Input leakage
1
Input leakage
V
IL
= 0 V
–88
–26
SLP_S3
V
V
HIGH-level input voltage
LOW-level input voltage
Input hysteresis
2.2
V
IH
IL
0.8
1
V
Hys
400
–1
mV
µA
I
L
Input leakage
SLP_S5
V
HIGH-level input voltage
LOW-level input voltage
Input hysteresis
2.2
V
IH
IL
V
0.8
1
V
Hys
400
–1
mV
µA
I
L
Input leakage
CPU_PRESENT
V
V
HIGH-level input voltage
LOW-level input voltage
Input hysteresis
2.0
V
IH
IL
0.8
V
Hys
400
–1
mV
µA
µA
I
IH
I
IL
Input leakage
V
V
= 3VSB
= 0 V
1
IH
Input leakage
–88
–26
IL
TEST_EN
V
V
HIGH-level input voltage
LOW-level input voltage
Input hysteresis
0.7*5VSB
V
IH
IL
0.2*5VSB
V
Hys
400
–1
mV
µA
µA
I
Input leakage
V
V
= 0 V
1
IH
IL
IL
I
Input leakage
= 5VSB
20
88
IH
9
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
LIMITS
= 0 °C to +70 °C
TYP
SYMBOL
PARAMETER
TEST CONDITION
T
amb
UNIT
MIN
MAX
HSYNC_3V
V
V
HIGH-level input voltage
LOW-level input voltage
Input leakage
2.2
–1
V
IH
IL
0.8
1
V
I
L
µA
VSYNC_3V
V
V
HIGH-level input voltage
LOW-level input voltage
Input leakage
2.2
–1
V
IH
IL
0.8
1
V
I
L
µA
GRN_BLNK
V
V
HIGH-level input voltage
LOW-level input voltage
Input leakage
2.2
V
IH
IL
0.8
1
V
I
IH
I
IL
–1
µA
µA
Input leakage
V
V
= 0 V
–88
–26
IL
YLW_BLNK
V
IH
V
IL
HIGH-level input voltage
LOW-level input voltage
Input leakage
2.0
V
0.8
1
V
I
IH
I
IL
–1
µA
µA
Input leakage
= 0 V
–88
–26
IL
GP3_IN
V
HIGH-level input voltage
LOW-level input voltage
Input leakage
2.2
–1
V
IH
IL
V
0.8
1
V
I
L
µA
AUD_RST
V
V
LOW-level output voltage
HIGH-level output voltage
Off state output current
I
I
= 6 mA
0.4
1
V
OL
OL
= –3 mA
2.4
–1
V
OH
OH
I
µA
OZ
AUD_SHDN
V
V
LOW-level output voltage
HIGH-level output voltage
Off state output current
I
I
= 6 mA
0.4
1
V
OL
OL
= –6 mA
2.4
–1
V
OH
OH
I
µA
OZ
REF5V
V
V
LOW-level output voltage
HIGH-level output voltage
Off state output current
V
V
> 1.5 V
V
V
– 0.05
– 0.05
V
V
+ 0.05
+ 0.05
V
OUT5
OUT3
OUTL
REF5in
REF5in
REF5in
> 1.5 V
V
REF3in
REF3in
REF3in
I
–20
20
µA
REF5V_STBY
V
LOW-level output voltage
HIGH-level output voltage
Off state output current
V_5P0_STBY > 1.5 V
V_5P0_STBY > 1.5 V
V_5P0_STBY – 0.05
V_5P0_STBY – 0.05
–20
V_5P0_STBY + 0.05
V_5P0_STBY + 0.05
20
V
OUT5
OUT3
OUTL
V
V
I
µA
HD_LED
V
LOW-level output voltage
Off state output current
I
OL
= 12 mA
0.4
1
V
OL
I
–1
µA
OZ
10
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
LIMITS
= 0 °C to +70 °C
TYP
SYMBOL
PARAMETER
TEST CONDITION
T
amb
UNIT
MIN
MAX
IDE_RSTDRV
V
V
LOW-level output voltage
HIGH-level output voltage
Off state output current
I
I
= 6 mA
0.4
1
V
OL
OL
= –6 mA
2.4
–1
V
OH
OH
I
µA
OZ
PCIRST_OUT
V
V
LOW-level output voltage
HIGH-level output voltage
Off state output current
I
I
= 6 mA
0.4
1
V
OL
OL
= –3 mA
2.4
–1
V
OH
OH
I
µA
OZ
PRWGD_3V
V
V
LOW-level output voltage
HIGH-level output voltage
Off state output current
I
I
= 6 mA
0.4
1
V
OL
OL
= –3 mA
2.4
–1
V
OH
OH
I
µA
OZ
INIT_OUT / GP2_OUT
V
LOW-level output voltage
Off state output current
I
OL
I
OL
I
OL
I
OL
= 12 mA
= 12 mA
= 6 mA
= 6 mA
0.4
1
V
OL
I
–1
–1
–1
–1
µA
OZ
FLUSH_OUT_CPU / GP1_OUT
V
OL
LOW-level output voltage
Off state output current
0.4
1
V
I
µA
OZ
BACKFEED_CUT
V
OL
LOW-level output voltage
Off state output current
0.4
1
V
I
µA
OZ
FLUSH_OUT_FWH
V
OL
LOW-level output voltage
Off state output current
0.4
1
V
I
µA
OZ
LATCHED_BACKFEED_CUT
V
V
LOW-level output voltage
HIGH-level output voltage
Off state output current
I
I
= 6 mA
0.4
1
V
OL
OL
= –6 mA
2.4
–1
V
OH
OH
I
µA
OZ
PS_ON
V
LOW-level output voltage
Off state output current
I
OL
= 6 mA
0.4
1
V
OL
I
–1
µA
OZ
RSMRST
V
V
LOW-level output voltage
HIGH-level output voltage
Off state output current
5VSB LOW trip voltage
I
I
= 6 mA
0.4
V
OL
OL
= –3 mA
2.4
–1
V
OH
OH
I
1
µA
V
OZ
VTRIP
SCK_BJT_GATE
1.8
3.5
V
LOW-level output voltage
Off state output current
I
OL
= 6 mA
0.4
1
V
OL
I
–1
µA
OZ
11
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
LIMITS
= 0 °C to +70 °C
TYP
SYMBOL
PARAMETER
TEST CONDITION
T
amb
UNIT
MIN
MAX
3V_DDCSDA
V
LOW-level output voltage
Input leakage
I
= 6 mA
0.4
2.5
1
V
OL
OL
I
I
5V_DDCSDA = V
–1
–1
µA
µA
H
DD
DD
DD
DD
Off state output current
OZ
5V_DDCSDA
V
OL
LOW-level output voltage
Input leakage
I
OL
= 6 mA
0.4
2.5
1
V
I
I
3V_DDCSDA = V
–1
–1
µA
µA
H
Off state output current
OZ
3V_DDCSCL
V
OL
LOW-level output voltage
Input leakage
I
OL
= 6 mA
0.4
2.5
1
V
I
I
5V_DDCSCL = V
–1
–1
µA
µA
H
Off state output current
OZ
5V_DDCSCL
V
OL
LOW-level output voltage
Input leakage
I
OL
= 6 mA
0.4
2.5
1
V
I
I
3V_DDCSCL = V
–1
–1
µA
µA
H
Off state output current
OZ
HSYNC_5V
V
V
LOW-level output voltage
HIGH-level output voltage
Off state output current
I
I
= 6 mA
0.4
1
V
OL
OL
= –6 mA
3.8
–1
V
OH
OH
I
µA
OZ
VSYNC_5V
V
V
LOW-level output voltage
HIGH-level output voltage
Off state output current
I
I
= 6 mA
0.4
1
V
OL
OL
= –6 mA
3.8
–1
V
OH
OH
I
µA
OZ
GRN_LED / YLW_LED
V
LOW-level output voltage
Off state output current
I
OL
I
OL
= 24 mA
= 6 mA
0.4
1
V
OL
I
–1
–1
µA
OZ
GP3_OUT
V
OL
LOW-level output voltage
Off state output current
I
1
µA
OZ
12
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
AC CHARACTERISTICS
V
CC1
= 3.3 V; V = 5.0 V
CC
LIMITS
= 0 _C to +70 _C
TYP
T
amb
SYMBOL
PARAMETER
UNITS
NOTES
MIN
MAX
100
t
RSMRST
RSMRST
4.0
ms
ns
RESET
t
100
RESET_FALL
Propagation Delay
AUD_EN to AUD_RST
PCIRST to AUD_RST
PCIRST to IDE_RSTDRV
PCIRST to PCIRST_OUT
t
/t
1.0
11.0
ns
PHL PLH
Propagation Delay
MUTE_AUD to MUTE_SHDN
t
t
/t
2.5
4.5
6.0
ns
ns
PLH PHL
Propagation Delay
PWRGD_PS to PWRGD_3V
FPRST to PWRGD_3V
/t
11.0
PLH PHL
Propagation Delay
HSYNC_3V to HSYNC_5V
VSYNC_3V to VSYNC_5V
t
t
/t
2.0
1.0
5.0
6.0
ns
ns
PLH PHL
Propagation Delay
PWRGD_PS to SCK_BJT_GATE
FPRST to SCK_BJT_GATE
/t
PLH PHL
Open Drain Prop Delay
PRIMARY_HD to HD_LED
PRIMARY_HD to HD_LED
PRIMARY_HD to HD_LED
t
/t
1.0
3.0
5.0
ns
ns
PLZ PZL
Open Drain Prop Delay
GP1_INA to GP1_OUT
GP2_INA to GP1_OUT
t
/t
25.0
PLZ PZL
Open Drain Prop Delay
GP2_IN to GP2_OUT
t
t
/t
3.0
1.0
7.0
4.0
ns
ns
PLZ PZL
Open Drain Prop Delay
GP3_IN to GP3_OUT
/t
PLZ PZL
Open Drain Prop Delay
SLP_S3 to BACKFEED_OUT
PRWGD_PS to BACKFEED_OUT
t
/t
1.0
6.0
ns
PLZ PZL
Open Drain Prop Delay
CPU_PRESENT to PS_ON
t
t
/t
2.0
2.0
10.0
10.0
ns
ns
PLZ PZL
Open Drain Prop Delay
SLP_S3 to PS_ON
/t
PLZ PZL
Open Drain Prop Delay
BACKFEED_OUT to
LATCHED_BACKFEED_OUT
t
t
t
/t
2.0
1.0
11.0
5.0
ns
ns
ns
PLZ PZL
Open Drain Prop Delay
SLP_S5 to YLW_LED
SLP_S5 to GRN_LED
YLW_BLNK to YLW_LED
GRN_BLNK to GRN_LED
/t
PLZ PZL
Open Drain Prop Delay
3V_DDOSDA to 5V_DDOSDA
3V_DDOSDA to 5V_DDOSDA
/t
1.0
3.5
5.0
PLZ PZL
Rise and Fall Times
HSYNC_5V
t , t
r
ns
f
f
VSYNC_5V
Rise and Fall Times
LATCHED_BACKFEED_OUT
t , t
r
1.0
µs
13
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
WAVEFORMS
V
IH
INPUT
INPUT
V
V
M
V
M
V
M
M
V
V
t
t
IL
PHL
PLH
t
t
PHL
PLH
V
V
OH
M
M
OUTPUT
V
V
M
OUTPUT
M
V
OL
SF01443
SW00720
Waveform 3.
Waveform 1.
V
I
V
DD
INPUT
GND
V
M
V
I
INPUT
GND
V
M
t
t
PZL
PLZ
V
DD
OUTPUT
LOW-to-OFF
OFF-to-LOW
t
t
PZL
PLZ
V
M
V
DD
V
X
V
OUTPUT
LOW-to-OFF
OFF-to-LOW
OL
V
M
t
V
X
t
PHZ
PZH
V
OL
SW00721
t
t
PHZ
PZH
Waveform 4.
SW00722
Waveform 2.
14
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
5V REFERENCE GENERATION
Supply
REF5V
VREF5IN < VREF3IN
VREF5IN > VREF3IN
VREF3IN
VREF5IN
3.3 V
VREF3IN
5 V
VREF5IN
5 V
3.3 V
REF5V
SW00580
Figure 1. REF5V when VREF3IN ramps before VREF5IN
3.3 V
VREF3IN
5 V
VREF5IN
5 V
REF5V
SW00581
Figure 2. REF5V when VREF5IN ramps before VREF3IN
15
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
5V STANDBY REFERENCE GENERATION
Standby Supply
REF5V_STBY
V_5PO_STBYtV_3P3_STBY
V_5PO_STBYuV_3P3_STBY
V_3P3_STBY
V_5PO_STBY
3.3 V
V_3P3_STBY
5 V
V_5P0_STBY
5 V
3.3 V
REF5V_STBY
SW00582
Figure 3. REF5V_STBY when V_3P3_STBY ramps before V_5PO_STBY
V_3P3_STBY
V_5P0_STBY
REF5V_STBY
SW00583
Figure 4. REF5V_STBY when V_5PO_STBY ramps before V_3P3_STBY
16
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
FLUSH OUT* / INIT OUT* CIRCUIT
V_VCCP
VCC3
1 kΩ
1 kΩ
1 kΩ
H_INIT_OUT*
ICH_A20M*
ICH_INIT*
CPU
H_FLUSH_OUT_CPU*
GLUE CHIP
H_FLUSH_OUT_FWH*
GPO_FLUSH_CACHE*
FWH
50 Ω
VCCP
VCCP_VREF
100 Ω
1 µF
SW00584
Figure 5. Block diagram for FLUSH_OUT*/INIT_OUT* circuit
Case
A20M*
GPO FLUSH
INIT*
FLUSH OUT
CPU*
FLUSH OUT
FWH*
INIT OUT*
CACHE*
falling edge
falling edge
1
1
2
3
4
5
6
1
1
X
X
0
0
0
1
0
1
1
0
0 (for t1)
0 (for t1)
Hi-Z
0 (for t1)
0 (for t1)
Hi-Z
0, Hi-Z, then 0 (delayed by t1-t, then active for 2*t)
Hi-Z, 0 (delayed by t1-t, then active for 2*t)
0
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
falling edge
falling edge
Hi-Z
Hi-Z
Hi-Z
Hi-Z
NOTE:
1. Nominal value timings with tolerances are listed in the DC Characteristics table for t and t1. All Hi-Z outputs are shown as 1’s or HIGH in the
following diagrams.
17
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
A20M*
GPO_FLUSH_CACHE*
INIT*
t1
t1
FLUSH_OUT_CPU*
FLUSH_OUT_FWH*
t
t
INIT_OUT*
SW00585
Figure 6. Waveforms for Case 1
A20M*
GPO_FLUSH_CACHE*
INIT*
t1
t1
FLUSH_OUT_CPU*
FLUSH_OUT_FWH*
t
t
INIT_OUT*
SW00586
Figure 7. Waveforms for Case 2
18
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
A20M*
GPO_FLUSH_CACHE*
INIT*
FLUSH_OUT_CPU*
FLUSH_OUT_FWH*
INIT_OUT*
SW00587
Figure 8. Waveforms for Case 3
A20M*
GPO_FLUSH_CACHE*
INIT*
FLUSH_OUT_CPU*
FLUSH_OUT_FWH*
INIT_OUT*
SW00588
Figure 9. Waveforms for Case 4
19
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
A20M*
GPO_FLUSH_CACHE*
INIT*
FLUSH_OUT_CPU*
FLUSH_OUT_FWH*
INIT_OUT*
SW00589
Figure 10. Waveforms for Case 5
A20M*
GPO_FLUSH_CACHE*
INIT*
FLUSH_OUT_CPU*
FLUSH_OUT_FWH*
INIT_OUT*
SW00590
Figure 11. Waveforms for Case 6
20
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
A20M*
GPO_FLUSH_CACHE*
t1
INIT*
t1
t1
FLUSH_OUT_CPU*
FLUSH_OUT_FWH*
INIT_OUT*
t
t
t
SW00591
Figure 12. Waveforms for Case 7
A20M*
GPO_FLUSH_CACHE*
INIT*
t1
t1
FLUSH_OUT_CPU*
FLUSH_OUT_FWH*
t
t
INIT_OUT*
SW00592
Figure 13. Waveforms for boundary GPO_FLUSH_CACHE* Case
• Timings should remain the same for both a 66 MHz or 33 MHz
GPO_FLUSH_CACHE* – input to logic, GPO from the ICH2,
programmed active LOW.
CLK_IN input.
• The boundary condition for INIT listed above, is a special case
where immediately following the FLUSH_OUT*, INIT_OUT* cycle,
the ICH2 asserts INIT* into the Glue Chip.
INIT* – input to logic, INIT* signal from the ICH2.
A20M* – input to logic, A20M* signal from the ICH2.
FLUSH_OUT_CPU* – output of logic, route to CPU FLUSH* pin.
FLUSH_OUT_CPU* – output of logic, routed to FWH INIT* pin.
INIT_OUT* – output of logic, routed to CPU INIT* pin.
• The boundary condition for GPO_FLUSH_CACHE* listed above,
is a special case where immediately following the first assertion of
GPO_FLUSH_CACHE*, the GPO is de-asserted, then re-asserted
again before the timings have had a chance to complete.
NOTE:
1. Nominal timing values with tolerances are listed in the DC
Characteristics table.
21
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
T1
BACKFEED_CUT*
SLP_S5*
T2
LATCHED_BACKFEED_CUT
SW00593
Figure 14. Power up signal sequencing
Power up signal sequencing is shown in Figure 14. BACKFEED_CUT* is following the power rail up to its final value.
LATCHED_BACKFEED_CUT should stay LOW, never turning on. SLP_S5* goes to its HIGH value when the power rails have stabilized,
X25 msec after power on. BACKFEED_CUT* is pulled LOW a period T1 after SLP_S5* goes HIGH. T1 can be as short as 1msec. Typical
measured values are X200 msec. T1 and T2 are guaranteed by the inherent design of the system and are not controlled by Glue Chip.
SLP_S5*
Tpropr
Tpropf
BACKFEED_CUT*
Tf
Tr
LATCHED_BACKFEED_CUT
SW00594
Figure 15. 1st sequence timing
The first possible sequence is with SLP_S5*staying HIGH and BACKFEED_CUT* transitioning from LOW to HIGH, remaining HIGH for an
undetermined period and then going back to LOW and the system is back at the end of the power-up sequence. The power-up sequence is
shown in Figure 15. During these BACKFEED_CUT* transitions, the propagation delays, rise and fall times, and going into regulation times
LATCHED_BACKFEED_CUT are as described in Figure 16. The first sequence starts can start at the end of the power-up sequence at any time.
T4
T3
BACKFEED_CUT*
SLP_S5*
Tpropr
Tpropf
LATCHED_BACKFEED_CUT
Tr
Tf
SW00595
Figure 16. 2nd sequence timing
Signal sequencing for the second possible sequence is shown in Figure 16. BACKFEED_CUT* goes from LOW to HIGH and SLP_S5* goes
from HIGH to LOW, 30 µsec to 65 µsec (T3) later. LATCHED_BACKFEED_CUT goes HIGH when BACKFEED_CUT* goes HIGH and then
LATCHED_BACKFEED_CUT returns to LOW when SLP_S5* goes LOW. BACKFEED_CUT* stays HIGH and SLP_S5* stays LOW for an
indeterminate time and then SLP_S5* will go HIGH. A minimum of 1msec (T4) later, BACKFEED_CUT* will go LOW and the system is back at
the end of the power-up sequence. Typical measured values of T4 are X250 msec. During all transitions, the propagation delays, rise and fall
times, and going into regulation times for LATCHED_BACKFEED_CUT are as described in Figure 16. The first sequence starts can start at the
end of the power-up sequence at any time.
22
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
RSMRST* GENERATION
RSMRST* is a delayed 3.3 V hysteresis copy of V_5PO_STBY. RSMRST* is delayed going inactive from the rising edge of V_5PO_STBY by
32 ms, nominal. This delay starts when V_5PO_STBY hits the trip point. There is minimal delay on the falling edge.
max
V
TRIP
min
V_5P0_STBY
t
reset
RSMRST*
SW00596
Figure 17. Resume reset functionality
V_5P0_STBY
t
RESET
t
RESET_FALL
RSMRST*
SW00597
Figure 18. Resume reset functionality during brown out
23
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
AUDIO-DISABLE
AUD_EN
PCIRST
AUD_RST
0
0
1
1
0
1
0
1
0
0
0
1
MUTE AUDIO CIRCUIT
MUTE_AUD
AUD_SHDN
0
1
1
0
HD SINGLE COLOR LED DRIVER
PRIMARY_HD
SECONDARY_HD
SCSI
HD_LED
0
0
0
X
0
0
X
X
0
0
0
X
X
1
0
X
1
0
1
HI–Z
IDE RESET SIGNAL GENERATION AND PCRIST DRIVE STRENGTH
1
PCIRST
IDE_RSTDRV
PCIRST_OUT
0
1
0
1
0
1
NOTE:
1. IDE_RSTDRV is a 5 V copy of PCIRST. PCIRST_OUT is a 3.3 V copy of PCIRST.
PWRGD SIGNAL GENERATION
FPRST
PWRGD_PS
PWRGD_3V
0
0
1
1
0
1
0
1
0
0
0
1
FLUSH_OUT / INIT_OUT CIRCUIT
CASE
A20M
GPO_FLUSH_CACHE
INIT
FLUSH_OUT_CPU
FLUSH_OUT_FWH
INIT_OUT
1
1
Falling edge
0
0(for t1)
0(for t1)
0, Hi-Z, then 0 (delayed by
t1-t, then active for 2*t)
2
1
Falling edge
1
0(for t1)
0(for t1)
Hi-Z, 0 (delayed by t1-t,
then active for 2*t)
3
4
5
6
X
X
0
0
1
0
1
1
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
1
Hi-Z
Hi-Z
0
Falling edge
Falling edge
CLK_IN AND SEL_33_66
SEL_33_66
CLK_IN RATE
0
1
66 MHz
33 MHz
24
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
CLK_IN
B2
CLK
SEL_33_66
SW00603
Figure 19.
GP_IN/GP_OUT GENERAL PURPOSE GATES
GP1_INA
GP1_INB
GP1_OUT
0
0
1
1
0
1
0
1
1
1
1
0
GP_IN/GP_OUT GENERAL PURPOSE GATES (continued)
GP2_IN
GP2_OUT
0
1
1
0
GP_IN/GP_OUT GENERAL PURPOSE GATES (continued)
GP3_IN
GP3_OUT
0
1
0
1
POWER SEQUENCING / BACKFEED_CUT
PWRGD_PS
SLP_S3
BACKFEED_CUT
0
0
1
1
0
1
0
1
HI-Z
HI-Z
HI-Z
0
POWER SUPPLY TURN-ON CIRCUIT
SLOTOCC
SLP_S3
SLP_S3A
Hi-Z
0
0
1
1
0
1
0
1
0
Hi-Z
Hi-Z
RAMBUS_SCK_BJT
PWRGD_3V
SCK_BJT_GATE
0
1
Hi-Z
0
25
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
VGA DCC VOLTAGE TRANSLATION
3V_DDCSDA
3V_DDCSCL
5V_DDCSDA
5V_DDCSCL
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
HSYNC / VSYNC VOLTAGE TRANSLATION
HSYNC_3V
HSYNC_5V
VSYNC_3V
VSYNC_5V
0
1
0
1
0
1
0
1
POWER LED DRIVER
YLW_BLNK
SLP_S5
YLW_LED
GRN_BLNK
SLP_S5
GRN_LED
0
0
1
1
0
1
0
1
0
0
0
0
1
1
0
1
0
1
0
0
0
0
HI-Z
Hi-Z
26
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
27
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
REVISION HISTORY
Rev
Date
Description
_5
20040511
Product data (9397 750 13279). Supersedes data of 2003 Nov 10 (9397 750 12288).
Modifications:
• Page 24, Audio-disable table: AUD_EN column (reading veritcally) changed from ‘0000’ to ‘0011’.
_4
_3
20031110
20030328
Product data (9397 750 12288); ECN 853-2206 30409 dated 10 October 2003.
Supersedes data of 28 March 2003 (9397 750 09602).
Product data (9397 750 09602); ECN: 853–2206 27930 (2003 Mar 28)
28
2004 May 11
Philips Semiconductors
Product data
Glue chip 4
PCA9504A
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys
nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2004
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 05-04
9397 750 13279
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
相关型号：
PCA9504ADGG,118
IC SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56, 6.10 MM, PLASTIC, MO-153, SOT-364-1, TSSOP-56, Microprocessor IC:Other
NXP
PCA9505DGG-T
IC 8 I/O, PIA-GENERAL PURPOSE, PDSO56, 6.10 MM, PLASTIC, MO-153, SOT364-1, TSSOP-56, Parallel IO Port
NXP
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