PCA9506DGG,518_技术文档

PCA9505/06

40-bit I²C-bus I/O port with RESET, OE and INT

Rev. 03 — 6 June 2007

Product data sheet

1. General description

The PCA9505/PCA9506 provide 40-bit parallel input/output (I/O) port expansion for

I²C-bus applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are

capable of sourcing 10 mA and sinking 15 mA with a total package load of 600 mA to

allow direct driving of 40 LEDs. Any of the 40 I/O ports can be conﬁgured as an input or

output. Output ports are totem-pole and their logic state changes at the Acknowledge

(bank change). The PCA9505 is identical to the PCA9506 except that it includes 100 kΩ

internal pull-up resistors on all the I/Os. The PCA9506 does not include the internal

pull-ups on the I/Os to reduce power consumption when used as outputs or when the

input is driven by a push-pull driver.

The device can be conﬁgured to have each input port to be masked in order to prevent it

from generating interrupts when its state changes and to have the I/O data logic state to

be inverted when read by the system master.

An open-drain interrupt (INT) output pin allows monitoring of the input pins and is

asserted each time a change occurs in one or several input ports (unless masked).

The Output Enable (OE) pin 3-states any I/O selected as an output and can be used as an

input signal to blink or dim LEDs (PWM with frequency > 80 Hz and change duty cycle).

The internal Power-On Reset (POR) or hardware reset (RESET) pin initializes the 40 I/Os

as inputs. Three address select pins conﬁgure one of 8 slave addresses.

The PCA9506 is available in 56-pin TSSOP and HVQFN packages, while the PCA9505 is

available only in a TSSOP package. They are both speciﬁed over the −40 °C to +85 °C

industrial temperature range.

2. Features

I Standard mode (100 kHz) and Fast mode (400 kHz) compatible I²C-bus serial

interface

I 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os

I 40 conﬁgurable I/O pins that default to inputs at power-up

I PCA9505 includes 100 kΩ internal pull-up resistors on all the I/Os

I Outputs:

N Totem-pole (10 mA source, 15 mA sink) with controlled edge rate output structure

N Active LOW output enable (OE) input pin 3-states all outputs

N Output state change on Acknowledge

N Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level

change of pins programmed as inputs

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

I Inputs:

N Programmable Interrupt Mask Control for input pins that do not require an interrupt

when their states change

N Polarity Inversion register allows inversion of the polarity of the I/O pins when read

I Active LOW reset (RESET) input pin resets device to power-up default state

I 3 programmable address pins allowing 8 devices on the same bus

I Designed for live insertion

N Minimize line disturbance (I_OFFand power-up 3-state)

N Signal transient rejection (50 ns noise ﬁlter and robust I²C-bus state machine)

I Low standby current

I −40 °C to +85 °C operation

I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

I Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA

I Offered in TSSOP56 (PCA9505, PCA9506) and HVQFN56 (PCA9506) packages

3. Applications

I Servers

I RAID systems

I Industrial control

I Medical equipment

I PLCs

I Cell phones

I Gaming machines

I Instrumentation and test measurement

4. Ordering information

Table 1.

Ordering information

Type number

Topside mark

Package

Name

Description

Version

PCA9505DGG

PCA9506DGG

PCA9506BS

PCA9505DGG

PCA9506DGG

PCA9506BS

TSSOP56

plastic thin shrink small outline package; 56 leads;

body width 6.1 mm

SOT364-1

TSSOP56

HVQFN56

plastic thin shrink small outline package; 56 leads;

body width 6.1 mm

SOT364-1

SOT684-1

plastic thermal enhanced very thin quad ﬂat package;

no leads; 56 terminals; body 8 × 8 × 0.85 mm

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

2 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

5. Block diagram

OE

PCA9505/PCA9506

IO0_0

IO0_1

IO0_2

8-bit

A0

A1

A2

INPUT/

OUTPUT

IO0_3

PORTS

IO0_4

IO0_5

IO0_6

IO0_7

write pulse 0

read pulse 0

BANK 0

BANK 1

BANK 2

BANK 3

SCL

SDA

LOW PASS

INPUT

FILTERS

2

I C-BUS

CONTROL

IO4_0

IO4_1

IO4_2

IO4_3

IO4_4

IO4_5

IO4_6

IO4_7

8-bit

INPUT/

OUTPUT

PORTS

write pulse 4

read pulse 4

V

DD

BANK 4

POWER-ON

RESET

V

SS

RESET

INTERRUPT

MANAGEMENT

INT

LP FILTER

002aab492

All I/Os are set to inputs at power-up and RESET.

Fig 1. Block diagram of PCA9505/06

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

3 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

configuration port register data (Cx[y])

output port register data (Ox[y])

I/O configuration

register

data from

shift register

D

Q

V

DD

PCA9505

only

write configuration

pulse

100 kΩ

CK

Q

IOx_y

ESD protection

diode

data from

shift register

D

Q

V

SS

write pulse

CK

Mx[y]

output port

register

INTERRUPT

MANAGEMENT

INT

input port

register

D

Q

input port

register data

(Ix[y])

read pulse

CK

polarity inversion

register

data from

shift register

polarity

register data

(Px[y])

D

Q

write polarity

pulse

CK

002aab493

On power-up or RESET, all registers return to default values.

Fig 2. Simpliﬁed schematic of IO0_0 to IO4_7

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

4 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

6. Pinning information

6.1 Pinning

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

SDA

SCL

RESET

INT

2

3

IO0_0

IO0_1

IO0_2

IO4_7

IO4_6

IO4_5

4

5

6

V

SS

V

SS

7

IO0_3

IO0_4

IO0_5

IO0_6

IO4_4

IO4_3

IO4_2

IO4_1

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

V

SS

V

DD

IO0_7

IO1_0

IO1_1

IO1_2

IO1_3

IO1_4

IO4_0

IO3_7

IO3_6

IO3_5

IO3_4

IO3_3

PCA9505DGG

PCA9506DGG

V

DD

V

SS

IO1_5

IO1_6

IO1_7

IO2_0

IO3_2

IO3_1

IO3_0

IO2_7

V

SS

V

SS

IO2_1

IO2_2

IO2_3

A0

IO2_6

IO2_5

IO2_4

OE

A1

A2

002aab491

Fig 3. Pin conﬁguration for TSSOP56

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

5 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

terminal 1

index area

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

IO0_4

IO0_5

IO0_6

IO4_3

IO4_2

IO4_1

3

4

V

SS

V

DD

5

IO0_7

IO1_0

IO1_1

IO1_2

IO1_3

IO1_4

IO4_0

IO3_7

IO3_6

IO3_5

IO3_4

IO3_3

6

7

PCA9506BS

8

9

10

11

12

13

14

V

DD

V

SS

IO1_5

IO1_6

IO1_7

IO3_2

IO3_1

IO3_0

002aab975

Transparent top view

Fig 4. Pin conﬁguration for HVQFN56

6.2 Pin description

Table 2.

Pin description

Symbol

Type

Description

TSSOP56

HVQFN56

SDA

SCL

1

2

50

51

I/O

I

serial data line

serial clock line

input/output bank 0

IO0_0 to IO0_7 3, 4, 5, 7, 8, 9, 52, 53, 54, 56, 1, I/O

10, 12 2, 3, 5

IO1_0 to IO1_7 13, 14, 15, 16, 6, 7, 8, 9, 10, 12, I/O

17, 19, 20, 21 13, 14

input/output bank 1

input/output bank 2

input/output bank 3

input/output bank 4

ground supply voltage

supply voltage

IO2_0 to IO2_7 22, 24, 25, 26, 15, 17, 18, 19,

31, 32, 33, 35 24, 25, 26, 28

I/O

IO3_0 to IO3_7 36, 37, 38, 40, 29, 30, 31, 33,

41, 42, 43, 44 34, 35, 36, 37

IO4_0 to IO4_7 45, 47, 48, 49, 38, 40, 41, 42,

50, 52, 53, 54

43, 45, 46, 47

V_SS

V_DD

6, 11, 23, 34,

39, 51

4, 16, 27, 32, 44, power

55^[1]

supply

18, 46

11, 39

power

supply

A0

A1

A2

27

28

29

20

21

22

I

address input 0

address input 1

address input 2

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

6 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

Table 2.

Pin description …continued

Symbol

Type

Description

TSSOP56

HVQFN56

OE

30

55

56

23

48

49

I

active LOW output enable input

active LOW interrupt output

active LOW reset input

INT

O

I

RESET

[1] HVQFN package die supply ground is connected to both V_SSpins and exposed center pad. V_SSpins must

be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board

level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad

on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the

printed-circuit board in the thermal pad region.

7. Functional description

Refer to Figure 1 “Block diagram of PCA9505/06” and Figure 2 “Simpliﬁed schematic of

IO0_0 to IO4_7”.

7.1 Device address

Following a START condition, the bus master must send the address of the slave it is

accessing and the operation it wants to perform (read or write). The address of the

PCA9505/06 is shown in Figure 5. Slave address pins A2, A1, and A0 choose 1 of 8 slave

addresses and need to be connected to V_DD(1) or V_SS(0). To conserve power, no internal

pull-up resistors are incorporated on A2, A1, and A0.

slave address

0

1

0

A2 A1 A0 R/W

fixed

programmable

002aab494

Fig 5. PCA9505/06 address

The last bit of the ﬁrst byte deﬁnes the operation to be performed. When set to logic 1 a

read is selected, while a logic 0 selects a write operation.

7.2 Command register

Following the successful acknowledgement of the slave address + R/W bit, the bus master

will send a byte to the PCA9505/06, which will be stored in the Command register.

AI

1

−

D5 D4 D3 D2 D1 D0

default at power-up

or after RESET

0

register number

002aab495

Auto-Increment

Fig 6. Command register

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

7 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

The lowest 6 bits are used as a pointer to determine which register will be accessed. The

registers are:

• IP: Input Port registers (5 registers)

• OP: Output Port registers (5 registers)

• PI: Polarity Inversion registers (5 registers)

• IOC: I/O Conﬁguration registers (5 registers)

• MSK: Mask interrupt registers (5 registers)

If the Auto-Increment ﬂag is set (AI = 1), the 3 least signiﬁcant bits are automatically

incremented after a read or write. This allows the user to program and/or read the

5 register banks sequentially.

If more than 5 bytes of data are written and AI = 1, previous data in the selected registers

will be overwritten. Reserved registers are skipped and not accessed (refer to Table 3).

If the Auto-Increment ﬂag is cleared (AI = 0), the 3 least signiﬁcant bits are not

incremented after data is read or written. During a read operation, the same register bank

is read each time. During a write operation, data is written to the same register bank each

time.

Only a Command register code with the 5 least signiﬁcant bits equal to the 25 allowable

values as deﬁned in Table 3 are valid. Reserved or undeﬁned command codes must not

be accessed for proper device functionality. At power-up, this register defaults to 0x80,

with the AI bit set to logic 1, and the lowest 7 bits set to logic 0.

During a write operation, the PCA9505/06 will acknowledge a byte sent to OPx, PIx, and

IOCx and MSKx registers, but will not acknowledge a byte sent to the IPx registers since

these are read-only registers.

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

8 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

7.3 Register deﬁnitions

Table 3.

Register summary

Register # D5

(hex)

D4

D3

D2

D1

D0

Symbol

Access

Description

Input Port registers

00

01

02

03

04

05

06

07

0

1

0

1

0

1

0

1

0

1

0

1

0

1

IP0

IP1

IP2

IP3

IP4

-

read only

Input Port register bank 0

Input Port register bank 1

Input Port register bank 2

Input Port register bank 3

Input Port register bank 4

reserved for future use

read only

-

Output Port registers

08

09

0A

0B

0C

0D

0E

0F

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

OP0

OP1

OP2

OP3

OP4

-

read/write

Output Port register bank 0

Output Port register bank 1

Output Port register bank 2

Output Port register bank 3

Output Port register bank 4

reserved for future use

read/write

-

reserved for future use

-

reserved for future use

Polarity Inversion registers

10

11

12

13

14

15

16

17

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PI0

PI1

PI2

PI3

PI4

-

read/write

Polarity Inversion register bank 0

Polarity Inversion register bank 1

Polarity Inversion register bank 2

Polarity Inversion register bank 3

Polarity Inversion register bank 4

reserved for future use

read/write

-

reserved for future use

-

reserved for future use

I/O Conﬁguration registers

18

19

1A

1B

1C

1D

1E

1F

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

IOC0

IOC1

IOC2

IOC3

IOC4

-

read/write

I/O Conﬁguration register bank 0

I/O Conﬁguration register bank 1

I/O Conﬁguration register bank 2

I/O Conﬁguration register bank 3

I/O Conﬁguration register bank 4

reserved for future use

read/write

-

reserved for future use

-

reserved for future use

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

9 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

Table 3.

Register summary …continued

Register # D5

(hex)

D4

D3

D2

D1

D0

Symbol

Access

Description

Mask Interrupt registers

20

21

22

23

24

25

26

27

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MSK0

MSK1

MSK2

MSK3

MSK4

-

read/write

Mask Interrupt register bank 0

Mask Interrupt register bank 1

Mask Interrupt register bank 2

Mask Interrupt register bank 3

Mask Interrupt register bank 4

reserved for future use

read/write

-

reserved for future use

-

reserved for future use

7.3.1 IP0 to IP4 - Input Port registers

These registers are read-only. They reﬂect the incoming logic levels of the port pins

regardless of whether the pin is deﬁned as an input or an output by the I/O Conﬁguration

register. If the corresponding Px[y] bit in the PI registers is set to logic 0, or the inverted

incoming logic levels if the corresponding Px[y] bit in the PI register is set to logic 1. Writes

to these registers have no effect.

Table 4.

IP0 to IP4 - Input Port registers (address 00h to 04h) bit description

Legend: * default value ‘X’ determined by the externally applied logic level.

Address

00h

Register

IP0

Bit

Symbol

I0[7:0]

I1[7:0]

I2[7:0]

I3[7:0]

I4[7:0]

Access

Value

Description

7 to 0

R

XXXX XXXX*

Input Port register bank 0

Input Port register bank 1

Input Port register bank 2

Input Port register bank 3

Input Port register bank 4

01h

IP1

02h

IP2

03h

IP3

04h

IP4

The Polarity Inversion register can invert the logic states of the port pins. The polarity of

the corresponding bit is inverted when Px[y] bit in the PI register is set to logic 1. The

polarity of the corresponding bit is not inverted when Px[y] bits in the PI register is set to

logic 0.

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

10 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

7.3.2 OP0 to OP4 - Output Port registers

These registers reﬂect the outgoing logic levels of the pins deﬁned as outputs by the

I/O Conﬁguration register. Bit values in these registers have no effect on pins deﬁned as

inputs. In turn, reads from these registers reﬂect the values that are in the ﬂip-ﬂops

controlling the output selection, not the actual pin values.

Ox[y] = 0: IOx_y = 0 if IOx_y deﬁned as output (Cx[y] in IOC register = 0).

Ox[y] = 1: IOx_y = 1 if IOx_y deﬁned as output (Cx[y] in IOC register = 0).

Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).

Table 5.

OP0 to OP4 - Output Port registers (address 08h to 0Ch) bit description

Legend: * default value.

Address

08h

Register

OP0

Bit

Symbol

O0[7:0]

O1[7:0]

O2[7:0]

O3[7:0]

O4[7:0]

Access

R/W

Value

Description

7 to 0

0000 0000*

Output Port register bank 0

Output Port register bank 1

Output Port register bank 2

Output Port register bank 3

Output Port register bank 4

09h

OP1

R/W

0Ah

OP2

R/W

0Bh

OP3

R/W

0Ch

OP4

R/W

7.3.3 PI0 to PI4 - Polarity Inversion registers

These registers allow inversion of the polarity of the corresponding Input Port register.

Px[y] = 0: The corresponding Input Port register data polarity is retained.

Px[y] = 1: The corresponding Input Port register data polarity is inverted.

Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).

Table 6.

PI0 to PI4 - Polarity Inversion registers (address 10h to 14h) bit description

Legend: * default value.

Address

10h

Register

PI0

Bit

Symbol

P0[7:0]

P1[7:0]

P2[7:0]

P3[7:0]

P4[7:0]

Access

R/W

Value

Description

7 to 0

0000 0000*

Polarity Inversion register bank 0

Polarity Inversion register bank 1

Polarity Inversion register bank 2

Polarity Inversion register bank 3

Polarity Inversion register bank 4

11h

PI1

R/W

12h

PI2

R/W

13h

PI3

R/W

14h

PI4

R/W

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

11 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

7.3.4 IOC0 to IOC4 - I/O Conﬁguration registers

These registers conﬁgure the direction of the I/O pins.

Cx[y] = 0: The corresponding port pin is an output.

Cx[y] = 1: The corresponding port pin is an input.

Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).

Table 7.

IOC0 to IOC4 - I/O Conﬁguration registers (address 18h to 1Ch) bit description

Legend: * default value.

Address

18h

Register

IOC0

Bit

Symbol

C0[7:0]

C1[7:0]

C2[7:0]

C3[7:0]

C4[7:0]

Access

R/W

Value

Description

7 to 0

1111 1111*

I/O Conﬁguration register bank 0

I/O Conﬁguration register bank 1

I/O Conﬁguration register bank 2

I/O Conﬁguration register bank 3

I/O Conﬁguration register bank 4

19h

IOC1

R/W

1Ah

IOC2

R/W

1Bh

IOC3

R/W

1Ch

IOC4

R/W

7.3.5 MSK0 to MSK4 - Mask interrupt registers

These registers mask the interrupt due to a change in the I/O pins conﬁgured as inputs. ‘x’

refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).

Mx[y] = 0: A level change at the I/O will generate an interrupt if IOx_y deﬁned as input

(Cx[y] in IOC register = 1).

Mx[y] = 1: A level change in the input port will not generate an interrupt if IOx_y deﬁned

as input (Cx[y] in IOC register = 1).

Table 8.

MSK0 to MSK4 - Mask interrupt registers (address 20h to 24h) bit description

Legend: * default value.

Address

20h

Register

MSK0

MSK1

MSK2

MSK3

MSK4

Bit

Symbol

M0[7:0]

M1[7:0]

M2[7:0]

M3[7:0]

M4[7:0]

Access

R/W

Value

Description

7 to 0

1111 1111*

Mask Interrupt register bank 0

Mask Interrupt register bank 1

Mask Interrupt register bank 2

Mask Interrupt register bank 3

Mask Interrupt register bank 4

21h

R/W

22h

R/W

23h

R/W

24h

R/W

7.4 Power-on reset

When power is applied to V_DD, an internal Power-On Reset (POR) holds the PCA9505/06

in a reset condition until V_DDhas reached V_POR. At that point, the reset condition is

released and the PCA9505/06 registers and I²C-bus state machine will initialize to their

default states. Thereafter, V_DDmust be lowered below 0.2 V to reset the device.

7.5 RESET input

A reset can be accomplished by holding the RESET pin LOW for a minimum of t_w(rst). The

PCA9505/06 registers and I²C-bus state machine will be held in their default states until

the RESET input is once again HIGH.

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

12 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

7.6 Interrupt output (INT)

The open-drain active LOW interrupt is activated when one of the port pins changes state

and the port pin is conﬁgured as an input and the interrupt on it is not masked. The

interrupt is deactivated when the port pin input returns to its previous state or the Input

Port register is read.

Remark: Changing an I/O from an output to an input may cause a false interrupt to occur

if the state of the pin does not match the contents of the Input Port register.

Only a read of the Input Port register that contains the bit(s) image of the input(s) that

generated the interrupt clears the interrupt condition.

If more than one input register changed state before a read of the Input Port register is

initiated, the interrupt is cleared when all the input registers containing all the inputs that

changed are read.

Example: If IO0_5, IO2_3, and IO3_7 change state at the same time, the interrupt is

cleared only when INREG0, INREG2, and INREG3 are read.

7.7 Output enable input (OE)

The active LOW output enable pin allows to enable or disable all the I/Os at the same

time. When a LOW level is applied to the OE pin, all the I/Os conﬁgured as outputs are

enabled and the logic value programmed in their respective OP registers is applied to the

pins. When a HIGH level is applied to the OE pin, all the I/Os conﬁgured as outputs are

3-stated.

For applications requiring LED blinking with brightness control, this pin can be used to

control the brightness by applying a high frequency PWM signal on the OE pin. LEDs can

be blinked using the Output Port registers and can be dimmed using the PWM signal on

the OE pin thus controlling the brightness by adjusting the duty cycle.

7.8 Live insertion

The PCA9505/06 are fully speciﬁed for live insertion applications using I_OFF, power-up

3-states, robust state machine, and 50 ns noise ﬁlter. The I_OFFcircuitry disables the

outputs, preventing damaging current backﬂow through the device when it is powered

down. The power-up 3-state’s circuitry places the outputs in the high-impedance state

during power-up and power-down, which prevents driver conﬂict and bus contention.

The robust state machine does not respond until it sees a valid START condition and the

50 ns noise ﬁlter will ﬁlter out any insertion glitches. The PCA9505/06 will not cause

corruption of active data on the bus, nor will the device be damaged or cause damage to

devices already on the bus when similar featured devices are being used.

7.9 Standby

The PCA9505/06 goes into standby when the I²C-bus is idle. Standby supply current is

lower than 1 µA (typical).

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

13 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

8. Characteristics of the I²C-bus

The I²C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 7).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 7. Bit transfer

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P) (see Figure 8).

SDA

SCL

SDA

SCL

S

P

STOP condition

START condition

mba608

Fig 8. Deﬁnition of START and STOP conditions

8.2 System conﬁguration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master' and the devices which are controlled by

the master are the ‘slaves' (see Figure 9).

PCA9505_9506_3

Product data sheet

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14 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

SDA

SCL

SLAVE

TRANSMITTER/

RECEIVER

MASTER

2

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER

I C-BUS

TRANSMITTER/

RECEIVER

MULTIPLEXER

SLAVE

002aaa966

Fig 9. System conﬁguration

8.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from master

1

2

8

9

S

clock pulse for

START

condition

acknowledgement

002aaa987

Fig 10. Acknowledgement on the I²C-bus

8.4 Bus transactions

Data is transmitted to the PCA9505/06 registers using Write Byte transfers (see

Figure 11, Figure 12, and Figure 13). Data is read from the PCA9505/06 registers using

Read and Receive Byte transfers (see Figure 14).

PCA9505_9506_3

Product data sheet

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15 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

9. Application design-in information

5 V

V

DD

SUB-SYSTEM 1

(e.g., temp sensor)

1.6 kΩ

1.1 kΩ

2 kΩ

1.1 kΩ

V

DD

(optional)

INT

MASTER

CONTROLLER

SCL

PCA9505/06

SCL

IO0_0

SUB-SYSTEM 2

(e.g., counter)

SDA

IO0_1

IO0_2

IO0_3

IO0_4

IO0_5

RESET

A

INT

OE

INT

OE

GND

controlled

switch

(e.g., CBT device)

ENABLE

B

IO1_0

IO3_7

SUB-SYSTEM 3

(e.g., alarm system)

A2

A1

A0

ALARM

IO4_0

IO4_7

V

DD

V

SS

ALPHA NUMERIC

KEYPAD

24 LED MATRIX

002aab500

Device address conﬁgured as 0100 000X for this example.

IO0_0, IO0_2, IO0_3, IO1_0 to IO3_7 are conﬁgured as outputs.

IO0_1, IO0_4, IO4_0 to IO4_7 conﬁgured as inputs.

Fig 15. Typical application

PCA9505_9506_3

Product data sheet

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18 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

10. Limiting values

Table 9.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

V_I

Parameter

Conditions

Min

Max

+6

Unit

V

supply voltage

−0.5

input voltage

V

-

_SS− 0.5

5.5

V

I_I

input current

±20

5.5

mA

V

V_I/O(n)

V_I/O(IO0n)

I_O(I/On)

I_DD

input/output voltage on any other pin

input/output voltage on pin IO0_n

output current on an I/O pin

supply current

V

_SS− 0.5

5.5

V

−20

+50

500

1100

500

+150

+85

125

150

mA

mW

°C

-

I_SS

ground supply current

total power dissipation

storage temperature

ambient temperature

junction temperature

-

P_tot

-

T_stg

−65

T_amb

T_j

operating

storage

−40

-

11. Static characteristics

Table 10. Static characteristics

V_DD= 2.3 V to 5.5 V; V_SS= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Supply

V_DD

Parameter

Conditions

Min

Typ

Max

Unit

supply voltage

supply current

2.3

-

5.5

V

I_DD

PCA9506 only;

operating mode; no load;

f

_SCL= 400 kHz

V_DD= 2.3 V

V_DD= 3.3 V

V_DD= 5.5 V

-

56

95

µA

98

150

300

225

PCA9505 only;

operating mode; no load;

f

_SCL= 400 kHz

V_DD= 2.3 V

V_DD= 3.3 V

V_DD= 5.5 V

-

1

1.5

2

mA

1.5

2.7

3.5

I_stbH

HIGH-level standby current

no load; f_SCL= 0 kHz;

I/O = inputs; V_I= V_DD

V_DD= 2.3 V

V_DD= 3.3 V

-

0.15

0.25

0.75

2

11

12

µA

V

V_DD= 5.5 V

15.5

5

I_stbL

LOW-level standby current

power-on reset voltage^[1]

PCA9505 only

no load; V_I= V_DDor V_SS

V_POR

1.70

2.0

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

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PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

Table 10. Static characteristics …continued

V_DD= 2.3 V to 5.5 V; V_SS= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input SCL; input/output SDA

V_IL

V_IH

I_OL

I_L

LOW-level input voltage

−0.5

0.7V_DD

20

-

+0.3V_DD

V

HIGH-level input voltage

LOW-level output current

leakage current

-

5.5

-

V

V_OL= 0.4 V

V_I= V_DD= V_SS

V_I= V_SS

-

mA

µA

pF

−1

-

+1

10

C_i

input capacitance

-

5

I/Os

V_IL

V_IH

I_OL

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

−0.5

-

+0.8

5.5

V

2

V_OL= 0.5 V

V_DD= 2.3 V

10

12

15

-

mA

A

V_DD= 3.0 V

-

V_DD= 4.5 V

-

I_OL(tot)

V_OH

total LOW-level output current

HIGH-level output voltage

V_OL= 0.5 V; V_DD= 4.5 V

I_OH= −10 mA

V_DD= 2.3 V

0.6

1.6

2.3

4.0

−1

-

V

V_DD= 3.0 V

-

V

V_DD= 4.5 V

-

V

I_LIH

I_LIL

HIGH-level input leakage current V_DD= 3.6 V; V_I= V_DD

+1

µA

LOW-level input leakage current

V_DD= 5.5 V; V_I= V_SS

PCA9506 only

−1

-

+1

7

µA

pF

PCA9505 only

−100

-

C_i

input capacitance

output capacitance

-

6

C_o

7

Interrupt INT

I_OL

I_OH

C_o

LOW-level output current

HIGH-level output current

output capacitance

V_OL= 0.4 V

6

-

mA

µA

pF

−1

-

+1

5

3.0

Inputs RESET and OE

V_IL

V_IH

I_LI

LOW-level input voltage

−0.5

2

-

+0.8

5.5

+1

V

HIGH-level input voltage

input leakage current

input capacitance

-

V

−1

-

µA

pF

C_i

3.0

5

Inputs A0, A1, A2

V_IL

V_IH

I_LI

LOW-level input voltage

−0.5

0.7V_DD

−1

-

+0.3V_DD

V

HIGH-level input voltage

input leakage current

input capacitance

-

5.5

+1

5

V

-

µA

pF

C_i

-

3.5

[1] V_DDmust be lowered to 0.2 V in order to reset part.

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

20 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

12. Dynamic characteristics

Table 11. Dynamic characteristics

Symbol Parameter

Conditions

Standard mode

I²C-bus

Fast mode I²C-bus

Unit

Min

0

Max

100

-

Min

0

Max

400

-

[1]

f_SCL

t_BUF

SCL clock frequency

kHz

bus free time between a STOP and

START condition

4.7

1.3

µs

t_HD;STA

t_SU;STA

hold time (repeated) START

condition

4.0

4.7

-

0.6

-

µs

set-up time for a repeated START

condition

t_SU;STO

t_HD;DAT

t_VD;ACK

t_VD;DAT

t_SU;DAT

t_LOW

set-up time for STOP condition

data hold time

data valid acknowledge time^[2]

data valid time^[3]

4.0

0

-

0.6

-

µs

ns

µs

ns

µs

ns

-

3.45

-

0

0.1

250

4.7

4.0

-

0.9

-

0.1

data set-up time

100

LOW period of the SCL clock

HIGH period of the SCL clock

-

1.3

-

t_HIGH

-

0.6

-

[4][5]

[7]

[6]

t_f

fall time of both SDA and SCL

signals

300

20 + 0.1C_b

300

t_r

rise time of both SDA and SCL

signals

-

1000

50

20 + 0.1C_b

-

300

50

ns

t_SP

pulse width of spikes that must be

suppressed by the input ﬁlter

Port timing

t_en

enable time

output

-

80

40

250

-

80

40

250

-

ns

µs

t_dis

disable time

t_v(Q)

data output valid time

data input set-up time

data input hold time

-

t_su(D)

t_h(D)

100

0.5

100

0.5

-

Interrupt timing

t_{v(INT_N)}

valid time on pin INT_N

-

4

-

4

µs

t_{rst(INT_N)}reset time on pin INT_N

Reset

t_w(rst)

t_rec(rst)

t_rst

reset pulse width

reset recovery time

reset time

4

0

-

4

0

-

ns

100

[1] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held

LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.

[2] t_VD;ACK= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

[3] t_VD;DAT= minimum time for SDA data out to be valid following SCL LOW.

[4] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_ILof the SCL signal) in order to

bridge the undeﬁned region SCL’s falling edge.

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

21 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

[5] The maximum t_ffor the SDA and SCL bus lines is speciﬁed at 300 ns. The maximum fall time for the SDA output stage t_fis speciﬁed at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum speciﬁed t_f.

[6] C_b= total capacitance of one bus line in pF.

[7] Input ﬁlters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

SDA

t

SP

t

r

f

HD;STA

BUF

t

LOW

SCL

t

SU;STO

HD;STA

SU;STA

t

SU;DAT

HD;DAT

HIGH

P

S

Sr

P

002aaa986

Fig 16. Deﬁnition of timing on the I²C-bus

START

condition

(S)

bit 7

MSB

(A7)

STOP

condition

(P)

bit 6

(A6)

bit 0 acknowledge

(R/W) (A)

protocol

t

HIGH

SU;STA

LOW

1

/f

SCL

SDA

t

BUF

f

t

r

t

HD;DAT

VD;DAT

VD;ACK

SU;STO

002aab175

HD;STA

SU;DAT

Rise and fall times refer to V_ILand V_IH.

Fig 17. I²C-bus timing diagram

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

22 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

ACK or read cycle

START

SCL

SDA

30 %

t

rst

RESET

IOx_y

50 %

t

rec(rst)

t

w(rst)

t

rst

50 %

output off

002aac018

Fig 18. Reset timing

13. Test information

2V

DD

open

V

SS

V

R

L

500 Ω

DD

V

O

I

PULSE

DUT

GENERATOR

C

50 pF

L

R

T

500 Ω

002aac019

R_L= load resistance

C_L= load capacitance includes jig and probe capacitance

R_T= termination resistance should be equal to the output impedance Z_oof the pulse

generators.

Fig 19. Test circuitry for switching times

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

23 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

14. Package outline

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm

SOT364-1

E

D

A

X

c

H

v

M

A

y

E

Z

56

29

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

28

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

14.1

13.9

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.5

0.1

mm

1.2

0.5

1

0.25

0.08

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT364-1

MO-153

Fig 20. Package outline SOT364-1 (TSSOP56)

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

24 of 31

PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

HVQFN56: plastic thermal enhanced very thin quad flat package; no leads;

56 terminals; body 8 x 8 x 0.85 mm

SOT684-1

D

B

A

terminal 1

index area

A

E

A

1

c

detail X

C

e

1

y

e

1/2 e

b

v

M

C

A

B

C

1

w

15

28

L

29

14

e

E

h

2

1/2 e

1

42

terminal 1

index area

56

43

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

max.

(1)

E

UNIT

A

1

b

c

E

e

1

e

2

y

D

L

v

w

y

1

h

0.05 0.30

0.00 0.18

8.1

7.9

4.45

4.15

8.1

7.9

4.45

4.15

0.5

0.3

mm

0.2

0.5

6.5

0.05

0.1

1

0.1 0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-22

SOT684-1

- - -

MO-220

- - -

Fig 21. Package outline SOT684-1 (HVQFN56)

PCA9505_9506_3

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PCA9505/06

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40-bit I²C-bus I/O port with RESET, OE and INT

15. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.

However, to be completely safe you must take normal precautions appropriate to handling

integrated circuits.

16. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

PCA9505_9506_3

Product data sheet

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PCA9505/06

NXP Semiconductors

40-bit I²C-bus I/O port with RESET, OE and INT

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

16.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 22) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 12 and 13

Table 12. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 13. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 22.

PCA9505_9506_3

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 22. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

17. Abbreviations

Table 14. Abbreviations

Acronym

CDM

DUT

Description

Charged Device Model

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

Integrated Circuit

HBM

IC

I²C-bus

LED

Inter IC bus

Light Emitting Diode

Machine Model

MM

PLC

Programmable Logic Controller

Power-On Reset

POR

PWM

RAID

Pulse Width Modulation

Redundant Array of Independent Disks

PCA9505_9506_3

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Rev. 03 — 6 June 2007

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18. Revision history

Table 15. Revision history

Document ID

Release date

20070606

Data sheet status

Change notice

Supersedes

PCA9505_9506_3

Modiﬁcations:

Product data sheet

-

PCA9506_2

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Added device PCA9505

• Section 1 “General description”:

–

1st paragraph: added last 2 sentences

–

6th paragraph re-written

• Section 2 “Features”:

–

added (new) 4th bullet item

moved (old) 1st sub-bullet below “Inputs:” to 4th sub-bullet below “Outputs:”

last bullet item re-written to indicate which package offered for each type number

• Table 1 “Ordering information”: added Type number PCA9505DGG

• Figure 2 “Simpliﬁed schematic of IO0_0 to IO4_7”: added pull-up resistor for PCA9505

• Table 10 “Static characteristics”, sub-section “Supply”:

–

symbol I_DD: added separate speciﬁcations for PCA9505

changed symbol from “I_stb, standby current” to “I_stbH, HIGH-level standby current”

added symbol “I_stbL, LOW-level standby current” (applies to PCA9505 only)

• Table 10 “Static characteristics”, sub-section “I/Os”:

symbol I_LIL: added separate speciﬁcations for PCA9505

–

PCA9506_2

20060509

20060214

Product data sheet

-

PCA9506_1

-

PCA9506_1

(9397 750 14939)

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

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19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

result in personal injury, death or severe property or environmental damage.

19.2 Deﬁnitions

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

19.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

19.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

I²C-bus — logo is a trademark of NXP B.V.

20. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

PCA9505_9506_3

Product data sheet

Rev. 03 — 6 June 2007

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PCA9505/06

NXP Semiconductors

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21. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

19.1

19.2

19.3

19.4

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

20

21

Contact information . . . . . . . . . . . . . . . . . . . . 30

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7

7.1

7.2

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.4

Functional description . . . . . . . . . . . . . . . . . . . 7

Device address. . . . . . . . . . . . . . . . . . . . . . . . . 7

Command register . . . . . . . . . . . . . . . . . . . . . . 7

Register deﬁnitions . . . . . . . . . . . . . . . . . . . . . . 9

IP0 to IP4 - Input Port registers . . . . . . . . . . . 10

OP0 to OP4 - Output Port registers . . . . . . . . 11

PI0 to PI4 - Polarity Inversion registers. . . . . . 11

IOC0 to IOC4 - I/O Conﬁguration registers. . . 12

MSK0 to MSK4 - Mask interrupt registers . . . 12

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 12

RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . 12

Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 13

Output enable input (OE) . . . . . . . . . . . . . . . . 13

Live insertion . . . . . . . . . . . . . . . . . . . . . . . . . 13

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.5

7.6

7.7

7.8

7.9

8

Characteristics of the I²C-bus. . . . . . . . . . . . . 14

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

START and STOP conditions . . . . . . . . . . . . . 14

System conﬁguration . . . . . . . . . . . . . . . . . . . 14

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15

Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 15

8.1

8.1.1

8.2

8.3

8.4

9

Application design-in information . . . . . . . . . 18

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19

Static characteristics. . . . . . . . . . . . . . . . . . . . 19

Dynamic characteristics . . . . . . . . . . . . . . . . . 21

Test information. . . . . . . . . . . . . . . . . . . . . . . . 23

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 24

Handling information. . . . . . . . . . . . . . . . . . . . 26

10

11

12

13

14

15

16

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Introduction to soldering . . . . . . . . . . . . . . . . . 26

Wave and reﬂow soldering . . . . . . . . . . . . . . . 26

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 26

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 27

16.1

16.2

16.3

16.4

17

18

19

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 28

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 29

Legal information. . . . . . . . . . . . . . . . . . . . . . . 30

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 6 June 2007

Document identifier: PCA9505_9506_3


型号：	PCA9506DGG,518
厂家：	NXP
描述：	PCA9505/06 - 40-bit I2C-bus I/O port with RESET, OE and INT TSSOP 56-Pin PC 光电二极管外围集成电路
文件：	总31页 (文件大小：157K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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