PCA9538BS,118 [NXP]
PCA9538 - 8-bit I²C-bus and SMBus low power I/O port with interrupt and reset QFN 16-Pin;
| 型号： | PCA9538BS,118 |
| 厂家： | 
NXP |
| 描述： | PCA9538 - 8-bit I²C-bus and SMBus low power I/O port with interrupt and reset QFN 16-Pin PC 外围集成电路 |
| 文件： | 总34页 (文件大小：450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9538
8-bit I2C-bus and SMBus low power I/O port with interrupt and
reset
Rev. 8 — 8 November 2017
Product data sheet
1. General description
The PCA9538 is a 16-pin CMOS device that provides 8 bits of General Purpose parallel
Input/Output (GPIO) expansion with interrupt and reset for I2C-bus/SMBus applications
and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders.
I/O expanders provide a simple solution when additional I/O is needed for ACPI power
switches, sensors, push-buttons, LEDs, fans, etc.
The PCA9538 consists of an 8-bit Configuration register (input or output selection),
8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity Inversion register
(active HIGH or active LOW operation). The system master can enable the I/Os as either
inputs or outputs by writing to the I/O configuration bits. The data for each input or output
is kept in the corresponding Input Port or Output Port register. The polarity of the Input
Port register can be inverted with the Polarity Inversion register. All registers can be read
by the system master.
The PCA9538 is identical to the PCA9554 except for the removal of the internal I/O
pull-up resistor which greatly reduces power consumption when the I/Os are held LOW,
replacement of A2 with RESET and different address range.
The PCA9538 open-drain interrupt output (INT) is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed. The power-on reset sets the registers to their
default values and initializes the device state machine. The RESET pin causes the same
reset/initialization to occur without de-powering the device.
Two hardware pins (A0 and A1) vary the fixed I2C-bus address and allow up to four
devices to share the same I2C-bus/SMBus.
2. Features and benefits
8-bit I2C-bus GPIO with interrupt and reset
Operating power supply voltage range of 2.3 V to 5.5 V (3.0 V to 5.5 V
for PCA9538PW/Q900)
5 V tolerant I/Os
Polarity Inversion register
Active LOW interrupt output
Active LOW reset input
Low standby current
Noise filter on SCL/SDA inputs
No glitch on power-up
PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Internal power-on reset
8 I/O pins which default to 8 inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Offered in three different packages: SO16, TSSOP16 and HVQFN16
3. Ordering information
Table 1.
Ordering information
Type number
Topside
marking
Package
Name
Description
Version
PCA9538BS
PCA9538D
PCA9538PW
9538
HVQFN16
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 4 4 0.85 mm
SOT629-1
PCA9538D
PCA9538
SO16
plastic small outline package; 16 leads;
body width 7.5 mm
SOT162-1
SOT403-1
SOT403-1
TSSOP16
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
PCA9538PW/Q900[1] PCA9538
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
[1] PCA9538PW/Q900 is AEC-Q100 compliant. Contact i2c.support@nxp.com for PPAP.
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable part number Package
Packing method
Minimum Temperature
order
quantity
PCA9538BS
PCA9538D
PCA9538BS,118
HVQFN16 Reel pack, SMD,
13-inch
6000
Tamb = 40 C to +85 C
PCA9538D,112
PCA9538D,118
SO16
SO16
Tube, bulk pack
1920
1000
Tamb = 40 C to +85 C
Tamb = 40 C to +85 C
Reel pack, SMD,
13-inch
PCA9538PW
PCA9538PW,112
PCA9538PW,118
TSSOP16
TSSOP16
Tube, bulk pack
2400
2500
Tamb = 40 C to +85 C
Tamb = 40 C to +85 C
Reel pack, SMD,
13-inch
PCA9538PW/Q900 PCA9538PW/Q900,118 TSSOP16
Reel pack, SMD,
13-inch
2500
Tamb = 40 C to +125 C
PCA9538
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 8 — 8 November 2017
2 of 34
PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
4. Block diagram
IO0
A0
A1
IO1
IO2
IO3
IO4
8-bit
INPUT/
OUTPUT
PORTS
SCL
SDA
INPUT
FILTER
2
I C-BUS/SMBus
CONTROL
write pulse
read pulse
IO5
IO6
IO7
V
DD
POWER-ON
RESET
V
DD
RESET
PCA9538
INT
LP
FILTER
V
SS
002aae667
Remark: All I/Os are set to inputs at reset.
Fig 1. Block diagram of PCA9538
PCA9538
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 8 — 8 November 2017
3 of 34
PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
5. Pinning information
5.1 Pinning
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
1
2
3
4
5
6
7
8
16
V
DD
A0
A1
V
DD
15 SDA
SDA
SCL
INT
IO7
IO6
IO5
IO4
14
13
RESET
IO0
SCL
INT
RESET
IO0
PCA9538PW
PCA9538PW/Q900
PCA9538D
12 IO7
11 IO6
10 IO5
IO1
IO1
IO2
IO2
IO3
IO3
9
V
IO4
V
SS
SS
002aae668
002aae669
Fig 2. Pin configuration for SO16
Fig 3. Pin configuration for TSSOP16
terminal 1
index area
1
2
3
4
12
11
10
9
RESET
IO0
SCL
INT
IO7
IO6
PCA9538BS
IO1
IO2
002aae670
Transparent top view
Fig 4. Pin configuration for HVQFN16
PCA9538
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Product data sheet
Rev. 8 — 8 November 2017
4 of 34
PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
5.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SO16, TSSOP16 HVQFN16
A0
1
15
16
1
address input 0
address input 1
active LOW reset input
input/output 0
A1
2
RESET
IO0
IO1
IO2
IO3
VSS
IO4
IO5
IO6
IO7
INT
SCL
SDA
VDD
3
4
2
5
3
input/output 1
6
4
input/output 2
7
5
6[1]
input/output 3
8
supply ground
9
7
input/output 4
10
11
12
13
14
15
16
8
input/output 5
9
input/output 6
10
11
12
13
14
input/output 7
interrupt output (open-drain)
serial clock line
serial data line
supply voltage
[1] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
PCA9538
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 8 — 8 November 2017
5 of 34
PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6. Functional description
Refer to Figure 1 “Block diagram of PCA9538”.
6.1 Device address
slave address
1
1
1
0
0
A1 A0 R/W
fixed
hardware
selectable
002aae707
Fig 5. PCA9538 address
6.2 Registers
6.2.1 Command byte
The command byte is the first byte to follow the address byte during a write transmission.
It is used as a pointer to determine which of the registers will be written or read.
Table 4.
Command byte
Protocol
Command
Function
0
1
2
3
read byte
Input Port register
Output Port register
Polarity Inversion register
Configuration register
read/write byte
read/write byte
read/write byte
6.2.2 Register 0 - Input Port register
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by Register 3. Writes to this register
have no effect.
The default value ‘X’ is determined by the externally applied logic level.
Table 5.
Register 0 - Input Port register bit description
Legend: * default value.
Bit
7
Symbol
Access
Value
X*
Description
I7
I6
I5
I4
I3
I2
I1
I0
read only
read only
read only
read only
read only
read only
read only
read only
value ‘X’ is determined by externally applied
logic level
6
X*
5
X*
4
X*
3
X*
2
X*
1
X*
0
X*
PCA9538
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Product data sheet
Rev. 8 — 8 November 2017
6 of 34
PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.2.3 Register 1 - Output Port register
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3.
Bit values in this register have no effect on pins defined as inputs. Reads from this register
return the value that is in the flip-flop controlling the output selection, not the actual pin
value.
Table 6.
Register 1 - Output Port register bit description
Legend: * default value.
Bit
7
Symbol
O7
Access
Value
1*
Description
R
R
R
R
R
R
R
R
reflects outgoing logic levels of pins defined as outputs
by Register 3
6
O6
1*
5
O5
1*
4
O4
1*
3
O3
1*
2
O2
1*
1
O1
1*
0
O0
1*
6.2.4 Register 2 - Polarity Inversion register
This register allows the user to invert the polarity of the Input Port register data. If a bit in
this register is set (written with 1), the corresponding Input Port data is inverted. If a bit in
this register is cleared (written with a 0), the Input Port data polarity is retained.
Table 7.
Register 2 - Polarity Inversion register bit description
Legend: * default value.
Bit
7
Symbol
N7
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
0*
Description
inverts polarity of Input Port register data
0 = Input Port register data retained (default value)
1 = Input Port register data inverted
6
N6
0*
5
N5
0*
4
N4
0*
3
N3
0*
2
N2
0*
1
N1
0*
0
N0
0*
PCA9538
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Product data sheet
Rev. 8 — 8 November 2017
7 of 34
PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.2.5 Register 3 - Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs.
Table 8.
Register 3 - Configuration register bit description
Legend: * default value.
Bit
7
Symbol
C7
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
1*
Description
configures the directions of the I/O pins
0 = corresponding port pin enabled as an output
6
C6
1*
1 = corresponding port pin configured as an input
(default value)
5
C5
1*
4
C4
1*
3
C3
1*
2
C2
1*
1
C1
1*
0
C0
1*
6.3 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9538 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9538 registers and state machine will initialize to their default states.
Thereafter, VDD must be lowered below 0.2 V to reset the device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
6.4 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst)
.
The PCA9538 registers and SMBus/I2C-bus state machine will be held in their default
state until the RESET input is once again HIGH. This input requires a pull-up resistor to
VDD if no active connection is used.
6.5 Interrupt output
The open-drain interrupt output (INT) is activated when one of the port pins changes state
and the pin is configured as an input. The interrupt is de-activated when the input returns
to its previous state or the Input Port register is read.
Note that changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
PCA9538
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Product data sheet
Rev. 8 — 8 November 2017
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.6 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
state of the Output Port register. Care should be exercised if an external voltage is applied
to an I/O configured as an output because of the low-impedance paths that exist between
the pin and either VDD or VSS
.
data from
shift register
configuration
register
output port
register data
V
DD
data from
shift register
Q1
D
Q
FF
write
configuration
pulse
D
Q
CK
Q
FF
I/O pin
Q2
write pulse
CK
V
input port
register
SS
output port
register
D
Q
input port
register data
FF
read pulse
CK
to INT
polarity inversion
register
data from
shift register
polarity
inversion
register data
D
Q
FF
write polarity
pulse
CK
002aad723
Remark: At power-on reset, all registers return to default values.
Fig 6. Simplified schematic of IO0 to IO7
PCA9538
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 8 — 8 November 2017
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
6.7 Bus transactions
Data is transmitted to the PCA9538 registers using the write mode as shown in Figure 7
and Figure 8. Data is read from the PCA9538 registers using the read mode as shown in
Figure 9 and Figure 10. These devices do not implement an auto-increment function so
once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.
SCL
1
2
3
4
5
6
7
8
9
STOP
condition
slave address
command byte
data to port
DATA 1
SDA
S
1
1
1
0
0
A1 A0
0
A
0
0
0
0
0
0
0
1
A
A
P
START condition
R/W acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
write to port
t
v(Q)
data out from port
DATA 1 VALID
002aae708
Expanded diagram is shown in Figure 18.
Fig 7. Write to output port register
SCL
1
2
3
4
5
6
7
8
9
STOP
condition
slave address
command byte
data to register
DATA 1
SDA
S
1
1
1
0
0
A1 A0
0
A
0
0
0
0
0
0
1
1/0
A
A
P
START condition
R/W acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
data to register
002aae709
Fig 8. Write to configuration or polarity inversion registers
PCA9538
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Product data sheet
Rev. 8 — 8 November 2017
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
slave address
(cont.)
SDA
S
1
1
1
0
0
A1 A0
0
A
COMMAND BYTE
A
START condition
R/W
acknowledge
from slave
acknowledge
from slave
slave address
A1 A0
data from register
DATA (first byte)
data from register
DATA (last byte)
(cont.)
S
1
1
1
0
0
1
A
A
NA P
(repeated)
START condition
R/W
acknowledge
from master
no acknowledge STOP
from master condition
acknowledge
from slave
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
002aae710
Fig 9. Read from register
SCL
1
2
3
4
5
6
7
8
9
no acknowledge
from master
slave address
data from port
DATA 1
data from port
DATA 4
SDA
S
1
1
1
0
0
A1 A0
1
A
A
NA
P
START condition
R/W acknowledge
from slave
acknowledge
from master
STOP
condition
read from
port
data into
DATA 1
DATA 2
DATA 3
DATA 4
port
t
t
su(D)
h(D)
INT
t
t
rst(INT)
v(INT)
002aae711
This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition.
Expanded diagram is shown in Figure 17.
Fig 10. Read input port register
PCA9538
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Product data sheet
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
7. Application design-in information
V
DD
(5 V)
SUB-SYSTEM 1
(e.g., temp sensor)
100 kΩ
(× 3)
10 kΩ
10 kΩ
10 kΩ
10 kΩ
2 kΩ
V
DD
V
DD
INT
MASTER
CONTROLLER
PCA9538
SCL
SDA
SCL
IO0
SUB-SYSTEM 2
(e.g., counter)
SDA
IO1
IO2
IO3
IO4
IO5
IO6
IO7
INT
INT
RESET
A
RESET
RESET
V
SS
controlled
switch
(e.g., CBT device)
enable
B
A1
A0
SUB-SYSTEM 3
(e.g., alarm system)
V
SS
ALARM
V
DD
002aae712
Device address is 1110 000x for this example.
IO0, IO2, IO3 configured as outputs.
IO1, IO4, IO5 configured as inputs.
IO6, IO7 are not used and need 100 k pull-up resistors to protect them from floating.
Fig 11. Typical application
PCA9538
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Product data sheet
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
7.1 Minimizing IDD when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 11. Since the LED acts as a diode, when the LED is off the
I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes
lower than VDD
.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater than or equal to VDD when the LED is off.
Figure 12 shows a high value resistor in parallel with the LED. Figure 13 shows VDD less
than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI
at or above VDD and prevents additional supply current consumption when the LED is off.
3.3 V
5 V
V
DD
V
100 kΩ
V
DD
DD
LED
LED
IOn
IOn
002aac660
002aac661
Fig 12. High value resistor in parallel with
the LED
Fig 13. Device supplied by a lower voltage
8. Limiting values
Table 9.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
+6.0
20
5.5
Unit
V
VDD
II
supply voltage
0.5
input current
-
mA
V
VI/O
IO(IOn)
IDD
voltage on an input/output pin
output current on pin IOn
supply current
VSS 0.5
-
50
85
mA
mA
mA
mW
C
-
ISS
ground supply current
total power dissipation
storage temperature
ambient temperature
-
100
200
+150
Ptot
Tstg
Tamb
-
65
operating
all devices except PCA9538PW/Q900
PCA9538PW/Q900
40
40
-
+85
C
C
C
+125
+125
Tj(max)
maximum junction temperature
PCA9538
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 8 — 8 November 2017
13 of 34
PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
9. Static characteristics
Table 10. Static characteristics for all devices except PCA9538PW/Q900
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Supplies
VDD
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
supply current
2.3
-
-
5.5
V
IDD
operating mode; VDD = 5.5 V;
no load; fSCL = 100 kHz
104
175
A
IstbL
LOW-level standby current
HIGH-level standby current
power-on reset voltage
Standby mode; VDD = 5.5 V;
-
-
-
0.25
0.25
1.7
1
A
A
V
no load; VI = VSS
;
fSCL = 0 kHz; I/O = inputs
IstbH
Standby mode; VDD = 5.5 V;
1
no load; VI = VDD
;
fSCL = 0 kHz; I/O = inputs
[1]
VPOR
no load; VI = VDD or VSS
2.2
Input SCL; input/output SDA
VIL
VIH
IOL
IL
LOW-level input voltage
HIGH-level input voltage
LOW-level output current
leakage current
0.5
-
+0.3VDD
V
0.7VDD
-
5.5
-
V
VOL = 0.4 V
VI = VDD = VSS
VI = VSS
3
7
-
mA
A
pF
1
-
+1
10
Ci
input capacitance
5
I/Os
VIL
VIH
IOL
LOW-level input voltage
HIGH-level input voltage
LOW-level output current
0.5
-
-
+0.8
5.5
V
V
2.0
VOL = 0.5 V
VDD = 2.3 V
VDD = 3.0 V
VDD = 4.5 V
VOL = 0.7 V
VDD = 2.3 V
VDD = 3.0 V
VDD = 4.5 V
IOH = 8 mA
VDD = 2.3 V
VDD = 3.0 V
VDD = 4.5 V
IOH = 10 mA
VDD = 2.3 V
VDD = 3.0 V
VDD = 4.5 V
VI = VDD = VSS
[2]
[2]
[2]
8
8
8
10
14
17
-
-
-
mA
mA
mA
[2]
[2]
[2]
10
10
10
13
19
24
-
-
-
mA
mA
mA
VOH
HIGH-level output voltage
[3]
[3]
[3]
1.8
2.6
4.1
-
-
-
-
-
-
V
V
V
[3]
[3]
[3]
1.7
2.5
4.0
1
-
-
-
V
-
-
V
-
-
V
ILI
Ci
input leakage current
input capacitance
-
+1
10
A
pF
5
PCA9538
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8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Table 10. Static characteristics for all devices except PCA9538PW/Q900 …continued
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Interrupt INT
IOL
LOW-level output current
VOL = 0.4 V
3
13
-
mA
Select inputs A0, A1, RESET
VIL
VIH
ILI
LOW-level input voltage
0.5
2.0
1
-
-
-
+0.8
5.5
+1
V
HIGH-level input voltage
input leakage current
V
A
[1] VDD must be lowered to 0.2 V in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3] The total current sourced by all I/Os must be limited to 85 mA.
Table 11. Static characteristics for PCA9538PW/Q900 AEC-Q100 compliant device
VDD = 3.0 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +125 C; unless otherwise specified.
Symbol
Supplies
VDD
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
supply current
3.0
-
-
5.5
V
IDD
operating mode; VDD = 5.5 V;
no load; fSCL = 100 kHz
104
175
A
IstbL
LOW-level standby current
HIGH-level standby current
power-on reset voltage
Standby mode; VDD = 5.5 V;
-
-
-
0.25
0.25
1.7
1
A
A
V
no load; VI = VSS
;
fSCL = 0 kHz; I/O = inputs
IstbH
Standby mode; VDD = 5.5 V;
1
no load; VI = VDD
;
fSCL = 0 kHz; I/O = inputs
[1]
VPOR
no load; VI = VDD or VSS
2.2
Input SCL; input/output SDA
VIL
VIH
IOL
LOW-level input voltage
0.5
-
-
+0.3VDD
5.5
V
V
HIGH-level input voltage
LOW-level output current, SDA
0.7VDD
VOL = 0.4 V
VDD = 5.5 V
VDD = 3.0 V
VI = VDD = VSS
VI = VSS
3
7
-
-
mA
mA
A
pF
2.5
1
-
-
IL
leakage current
-
+1
10
Ci
input capacitance
5
I/Os
VIL
VIH
IOL
LOW-level input voltage
HIGH-level input voltage
LOW-level output current
0.5
-
-
+0.8
5.5
V
V
2.0
VOL = 0.5 V
VDD = 4.5 V
VDD = 3.0 V
VOL = 0.7 V
VDD = 4.5 V
VDD = 3.0 V
[2]
[2]
8
17
-
-
-
mA
mA
7.5
[2]
[2]
10
24
-
-
-
mA
mA
9.5
PCA9538
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Table 11. Static characteristics for PCA9538PW/Q900 AEC-Q100 compliant device …continued
VDD = 3.0 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +125 C; unless otherwise specified.
Symbol
Parameter
Conditions
IOH = 8 mA
VDD = 4.5 V
VDD = 3.0 V
IOH = 10 mA
VDD = 4.5 V
VDD = 3.0 V
VI = VDD = VSS
Min
Typ
Max
Unit
VOH
HIGH-level output voltage
[3]
[3]
4.1
2.5
-
-
-
-
V
V
[3]
[3]
4.0
2.4
1
-
-
-
V
-
-
V
ILI
Ci
input leakage current
input capacitance
-
+1
10
A
pF
5
Interrupt INT
IOL
LOW-level output current
VOL = 0.4 V
3
13
-
mA
Select inputs A0, A1, RESET
VIL
VIH
ILI
LOW-level input voltage
0.5
2.0
1
-
-
-
+0.8
5.5
+1
V
HIGH-level input voltage
input leakage current
V
A
[1] VDD must be lowered to 0.2 V in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3] The total current sourced by all I/Os must be limited to 85 mA.
PCA9538
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
10. Dynamic characteristics
Table 12. Dynamic characteristics
Symbol Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode I2C-bus Unit
Min
0
Max
100
-
Min
0
Max
400
-
fSCL
tBUF
SCL clock frequency
kHz
bus free time between a STOP and
START condition
4.7
1.3
s
tHD;STA
tSU;STA
hold time (repeated) START condition
4.0
4.7
-
-
0.6
0.6
-
-
s
s
set-up time for a repeated START
condition
tSU;STO
tHD;DAT
tVD;ACK
tVD;DAT
tSU;DAT
tLOW
tHIGH
tr
set-up time for STOP condition
data hold time
4.0
0
-
0.6
-
s
ns
s
ns
ns
s
s
ns
ns
ns
-
0
-
0.9
-
[1]
[2]
data valid acknowledge time
data valid time
0.3
300
250
4.7
4.0
-
3.45
0.1
-
50
data set-up time
-
-
100
1.3
-
LOW period of the SCL clock
HIGH period of the SCL clock
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
-
-
0.6
-
[3]
[3]
1000
300
50
20 + 0.1Cb
20 + 0.1Cb
-
300
300
50
tf
-
tSP
pulse width of spikes that must be
suppressed by the input filter
-
Port timing
tv(Q)
tsu(D)
th(D)
data output valid time
-
100
1
200
-
100
1
200
ns
ns
s
data input set-up time
data input hold time
-
-
-
-
Interrupt timing
tv(INT)
trst(INT)
RESET
tw(rst)
valid time on pin INT
-
-
4
4
-
-
4
4
s
s
reset time on pin INT
reset pulse width
reset recovery time
reset time
4
0
-
-
-
4
0
-
-
-
ns
ns
ns
trec(rst)
trst
400
400
[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] VD;DAT = minimum time for the SDA data out to be valid following SCL LOW.
t
[3] Cb = total capacitance of one bus line in pF.
PCA9538
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PCA9538
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8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
0.7 × V
0.3 × V
DD
SDA
DD
t
t
t
t
SP
t
r
f
HD;STA
BUF
t
LOW
0.7 × V
0.3 × V
DD
SCL
DD
t
t
t
SU;STO
HD;STA
SU;STA
t
t
t
SU;DAT
HD;DAT
HIGH
P
S
Sr
P
002aaa986
Fig 14. Definition of timing
START
condition
(S)
bit 7
MSB
(A7)
STOP
condition
(P)
bit 6
(A6)
bit 1
(D1)
bit 0
(D0)
acknowledge
(A)
protocol
t
t
t
HIGH
SU;STA
LOW
1 / f
SCL
0.7 × V
0.3 × V
DD
SCL
SDA
DD
t
t
BUF
f
t
r
0.7 × V
0.3 × V
DD
DD
t
t
t
t
t
t
HD;DAT
VD;DAT
VD;ACK
SU;STO
HD;STA
SU;DAT
002aab285
Rise and fall times refer to VIL and VIH.
Fig 15. I2C-bus timing diagram
ACK or read cycle
START
SCL
SDA
30 %
t
rst
RESET
50 %
50 %
50 %
t
t
rec(rst)
w(rst)
t
rst
after reset,
I/Os reconfigured
as inputs
IOn
50 %
002aad732
Fig 16. Definition of RESET timing
PCA9538
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
70 %
SCL
SDA
input
INT
2
1
0
A
P
30 %
t
t
h(D)
su(D)
50 %
t
v(INT)
t
rst(INT)
002aae641
Fig 17. Expanded view of read input port register
70 %
SCL
SDA
2
1
0
A
P
t
v(Q)
output
50 %
002aad735
Fig 18. Expanded view of write to output port register
PCA9538
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
11. Test information
V
open
DD
V
SS
V
R
500 Ω
DD
L
V
V
O
I
PULSE
DUT
GENERATOR
C
50 pF
L
R
T
002aab880
RL = load resistor.
CL = load capacitance includes jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generators.
Fig 19. Test circuitry for switching times
R
L
2V
DD
S1
from output under test
open
GND
500 Ω
C
50 pF
R
L
500 Ω
L
002aac226
Fig 20. Test circuit
Table 13. Test data
Test
Load
RL
Switch
CL
50 pF
tv(Q)
500
2 VDD
PCA9538
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
12. Package outline
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
D
E
A
X
c
H
v
M
A
E
y
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
detail X
e
w
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
10.5
10.1
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.41
0.014 0.009 0.40
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT162-1
075E03
MS-013
Fig 21. Package outline SOT162-1 (SO16)
PCA9538
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 22. Package outline SOT403-1 (TSSOP16)
PCA9538
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 4 x 4 x 0.85 mm
SOT629-1
B
A
D
terminal 1
index area
A
A
1
E
c
detail X
e
1
C
1/2 e
y
y
e
v
M
M
b
C
C
A B
C
1
w
5
8
L
9
4
1
e
e
E
h
2
1/2 e
12
terminal 1
index area
16
13
X
D
h
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
e
2
y
D
D
E
L
v
w
y
1
h
1
h
max.
0.05 0.38
0.00 0.23
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.75
0.50
mm
0.05
0.1
1
0.2
0.65
1.95 1.95
0.1 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
01-08-08
02-10-22
SOT629-1
- - -
MO-220
- - -
Fig 23. Package outline SOT629-1 (HVQFN16)
PCA9538
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
13. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
PCA9538
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 24) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 14 and 15
Table 14. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 15. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 24.
PCA9538
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 24. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCA9538
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NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
15. Soldering: PCB footprints
Footprint information for reflow soldering of SO16 package
SOT162-1
Hx
Gx
P2
(0.125)
(0.125)
Hy Gy
By Ay
C
D2 (4x)
P1
D1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
1.270 1.320 11.200 6.400 2.400 0.700 0.800 10.040 8.600 11.900 11.450
sot162-1_fr
Fig 25. PCB footprint for SOT162-1 (SO16); reflow soldering
PCA9538
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Footprint information for reflow soldering of TSSOP16 package
SOT403-1
Hx
Gx
P2
(0.125)
(0.125)
Hy Gy
By Ay
C
D2 (4x)
P1
D1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1 P2 Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650 0.750 7.200 4.500 1.350 0.400 0.600 5.600 5.300 5.800 7.450
sot403-1_fr
Fig 26. PCB footprint for SOT403-1 (TSSOP16); reflow soldering
PCA9538
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Rev. 8 — 8 November 2017
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Footprint information for reflow soldering of HVQFN16 package
SOT629-1
Hx
Gx
D
P
0.025
0.025
C
(0.105)
SPx
SPy
nSPx
Hy Gy
SLy By
Ay
nSPy
SPx tot
SLx
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
occupied area
nSPx nSPy
2
2
Dimensions in mm
Ax
P
Ay
Bx
By
C
D
SLx
SLy
SPx tot
1.200
SPy tot
1.200
SPx
SPy
Gx
Gy
Hx
Hy
0.650 5.000 5.000 2.800 2.800 1.100 0.300 2.000 2.000
0.450 0.450 4.300 4.300 5.250 5.250
07-05-07
Issue date
sot629-1_fr
09-06-15
Fig 27. PCB footprint for SOT629-1 (HVQFN16); reflow soldering
PCA9538
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Product data sheet
Rev. 8 — 8 November 2017
29 of 34
PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
16. Abbreviations
Table 16. Abbreviations
Acronym
Description
ACPI
CBT
CDM
CMOS
DUT
ESD
FET
Advanced Configuration and Power Interface
Cross-Bar Technology
Charged-Device Model
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Field-Effect Transistor
Flip-Flop
FF
GPIO
HBM
I2C-bus
I/O
General Purpose Input/Output
Human Body Model
Inter-Integrated Circuit bus
Input/Output
LED
Light Emitting Diode
LP
Low-Pass
POR
SMBus
Power-On Reset
System Management Bus
PCA9538
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Product data sheet
Rev. 8 — 8 November 2017
30 of 34
PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
17. Revision history
Table 17. Revision history
Document ID
PCA9538 v.8
Modifications:
Release date
Data sheet status
Change notice
Supersedes
20171108
Product data sheet
201710002I
PCA9538 v.7
• Table 10 “Static characteristics for all devices except PCA9538PW/Q900”, Table 11 “Static
characteristics for PCA9538PW/Q900 AEC-Q100 compliant device”: Corrected VPOR typ and max
limit
PCA9538 v.7
Modifications:
20141126
Product data sheet
PCA9538 v.6
• Table 11 “Static characteristics for PCA9538PW/Q900 AEC-Q100 compliant device”: updated IOL
and VOH; changed operating power supply voltage range from “5.0 V 10 %” to “3.0 V to 5.5 V”
for PCA9538PW/Q900
PCA9538 v.6
PCA9538 v.5
PCA9538 v.4
20130206
20090528
20060921
20041005
Product data sheet
Product data sheet
Product data sheet
Product data sheet
PCA9538 v.5
PCA9538 v.4
PCA9538 v.3
PCA9538 v.2
-
-
-
PCA9538 v.3
(9397 750 14176)
PCA9538 v.2
(9397 750 14049)
20040930
20040820
Objective data sheet
Objective data sheet
-
-
PCA9538 v.1
-
PCA9538 v.1
(9397 750 12881)
PCA9538
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Product data sheet
Rev. 8 — 8 November 2017
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PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
18.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
PCA9538
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 8 — 8 November 2017
32 of 34
PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9538
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© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 8 — 8 November 2017
33 of 34
PCA9538
NXP Semiconductors
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
20. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
20
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
3.1
4
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.3
6.4
6.5
6.6
6.7
Functional description . . . . . . . . . . . . . . . . . . . 6
Device address. . . . . . . . . . . . . . . . . . . . . . . . . 6
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6
Register 0 - Input Port register . . . . . . . . . . . . . 6
Register 1 - Output Port register. . . . . . . . . . . . 7
Register 2 - Polarity Inversion register . . . . . . . 7
Register 3 - Configuration register . . . . . . . . . . 8
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8
RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 8
I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 10
7
7.1
Application design-in information . . . . . . . . . 12
Minimizing IDD when the I/Os are used to control
LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13
Static characteristics. . . . . . . . . . . . . . . . . . . . 14
Dynamic characteristics . . . . . . . . . . . . . . . . . 17
Test information. . . . . . . . . . . . . . . . . . . . . . . . 20
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21
Handling information. . . . . . . . . . . . . . . . . . . . 24
9
10
11
12
13
14
Soldering of SMD packages . . . . . . . . . . . . . . 24
Introduction to soldering . . . . . . . . . . . . . . . . . 24
Wave and reflow soldering . . . . . . . . . . . . . . . 24
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 24
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 25
14.1
14.2
14.3
14.4
15
16
17
Soldering: PCB footprints. . . . . . . . . . . . . . . . 27
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 31
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 32
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 32
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 33
18.1
18.2
18.3
18.4
19
Contact information. . . . . . . . . . . . . . . . . . . . . 33
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2017.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 November 2017
Document identifier: PCA9538
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