PCA9539RPW,118_技术文档

PCA9539; PCA9539R

16-bit I²C-bus and SMBus low power I/O port with interrupt

and reset

Rev. 6 — 6 February 2013

Product data sheet

1. General description

The PCA9539; PCA9539R is a 24-pin CMOS device that provides 16 bits of General

Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for

I²C-bus/SMBus applications and was developed to enhance the NXP Semiconductors

family of I²C-bus I/O expanders. I/O expanders provide a simple solution when additional

I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.

The PCA9539; PCA9539R consists of two 8-bit configuration (input or output selection),

input, output and polarity inversion (active HIGH or active LOW operation) registers. The

system master can enable the I/Os as either inputs or outputs by writing to the I/O

configuration bits. The data for each input or output is kept in the corresponding Input or

Output register. The polarity of the read register can be inverted with the Polarity inversion

register. All registers can be read by the system master.

The PCA9539; PCA9539R is identical to the PCA9555 except for the removal of the

internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are

held LOW, replacement of A2 with RESET and a different address range.

The PCA9539; PCA9539R open-drain interrupt output is activated when any input state

differs from its corresponding input port register state and is used to indicate to the system

master that an input state has changed.

The power-on reset sets the registers to their default values and initializes the device state

machine. In the PCA9539, the RESET pin causes the same reset/default I/O input

configuration to occur without de-powering the device, holding the registers and I²C-bus

state machine in their default state until the RESET input is once again HIGH. This input

requires a pull-up to V_DD. In the PCA9539R however, only the device state machine is

initialized by the RESET pin and the internal general-purpose registers remain

unchanged. Using the PCA9539R RESET pin will only reset the I²C-bus interface should

it be stuck LOW to regain access to the I²C-bus. This allows the I/O pins to retain their last

configured state so that they can keep any lines in their previously defined state and not

cause system errors while the I²C-bus is being restored.

Two hardware pins (A0, A1) vary the fixed I²C-bus address and allow up to four devices to

share the same I²C-bus/SMBus.

2. Features and benefits

 16-bit I²C-bus GPIO with interrupt and reset

 Operating power supply voltage range of 2.3 V to 5.5 V

(5.0 V  10 % for PCA9539PW/Q900 AEC-Q100 compliant devices)

 5 V tolerant I/Os

PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

 Polarity inversion register

 Active LOW interrupt output

 Active LOW reset input

 Low standby current

 Noise filter on SCL/SDA inputs

 No glitch on power-up

 Internal power-on reset

 16 I/O pins which default to 16 inputs

 0 Hz to 400 kHz clock frequency

 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

 Offered in three different packages: SO24, TSSOP24, and HVQFN24

3. Ordering information

Table 1.

Ordering information

Type number

Topside

marking

Package

Name

Description

Version

PCA9539BS

PCA9539RBS

PCA9539D

9539

HVQFN24 plastic thermal enhanced very thin quad flat package;

SOT616-1

no leads; 24 terminals; body 4  4  0.85 mm

539R

PCA9539D

SO24

plastic small outline package; 24 leads;

body width 7.5 mm

SOT137-1

SOT355-1

PCA9539PW

PCA9539PW/Q900^[1]PCA9539PW

PCA9539PW TSSOP24 plastic thin shrink small outline package; 24 leads;

body width 4.4 mm

PCA9539RPW

PA9539RPW

[1] PCA9539PW/Q900 is AEC-Q100 compliant. Contact ics.support@nxp.com for PPAP.

3.1 Ordering options

Table 2.

Ordering options

Type number

Orderable part number Package

Packing method Minimum Temperature

order

quantity

PCA9539BS

PCA9539BS,115

PCA9539BS,118

PCA9539RBS,118

HVQFN24 Reel pack, SMD,

1500

6000

T_amb= 40 C to +85 C

7-inch

HVQFN24 Reel pack, SMD,

13-inch

PCA9539RBS

PCA9539D

HVQFN24 Reel pack, SMD,

13-inch

T_amb= 40 C to +85 C

PCA9539D,112

PCA9539D,118

SO24

Tube, bulk pack

1200

1000

T_amb= 40 C to +85 C

Reel pack, SMD,

13-inch

PCA9539_PCA9539R

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Product data sheet

Rev. 6 — 6 February 2013

2 of 37

PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

Table 2.

Ordering options …continued

Type number

Orderable part number Package

Packing method Minimum Temperature

order

quantity

PCA9539PW

PCA9539PW,112

PCA9539PW,118

TSSOP24 Tube, bulk pack

1575

2500

T_amb= 40 C to +85 C

TSSOP24 Reel pack, SMD,

13-inch

T_amb= 40 C to +85 C

PCA9539PW/Q900 PCA9539PW/Q900,118 TSSOP24 Reel pack, SMD,

13-inch

2500

T_amb= 40 C to +125 C

PCA9539RPW

PCA9539RPW,118

TSSOP24 Reel pack, SMD,

13-inch

T

_amb= 40 C to +85 C

4. Block diagram

PCA9539

PCA9539R

IO1_0

IO1_1

IO1_2

8-bit

A0

A1

INPUT/

OUTPUT

PORTS

IO1_3

IO1_4

IO1_5

IO1_6

IO1_7

write pulse

read pulse

2

I C-BUS/SMBus

CONTROL

SCL

SDA

IO0_0

IO0_1

IO0_2

IO0_3

IO0_4

IO0_5

IO0_6

IO0_7

INPUT

FILTER

8-bit

INPUT/

OUTPUT

PORTS

write pulse

read pulse

V

DD

POWER-ON

RESET

V

DD

V

SS

INT

LP

FILTER

002aad722

Remark: All I/Os are set to inputs at reset.

Fig 1. Block diagram of PCA9539; PCA9539R

PCA9539_PCA9539R

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Product data sheet

Rev. 6 — 6 February 2013

3 of 37

PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

5. Pinning information

5.1 Pinning

1

24

23

22

21

20

19

18

17

16

15

14

13

1

2

24

23

22

21

20

19

18

17

16

15

14

13

INT

A1

V

INT

A1

V

DD

2

3

SDA

RESET

IO0_0

IO0_1

IO0_2

IO0_3

IO0_4

IO0_5

IO0_6

IO0_7

SCL

RESET

IO0_0

IO0_1

IO0_2

IO0_3

IO0_4

IO0_5

IO0_6

IO0_7

3

SCL

4

A0

5

IO1_7

IO1_6

IO1_5

IO1_4

IO1_3

IO1_2

IO1_1

IO1_0

IO1_7

IO1_6

IO1_5

IO1_4

IO1_3

IO1_2

IO1_1

IO1_0

PCA9539PW

PCA9539PW/Q900

PCA9539RPW

6

PCA9539D

7

8

9

10

11

12

10

11

12

V

SS

V

SS

002aad719

002aad720

Fig 2. Pin configuration for SO24

Fig 3. Pin configuration for TSSOP24

PCA9539BS

PCA9539RBS

terminal 1

index area

1

2

3

4

5

6

18

17

16

15

14

13

IO0_0

IO0_1

IO0_2

IO0_3

IO0_4

IO0_5

A0

IO1_7

IO1_6

IO1_5

IO1_4

IO1_3

002aad721

Transparent top view

Fig 4. Pin configuration for HVQFN24

PCA9539_PCA9539R

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Product data sheet

Rev. 6 — 6 February 2013

4 of 37

PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

5.2 Pin description

Table 3.

Symbol

Pin description

Description

SO24, TSSOP24

HVQFN24

INT

1

2

3

22

23

24

interrupt output (open-drain)

address input 1

A1

RESET

active LOW reset input. Driving this pin LOW

causes:

• PCA9539 to reset its state machine and

registers

• PCA9539R to reset its state machine, but

has no effect on its registers

IO0_0

IO0_1

IO0_2

IO0_3

IO0_4

IO0_5

IO0_6

IO0_7

V_SS

4

1

port 0 input/output 0

port 0 input/output 1

port 0 input/output 2

port 0 input/output 3

port 0 input/output 4

port 0 input/output 5

port 0 input/output 6

port 0 input/output 7

supply ground

5

2

6

3

7

4

8

5

9

6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

7

8

9^[1]

10

11

12

13

14

15

16

17

18

19

20

21

IO1_0

IO1_1

IO1_2

IO1_3

IO1_4

IO1_5

IO1_6

IO1_7

A0

port 1 input/output 0

port 1 input/output 1

port 1 input/output 2

port 1 input/output 3

port 1 input/output 4

port 1 input/output 5

port 1 input/output 6

port 1 input/output 7

address input 0

SCL

serial clock line input

serial data line open-drain input/output

supply voltage

SDA

V_DD

[1] HVQFN24 package die supply ground is connected to both V_SSpin and exposed center pad. V_SSpin must

be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board

level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad

on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the

PCB in the thermal pad region.

PCA9539_PCA9539R

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Product data sheet

Rev. 6 — 6 February 2013

5 of 37

PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

6. Functional description

Refer to Figure 1 “Block diagram of PCA9539; PCA9539R”.

6.1 Device address

slave address

1

0

1

A1 A0 R/W

fixed

programmable

002aad724

Fig 5. PCA9539; PCA9539R device address

6.2 Registers

6.2.1 Command byte

The command byte is the first byte to follow the address byte during a write transmission.

It is used as a pointer to determine which of the following registers will be written or read.

Table 4.

Command byte

Register

Command

0

1

2

3

4

5

6

7

Input port 0

Input port 1

Output port 0

Output port 1

Polarity inversion port 0

Polarity inversion port 1

Configuration port 0

Configuration port 1

PCA9539_PCA9539R

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Product data sheet

Rev. 6 — 6 February 2013

6 of 37

PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

6.2.2 Registers 0 and 1: Input port registers

This register is an input-only port. It reflects the incoming logic levels of the pins,

regardless of whether the pin is defined as an input or an output by Register 3. Writes to

this register have no effect.

The default value ‘X’ is determined by the externally applied logic level.

Table 5.

Bit

Input port 0 register

7

I0.7

X

6

I0.6

X

5

I0.5

X

4

I0.4

X

3

I0.3

X

2

I0.2

X

1

I0.1

X

0

I0.0

X

Symbol

Default

Table 6.

Bit

Input port 1 register

7

I1.7

X

6

I1.6

X

5

I1.5

X

4

I1.4

X

3

I1.3

X

2

I1.2

X

1

I1.1

X

0

I1.0

X

Symbol

Default

6.2.3 Registers 2 and 3: Output port registers

This register is an output-only port. It reflects the outgoing logic levels of the pins defined

as outputs by Registers 6 and 7. Bit values in this register have no effect on pins defined

as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling

the output selection, not the actual pin value.

Table 7.

Bit

Output port 0 register

7

O0.7

1

6

O0.6

1

5

O0.5

1

4

O0.4

1

3

O0.3

1

2

O0.2

1

O0.1

1

0

O0.0

1

Symbol

Default

Table 8.

Bit

Output port 1 register

7

O1.7

1

6

O1.6

1

5

O1.5

1

4

O1.4

1

3

O1.3

1

2

O1.2

1

O1.1

1

0

O1.0

1

Symbol

Default

6.2.4 Registers 4 and 5: Polarity inversion registers

This register allows the user to invert the polarity of the Input port register data. If a bit in

this register is set (written with ‘1’), the Input port data polarity is inverted. If a bit in this

register is cleared (written with a ‘0’), the Input port data polarity is retained.

Table 9.

Bit

Polarity inversion port 0 register

7

N0.7

0

6

N0.6

0

5

N0.5

0

4

N0.4

0

3

N0.3

0

2

N0.2

0

1

N0.1

0

N0.0

0

Symbol

Default

Table 10. Polarity inversion port 1 register

Bit

7

N1.7

0

6

N1.6

0

5

N1.5

0

4

N1.4

0

3

N1.3

0

2

N1.2

0

1

N1.1

0

N1.0

0

Symbol

Default

PCA9539_PCA9539R

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Product data sheet

Rev. 6 — 6 February 2013

7 of 37

PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

6.2.5 Registers 6 and 7: Configuration registers

This register configures the directions of the I/O pins. If a bit in this register is set (written

with ‘1’), the corresponding port pin is enabled as an input with high-impedance output

driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is

enabled as an output. At reset, the device's ports are inputs.

Table 11. Configuration port 0 register

Bit

7

C0.7

1

6

C0.6

1

5

C0.5

1

4

C0.4

1

3

C0.3

1

2

C0.2

1

C0.1

1

0

C0.0

1

Symbol

Default

Table 12. Configuration port 1 register

Bit

7

C1.7

1

6

C1.6

1

5

C1.5

1

4

C1.4

1

3

C1.3

1

2

C1.2

1

C1.1

1

0

C1.0

1

Symbol

Default

6.3 Power-on reset

When power is applied to V_DD, an internal power-on reset holds the PCA9539; PCA9539R

in a reset condition until V_DDhas reached V_POR. At that point, the reset condition is

released and the PCA9539; PCA9539R registers and SMBus state machine will initialize

to their default states. Thereafter, V_DDmust be lowered below 0.2 V to reset the device.

For a power reset cycle, V_DDmust be lowered below 0.2 V and then restored to the

operating voltage.

6.4 RESET input

A reset can be accomplished by holding the RESET pin LOW for a minimum of t_w(rst). In

the PCA9539 the registers and SMBus/I²C-bus state machine will be held in their default

state until the RESET input is once again HIGH. This input typically requires a pull-up to

V

_DD. In the PCA9539R, only the device state machine is initialized. The internal

general-purpose registers remain unchanged. Using the PCA9539R hardware reset pin

will only reset the I²C-bus interface should it be stuck LOW to regain access to the

I²C-bus. This allows the I/O pins to retain their last configured state so that they can keep

any lines in their previously defined state and not cause system errors while the I²C-bus is

being restored.

6.5 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a

high-impedance input. The input voltage may be raised above V_DDto a maximum of 5.5 V.

If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of

the Output port register. Care should be exercised if an external voltage is applied to an

I/O configured as an output because of the low-impedance path that exists between the

pin and either V_DDor V_SS

.

PCA9539_PCA9539R

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Product data sheet

Rev. 6 — 6 February 2013

8 of 37

PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

data from

output port

shift register

register data

configuration

register

V

DD

data from

shift register

Q1

D

Q

FF

write

configuration

pulse

D

Q

CK

Q

FF

I/O pin

Q2

write pulse

CK

V

input port

register

SS

output port

register

D

Q

input port

register data

FF

read pulse

CK

to INT

polarity inversion

register

data from

shift register

polarity

inversion

register data

D

Q

FF

write polarity

pulse

CK

002aad723

At power-on reset, all registers return to default values.

Fig 6. Simplified schematic of I/Os

6.6 Bus transactions

6.6.1 Writing to the port registers

Data is transmitted to the PCA9539; PCA9539R by sending the device address and

setting the least significant bit to a logic 0 (see Figure 5 “PCA9539; PCA9539R device

address”). The command byte is sent after the address and determines which register will

receive the data following the command byte.

The eight registers within the PCA9539; PCA9539R are configured to operate as four

register pairs. The four pairs are Input ports, Output ports, Polarity inversion ports, and

Configuration ports. After sending data to one register, the next data byte will be sent to

the other register in the pair (see Figure 7 and Figure 8). For example, if the first byte is

sent to Output port 1 (register 3), then the next byte will be stored in Output port 0

(register 2). There is no limitation on the number of data bytes sent in one write

transmission. In this way, each 8-bit register may be updated independently of the other

registers.

PCA9539_PCA9539R

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Product data sheet

Rev. 6 — 6 February 2013

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PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

6.6.2 Reading the port registers

In order to read data from the PCA9539; PCA9539R, the bus master must first send the

PCA9539; PCA9539R address with the least significant bit set to a logic 0 (see Figure 5

“PCA9539; PCA9539R device address”). The command byte is sent after the address and

determines which register will be accessed. After a restart, the device address is sent

again, but this time the least significant bit is set to a logic 1. Data from the register

defined by the command byte will then be sent by the PCA9539; PCA9539R (see

Figure 9, Figure 10 and Figure 11). Data is clocked into the register on the falling edge of

the acknowledge clock pulse. After the first byte is read, additional bytes may be read but

the data will now reflect the information in the other register in the pair. For example, if you

read Input port 1, then the next byte read would be Input port 0. There is no limitation on

the number of data bytes received in one read transmission but the final byte received, the

bus master must not acknowledge the data.

slave address

A1 A0

(cont.)

SDA

S

1

0

1

0

A

COMMAND BYTE

A

START condition

R/W

acknowledge

from slave

acknowledge

from slave

data from lower or

upper byte of register

data from upper or

lower byte of register

slave address

A1 A0

MSB

LSB

MSB

LSB

(cont.)

S

1

0

1

A

DATA (first byte)

A

DATA (last byte)

NA P

(repeated)

START condition

R/W

acknowledge

from master

no acknowledge STOP

from master condition

acknowledge

from slave

at this moment master-transmitter becomes master-receiver

and slave-receiver becomes slave-transmitter

002aad727

Remark: Transfer can be stopped at any time by a STOP condition.

Fig 9. Read from register

PCA9539_PCA9539R

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Product data sheet

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PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

6.6.3 Interrupt output

The open-drain interrupt output is activated when one of the port pins changes state and

the pin is configured as an input. The interrupt is deactivated when the input returns to its

previous state or the Input port register is read (see Figure 10). A pin configured as an

output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt

caused by Port 0 will not be cleared by a read of Port 1 or the other way around.

Remark: Changing an I/O from an output to an input may cause a false interrupt to occur

if the state of the pin does not match the contents of the Input port register.

7. Characteristics of the I²C-bus

The I²C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

7.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 12).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 12. Bit transfer

7.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is defined as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P) (see Figure 13).

SDA

SCL

S

P

STOP condition

START condition

mba608

Fig 13. Definition of START and STOP conditions

PCA9539_PCA9539R

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Product data sheet

Rev. 6 — 6 February 2013

14 of 37

PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

7.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 14).

SDA

SCL

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

2

SLAVE

RECEIVER

MASTER

TRANSMITTER

I C-BUS

MULTIPLEXER

SLAVE

002aaa966

Fig 14. System configuration

7.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold

time must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

data output

by transmitter

not acknowledge

data output

by receiver

acknowledge

SCL from master

1

2

8

9

S

clock pulse for

START

condition

acknowledgement

002aaa987

Fig 15. Acknowledgement on the I²C-bus

PCA9539_PCA9539R

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PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

8. Application design-in information

V

DD

(5 V)

SUB-SYSTEM 1

(e.g., temp sensor)

10 kΩ

2 kΩ

100 kΩ

(×3)

V

DD

V

DD

INT

MASTER

CONTROLLER

PCA9539

SCL

SDA

SCL

IO0_0

IO0_1

IO0_2

IO0_3

IO0_4

IO0_5

SUB-SYSTEM 2

(e.g., counter)

SDA

INT

RESET

A

RESET

V

SS

controlled

switch

(e.g., CBT device)

enable

B

IO0_6

IO0_7

IO1_0

IO1_1

IO1_2

IO1_3

IO1_4

IO1_5

IO1_6

IO1_7

SUB-SYSTEM 3

(e.g., alarm system)

10 DIGIT

NUMERIC

KEYPAD

ALARM

V

DD

A1

A0

V

SS

002aad730

Device address configured as 1110 100X for this example.

IO0_0, IO0_2, IO0_3 configured as outputs.

IO0_1, IO0_4, IO0_5 configured as inputs.

IO0_6, IO0_7 and (IO1_0 to IO1_7) configured as inputs.

Fig 16. Typical application

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Product data sheet

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PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

8.1 Minimizing I_DDwhen the I/Os are used to control LEDs

When the I/Os are used to control LEDs, they are normally connected to V_DDthrough a

resistor as shown in Figure 16. Since the LED acts as a diode, when the LED is off the I/O

V_Iis about 1.2 V less than V_DD. The supply current, I_DD, increases as V_Ibecomes lower

than V_DD

.

Designs needing to minimize current consumption, such as battery power applications,

should consider maintaining the I/O pins greater than or equal to V_DDwhen the LED is off.

Figure 17 shows a high value resistor in parallel with the LED. Figure 18 shows V_DDless

than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O V_I

at or above V_DDand prevents additional supply current consumption when the LED is off.

3.3 V

5 V

V

DD

V

100 kΩ

V

DD

LED

LEDn

002aac189

002aac190

Fig 17. High value resistor in parallel with

the LED

Fig 18. Device supplied by a lower voltage

9. Limiting values

Table 13. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

Conditions

Min

Max

Unit

V

V_DD

V_I/O

I_O

supply voltage

0.5

+6.0

voltage on an input/output pin

output current

V_SS 0.5 6

V

on an I/O pin

-

50

mA

mW

C

I_I

input current

-

20

160

200

+150

I_DD

I_SS

P_tot

T_stg

T_amb

supply current

-

ground supply current

total power dissipation

storage temperature

ambient temperature

-

65

operating

all devices except PCA9539PW/Q900

PCA9539PW/Q900

40

-

+85

+125

125

C

T_j(max)

maximum junction temperature

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Product data sheet

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PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

10. Static characteristics

Table 14. Static characteristics for all devices except PCA9539PW/Q900

_DD= 2.3 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; unless otherwise specified.

V

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

supply voltage

supply current

2.3

-

5.5

V

I_DD

Operating mode; V_DD= 5.5 V;

135

200

A

no load; f_SCL= 100 kHz; I/O = inputs

I_stb

standby current

Standby mode; V_DD= 5.5 V; no load;

V_I= V_SS; f_SCL= 0 kHz; I/O = inputs

-

0.25

1.5

1

A

V

Standby mode; V_DD= 5.5 V; no load;

V_I= V_DD; f_SCL= 0 kHz; I/O = inputs

1

V_POR

power-on reset voltage^[1]

no load; V_I= V_DDor V_SS

1.65

Input SCL; input/output SDA

V_IL

V_IH

I_OL

I_L

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

leakage current

0.5

-

+0.3V_DD

V

0.7V_DD

-

5.5

-

V

V_OL= 0.4 V

V_I= V_DD= V_SS

V_I= V_SS

3

-

mA

A

pF

1

-

+1

10

C_i

input capacitance

6

I/Os

V_IL

V_IH

I_OL

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

0.5

0.7V_DD

8

-

+0.3V_DD

V

-

5.5

-

V

[2]

[3]

V_DD= 2.3 V to 5.5 V; V_OL= 0.5 V

V_DD= 2.3 V to 5.5 V; V_OL= 0.7 V

I_OH= 8 mA; V_DD= 2.3 V

I_OH= 10 mA; V_DD= 2.3 V

I_OH= 8 mA; V_DD= 3.0 V

I_OH= 10 mA; V_DD= 3.0 V

I_OH= 8 mA; V_DD= 4.75 V

I_OH= 10 mA; V_DD= 4.75 V

V_DD= 5.5 V; V_I= V_DD

9

mA

V

10

1.8

1.7

2.6

2.5

4.1

4.0

-

11

-

V_OH

HIGH-level output voltage

-

V

-

V

-

V

-

V

-

V

I_LIH

I_LIL

C_i

HIGH-level input leakage current

LOW-level input leakage current

input capacitance

-

1

1

5

A

pF

V_DD= 5.5 V; V_I= V_SS

-

3.7

C_o

output capacitance

-

Interrupt INT

I_OL

LOW-level output current

V_OL= 0.4 V

3

-

mA

Select inputs A0, A1 and RESET

V_IL

V_IH

I_LI

LOW-level input voltage

HIGH-level input voltage

input leakage current

0.5

0.7V_DD

1

-

+0.3V_DD

5.5

V

+1

A

[1] V_DDmust be lowered to 0.2 V for at least 5 s in order to reset part.

[2] Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a

maximum current of 100 mA for a device total of 200 mA.

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PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

[3] The total current sourced by all I/Os must be limited to 160 mA (80 mA for IO0_0 through IO0_7 and 80 mA for IO1_0 through IO1_7).

Table 15. Static characteristics for PCA9539PW/Q900

V_DD= 5.0 V  10 %; V_SS= 0 V; T_amb= 40 C to +125 C; unless otherwise specified.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

supply voltage

supply current

4.5

-

5.5

V

I_DD

Operating mode; V_DD= 5.5 V;

135

200

A

no load; f_SCL= 100 kHz; I/O = inputs

I_stb

standby current

Standby mode; V_DD= 5.5 V; no load;

V_I= V_SS; f_SCL= 0 kHz; I/O = inputs

-

0.25

1.5

1

A

V

Standby mode; V_DD= 5.5 V; no load;

V_I= V_DD; f_SCL= 0 kHz; I/O = inputs

1

V_POR

power-on reset voltage^[1]

no load; V_I= V_DDor V_SS

1.65

Input SCL; input/output SDA

V_IL

V_IH

I_OL

I_L

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

leakage current

0.5

-

+0.3V_DD

V

0.7V_DD

-

5.5

-

V

V_OL= 0.4 V

V_I= V_DD= V_SS

V_I= V_SS

3

-

mA

A

pF

1

-

+1

10

C_i

input capacitance

6

I/Os

V_IL

V_IH

I_OL

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

0.5

-

+0.3V_DD

V

0.7V_DD

-

5.5

-

V

[2]

[3]

V_DD= 4.5 V; V_OL= 0.5 V

V_DD= 4.5 V; V_OL= 0.7 V

I_OH= 8 mA; V_DD= 4.5 V

I_OH= 10 mA; V_DD= 4.5 V

V_DD= 5.5 V; V_I= V_DD

8

9

mA

V

10

4.1

4.0

-

11

-

V_OH

HIGH-level output voltage

-

V

I_LIH

I_LIL

C_i

HIGH-level input leakage current

LOW-level input leakage current

input capacitance

-

1

1

5

A

pF

V_DD= 5.5 V; V_I= V_SS

-

3.7

C_o

output capacitance

-

Interrupt INT

I_OL

LOW-level output current

V_OL= 0.4 V

3

-

mA

Select inputs A0, A1 and RESET

V_IL

V_IH

I_LI

LOW-level input voltage

HIGH-level input voltage

input leakage current

0.5

0.7V_DD

1

-

+0.3V_DD

5.5

V

+1

A

[1] V_DDmust be lowered to 0.2 V for at least 5 s in order to reset part.

[2] Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a

maximum current of 100 mA for a device total of 200 mA.

[3] The total current sourced by all I/Os must be limited to 160 mA (80 mA for IO0_0 through IO0_7 and 80 mA for IO1_0 through IO1_7).

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Product data sheet

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PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

11. Dynamic characteristics

Table 16. Dynamic characteristics

Symbol Parameter

Conditions

Standard-mode

I²C-bus

Fast-mode I²C-bus Unit

Min

0

Max

100

-

Min

0

Max

400

-

f_SCL

t_BUF

SCL clock frequency

kHz

bus free time between a STOP and

START condition

4.7

1.3

s

t_HD;STA

t_SU;STA

hold time (repeated) START condition

4.0

4.7

-

0.6

-

s

set-up time for a repeated START

condition

t_SU;STO

t_VD;ACK

t_HD;DAT

t_VD;DAT

t_SU;DAT

t_LOW

t_HIGH

t_f

set-up time for STOP condition

data valid acknowledge time

data hold time

4.0

0.3

0

-

0.6

-

0.9

-

s

ns

s

ns

[1]

[2]

3.45

0.1

-

0

data valid time

300

250

4.7

4.0

-

50

-

data set-up time

-

100

-

LOW period of the SCL clock

HIGH period of the SCL clock

fall time of both SDA and SCL signals

rise time of both SDA and SCL signals

1.3

0.6

-

[3]

300

1000

50

20 + 0.1C_b

-

300

50

t_r

-

t_SP

pulse width of spikes that must be

suppressed by the input filter

-

Port timing

[4]

t_v(Q)

t_su(D)

t_h(D)

data output valid time

-

150

1

200

-

150

1

200

ns

s

data input set-up time

data input hold time

-

Interrupt timing

t_{v(INT_N)}

valid time on pin INT

-

4

-

4

s

t_{rst(INT_N)}reset time on pin INT

RESET timing

t_w(rst)

t_rec(rst)

t_rst

reset pulse width

reset recovery time

reset time

4

0

-

4

0

-

ns

[5][6]

400

[1] t_VD;ACK= time for acknowledgement signal from SCL LOW to SDA (out) LOW.

[2] t_VD;DAT= minimum time for SDA data out to be valid following SCL LOW.

[3] C_b= total capacitance of one bus line in pF.

[4] t_v(Q)measured from 0.7V_DDon SCL to 50 % I/O output.

[5] Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.

[6] Upon reset, the full delay will be the sum of t_rstand the RC time constant of the SDA bus.

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Product data sheet

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PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

0.7 × V

0.3 × V

DD

SDA

DD

t

SP

t

r

f

HD;STA

BUF

t

LOW

0.7 × V

0.3 × V

DD

SCL

DD

t

SU;STO

HD;STA

SU;STA

t

SU;DAT

HD;DAT

HIGH

P

S

Sr

P

002aaa986

Fig 19. Definition of timing on the I²C-bus

ACK or read cycle

START

SCL

SDA

30 %

t

rst

RESET

50 %

t

rec(rst)

w(rst)

t

rst

after reset,

I/Os reconfigured

as inputs

IOn

50 %

002aad732

Fig 20. Definition of RESET timing in PCA9539

ACK or read cycle

START

SCL

SDA

30 %

t

rst

RESET

50 %

t

rec(rst)

t

w(rst)

t

rst

after reset, I/Os unchanged;

device state machine reset

IOn

50 %

002aad733

Fig 21. Definition of RESET timing in PCA9539R

PCA9539_PCA9539R

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Product data sheet

Rev. 6 — 6 February 2013

21 of 37

PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

70 %

SCL

SDA

input

INT

2

1

0

A

P

30 %

t

h(Q)

su(D)

50 %

t

v(INT_N)

t

rst(INT_N)

002aad734

Fig 22. Expanded view of read input port register

70 %

SCL

SDA

2

1

0

A

P

t

v(Q)

output

50 %

002aad735

Fig 23. Expanded view of write to output port register

START

condition

(S)

bit 7

MSB

(A7)

STOP

condition

(P)

bit 6

(A6)

bit 1

(D1)

bit 0

(D0)

acknowledge

(A)

protocol

t

HIGH

SU;STA

LOW

1 / f

SCL

0.7 × V

0.3 × V

DD

SCL

SDA

DD

t

BUF

f

t

r

0.7 × V

0.3 × V

DD

t

HD;DAT

VD;DAT

VD;ACK

SU;STO

HD;STA

SU;DAT

002aab285

Rise and fall times refer to V_ILand V_IH.

Fig 24. I²C-bus timing diagram

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Product data sheet

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PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

12. Test information

V

DD

open

GND

V

R

500 Ω

DD

L

V

O

I

PULSE

DUT

GENERATOR

C

50 pF

L

R

T

002aab284

R_L= load resistor.

C_L= load capacitance includes jig and probe capacitance.

R_T= termination resistance should be equal to the output impedance of Z_oof the pulse generators.

Fig 25. Test circuitry for switching times

R

L

2V

S1

DD

from output under test

open

GND

500 Ω

C

50 pF

R

L

500 Ω

L

002aac226

Fig 26. Load circuit

Table 17. Test data

Test

Load

C_L

Switch

R_L

500 

t_v(Q)

50 pF

2  V_DD

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Product data sheet

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PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

13. Package outline

SO24: plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

D

E

A

X

c

H

v

M

A

E

y

Z

24

13

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

12

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

15.6

15.2

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25 0.25

0.01

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.61

0.014 0.009 0.60

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT137-1

075E05

MS-013

Fig 27. Package outline SOT137-1 (SO24)

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PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm

SOT355-1

D

E

A

X

c

H

v

M

A

y

E

Z

13

24

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

1

12

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

7.9

7.7

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT355-1

MO-153

Fig 28. Package outline SOT355-1 (TSSOP24)

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Product data sheet

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PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.85 mm

SOT616-1

B

A

D

terminal 1

index area

A

1

E

c

detail X

e

1

C

1/2 e

y

C

1

e

v

M

C

A

B

b

7

12

w

L

13

6

e

E

h

2

1/2 e

1

18

terminal 1

index area

24

19

X

D

h

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

max.

(1)

UNIT

mm

A

b

c

E

e

y

D

E

L

v

w

y

1

h

1

2

h

0.05 0.30

0.00 0.18

4.1

3.9

2.25

1.95

4.1

3.9

2.25

1.95

0.5

0.3

0.05

0.1

1

0.2

0.5

2.5

0.1 0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

01-08-08

02-10-22

SOT616-1

- - -

MO-220

- - -

Fig 29. Package outline SOT616-1 (HVQFN24)

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Product data sheet

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PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

14. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate precautions are taken as

described in JESD625-A or equivalent standards.

15. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

15.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

15.3 Wave soldering

Key characteristics in wave soldering are:

PCA9539_PCA9539R

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Product data sheet

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NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

15.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 30) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 18 and 19

Table 18. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 19. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 30.

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Product data sheet

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PCA9539; PCA9539R

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16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 30. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

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Product data sheet

Rev. 6 — 6 February 2013

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16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

16. Soldering: PCB footprints

Footprint information for reflow soldering of SO24 package

SOT137-1

Hx

Gx

P2

(0.125)

Hy Gy

By Ay

C

D2 (4x)

P1

D1

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ay

By

C

D1

D2

Gx

Gy

Hx

Hy

1.270 1.320 11.200 6.400 2.400 0.700 0.800 15.120 8.600 17.000 11.450

sot137-1_fr

Fig 31. PCB footprint for SOT137-1 (SO24); reflow soldering

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Product data sheet

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16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

Footprint information for reflow soldering of TSSOP24 package

SOT355-1

Hx

Gx

P2

(0.125)

Hy Gy

By Ay

C

D2 (4x)

P1

D1

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

occupied area

DIMENSIONS in mm

P1 P2 Ay

By

C

D1

D2

Gx

Gy

Hx

Hy

0.650 0.750 7.200 4.500 1.350 0.400 0.600 8.200 5.300 8.600 7.450

sot355-1_fr

Fig 32. PCB footprint for SOT355-1 (TSSOP24); reflow soldering

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Product data sheet

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16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

Footprint information for reflow soldering of HVQFN24 package

SOT616-1

Hx

Gx

D

P

0.025

C

(0.105)

SPx

SPy

nSPx

Hy Gy

SLy By

Ay

nSPy

SPx tot

SLx

Bx

Ax

Generic footprint pattern

Refer to the package outline drawing for actual layout

solder land

solder paste deposit

solder land plus solder paste

occupied area

nSPx nSPy

2

Dimensions in mm

Ax

P

Ay

Bx

By

C

D

SLx

SLy

SPx tot

1.200

SPy tot

1.200

SPx

SPy

Gx

Gy

Hx

Hy

0.500 5.000 5.000 3.200 3.200 0.900 0.240 2.100 2.100

0.450 0.450 4.300 4.300 5.250 5.250

07-05-07

Issue date

sot616-1_fr

09-06-15

Fig 33. PCB footprint for SOT616-1 (HVQFN24); reflow soldering

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17. Abbreviations

Table 20. Abbreviations

Acronym

Description

ACPI

CBT

Advanced Configuration and Power Interface

Cross-Bar Technology

Charged-Device Model

Complementary Metal-Oxide Semiconductor

ElectroStatic Discharge

Field-Effect Transistor

Flip-Flop

CDM

CMOS

ESD

FET

FF

GPIO

HBM

I²C-bus

I/O

General Purpose Input/Output

Human Body Model

Inter-Integrated Circuit bus

Input/Output

LED

Light Emitting Diode

MM

Machine Model

SMBus

System Management Bus

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Product data sheet

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16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

18. Revision history

Table 21. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

PCA9539_PCA9539R v.6 20130206

Product data sheet

-

PCA9539_PCA9539R v.5

Modifications:

• Section 2 “Features and benefits”:

–

second bullet item: added phrase “ (5.0 V  10 % for PCA9539PW/Q900 AEC-Q100

compliant devices)”

–

thirteenth bullet item: deleted phrase “200 V MM per JESD22-A115”

• Table 1 “Ordering information”:

–

added column “Topside marking”

–

added type number PCA9539PW/Q900 (and Table note [1])

• Section 3.1 “Ordering options” re-written

• Table 13 “Limiting values”: T_amb: added separate row for PCA9539PW/Q900 device limits

• Table 14: appended phrase “for all devices except PCA9539PW/Q900” to table title

• Added (new) Table 15 “Static characteristics for PCA9539PW/Q900”

• Figure 19 “Definition of timing on the I²C-bus” modified: added 0.3  V_DDand 0.7  V_DD

reference lines

• Figure 24 “I²C-bus timing diagram” modified: added 0.3  V_DDand 0.7  V_DDreference

lines

• Added Section 16 “Soldering: PCB footprints”

PCA9539_PCA9539R v.5 20080728

Product data sheet

-

PCA9539_PCA9539R v.4

PCA9539 v.3

PCA9539_PCA9539R v.4 20080519

PCA9539 v.3

20060921

20040930

PCA9539 v.2

PCA9539 v.1

(9397 750 14048)

PCA9539 v.1

20040827

Product data sheet

-

(9397 750 12898)

PCA9539_PCA9539R

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Product data sheet

Rev. 6 — 6 February 2013

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16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

19.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

19.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

PCA9539_PCA9539R

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Product data sheet

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35 of 37

PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

19.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP B.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCA9539_PCA9539R

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Product data sheet

Rev. 6 — 6 February 2013

36 of 37

PCA9539; PCA9539R

NXP Semiconductors

16-bit I²C-bus and SMBus low power I/O port with interrupt and reset

21. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

18

Revision history . . . . . . . . . . . . . . . . . . . . . . . 34

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

19

Legal information . . . . . . . . . . . . . . . . . . . . . . 35

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 35

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 36

19.1

19.2

19.3

19.4

3

3.1

4

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

20

21

Contact information . . . . . . . . . . . . . . . . . . . . 36

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6

6.1

6.2

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.3

6.4

6.5

6.6

6.6.1

6.6.2

6.6.3

Functional description . . . . . . . . . . . . . . . . . . . 6

Device address. . . . . . . . . . . . . . . . . . . . . . . . . 6

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6

Registers 0 and 1: Input port registers . . . . . . . 7

Registers 2 and 3: Output port registers. . . . . . 7

Registers 4 and 5: Polarity inversion registers . 7

Registers 6 and 7: Configuration registers . . . . 8

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8

RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . . 8

I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Bus transactions. . . . . . . . . . . . . . . . . . . . . . . . 9

Writing to the port registers. . . . . . . . . . . . . . . . 9

Reading the port registers . . . . . . . . . . . . . . . 11

Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 14

7

Characteristics of the I²C-bus . . . . . . . . . . . . 14

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

START and STOP conditions . . . . . . . . . . . . . 14

System configuration . . . . . . . . . . . . . . . . . . . 15

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15

7.1

7.1.1

7.2

7.3

8

8.1

Application design-in information . . . . . . . . . 16

Minimizing I_DDwhen the I/Os are

used to control LEDs . . . . . . . . . . . . . . . . . . . 17

9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17

Static characteristics. . . . . . . . . . . . . . . . . . . . 18

Dynamic characteristics . . . . . . . . . . . . . . . . . 20

Test information. . . . . . . . . . . . . . . . . . . . . . . . 23

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 24

Handling information. . . . . . . . . . . . . . . . . . . . 27

10

11

12

13

14

15

Soldering of SMD packages . . . . . . . . . . . . . . 27

Introduction to soldering . . . . . . . . . . . . . . . . . 27

Wave and reflow soldering . . . . . . . . . . . . . . . 27

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 27

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 28

15.1

15.2

15.3

15.4

16

17

Soldering: PCB footprints. . . . . . . . . . . . . . . . 30

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 33

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 6 February 2013

Document identifier: PCA9539_PCA9539R


型号：	PCA9539RPW,118
厂家：	NXP
描述：	PCA9539; PCA9539R - 16-bit I²C-bus and SMBus low power I/O port with interrupt and reset TSSOP2 24-Pin PC 光电二极管外围集成电路
文件：	总37页 (文件大小：389K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCA9539RPW,118 [NXP]

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