PCA9540BD_技术文档

INTEGRATED CIRCUITS

PCA9540B

2-channel I²C multiplexer

Product data sheet

2004 Sep 29

Supersedes data of 2004 Apr 13

Philips

Semiconductors

Philips Semiconductors

Product data sheet

2-channel I²C multiplexer

PCA9540B

FEATURES

• 1-of-2 bi-directional translating multiplexer

2

• I C interface logic; compatible with SMBus standards

2

• Channel selection via I C-bus

• Power up with all multiplexer channels deselected

• Low Rds switches

ON

• Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and

5 V buses

PIN CONFIGURATION

• No glitch on power-up

• Supports hot insertion

• Low stand-by current

• Operating power supply voltage range of 2.3 V to 5.5 V

• 5 V tolerant Inputs

SCL

SDA

1

2

3

4

8

7

6

5

SC1

SD1

V

SS

DD

• 0 to 400 kHz clock frequency

SC0

SD0

• ESD protection exceeds 2000 V HBM per JESD22-A114,

200 V MM per JESD22-A115 and 1000 V per JESD22-C101

• Latch-up testing is done to JESDEC Standard JESD78 which

SW00491

exceeds 100 mA

Figure 1. Pin configuration

• Packages Offered: SO8, TSSOP8

PIN DESCRIPTION

DESCRIPTION

The PCA9540B is a 1-of-2 bi-directional translating multiplexer,

SYMBOL

FUNCTION

Serial clock line

NUMBER

2

controlled via the I C-bus. The SCL/SDA upstream pair fans out to

1

2

3

4

5

6

7

8

SCL

SDA

two SCx/SDx downstream pairs, or channels. Only one SCx/SDx

channel is selected at a time, determined by the contents of the

programmable control register.

Serial data line

Supply voltage

Serial data 0

Serial clock 0

Supply ground

Serial data 1

Serial clock 1

V

DD

A power-on reset function puts the registers in their default state and

SD0

SC0

2

initializes the I C state machine with no channels selected.

The pass gates of the multiplexer are constructed such that the V

pin can be used to limit the maximum high voltage which will be

passed by the PCA9540B. This allows the use of different bus

voltages on each SCx/SDx pair, so that 1.8 V, 2.5, or 3.3 V parts can

communicate with 5 V parts without any additional protection.

External pull-up resistors can pull the bus up to the desired voltage

level for this channel. All I/O pins are 5 V tolerant.

DD

V

SS

SD1

SC1

The PCA9540B has replaced the PCA9540 and all designs must

migrate to the PCA9540B. PCA9540B samples can be requested

from www.philipslogic.com/products/I2Cmuxes/.

ORDERING INFORMATION

PACKAGES

8-Pin Plastic SO

8-Pin Plastic TSSOP

TEMPERATURE RANGE

–40 °C to +85 °C

ORDER CODE

TOPSIDE MARK

PA9540B

DRAWING NUMBER

SOT96-1

PCA9540BD

–40 °C to +85 °C

PCA9540BDP

9540B

SOT505-1

Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.

2

2004 Sep 29

Philips Semiconductors

Product data sheet

2-channel I²C multiplexer

PCA9540B

BLOCK DIAGRAM

PCA9540B

SD0

SD1

SC0

SC1

SWITCH CONTROL LOGIC

V

SS

Power-on

Reset

V

DD

SCL

SDA

2

Input

Filter

I C-Bus

Control

SW02211

Figure 2. Block diagram

3

2004 Sep 29

Philips Semiconductors

Product data sheet

2-channel I²C multiplexer

PCA9540B

DEVICE ADDRESSING

POWER-ON RESET

Following a START condition the bus master must output the

address of the slave it is accessing. The address of the PCA9540B

is shown in Figure 3.

When power is applied to V , an internal Power-On Reset holds

DD

the PCA9540B in a reset condition until V has reached V

. At

DD

POR

this point, the reset condition is released and the PCA9540B

2

registers and I C state machine are initialized to their default states,

all zeroes causing all the channels to be deselected. Thereafter,

V

DD

must be lowered below 0.2 V to reset the device.

1

0

R/W

FIXED

SW00713

VOLTAGE TRANSLATION

The pass gate transistors of the PCA9540B are constructed such

Figure 3. Slave address

that the V voltage can be used to limit the maximum voltage that

DD

2

will be passed from one I C bus to another.

The last bit of the slave address defines the operation to be

performed. When set to logic 1, a read is selected while a logic 0

selects a write operation.

V

vs. V

DD

pass

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

CONTROL REGISTER

Following the successful acknowledgement of the slave address,

the bus master will send a byte to the PCA9540B which will be

stored in the Control Register. If multiple bytes are received by the

PCA9540B, it will save the last byte received. This register can be

MAXIMUM

TYPICAL

V

pass

2

written and read via the I C bus.

CHANNEL SELECTION BITS

(READ/WRITE)

MINIMUM

5.0

7

6

5

4

3

2

1

0

X

B2 B1 B0

2.0

2.5

3.0

3.5

4.0

4.5

5.5

V

DD

SW00839

SW00820

ENABLE BIT

Figure 4. Control register

Figure 5. V

voltage

pass

CONTROL REGISTER DEFINITION

A SCx/SDx downstream pair, or channel, is selected by the contents

of the control register. This register is written after the PCA9540B

has been addressed. The 2 LSBs of the control byte are used to

determine which channel is to be selected. When a channel is

selected, the channel will become active after a stop condition has

Figure 5 shows the voltage characteristics of the pass gate

transistors (note that the graph was generated using the data

specified in the DC Characteristics section of this datasheet). In

order for the PCA9540B to act as a voltage translator, the V

pass

voltage should be equal to, or lower than the lowest bus voltage. For

example, if the main bus was running at 5 V, and the downstream

2

been placed on the I C bus. This ensures that all SCx/SDx lines will

be in a HIGH state when the channel is made active, so that no

false conditions are generated at the time of connection.

buses were 3.3 V and 2.7 V, then V

should be equal to or below

pass

2.7 V to effectively clamp the downstream bus voltages. Looking at

Figure 5, we see that V (max.) will be at 2.7 V when the

pass

Table 1. Control Register; Write — Channel Selection/

Read — Channel Status

PCA9540B supply voltage is 3.5 V or lower so the PCA9540B

supply voltage could be set to 3.3 V. Pull-up resistors can then be

used to bring the bus voltages to their appropriate levels (see Figure

12).

D7 D6 D5 D4 D3 B2 B1 B0

COMMAND

X

0

X

0

X

0

X

0

X

0

1

0

X

0

1

0

X

0

1

X

0

No channel selected

Channel 0 enabled

Channel 1 enabled

No channel selected

More Information can be found in Application Note AN262 PCA954X

2

family of I C/SMBus multiplexers and switches.

No channel selected;

power-up default state

4

2004 Sep 29

Philips Semiconductors

Product data sheet

2-channel I²C multiplexer

PCA9540B

2

CHARACTERISTICS OF THE I C-BUS

Start and stop conditions

2

The I C-bus is for 2-way, 2-line communication between different ICs

Both data and clock lines remain HIGH when the bus is not busy. A

HIGH-to-LOW transition of the data line, while the clock is HIGH is

defined as the start condition (S). A LOW-to-HIGH transition of the

data line while the clock is HIGH is defined as the stop condition (P)

(see Figure 7).

or modules. The two lines are a serial data line (SDA) and a serial

clock line (SCL). Both lines must be connected to a positive supply

via a pull-up resistor when connected to the output stages of a device.

Data transfer may be initiated only when the bus is not busy.

Bit transfer

System configuration

One data bit is transferred during each clock pulse. The data on the

SDA line must remain stable during the HIGH period of the clock

pulse as changes in the data line at this time will be interpreted as

control signals (see FIgure 6).

A device generating a message is a ‘transmitter’, a device receiving

is the ‘receiver’. The device that controls the message is the

‘master’ and the devices which are controlled by the master are the

‘slaves’ (see Figure 8).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

SW00363

Figure 6. Bit transfer

SDA

SCL

S

P

START condition

STOP condition

SW00365

Figure 7. Definition of start and stop conditions

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

2

SLAVE

RECEIVER

I C

MASTER

TRANSMITTER

MULTIPLEXER

SLAVE

SW00366

Figure 8. System configuration

5

2004 Sep 29

Philips Semiconductors

Product data sheet

2-channel I²C multiplexer

PCA9540B

Acknowledge

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits

is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an

extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an

acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock

pulse, set-up and hold times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of

the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.

DATA OUTPUT

BY TRANSMITTER

not acknowledge

DATA OUTPUT

BY RECEIVER

acknowledge

SCL FROM

MASTER

1

2

8

9

S

clock pulse for

acknowledgement

START condition

SW00368

2

Figure 9. Acknowledgement on the I C-bus

SLAVE ADDRESS

CONTROL REGISTER

SDA

1

0

X

B2 B1 B0

A

P

S

0

A

start condition

R/W acknowledge

from slave

acknowledge

from slave

SW00800

Figure 10. WRITE control register

SLAVE ADDRESS

CONTROL REGISTER

last byte

SDA

1

0

S

1

A

X

B2 B1 B0 NA

P

start condition

R/W acknowledge

from slave

no acknowledge

from master

stop condition

SW00499

Figure 11. READ control register

6

2004 Sep 29

Philips Semiconductors

Product data sheet

2-channel I²C multiplexer

PCA9540B

TYPICAL APPLICATION

V

= 2.7 – 5.5 V

DD

V

= 3.3 V

DD

V = 2.7 – 5.5 V

SDA

SCL

SDA

SCL

SD0

SC0

CHANNEL 0

V = 2.7 – 5.5 V

2

I C/SMBus MASTER

SD1

SC1

CHANNEL 1

V

SS

PCA9540B

SW02212

Figure 12. Typical application

7

2004 Sep 29

Philips Semiconductors

Product data sheet

2-channel I²C multiplexer

PCA9540B

1, 2

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V).

SYMBOL

PARAMETER

DC supply voltage

CONDITIONS

RATING

UNIT

V

DD

–0.5 to +7.0

±20

V

I

DC input voltage

I

DC input current

mA

mW

°C

I

O

DC output current

±25

I

Supply current

±100

DD

I

SS

Supply current

±100

P

tot

total power dissipation

Storage temperature range

Operating ambient temperature

400

T

stg

–60 to +150

–40 to +85

T

amb

°C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.

DC CHARACTERISTICS

V

= 2.3 to 3.6 V; V = 0 V; T

= –40 to +85 °C; unless otherwise specified. (See page 9 for V = 3.6 to 5.5 V)

DD

SS

amb DD

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

Supply

V

Supply voltage

Supply current

2.3

—

3.6

50

V

DD

Operating mode; V = 3.6 V;

DD

no load; V = V or V ;

I

20

µA

I

DD

SS

DD

f

= 100 kHz

SCL

Standby mode; V = 3.6 V;

DD

I

Standby current

—

0.1

1.6

1

µA

stb

no load; V = V or V ; f = 0 kHz

I

DD

SS SLC

V

POR

Power-on reset voltage (Note 1)

no load; V = V or V

SS

2.1

V

I

DD

Input SCL; input/output SDA

V

LOW-level input voltage

HIGH-level input voltage

–0.5

—

7

0.3V

6

V

IL

DD

V

IH

0.7V

V

DD

V

= 0.4 V

= 0.6 V

3

6

—

+1

8

mA

µA

pF

OL

I

OL

LOW-level output current

OL

I

L

Leakage current

Input capacitance

V = V or V

SS

–1

—

I

DD

C

V = V

I SS

i

Pass Gate

V

= 3.0 to 3.6 V, V = 0.4 V, I = 15 mA

5

7

11

16

1.9

—

31

55

—

CC

O

R

Switch resistance

Ω

ON

= 2.3 to 2.7 V, V = 0.4 V, I = 10 mA

CC

O

V

= V = 3.3 V; I = –100 µA

swout

—

1.6

—

1.1

–1

—

swin

DD

V

= V = 3.0 to 3.6 V; I = –100 µA

swout

2.8

—

swin

DD

V

Pass

Switch output voltage

V

= V = 2.5 V; I = –100 µA

swout

1.5

—

swin

DD

= V = 2.3 to 2.7 V; I = –100 µA

swout

2.0

+1

5

swin

DD

I

Leakage current

V = V or V

—

µA

L

I

DD

SS

C

Input/output capacitance

V = V

I SS

2.5

pF

io

NOTE:

1. V must be lowered to 0.2 V in order to reset part.

DD

8

2004 Sep 29

Philips Semiconductors

Product data sheet

2-channel I²C multiplexer

PCA9540B

DC CHARACTERISTICS

V

= 3.6 to 5.5 V; V = 0 V; T

= –40 to +85 °C; unless otherwise specified. (See page 8 for V = 2.3 to 3.6 V)

DD

SS

amb DD

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

Supply

V

Supply voltage

Supply current

3.6

—

5.5

V

DD

Operating mode; V = 5.5 V;

DD

no load; V = V or V ;

I

65

100

µA

I

DD

SS

DD

f

= 100 kHz

SCL

Standby mode; V = 5.5 V;

DD

I

Standby current

—

0.3

1.6

1

µA

stb

no load; V = V or V

I

DD

SS

1

V

Power-on reset voltage

no load; V = V or V

2.1

V

POR

I

DD

SS

Input SCL; input/output SDA

V

LOW-level input voltage

HIGH-level input voltage

–0.5

—

6

0.3 V

6

V

IL

DD

V

IH

0.7 V

3

V

DD

V

= 0.4 V

= 0.6 V

—

1

mA

µA

mA

µA

pF

OL

I

OL

LOW-level output current

6

OL

I

IL

LOW-level input current

HIGH-level input current

Input capacitance

V = V

–1

—

I

SS

DD

SS

I

IH

V = V

1

I

C

V = V

8

i

I

Pass Gate

R

Switch resistance

V

= 4.5 to 5.5 V, V = 0.4 V, I = 15 mA

4

9

24

—

Ω

V

ON

CC

O

V

= V = 5.0 V; I = –100 µA

swout

—

3.6

—

swin

DD

V

Pass

Switch output voltage

V

swin

= V = 4.5 to 5.5 V; I = –100 µA

swout

2.6

–1

—

4.5

+1

5

V

DD

I

Leakage current

V = V or V

SS

—

µA

pF

L

I

DD

C

Input/output capacitance

V = V

I SS

2.5

io

NOTE:

1. V must be lowered to 0.2 V in order to reset part.

DD

9

2004 Sep 29

Philips Semiconductors

Product data sheet

2-channel I²C multiplexer

PCA9540B

AC CHARACTERISTICS

STANDARD-MODE

FAST-MODE

I C-BUS

2

I C-BUS

SYMBOL

PARAMETER

UNIT

MIN

—

MAX

MIN

MAX

1

t

Propagation delay from SDA to SD or SCL to SC

0.3

—

0

0.3

ns

kHz

µs

pd

n

f

SCL clock frequency

0

100

—

400

—

SCL

BUF

t

Bus free time between a STOP and START condition

4.7

1.3

Hold time (repeated) START condition

After this period, the first clock pulse is generated

t

4.0

—

0.6

—

µs

HD;STA

t

LOW period of the SCL clock

HIGH period of the SCL clock

Set-up time for a repeated START condition

Set-up time for STOP condition

Data hold time

4.7

4.0

4.7

4.0

—

1.3

0.6

—

µs

ns

µs

LOW

t

HIGH

—

SU;STA

SU;STO

t

—

2

t

0

3.45

—

0

0.9

—

HD;DAT

t

Data set-up time

250

—

100

20 + 0.1C

—

SU;DAT

3

t

R

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Capacitive load for each bus line

1000

300

400

300

400

b

t

F

—

C

—

b

Pulse width of spikes which must be suppressed

by the input filter

t

SP

—

50

—

50

ns

4

t

Data valid (HL)

—

1

0.6

1

—

1

0.6

1

µs

VD:DATL

4

t

Data valid (LH)

VD:DATH

t

Data valid Acknowledge

VD:ACK

NOTES:

1. Pass gate propagation delay is calculated from the 20 Ω typical R and and the 15 pF load capacitance.

ON

2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH

of the SCL signal) in order to bridge

min

the undefined region of the falling edge of SCL.

3. C = total capacitance of one bus line in pF.

b

4. Measurements taken with 1 kΩ pull-up resistor and 50 pF load.

SDA

t

R

t

F

t

SP

HD;STA

t

LOW

BUF

SCL

t

SU;STO

HD;STA

SU;STA

t

SU;DAT

HD;DAT

HIGH

P

S

Sr

P

SU00645

2

Figure 13. Definition of timing on the I C-bus

10

2004 Sep 29

Philips Semiconductors

Product data sheet

2-channel I²C multiplexer

PCA9540B

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

11

2004 Sep 29

Philips Semiconductors

Product data sheet

2-channel I²C multiplexer

PCA9540B

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm

SOT505-1

12

2004 Sep 29

Philips Semiconductors

Product data sheet

2-channel I²C multiplexer

PCA9540B

REVISION HISTORY

Rev

Date

Description

_2

20040929

Product data sheet (9397 750 13731). Supersedes data of 2004 Apr 13 (9397 750 12918).

Modifications:

• Section “Control Register Definition” on page 4: add “No channel selected; power-up default state” row to

bottom of Table 1.

• Section “Power-on Reset” on page 4 re-written.

• AC characterists table on page 10: Add Note 4 and references to it at parameters t

and t

.

VD;DATL

VD;DATH

_1

20040413

Product data (9397 750 12918).

13

2004 Sep 29

Philips Semiconductors

Product data sheet

2-channel I²C multiplexer

PCA9540B

2

Purchase of Philips I C components conveys a license under the Philips’ I C patent

2

to use the components in the I C system provided the system conforms to the

I C specifications defined by Philips. This specification can be ordered using the

2

code 9398 393 40011.

Data sheet status

Product

status

Definitions

[1]

Level

Data sheet status

[2] [3]

I

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

II

Preliminary data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

III

Product data

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given

in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no

representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree

to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described

or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated

viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys

nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,

copyright, or mask work right infringement, unless otherwise specified.

Koninklijke Philips Electronics N.V. 2004

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 09-04

9397 750 13731

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

14

2004 Sep 29


型号：	PCA9540BD
厂家：	NXP
描述：	2-channel I2C multiplexer 2通道I2C多路复用器解复用器逻辑集成电路光电二极管
文件：	总14页 (文件大小：142K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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