PCA9545 [NXP]
4-channel I2C switch with interrupt logic and reset; 与中断逻辑和复位4通道I2C开关
| 型号： | PCA9545 |
| 厂家： | 
NXP |
| 描述： | 4-channel I2C switch with interrupt logic and reset |
| 文件： | 总14页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PCA9545
4-channel I2C switch with interrupt logic
and reset
Product data
2002 Mar 28
Supersedes data of 2001 Nov 08
Philips
Semiconductors
Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
passed by the PCA9545. This allows the use of different bus
voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can
communicate with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5 V tolerant.
PIN CONFIGURATION
A0
A1
V
DD
1
2
3
4
5
6
7
8
20
19
18
FEATURES
SDA
SCL
RESET
INT0
• 1-of-4 bi-directional translating switches
2
17 INT
• I C interface logic; compatible with SMBus standards
SC3
16
SD0
• 4 active low interrupt inputs
• Active low interrupt output
• Active low reset input
• 2 address pins allowing up to 4 devices on the I C bus
• Channel selection via I C bus, in any combination
SD3
INT3
SC2
15
14
13
SC0
INT1
SD1
SC1
2
SD2
9
12
11
2
10
VSS
INT2
• Power up with all switch channels deselected
SW00762
• Low RDS switches
ON
Figure 1. Pin configuration
• Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses
PIN DESCRIPTION
• No glitch on power-up
• Supports hot insertion
• Low stand-by current
• Operating power supply voltage range of 2.3 V to 5.5 V
• 5 V tolerant Inputs
PIN
NUMBER
SYMBOL
FUNCTION
Address input 0
1
2
A0
A1
Address input 1
3
RESET
INT0
SD0
SC0
INT1
SD1
SC1
Active low reset input
Active low interrupt input 0
Serial data 0
• 0 to 400 kHz clock frequency
4
• ESD protection exceeds 2000 V HBM per JESD22-A114,
5
150 V MM per JESD22-A115 and 1000 V per JESD22-C101
6
Serial clock 0
• Latch-up testing is done to JESDEC Standard JESD78 which
7
Active low interrupt input 1
Serial data 1
exceeds 100 mA
• Package Offer: SO20, TSSOP20
8
9
Serial clock 1
DESCRIPTION
10
11
12
13
14
15
16
17
18
19
20
V
Supply ground
The PCA9545 is a quad bi-directional translating switch controlled
SS
2
via the I C bus. The SCL/SDA upstream pair fans out to four
INT2
SD2
SC2
INT3
SD3
SC3
INT
Active low interrupt input 2
Serial data 2
downstream pairs, or channels. Any individual SCx/SDx channel or
combination of channels can be selected, determined by the
contents of the programmable control register. Four interrupt inputs,
INT0 to INT3, one for each of the downstream pairs, are provided.
One interrupt output, INT, acts as an AND of the four interrupt
inputs.
Serial clock 2
Active low interrupt input 3
Serial data 3
Serial clock 3
An active-LOW reset input allows the PCA9545 to recover from a
situation where one of the downstream I C buses is stuck in a LOW
state. Pulling the RESET pin LOW resets the I C state machine and
causes all the channels to be deselected as does the internal power
on reset function.
2
Active low interrupt output
Serial clock line
2
SCL
SDA
Serial data line
The pass gates of the switches are constructed such that the V
pin can be used to limit the maximum high voltage which will be
DD
V
DD
Supply voltage
ORDERING INFORMATION
PACKAGES
20-Pin Plastic SO
20-Pin Plastic TSSOP
TEMPERATURE RANGE
–40 to +85 °C
ORDER CODE
PCA9545D
DRAWING NUMBER
SOT163-1
–40 to +85 °C
PCA9545PW
SOT360-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
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2002 Mar 28
853-2302 27940
Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
BLOCK DIAGRAM
PCA9545
SC0
SC1
SC2
SC3
SD0
SD1
SD2
SD3
SWITCH CONTROL LOGIC
V
V
SS
DD
POWER ON
RESET
RESET
SCL
SDA
A0
A1
2
I C-BUS
INPUT
FILTER
CONTROL
INT[0–3]
INT LOGIC
INT
SW00758
Figure 2. Block diagram
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2002 Mar 28
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Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
DEVICE ADDRESS
CONTROL REGISTER DEFINITION
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9545 is
shown in Figure 3. To conserve power, no internal pullup resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
One or several SCx/SDx downstream pair, or channel, is selected
by the contents of the control register. This register is written after
the PCA9545 has been addressed. The 2 LSBs of the control byte
are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a stop
2
condition has been placed on the I C bus. This ensures that all
SCx/SDx lines will be in a HIGH state when the channel is made
active, so that no false conditions are generated at the time of
connection.
1
1
1
0
0
A1 A0 R/W
FIXED
HARDWARE SELECTABLE
SW00893
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
Figure 3. Slave address
INT3 INT2 INT1 INT0
B3
B2
B1
B0
COMMAND
Channel 0
disabled
Channel 0
enabled
Channel 1
disabled
Channel 1
enabled
Channel 2
disabled
Channel 2
enabled
Channel 3
disabled
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9545, which will be stored
in the control register. If multiple bytes are received by the
PCA9545, it will save the last byte received. This register can be
0
1
X
X
X
X
2
written and read via the I C bus.
0
1
X
X
X
X
INTERRUPT BITS CHANNEL SELECTION BITS
(READ ONLY)
(READ/WRITE)
0
1
7
6
5
4
3
2
1
0
X
INT3 INT2 INT1 INT0 B3
B2
B1
B0
Channel 3
enabled
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
INT0
NOTE: Several channels can be enabled at the same time.
Ex: B3 = 0, B2 = 1, B1 = 1, B0 = 0, means that channel 0 and 3 are
disabled and channel 1 and 2 are enabled.
Care should be taken not to exceed the maximum bus capacity.
INT1
INT2
INT3
SW00949
Figure 4. Control Register
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Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
INTERRUPT HANDLING
POWER-ON RESET
The PCA9545 provides 4 interrupt inputs, one for each channel, and
one open drain interrupt output. When an interrupt is generated by any
device, it will be detected by the PCA9545 and the interrupt output
will be driven LOW. The channel does not need to be active for
detection of the interrupt. A bit is also set in the control register.
When power is applied to V , an internal Power On Reset holds
DD
the PCA9545 in a reset state until V has reached V
. At this
DD
POR
point, the reset condition is released and the PCA9545 registers and
2
I C state machine are initialized to their default states, all zeroes
causing all the channels to be deselected.
Bits 4 – 7 of the control register correspond to channels 0 – 3 of the
PCA9545, respectively. Therefore, if an interrupt is generated by any
device connected to channel 1, the state of the interrupt inputs is
loaded into the control register when a read is accomplished.
Likewise, an interrupt on any device connected to channel 0 would
cause bit 4 of the control register to be set on the read. The master
can then address the PCA9545 and read the contents of the control
register to determine which channel contains the device generating the
interrupt. The master can then reconfigure the PCA9545 to select this
channel, and locate the device generating the interrupt and clear it.
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9545 are constructed such that
the V voltage can be used to limit the maximum voltage that will
DD
2
be passed from one I C bus to another.
V
vs. V
DD
pass
It should be noted that more than one device can be providing an
interrupt on a channel, so it is up to the master to ensure that all
devices on a channel are interrogated for an interrupt.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
MAXIMUM
The interrupt inputs may be used as general purpose inputs if the
interrupt function is not required.
TYPICAL
V
pass
If unused, interrupt input(s) must be connected to V through a
DD
pull-up resistor.
Table 2. Control Register Read — Interrupt
MINIMUM
5.0
INT3 INT2 INT1 INT0
B3
B2
B1
B0
COMMAND
No interrupt
on channel 0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.5
X
X
X
X
X
X
X
X
X
X
V
DD
Interrupt on
channel 0
SW00820
1
No interrupt
on channel 1
0
1
Figure 5. V
voltage vs. V
DD
X
X
X
X
X
X
X
X
X
X
X
X
X
pass
Interrupt on
channel 1
Figure 5 shows the voltage characteristics of the pass gate
transistors (note that the graph was generated using the data
specified in the DC Characteristics section of this datasheet). In
order for the PCA9545 to act as a voltage translator, the V
voltage should be equal to, or lower than the lowest bus voltage. For
example, if the main bus was running at 5 V, and the downstream
buses were 3.3 V and 2.7 V, then V
2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 5, we see that V (max.) will be at 2.7 V when the
PCA9545 supply voltage is 3.5 V or lower so the PCA9545 supply
voltage could be set to 3.3 V. Pull-up resistors can then be used to
bring the bus voltages to their appropriate levels (see Figure 12).
No interrupt
on channel 2
0
1
X
X
X
X
Interrupt on
channel 2
pass
No interrupt
on channel 3
0
1
X
should be equal to or below
pass
Interrupt on
channel 3
pass
NOTE: Several interrupts can be active at the same time.
Ex: INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0, means that there is no
interrupt on channels 0 and 3, and there is interrupt on channels 1
and 2.
More Information can be found in Application Note AN262 PCA954X
2
family of I C/SMBus multiplexers and switches.
RESET INPUT
The RESET input is an active-LOW signal which may be used to
recover from a bus fault condition. By asserting this signal LOW for
2
a minimum of t , the PCA9545 will reset its registers and I C state
WL
machine and will deselect all channels. The RESET input must be
connected to V through a pull-up resistor.
DD
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Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
2
CHARACTERISTICS OF THE I C-BUS
Start and stop conditions
2
The I C-bus is for 2-way, 2-line communication between different ICs
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 7).
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
System configuration
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see Figure 6).
A device generating a message is a ‘transmitter’, a device receiving
is the ‘receiver’. The device that controls the message is the
‘master’ and the devices which are controlled by the master are the
‘slaves’ (see Figure 8).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
SW00363
Figure 6. Bit transfer
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
SW00365
Figure 7. Definition of start and stop conditions
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
2
SLAVE
RECEIVER
I C
MASTER
TRANSMITTER
MULTIPLEXER
SLAVE
SW00366
Figure 8. System configuration
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Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START condition
SW00368
2
Figure 9. Acknowledgement on the I C-bus
Bus transactions
Data is transmitted to the PCA9545 control register using the write mode as shown in Figure 10.
SLAVE ADDRESS
CONTROL REGISTER
SDA
1
1
1
0
0
A1 A0
X
X
X
X
B3 B2 B1 B0
A
P
S
0
A
stop condition
start condition
R/W acknowledge
from slave
acknowledge
from slave
SW00760
Figure 10. WRITE control register
Data is read from PCA9545 control register using the read mode as shown in Figure 11.
SLAVE ADDRESS
CONTROL REGISTER
last byte
SDA
1
1
1
0
0
A1 A0
S
1
A
INT3INT2INT1 INT0 B3 B2 B1 B0 NA
P
start condition
R/W acknowledge
from slave
no acknowledge
from master
stop condition
SW00761
Figure 11. READ control register
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2002 Mar 28
853-2302 27311
Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
TYPICAL APPLICATION
V
= 2.7 – 5.5 V
DD
V
= 3.3 V
DD
V = 2.7 – 5.5 V
SEE NOTE (1)
SDA
SCL
SDA
SD0
CHANNEL 0
SCL
INT
SC0
INT0
V = 2.7 – 5.5 V
SEE NOTE (1)
RESET
2
I C/SMBus MASTER
SD1
CHANNEL 1
SC1
INT1
V = 2.7 – 5.5 V
SEE NOTE (1)
SD2
CHANNEL 2
SC2
INT2
V = 2.7 – 5.5 V
SEE NOTE (1)
A1
A0
NOTE:
SD3
1.
If the device generating the Interrupt has an open-drain output structure or
can be tri-stated, a pull-up resistor is required.
CHANNEL 3
SC3
V
SS
If the device generating the Interrupt has a totem-pole output structure and
cannot be tri-stated, a pull-up resistor is not required.
INT3
PCA9545
The Interrupt inputs should not be left floating.
SW00810
Figure 12. Typical application
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Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V).
RATING
MAX
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
UNIT
MIN
–0.5
–0.5
—
V
DD
+7.0
+7.0
±20
V
V
V
I
DC input voltage
I
I
DC input current
mA
mA
mA
mA
mW
°C
I
O
DC output current
—
±25
I
DC Supply current
—
±100
±100
400
DD
I
SS
DC Supply current
—
P
tot
total power dissipation
Storage temperature range
Operating ambient temperature
—
T
stg
–60
–40
+150
+85
T
amb
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
DC CHARACTERISTICS
V
= 2.3 to 3.6 V; V = 0 V; T
= –40 to +85 °C; unless otherwise specified. (See page 11 for V = 3.6 to 5.5 V.)
DD
SS
amb
DD
LIMITS
SYMBOL
Supply
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
V
Supply voltage
Supply current
2.3
—
—
3.6
V
DD
Operating mode; V = 3.6 V;
DD
I
30
100
µA
no load; V = V or V ;
DD
I
DD
SS
f
= 100 kHz
SCL
Standby mode; V = 3.6 V;
DD
I
Standby current
—
—
20
100
2.1
µA
stb
no load; V = V or V
I
DD
SS
V
POR
Power-on reset voltage
no load; V = V or V
1.6
V
I
DD
SS
Input SCL; input/output SDA
V
LOW level input voltage
HIGH level input voltage
–0.5
—
—
—
—
—
12
0.3 V
6
V
V
IL
DD
V
IH
0.7 V
3
DD
V
V
= 0.4 V
= 0.6 V
—
OL
I
OL
LOW level output current
mA
6
—
OL
I
L
Leakage current
Input capacitance
V = V or V
SS
–1
—
+1
13
µA
I
DD
C
V = V
SS
pF
i
I
Select inputs A0 to A1 / INT0 to INT3 / RESET
V
LOW level input voltage
HIGH level input voltage
Input leakage current
Input capacitance
–0.5
—
—
+0.3 V
V
V
IL
IH
LI
DD
V
0.7 V
–1
V
DD
+ 0.5
DD
I
pin at V or V
—
+1
µA
pF
DD
SS
C
V = V
I SS
—
1.6
3
i
Pass Gate
V
V
= 3.0 to 3.6 V, V = 0.4 V, I = 15 mA
5
7
20
26
2.2
—
1.5
—
—
3
30
55
—
DD
O
O
R
Switch resistance
Ω
ON
= 2.3 to 2.7 V, V = 0.4 V, I = 10 mA
DD
O
O
V
= V = 3.3 V; I = –100 µA
swout
—
swin
DD
V
swin
= V = 3.0 to 3.6 V; I = –100 µA
swout
1.6
—
2.8
—
DD
V
Pass
Switch output voltage
V
V
= V = 2.5 V; I
= –100 µA
swout
swin
DD
V
swin
= V = 2.3 to 2.7 V; I = –100 µA
swout
1.1
–1
—
2.0
+1
5
DD
I
Leakage current
V = V or V
SS
µA
L
I
DD
C
Input/output capacitance
V = V
I SS
pF
io
INT Output
I
LOW level output current
HIGH level output current
V
OL
= 0.4 V
3
—
—
—
mA
OL
I
—
+100
µA
OH
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2002 Mar 28
853-2302 27311
Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
DC CHARACTERISTICS
V
= 3.6 to 5.5 V; V = 0 V; T
= –40 to +85 °C; unless otherwise specified. (See page 10 for V = 2.3 to 3.6 V.)
DD
SS
amb
DD
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MAX
MIN
TYP
Supply
V
I
Supply voltage
Supply current
3.6
—
—
5.5
V
DD
Operating mode; V = 5.5 V;
DD
575
600
µA
no load; V = V or V ;
DD
I
DD
SS
f
= 100 kHz
SCL
Standby mode; V = 5.5 V;
DD
I
Standby current
—
—
130
1.6
200
2.1
µA
stb
no load; V = V or V
I
DD
SS
V
POR
Power-on reset voltage
no load; V = V or V
V
I
DD
SS
Input SCL; input/output SDA
V
LOW level input voltage
HIGH level input voltage
–0.5
—
—
—
—
—
—
12
0.3 V
6
V
IL
DD
V
IH
0.7 V
V
DD
V
V
= 0.4 V
= 0.6 V
3
6
—
mA
mA
µA
µA
pF
OL
I
OL
LOW level output current
—
OL
I
IL
LOW level input current
HIGH level input current
Input capacitance
V = V
–10
—
+10
+100
13
I
SS
DD
SS
I
IH
V = V
I
C
V = V
—
i
I
Select inputs A0 to A1 / INT0 to INT3 / RESET
V
LOW level input voltage
HIGH level input voltage
Input leakage current
Input capacitance
–0.5
—
—
+0.3 V
V
V
IL
IH
LI
DD
V
0.7 V
–1
V
DD
+ 0.5
DD
I
pin at V or V
—
+50
µA
pF
DD
SS
C
V = V
I SS
—
1.6
3
i
Pass Gate
R
Switch resistance
V
= 4.5 to 5.5 V, V = 0.4 V, I = 15 mA
4
11
3.5
—
—
3
24
—
Ω
V
ON
CC
O
O
V
= V = 5.0 V; I = –100 µA
swout
—
swin
DD
V
Pass
Switch output voltage
V
swin
= V = 4.5 to 5.5 V; I = –100 µA
swout
2.6
–1
—
4.5
+100
5
V
DD
I
Leakage current
V = V or V
SS
µA
pF
L
I
DD
C
Input/output capacitance
V = V
I SS
io
INT Output
I
LOW level output current
HIGH level output current
V
OL
= 0.4 V
3
—
—
—
mA
OL
I
—
+100
µA
OH
10
2002 Mar 28
853-2302 27311
Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
AC CHARACTERISTICS
STANDARD-MODE
2
FAST-MODE I C-BUS
2
I C-BUS
SYMBOL
PARAMETER
UNIT
MIN
—
MAX
MIN
—
MAX
1
1
t
Propagation delay from SDA to SD or SCL to SC
0.3
0.3
ns
kHz
µs
pd
n
n
f
SCL clock frequency
0
100
—
0
400
—
SCL
BUF
t
Bus free time between a STOP and START condition
4.7
1.3
Hold time (repeated) START condition
After this period, the first clock pulse is generated
t
t
4.0
—
0.6
—
µs
HD;STA
t
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Set-up time for STOP condition
Data hold time
4.7
4.0
4.7
4.0
—
—
1.3
0.6
0.6
0.6
—
—
µs
µs
µs
µs
µs
ns
ns
µs
µs
LOW
t
HIGH
—
—
SU;STA
SU;STO
t
—
—
2
2
t
0
3.45
—
0
0.9
—
HD;DAT
t
Data set-up time
250
—
100
20 + 0.1C
20 + 0.1C
—
SU;DAT
3
3
t
R
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Capacitive load for each bus line
1000
300
400
300
300
400
b
b
t
F
—
C
—
b
Pulse width of spikes which must be suppressed
by the input filter
t
SP
—
50
—
50
ns
t
Data valid (HL)
—
—
—
1
0.6
1
—
—
—
1
0.6
1
µs
µs
µs
VD:DATL
t
Data valid (LH)
VD:DATH
t
Data valid Acknowledge
VD:ACK
INT
t
INTn to INT active valid time
—
—
1
4
2
—
—
1
4
2
µs
µs
µs
µs
iv
t
INTn to INT inactive delay time
ir
L
pwr
LOW level pulse width rejection or INTn inputs
HIGH level pulse width rejection or INTn inputs
—
—
—
—
H
0.5
0.5
pwr
RESET
t
Pulse width low reset
Reset time (SDA clear)
Recovery to Start
4
500
0
—
—
—
4
500
0
—
—
—
ns
ns
ns
WL(rst)
t
rst
t
REC:STA
NOTES:
1. Pass gate propagation delay is calculated from the 20 Ω typical R and the 15 pF load capacitance.
ON
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH
the undefined region of the falling edge of SCL.
of the SCL signal) in order to bridge
min
3. C = total capacitance of one bus line in pF.
b
SDA
t
R
t
F
t
t
SP
HD;STA
t
t
LOW
BUF
SCL
t
t
t
SU;STO
HD;STA
SU;STA
t
t
t
SU;DAT
HD;DAT
HIGH
P
S
Sr
P
SU00645
2
Figure 13. Definition of timing on the I C-bus
11
2002 Mar 28
853-2302 27311
Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
12
2002 Mar 28
853-2302 27311
Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
13
2002 Mar 28
853-2302 27311
Philips Semiconductors
Product data
4-channel I2C switch with interrupt logic and reset
PCA9545
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
Data sheet status
Product
status
Definitions
[1]
Data sheet status
[2]
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
Preliminary data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
Product data
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Koninklijke Philips Electronics N.V. 2002
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 03-02
9397 750 09608
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
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