PCA9546PW-T [NXP]
IC 9546 SERIES, 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16, Multiplexer/Demultiplexer;
| 型号： | PCA9546PW-T |
| 厂家： | 
NXP |
| 描述： | IC 9546 SERIES, 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16, Multiplexer/Demultiplexer 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总17页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PCA9546
4-channel I2C switch with reset
Product data sheet
2004 Sep 30
Supersedes data of 2002 Feb 19
Philips
Semiconductors
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
DESCRIPTION
The PCA9546 is a quad bi-directional translating switch controlled
2
by the I C-bus. The SCL/SDA upstream pair fans out to four
downstream pairs, or channels. Any individual SCx/SDx channel or
combination of channels can be selected, determined by the
contents of the programmable Control Register.
An active-LOW reset input allows the PCA9546 to recover from a
2
situation where one of the downstream I C-buses is stuck in a LOW
2
state. Pulling the RESET pin LOW resets the I C state machine and
causes all the channels to be deselected as does the internal power
on reset function.
FEATURES
• 1-of-4 bi-directional translating switches
The pass gates of the switches are constructed such that the V
DD
2
• I C interface logic; compatible with SMBus standards
pin can be used to limit the maximum high voltage which will be
passed by the PCA9546. This allows the use of different bus
voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can
communicate with 5 V parts without any additional protection.
External pull-up resistors pull the bus up to the desired voltage level
for each channel. All I/O pins are 5 V tolerant.
• Active LOW Reset Input
• 3 address pins allowing up to 8 devices on the I C-bus
• Channel selection via I C-bus, in any combination
• Power–up with all switch channels deselected
2
2
• Low Rds switches
ON
• Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses
• No glitch on power-up
• Supports hot insertion
• Low stand-by current
• Operating power supply voltage range of 2.3 V to 5.5 V
• 5 V tolerant Inputs
• 0 kHz to 400 kHz clock frequency
• ESD protection exceeds 2000 V HBM per JESD22-A114,
150 V MM per JESD22-A115 and 1000 V per JESD22-C101
• Latchup testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
• Packages offered: SO16, TSSOP16
ORDERING INFORMATION
PACKAGES
16-Pin Plastic SO
16-Pin Plastic TSSOP
TEMPERATURE RANGE
–40 °C to +85 °C
ORDER CODE
PCA9546D
DRAWING NUMBER
SOT109-1
–40 °C to +85 °C
PCA9546PW
SOT403-1
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
2
2004 Sep 30
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
PIN CONFIGURATION — SO, TSSOP
PIN DESCRIPTION
SO, TSSOP
PIN NUMBER
SYMBOL
FUNCTION
V
1
2
3
4
5
6
7
8
16
DD
A0
A1
1
2
A0
A1
Address input 0
Address input 1
15 SDA
SCL
14
RESET
SD0
3
RESET
SD0
SC0
SD1
SC1
Active LOW reset input
Serial data 0
A2
13
4
SC3
SD3
SC0
12
11
10
9
5
Serial clock 0
Serial data 1
SD1
SC1
6
SC2
SD2
7
Serial clock 1
Supply ground
Serial data 2
V
SS
8
V
SS
9
SD2
SC2
SD3
SC3
A2
SW00913
10
11
12
13
14
15
16
Serial clock 2
Serial data 3
Figure 1. Pin configuration — SO, TSSOP
Serial clock 3
Address input 2
Serial clock line
Serial data line
Supply voltage
SCL
SDA
V
DD
3
2004 Sep 30
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
BLOCK DIAGRAM
PCA9546
SC0
SC1
SC2
SC3
SD0
SD1
SD2
SD3
SWITCH CONTROL LOGIC
V
V
SS
DD
RESET
CIRCUIT
RESET
A0
A1
A2
SCL
SDA
2
I C-BUS
INPUT
FILTER
CONTROL
SW00914
Figure 2. Block diagram
4
2004 Sep 30
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
DEVICE ADDRESSING
CONTROL REGISTER DEFINITION
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9546 is
shown in Figure 3. To conserve power, no internal pull-up resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
One or several SCx/SDx downstream pair, or channel, is selected
by the contents of the control register. This register is written after
the PCA9546 has been addressed. The 2 LSBs of the control byte
are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a stop
2
condition has been placed on the I C-bus. This ensures that all
SCx/SDx lines will be in a HIGH state when the channel is made
active, so that no false conditions are generated at the time of
connection.
1
1
1
0
A2 A1 A0 R/W
FIXED
HARDWARE SELECTABLE
Table 1. Control Register; Write — Channel Selection/
Read — Channel Status
SW00915
Figure 3. Slave address
The last bit of the slave address defines the operation to be
performed. When set to logic 1, a read is selected while a logic 0
selects a write operation.
D7 D6 D5 D4 B3 B2 B1 B0
COMMAND
Channel 0
disabled
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Channel 0
enabled
1
Channel 1
disabled
CONTROL REGISTER
0
1
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9546, which will be stored
in the control register. If multiple bytes are received by the
PCA9546, it will save the last byte received. This register can be
X
Channel 1
enabled
Channel 2
disabled
0
1
2
written and read via the I C-bus.
X
X
Channel 2
enabled
CHANNEL SELECTION BITS
(READ/WRITE)
Channel 3
disabled
0
1
7
6
5
4
3
2
1
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
X
X
X
B3
B2
B1
B0
Channel 3
enabled
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
No channel
selected;
power-up/reset
default state
0
SW01026
NOTE: Several channels can be enabled at the same time.
Ex: B3 = 0, B2 = 1, B1 = 1, B0 = 0, means that channel 0 and 3 are
disabled and channel 1 and 2 are enabled.
Figure 4. Control register
Care should be taken not to exceed the maximum bus capacity.
RESET INPUT
The RESET input is an active-LOW signal which may be used to
recover from a bus fault condition. By asserting this signal LOW for
2
a minimum of t , the PCA9546 will reset its registers and I C state
WL
machine and will deselect all channels. The RESET input must be
connected to V through a pull-up resistor.
DD
POWER-ON RESET
When power is applied to V , an internal Power On Reset holds
DD
the PCA9546 in a reset state until V has reached V
. At this
DD
POR
point, the reset condition is released and the PCA9546 registers and
2
I C state machine are initialized to their default states, all zeroes
causing all the channels to be deselected.
5
2004 Sep 30
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
Figure 5 shows the voltage characteristics of the pass gate
transistors (note that the PCA9546 is only tested at the points
specified in the DC Characteristics section of this datasheet). In
VOLTAGE TRANSLATION
The pass gate transistors of the PCA9546 are constructed such that
the V voltage can be used to limit the maximum voltage that will
DD
2
order for the PCA9546 to act as a voltage translator, the V
pass
be passed from one I C-bus to another.
voltage should be equal to, or lower than the lowest bus voltage. For
example, if the main bus was running at 5 V, and the downstream
buses were 3.3 V and 2.7 V, then V
should be equal to or below
pass
V
vs. V
DD
pass
2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 5, we see that V (max.) will be at 2.7 V when the
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
pass
PCA9546 supply voltage is 3.5 V or lower so the PCA9546 supply
voltage could be set to 3.3 V. Pull-up resistors can then be used to
bring the bus voltages to their appropriate levels (see Figure 12).
MAXIMUM
TYPICAL
More Information can be found in Application Note AN262 PCA954X
V
pass
2
family of I C/SMBus multiplexers and switches.
MINIMUM
5.0
2.0
2.5
3.0
3.5
4.0
4.5
5.5
V
DD
SW00820
Figure 5. V
voltage vs. V
DD
pass
6
2004 Sep 30
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
2
Start and stop conditions
CHARACTERISTICS OF THE I C-BUS
2
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 7).
The I C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
System configuration
Bit transfer
A device generating a message is a ‘transmitter’, a device receiving
is the ‘receiver’. The device that controls the message is the
‘master’ and the devices which are controlled by the master are the
‘slaves’ (see Figure 8).
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see Figure 6).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
SW00363
Figure 6. Bit transfer
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
SW00365
Figure 7. Definition of start and stop conditions
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
2
SLAVE
RECEIVER
I C
MASTER
TRANSMITTER
MULTIPLEXER
SLAVE
SW00366
Figure 8. System configuration
7
2004 Sep 30
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START condition
SW00368
2
Figure 9. Acknowledgement on the I C-bus
SLAVE ADDRESS
CONTROL REGISTER
SDA
1
1
1
0
A2 A1 A0
X
X
X
X
B3 B2 B1 B0
A
P
S
0
A
start condition
R/W acknowledge
from slave
acknowledge
from slave
SW00917
Figure 10. WRITE control register
SLAVE ADDRESS
CONTROL REGISTER
last byte
SDA
1
1
1
0
A2 A1 A0
X
S
1
A
X
X
X
B3 B2 B1 B0 NA
P
start condition
R/W acknowledge
from slave
no acknowledge
from master
stop condition
SW00918
Figure 11. READ control register
8
2004 Sep 30
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
TYPICAL APPLICATION
V
= 2.7 – 5.5 V
DD
V
= 3.3 V
DD
V = 2.7 – 5.5 V
SDA
SCL
SDA
SCL
SD0
SC0
CHANNEL 0
V = 2.7 – 5.5 V
RESET
2
I C/SMBus MASTER
SD1
SC1
CHANNEL 1
V = 2.7 – 5.5 V
SD2
SC2
CHANNEL 2
V = 2.7 – 5.5 V
A2
A1
SD3
SC3
A0
CHANNEL 3
V
SS
PCA9546
SW00919
Figure 12. Typical application
9
2004 Sep 30
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
–0.5 to +7.0
–0.5 to +7.0
±20
UNIT
V
V
DD
V
I
DC input voltage
V
I
I
DC input current
mA
mA
mA
mA
mW
°C
I
O
DC output current
±25
I
Supply current
±100
DD
I
SS
Supply current
±100
P
tot
total power dissipation
Storage temperature range
Operating ambient temperature
400
T
stg
–60 to +150
–40 to +85
T
amb
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
DC CHARACTERISTICS
V
= 2.3 V to 3.6 V; V = 0 V; T
= –40 °C to +85 °C; unless otherwise specified. (See page 11 for V = 3.6 V to 5.5 V)
DD
SS
amb
DD
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
Supply
V
Supply voltage
2.3
—
—
3.6
V
DD
Operating mode; V = 3.6 V;
DD
no load; V = V or V ;
I
Supply current
40
100
µA
I
DD
SS
DD
f
= 100 kHz
SCL
Standby mode; V = 3.6 V;
DD
I
Standby current
—
—
20
100
2.1
µA
stb
no load; V = V or V
I
DD
SS
V
POR
Power-on reset voltage
no load; V = V or V
1.6
V
I
DD
SS
Input SCL; input/output SDA
V
LOW-level input voltage
HIGH-level input voltage
–0.5
—
—
—
—
—
12
0.3V
6
V
V
IL
DD
V
IH
0.7V
DD
V
V
= 0.4 V
= 0.6 V
3
6
—
—
+1
13
OL
I
OL
LOW-level output current
mA
OL
I
L
Leakage current
Input capacitance
V = V or V
SS
–1
—
µA
I
DD
C
V = V
SS
pF
i
I
Select inputs A0 to A2 / RESET
V
LOW-level input voltage
HIGH-level input voltage
Input leakage current
Input capacitance
–0.5
—
—
+0.3V
V
V
IL
IH
LI
DD
V
0.7V
V
DD
+ 0.5
DD
I
pin at V or V
–1
—
—
+1
µA
pF
DD
SS
C
V = V
I SS
1.6
3
i
Pass Gate
V
= 3.67 V; V = 0.4 V; I = 15 mA
5
7
20
26
2.2
—
1.5
—
—
3
30
55
—
CC
O
O
R
Switch resistance
Ω
ON
V
= 2.3 V to 2.7 V; V = 0.4V; I = 10 mA
CC
O
O
V
= V = 3.3 V; I = –100 µA
swout
—
1.6
—
1.1
–1
—
swin
DD
V
= V = 3.0 V to 3.6 V; I = –100 µA
swout
2.8
—
swin
DD
V
Pass
Switch output voltage
V
V
= V = 2.5 V; I
= –100 µA
swout
swin
DD
V
= V = 2.3 V to 2.7 V; I = –100 µA
swout
2.0
+1
5
swin
DD
I
Leakage current
V = V or V
SS
µA
L
I
DD
C
Input/output capacitance
V = V
I SS
pF
io
10
2004 Sep 30
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
DC CHARACTERISTICS
V
= 3.6 V to 5.5 V; V = 0 V; T
= –40 °C to +85 °C; unless otherwise specified. (See page 10 for V = 2.3 V to 3.6 V)
DD
SS
amb
DD
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
MAX
MIN
TYP
Supply
V
Supply voltage
3.6
—
—
5.5
V
DD
Operating mode; V = 5.5 V;
DD
no load; V = V or V ;
I
Supply current
570
600
µA
I
DD
SS
DD
f
= 100 kHz
SCL
Standby mode; V = 5.5 V;
DD
I
Standby current
—
—
250
1.7
300
2.1
µA
stb
no load; V = V or V
I
DD
SS
V
POR
Power-on reset voltage
no load; V = V or V
V
I
DD
SS
Input SCL; input/output SDA
V
LOW-level input voltage
HIGH-level input voltage
–0.5
—
—
—
—
—
—
12
0.3V
6
V
IL
DD
V
IH
0.7V
V
DD
V
V
= 0.4 V
= 0.6 V
3
6
—
—
mA
mA
µA
µA
pF
OL
I
OL
LOW-level output current
OL
I
IL
LOW-level input current
HIGH-level input current
Input capacitance
V = V
–10
—
—
+10
100
13
I
SS
DD
SS
I
IH
V = V
I
C
V = V
I
i
Select inputs A0 to A2 / RESET
V
LOW-level input voltage
HIGH-level input voltage
Input leakage current
Input capacitance
–0.5
—
—
—
2
+0.3V
V
V
IL
IH
LI
DD
V
0.7V
V
DD
+ 0.5
DD
I
pin at V or V
–1
—
+50
µA
pF
DD
SS
C
V = V
I SS
3
i
Pass Gate
R
Switch resistance
V
= 4.5 V to 5.5 V; V = 0.4 V; I = 15 mA
4
11
3.5
—
—
3
24
—
Ω
V
ON
CC
O
O
V
swin
= V = 5.0 V; I = –100 µA
swout
—
DD
V
Pass
Switch output voltage
V
swin
= V = 4.5 V to 5.5 V; I = –100 µA
swout
2.6
–10
—
4.5
+100
5
V
DD
I
Leakage current
V = V or V
SS
µA
pF
L
I
DD
C
Input/output capacitance
V = V
I SS
io
11
2004 Sep 30
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
AC CHARACTERISTICS
STANDARD-MODE
FAST-MODE
I C-BUS
2
2
I C-BUS
SYMBOL
PARAMETER
UNIT
MIN
—
MAX
MIN
MAX
1
1
t
Propagation delay from SDA to SD or SCL to SC
0.3
—
0
0.3
ns
kHz
µs
pd
n
n
f
SCL clock frequency
0
100
—
400
—
SCL
BUF
t
Bus free time between a STOP and START condition
4.7
1.3
Hold time (repeated) START condition
After this period, the first clock pulse is generated
t
t
4.0
—
0.6
—
µs
HD;STA
t
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Set-up time for STOP condition
Data hold time
4.7
4.0
4.7
4.0
—
—
1.3
0.6
0.6
0.6
—
—
µs
µs
µs
µs
µs
ns
ns
µs
µs
LOW
t
HIGH
—
—
SU;STA
SU;STO
t
—
—
2
2
t
0
3.45
—
0
0.9
—
HD;DAT
t
Data set-up time
250
—
100
20 + 0.1C
20 + 0.1C
—
SU;DAT
3
3
t
R
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Capacitive load for each bus line
1000
300
400
300
300
400
b
b
t
F
—
C
—
b
Pulse width of spikes which must be suppressed
by the input filter
t
SP
—
50
—
50
ns
t
Data valid (HL)
—
—
—
1
0.6
1
—
—
—
1
0.6
1
µs
µs
µs
VD:DATL
t
Data valid (LH)
VD:DATH
t
Data valid Acknowledge
VD:ACK
RESET
t
Pulse width low reset
Reset time (SDA clear)
Recovery to Start
4
500
0
—
—
—
4
500
0
—
—
—
ns
ns
ns
WL(rst)
t
rst
t
REC:STA
NOTES:
1. Pass gate propagation delay is calculated from the 20 Ω typical R and the 15 pF load capacitance.
ON
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
of the SCL signal) in order to bridge
IH(min)
the undefined region of the falling edge of SCL.
3. C = total capacitance of one bus line in pF.
b
SDA
t
R
t
F
t
t
SP
HD;STA
t
t
LOW
BUF
SCL
t
t
t
SU;STO
HD;STA
SU;STA
t
t
t
SU;DAT
HD;DAT
HIGH
P
S
Sr
P
SU00645
2
Figure 13. Definition of timing on the I C-bus
12
2004 Sep 30
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
13
2004 Sep 30
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
14
2004 Sep 30
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals;
body 4 x 4 x 0.85 mm
SOT629-1
15
2004 Sep 30
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
REVISION HISTORY
Rev
Date
Description
_2
20040930
Product data sheet (9397 750 14123). Supersedes data of 2002 Feb 19 (9397 750 09459).
Modifications:
• Table 1, “Control register; Write—Channel Selection / Read—Channel Status”: add ‘No channel selected;
power-up/reset default state’ row to bottom of table.
_1
20020219
Product data (9397 750 09459). ECN 853-2317 27757 of 19 February 2002.
16
2004 Sep 30
Philips Semiconductors
Product data sheet
4-channel I2C switch with reset
PCA9546
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data sheet
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data sheet
Product data sheet
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys
nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2004
All rights reserved. Published in the U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 09-04
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document number:
9397 750 14123
Philips
Semiconductors
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