PCA9547D,118 [NXP]
PCA9547 - 8-channel I2C-bus multiplexer with reset SOP 24-Pin;
| 型号： | PCA9547D,118 |
| 厂家： | 
NXP |
| 描述： | PCA9547 - 8-channel I2C-bus multiplexer with reset SOP 24-Pin PC |
| 文件： | 总30页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9547
8-channel I2C-bus multiplexer with reset
Rev. 4 — 1 April 2014
Product data sheet
1. General description
The PCA9547 is an octal bidirectional translating multiplexer controlled by the I2C-bus.
The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only one
SCx/SDx channel can be selected at a time, determined by the contents of the
programmable control register. The device powers up with Channel 0 connected, allowing
immediate communication between the master and downstream devices on that channel.
An active LOW reset input allows the PCA9547 to recover from a situation where one of
the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets
the I2C-bus state machine causing all the channels to be deselected, except Channel 0 so
that the master can regain control of the bus.
The pass gates of the multiplexers are constructed such that the VDD pin can be used to
limit the maximum high voltage which will be passed by the PCA9547. This allows the use
of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can communicate
with 5 V parts without any additional protection. External pull-up resistors pull the bus up
to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
2. Features and benefits
1-of-8 bidirectional translating multiplexer
I2C-bus interface logic; compatible with SMBus standards
Active LOW RESET input
3 address pins allowing up to 8 devices on the I2C-bus
Channel selection via I2C-bus, one channel at a time
Power-up with all channels deselected except Channel 0 which is connected
Low Ron multiplexers
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO24, TSSOP24, HVQFN24
PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
3. Ordering information
Table 1.
Ordering information
Type number Topside
marking
Package
Name
Description
plastic small outline package; 24 leads; body width 7.5 mm
Version
PCA9547D
PCA9547D
SO24
SOT137-1
PCA9547PW
PCA9547PW
TSSOP24 plastic thin shrink small outline package; 24 leads; body width SOT355-1
4.4 mm
PCA9547BS
9547
HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; SOT616-1
24 terminals; body 4 4 0.85 mm
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable part
number
Package
Packing method
Minimum
order
Temperature range
quantity
PCA9547D
PCA9547PW
PCA9547BS
PCA9547D,112
PCA9547D,118
PCA9547PW,112
PCA9547PW,118
PCA9547BS,118
SO24
Standard marking
* IC’s tube - DSC bulk pack
1200
1000
1575
2500
6000
T
amb = 40 C to +85 C
Tamb = 40 C to +85 C
amb = 40 C to +85 C
Tamb = 40 C to +85 C
amb = 40 C to +85 C
SO24
Reel 13” Q1/T1
*Standard mark SMD
TSSOP24
TSSOP24
HVQFN24
Standard marking
* IC’s tube - DSC bulk pack
T
Reel 13” Q1/T1
*Standard mark SMD
Reel 13” Q1/T1
T
*Standard mark SMD
PCA9547
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 1 April 2014
2 of 30
PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
4. Block diagram
PCA9547
SC0
SC1
SC2
SC3
SC4
SC5
SC6
SC7
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
V
SS
SWITCH CONTROL LOGIC
V
DD
RESET
CIRCUIT
RESET
A0
A1
A2
SCL
SDA
2
INPUT
FILTER
I C-BUS
CONTROL
002aaa961
Fig 1. Block diagram of PCA9547
PCA9547
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Product data sheet
Rev. 4 — 1 April 2014
3 of 30
PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
5. Pinning information
5.1 Pinning
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
1
2
24
23
22
21
20
19
18
17
16
15
14
13
A0
A1
V
A0
A1
V
DD
DD
SDA
SCL
A2
SDA
SCL
A2
3
RESET
SD0
RESET
SD0
SC0
SD1
SC1
SD2
SC2
SD3
SC3
4
5
SC0
SC7
SD7
SC6
SD6
SC5
SD5
SC4
SD4
SC7
SD7
SC6
SD6
SC5
SD5
SC4
SD4
6
SD1
PCA9547D
PCA9547PW
7
SC1
8
SD2
9
SC2
10
11
12
10
11
12
SD3
SC3
V
SS
V
SS
002aaa958
002aaa959
Fig 2. Pin configuration for SO24
Fig 3. Pin configuration for TSSOP24
terminal 1
index area
1
2
3
4
5
6
18
17
16
15
14
13
SD0
SC0
SD1
SC1
SD2
SC2
A2
SC7
SD7
SC6
SD6
SC5
PCA9547BS
002aaa960
Transparent top view
Fig 4. Pin configuration for HVQFN24 (transparent top view)
PCA9547
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Product data sheet
Rev. 4 — 1 April 2014
4 of 30
PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
5.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
SO24, TSSOP24 HVQFN24
A0
1
22
23
24
1
address input 0
A1
2
address input 1
RESET
SD0
SC0
SD1
SC1
SD2
SC2
SD3
SC3
VSS
3
active LOW reset input
serial data output 0
serial clock output 0
serial data output 1
serial clock output 1
serial data output 2
serial clock output 2
serial data output 3
serial clock output 3
supply ground
4
5
2
6
3
7
4
8
5
9
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
7
8
9[1]
10
11
12
13
14
15
16
17
18
19
20
21
SD4
SC4
SD5
SC5
SD6
SC6
SD7
SC7
A2
serial data output 4
serial clock output 4
serial data output 5
serial clock output 5
serial data output 6
serial clock output 6
serial data output 7
serial clock output 7
address input 2
SCL
SDA
VDD
serial clock line
serial data line
supply voltage
[1] HVQFN24 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
PCA9547
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Product data sheet
Rev. 4 — 1 April 2014
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PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
6. Functional description
6.1 Device addressing
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9547 is shown in Figure 5. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
1
1
1
0
A2 A1 A0 R/W
fixed
hardware
selectable
002aaa962
Fig 5. Slave address
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9547, which will be stored in the Control register. If multiple bytes are
received by the PCA9547, it will save the last byte received. This register can be written
and read via the I2C-bus.
channel selection bits
(read/write)
7
6
5
4
3
2
1
0
X
X
X
X
B3 B2 B1 B0
002aaa963
enable bit
Fig 6. Control register
6.2.1 Control register definition
A SCx/SDx downstream pair, or channel, is selected by the contents of the control
register. This register is written after the PCA9547 has been addressed. The 4 LSBs of
the control byte are used to determine which channel is to be selected. When a channel is
selected, the channel will become active after a STOP condition has been placed on the
I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is
made active, so that no false conditions are generated at the time of connection.
PCA9547
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Product data sheet
Rev. 4 — 1 April 2014
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PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
Table 4.
Control register
Write = channel selection; Read = channel status
D7
X
X
X
X
X
X
X
X
X
0
D6
X
X
X
X
X
X
X
X
X
0
D5
X
X
X
X
X
X
X
X
X
0
D4
X
X
X
X
X
X
X
X
X
0
B3
0
B2
X
0
B1
X
0
B0
X
0
Command
no channel selected
channel 0 enabled
channel 1 enabled
channel 2 enabled
channel 3 enabled
channel 4 enabled
channel 5 enabled
channel 6 enabled
channel 7 enabled
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
0
0
0
channel 0 enabled;
power-up/reset default state
6.3 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9547 will reset its
register and I2C-bus state machine and will deselect all channels except channel 0. The
RESET input must be connected to VDD through a pull-up resistor.
6.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9547 in
a reset condition until VDD has reached VPOR. At this point, the reset condition is released
and the PCA9547 register and I2C-bus state machine are initialized to their default states,
causing all the channels to be deselected except channel 0. Thereafter, VDD must be
lowered below 0.2 V for at least 5 s in order to reset the device.
PCA9547
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Product data sheet
Rev. 4 — 1 April 2014
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PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
6.5 Voltage translation
The pass gate transistors of the PCA9547 are constructed such that the VDD voltage can
be used to limit the maximum voltage that will be passed from one I2C-bus to another.
002aab802
5.0
V
o(mux)
(V)
4.0
(1)
(2)
(3)
3.0
2.0
1.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
DD
5.5
(V)
V
(1) maximum
(2) typical
(3) minimum
Fig 7. Pass gate voltage as a function of supply voltage
Figure 7 shows the voltage characteristics of the pass gate transistors (note that the
PCA9547 is only tested at the points specified in Section 11 “Static characteristics” of this
data sheet). In order for the PCA9547 to act as a voltage translator, the Vo(mux) voltage
should be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(mux) should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 7, we see that Vo(mux)(max) will be at 2.7 V when the PCA9547 supply voltage is
3.5 V or lower so the PCA9547 supply voltage could be set to 3.3 V. Pull-up resistors can
then be used to bring the bus voltages to their appropriate levels (see Figure 14).
More information can be found in Application Note AN262, PCA954X family of I2C/SMBus
multiplexers and switches.
PCA9547
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Product data sheet
Rev. 4 — 1 April 2014
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PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
7. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 8).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 8. Bit transfer
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (seeFigure 9.)
SDA
SCL
S
P
STOP condition
START condition
mba608
Fig 9. Definition of START and STOP conditions
PCA9547
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Product data sheet
Rev. 4 — 1 April 2014
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PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
7.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 10).
SDA
SCL
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
2
SLAVE
RECEIVER
MASTER
TRANSMITTER
I C-BUS
MULTIPLEXER
SLAVE
002aaa966
Fig 10. System configuration
7.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from master
1
2
8
9
S
clock pulse for
START
condition
acknowledgement
002aaa987
Fig 11. Acknowledgement on the I2C-bus
PCA9547
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Product data sheet
Rev. 4 — 1 April 2014
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PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
7.4 Bus transactions
Data is transmitted to the PCA9547 control register using the Write mode as shown in
Figure 12.
slave address
control register
SDA
S
1
1
1
0
A2 A1 A0
0
A
X
X
X
X
B3 B2 B1 B0
A
P
START condition
R/W acknowledge
from slave
acknowledge
from slave
STOP condition
002aaa988
Fig 12. Write control register
Data is read from PCA9547 using the Read mode as shown in Figure 13.
last byte
slave address
control register
X
SDA
S
1
1
1
0
A2 A1 A0
1
A
X
X
X
B3 B2 B1 B0 NA
P
START condition
R/W acknowledge
from slave
no acknowledge
from master
STOP condition
002aaa989
Fig 13. Read control register
PCA9547
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Product data sheet
Rev. 4 — 1 April 2014
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PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
8. Application design-in information
V
= 2.7 V to 5.5 V
DD
V
= 3.3 V
DD
V = 2.7 V to 5.5 V
SDA
SCL
SDA
SCL
SD0
SC0
channel 0
V = 2.7 V to 5.5 V
RESET
2
I C-bus/SMBus
master
SD1
SC1
channel 1
V = 2.7 V to 5.5 V
SD2
SC2
channel 2
V = 2.7 V to 5.5 V
SD3
SC3
channel 3
V = 2.7 V to 5.5 V
PCA9547
SD4
SC4
channel 4
V = 2.7 V to 5.5 V
SD5
SC5
channel 5
V = 2.7 V to 5.5 V
SD6
SC6
channel 6
V = 2.7 V to 5.5 V
A2
A1
A0
SD7
SC7
channel 7
002aaa965
V
SS
Fig 14. Typical application
PCA9547
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Product data sheet
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PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
VDD
VI
Parameter
Conditions
Min
0.5
0.5
20
25
100
100
-
Max
+7.0
+7.0
+20
Unit
V
supply voltage
input voltage
V
II
input current
mA
mA
mA
mA
mW
C
IO
output current
+25
IDD
supply current
ground supply current
total power dissipation
+100
+100
400
ISS
Ptot
Tj(max)
[1]
maximum junction
temperature
-
+125
Tstg
storage temperature
ambient temperature
60
40
+150
+85
C
C
Tamb
[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 125 C.
10. Thermal characteristics
Table 6.
Thermal characteristics
Parameter
Symbol
Conditions
Typ
40
Unit
Rth(j-a)
thermal resistance from junction HVQFN24 package
C/W
C/W
C/W
to ambient
SO24 package
77
TSSOP24 package
128
PCA9547
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Product data sheet
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PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
11. Static characteristics
Table 7.
V
Static characteristics at VDD = 2.3 V to 3.6 V
SS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. See Table 8 on page 15 for VDD = 4.5 V to 5.5 V.[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply
VDD
supply voltage
supply current
2.3
-
-
3.6
50
V
IDD
operating mode; VDD = 3.6 V; no load;
VI = VDD or VSS; fSCL = 100 kHz
20
A
Istb
standby current
Standby mode; VDD = 3.6 V; no load;
VI = VDD or VSS
-
-
0.1
1.6
2
A
[2]
VPOR
power-on reset voltage
no load; VI = VDD or VSS
2.1
V
Input SCL; input/output SDA
VIL
VIH
IOL
LOW-level input voltage
HIGH-level input voltage
0.5
-
+0.3VDD
V
0.7VDD
-
6
V
LOW-level output current VOL = 0.4 V
VOL = 0.6 V
3
-
-
mA
mA
A
pF
6
-
-
IL
leakage current
VI = VDD or VSS
1
-
-
+1
19
Ci
input capacitance
VI = VSS
14
Select inputs A0, A1, A2, RESET
VIL
LOW-level input voltage
HIGH-level input voltage
input leakage current
input capacitance
0.5
0.7VDD
1
-
+0.3VDD
V
VIH
-
6
V
ILI
pin at VDD or VSS
VI = VSS
-
+1
5
A
pF
Ci
-
2
Pass gate
Ron
ON-state resistance
multiplexer; VDD = 3.6 V; VO = 0.4 V;
IO = 15 mA
5
7
11
16
30
55
multiplexer; VDD = 2.3 V to 2.7 V;
VO = 0.4 V; IO = 10 mA
Vo(mux)
multiplexer output voltage Vi(mux) = VDD = 3.3 V; Io(mux) = 100 A
-
1.9
-
-
V
V
Vi(mux) = VDD = 3.0 V to 3.6 V;
1.6
2.8
I
o(mux) = 100 A
Vo(mux) = VDD = 2.5 V;
Io(mux) = 100 A
-
1.5
-
-
V
V
Vo(mux) = VDD = 2.3 V to 2.7 V;
0.9
2.0
Io(mux) = 100 A
IL
leakage current
VI = VDD or VSS
1
-
+1
5
A
Cio
input/output capacitance VI = VSS
-
3
pF
[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.
[2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
PCA9547
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© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 1 April 2014
14 of 30
PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
Table 8.
Static characteristics at VDD = 4.5 V to 5.5 V
VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. See Table 7 on page 14 for VDD = 2.3 V to 3.6 V.[1]
Symbol
Supply
VDD
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
supply current
4.5
-
-
5.5
V
IDD
operating mode; VDD = 5.5 V;
65
100
A
no load; VI = VDD or VSS
fSCL = 100 kHz
;
Istb
standby current
Standby mode; VDD = 5.5 V;
no load; VI = VDD or VSS
-
-
0.6
1.7
2
A
[2]
VPOR
power-on reset voltage
no load; VI = VDD or VSS
2.1
V
Input SCL; input/output SDA
VIL
VIH
IOL
LOW-level input voltage
HIGH-level input voltage
LOW-level output current
0.5
-
+0.3VDD
V
0.7VDD
-
6
V
VOL = 0.4 V
VOL = 0.6 V
VI = VSS
3
-
-
mA
mA
A
A
pF
6
-
-
IIL
IIH
Ci
LOW-level input current
HIGH-level input current
input capacitance
1
1
-
-
+1
+1
19
VI = VSS
-
VI = VSS
14
Select inputs A0, A1, A2, RESET
VIL
LOW-level input voltage
HIGH-level input voltage
input leakage current
input capacitance
0.5
0.7VDD
1
-
+0.3VDD
V
VIH
-
6
V
ILI
pin at VDD or VSS
VI = VSS
-
+1
5
A
pF
Ci
-
2
Pass gate
Ron
ON-state resistance
multiplexer; VDD = 4.5 V to 5.5 V;
VO = 0.4 V; IO = 15 mA
4
9
24
-
V
V
Vo(mux)
multiplexer output voltage Vi(mux) = VDD = 5.0 V;
-
3.6
-
Io(mux) = 100 A
Vi(mux) = VDD = 4.5 V to 5.5 V;
2.6
4.5
Io(mux) = 100 A
VI = VDD or VSS
VI = VSS
IL
leakage current
1
-
+1
5
A
Cio
input/output capacitance
-
3
pF
[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.
[2] DD must be lowered to 0.2 V for at least 5 s in order to reset part.
V
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8-channel I2C-bus multiplexer with reset
12. Dynamic characteristics
Table 9.
Symbol
Dynamic characteristics
Parameter
Conditions
Standard-mode Fast-mode I2C-bus Unit
I2C-bus
Min
Max
Min
Max
tPD
propagation delay
from SDA to SDx,
or SCL to SCx
-
0.3[1]
-
0.3[1] ns
fSCL
tBUF
SCL clock frequency
0
100
-
0
400 kHz
bus free time between a STOP and
START condition
4.7
1.3
-
s
[2]
tHD;STA
tLOW
hold time (repeated) START condition
LOW period of the SCL clock
4.0
4.7
4.0
4.7
-
-
-
-
0.6
1.3
0.6
0.6
-
-
-
-
s
s
s
s
tHIGH
HIGH period of the SCL clock
tSU;STA
set-up time for a repeated START
condition
tSU;STO
tHD;DAT
tSU;DAT
tr
set-up time for STOP condition
data hold time
4.0
0[3]
-
0.6
0[3]
-
s
3.45
-
0.9 s
ns
data set-up time
250
100
-
[4]
[4]
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
capacitive load for each bus line
-
-
-
-
1000
300
400
50
20 + 0.1Cb
300 ns
300 ns
400 pF
tf
20 + 0.1Cb
Cb
-
-
tSP
pulse width of spikes that must be
suppressed by the input filter
50
ns
[5]
[5]
tVD;DAT
data valid time
HIGH-to-LOW
LOW-to-HIGH
-
-
-
1
0.6
1
-
-
-
1
s
0.6 s
tVD;ACK
RESET
tw(rst)L
trst
data valid acknowledge time
1
s
LOW-level reset time
reset time
4
500
0
-
-
-
4
500
0
-
-
-
ns
ns
ns
SDA clear
trec(rst)
reset recovery time
[1] Pass gate propagation delay is calculated from the 20 typical Ron and the 15 pF load capacitance.
[2] After this period, the first clock pulse is generated.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4] Cb = total capacitance of one bus line in pF.
[5] Measurements taken with 1 k pull-up resistor and 50 pF load.
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8-channel I2C-bus multiplexer with reset
0.7 × V
0.3 × V
DD
SDA
DD
t
t
t
t
SP
t
r
f
HD;STA
BUF
t
LOW
0.7 × V
0.3 × V
DD
SCL
DD
t
t
t
SU;STO
HD;STA
SU;STA
t
t
t
SU;DAT
HD;DAT
HIGH
P
S
Sr
P
002aaa986
Fig 15. Definition of timing on the I2C-bus
ACK or read cycle
START
SCL
70 %
SDA
t
rst
RESET
50 %
50 %
50 %
t
rec(rst)
t
w(rst)L
002aac314
Fig 16. Definition of RESET timing
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8-channel I2C-bus multiplexer with reset
13. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
H
v
M
A
E
y
Z
24
13
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
12
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.61
0.014 0.009 0.60
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT137-1
075E05
MS-013
Fig 17. SO24 package outline (SOT137-1)
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8-channel I2C-bus multiplexer with reset
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT355-1
MO-153
Fig 18. TSSOP24 package outline (SOT355-1)
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8-channel I2C-bus multiplexer with reset
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm
SOT616-1
B
A
D
terminal 1
index area
A
A
1
E
c
detail X
e
1
C
1/2 e
y
y
C
1
e
v
M
M
C
C
A
B
b
7
12
w
L
13
6
e
e
E
h
2
1/2 e
1
18
terminal 1
index area
24
19
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
(1)
(1)
UNIT
mm
A
b
c
E
e
e
e
y
D
D
E
L
v
w
y
1
1
h
1
2
h
0.05 0.30
0.00 0.18
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.5
0.3
0.05
0.1
1
0.2
0.5
2.5
2.5
0.1 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
01-08-08
02-10-22
SOT616-1
- - -
MO-220
- - -
Fig 19. HVQFN24 package outline (SOT616-1)
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8-channel I2C-bus multiplexer with reset
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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8-channel I2C-bus multiplexer with reset
14.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 20) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 10 and 11
Table 10. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
235
350
220
< 2.5
2.5
220
220
Table 11. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350
260
350 to 2000
> 2000
260
< 1.6
260
250
245
1.6 to 2.5
> 2.5
260
245
250
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 20.
PCA9547
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8-channel I2C-bus multiplexer with reset
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 20. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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8-channel I2C-bus multiplexer with reset
15. Soldering: PCB footprints
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%\
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*\
+[
+\
ꢁꢃꢂꢇꢄ ꢁꢃꢌꢂꢄ ꢁꢁꢃꢂꢄꢄ ꢅꢃꢆꢄꢄ ꢂꢃꢆꢄꢄ ꢄꢃꢇꢄꢄ ꢄꢃꢈꢄꢄ ꢁꢉꢃꢁꢂꢄ ꢈꢃꢅꢄꢄ ꢁꢇꢃꢄꢄꢄ ꢁꢁꢃꢆꢉꢄ
VRWꢀꢁꢂꢃꢀBIUꢄ
Fig 21. PCB footprint for SOT137-1 (SO24); reflow soldering
PCA9547
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Product data sheet
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PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
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ꢄꢃꢅꢉꢄ ꢄꢃꢇꢉꢄ ꢇꢃꢂꢄꢄ ꢆꢃꢉꢄꢄ ꢁꢃꢌꢉꢄ ꢄꢃꢆꢄꢄ ꢄꢃꢅꢄꢄ ꢈꢃꢂꢄꢄ ꢉꢃꢌꢄꢄ ꢈꢃꢅꢄꢄ ꢇꢃꢆꢉꢄ
VRWꢁꢅꢅꢃꢀBIU
Fig 22. PCB footprint for SOT355-1 (TSSOP24); reflow soldering
PCA9547
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Product data sheet
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PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
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63[
63\
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ꢄꢃꢉꢄꢄ ꢉꢃꢄꢄꢄ ꢉꢃꢄꢄꢄ ꢌꢃꢂꢄꢄ ꢌꢃꢂꢄꢄ ꢄꢃꢍꢄꢄ ꢄꢃꢂꢆꢄ ꢂꢃꢁꢄꢄ ꢂꢃꢁꢄꢄ
ꢄꢃꢆꢉꢄ ꢄꢃꢆꢉꢄ ꢆꢃꢌꢄꢄ ꢆꢃꢌꢄꢄ ꢉꢃꢂꢉꢄ ꢉꢃꢂꢉꢄ
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ꢄꢍꢎꢄꢅꢎꢁꢉ
Fig 23. PCB footprint for SOT616-1; reflow soldering
PCA9547
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8-channel I2C-bus multiplexer with reset
16. Abbreviations
Table 12. Abbreviations
Acronym
CDM
Description
Charged Device Model
ElectroStatic Discharge
Human Body Model
Inter-Integrated Circuit bus
Input/Output
ESD
HBM
I2C-bus
I/O
LSB
Least Significant Bit
Printed-Circuit Board
System Management Bus
PCB
SMBus
17. Revision history
Table 13. Revision history
Document ID Release date
PCA9547 v.4 20140401
Data sheet status
Product data sheet
Change notice
Supersedes
-
PCA9547 v.3
Modifications:
• Section 2 “Features and benefits”, 15th bullet item: deleted phrase “200 V MM per JESD22-A115”
• Table 1 “Ordering information”:
–
added column “Topside marking” (moved from Table 2)
–
Type number PCA9547PW: Topside mark corrected from “PCA9547” to “PCA9547PW” (this is a
correction to documentation only, no change to device)
• Table 2 “Ordering options”:
–
added columns “Orderable part number”, “Package”, “Packing method”, “Minimum order quantity”
–
deleted column “Topside mark” (moved to Table 1)
• Section 6.4 “Power-on reset”, first paragraph, third sentence: corrected from “VDD must be lowered
below 0.2 V to reset the device” to “VDD must be lowered below 0.2 V for at least 5 s in order to reset
the device”
• Table 5 “Limiting values”: added limiting value “Tj(max)
”
• Added Section 10 “Thermal characteristics”
• Table 7 “Static characteristics at VDD = 2.3 V to 3.6 V”:
–
sub-section “Select inputs A0, A1, A2, RESET”: Max value for VIH corrected from “VDD + 0.5 V”
to “6 V”
–
Table note [2]: inserted phrase “for at least 5 s”
• Table 8 “Static characteristics at VDD = 4.5 V to 5.5 V”:
–
sub-section “Select inputs A0, A1, A2, RESET”: Max value for VIH corrected from “VDD + 0.5 V”
to “6 V”
–
Table note [2]: inserted phrase “for at least 5 s”
• Added Section 15 “Soldering: PCB footprints”
PCA9547 v.3 20090710
PCA9547 v.2 20060912
PCA9547 v.1 20051005
Product data sheet
Product data sheet
Product data sheet
-
-
-
PCA9547 v.2
PCA9547 v.1
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PCA9547
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 1 April 2014
27 of 30
PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
18.2 Definitions
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
PCA9547
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 1 April 2014
28 of 30
PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
non-automotive qualified products in automotive equipment or applications.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9547
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 1 April 2014
29 of 30
PCA9547
NXP Semiconductors
8-channel I2C-bus multiplexer with reset
20. Contents
1
General description. . . . . . . . . . . . . . . . . . . . . . 1
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
3.1
4
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6
Functional description . . . . . . . . . . . . . . . . . . . 6
Device addressing . . . . . . . . . . . . . . . . . . . . . . 6
Control register. . . . . . . . . . . . . . . . . . . . . . . . . 6
Control register definition . . . . . . . . . . . . . . . . . 6
RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7
Voltage translation . . . . . . . . . . . . . . . . . . . . . . 8
6.1
6.2
6.2.1
6.3
6.4
6.5
7
Characteristics of the I2C-bus . . . . . . . . . . . . . 9
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
START and STOP conditions . . . . . . . . . . . . . . 9
System configuration . . . . . . . . . . . . . . . . . . . 10
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 11
7.1
7.1.1
7.2
7.3
7.4
8
Application design-in information . . . . . . . . . 12
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13
Thermal characteristics . . . . . . . . . . . . . . . . . 13
Static characteristics. . . . . . . . . . . . . . . . . . . . 14
Dynamic characteristics . . . . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
9
10
11
12
13
14
Soldering of SMD packages . . . . . . . . . . . . . . 21
Introduction to soldering . . . . . . . . . . . . . . . . . 21
Wave and reflow soldering . . . . . . . . . . . . . . . 21
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 21
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 22
14.1
14.2
14.3
14.4
15
16
17
Soldering: PCB footprints. . . . . . . . . . . . . . . . 24
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 27
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27
18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 28
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29
18.1
18.2
18.3
18.4
19
20
Contact information. . . . . . . . . . . . . . . . . . . . . 29
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 April 2014
Document identifier: PCA9547
相关型号：
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