PCA9555PW [NXP]

16-bit I2C and SMBus I/O port with interrupt; 16位I²C和SMBus I / O端口与中断


型号：	PCA9555PW
厂家：	NXP
描述：	16-bit I2C and SMBus I/O port with interrupt 16位I²C和SMBus I / O端口与中断
文件：	总22页 (文件大小：185K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

PCA9555

16-bit I²C and SMBus I/O port with interrupt

Product data sheet

2004 Sep 30

Supersedes data of 2004 Jul 27

Philips

Semiconductors

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

DESCRIPTION

The PCA9555 is a 24-pin CMOS device that provide 16 bits of

General Purpose parallel Input/Output (GPIO) expansion for

I C/SMBus applications and was developed to enhance the Philips

family of I@C I/O expanders. The improvements include higher drive

capability, 5 V I/O tolerance, lower supply current, individual I/O

configuration, and smaller packaging. I/O expanders provide a

simple solution when additional I/O is needed for ACPI power

switches, sensors, pushbuttons, LEDs, fans, etc.

The PCA9555 consist of two 8-bit Configuration (Input or Output

selection); Input, Output and Polarity inversion (Active-HIGH or

Active-LOW operation) registers. The system master can enable the

I/Os as either inputs or outputs by writing to the I/O configuration

bits. The data for each Input or Output is kept in the corresponding

Input or Output register. The polarity of the read register can be

inverted with the Polarity Inversion Register. All registers can be

read by the system master. Although pin-to-pin and I C address

compatible with the PCF8575, software changes are required due to

the enhancements and are discussed in Application Note AN469.

FEATURES

• Operating power supply voltage range of 2.3 V to 5.5 V

• 5 V tolerant I/Os

• Polarity inversion register

• Active-LOW interrupt output

• Low stand-by current

• Noise filter on SCL/SDA inputs

• No glitch on power-up

• Internal power-on reset

• 16 I/O pins which default to 16 inputs

• 0 kHz to 400 kHz clock frequency

• ESD protection exceeds 2000 V HBM per JESD22-A114,

200 V MM per JESD22-A115, and 1000 V CDM per

JESD22-C101

The PCA9555 open-drain interrupt output is activated when any

input state differs from its corresponding input port register state and

is used to indicate to the system master that an input state has

changed. The power-on reset sets the registers to their default

values and initializes the device state machine.

Three hardware pins (A0, A1, A2) vary the fixed I C address and

allow up to eight devices to share the same I C/SMBus. The fixed

I C address of the PCA9555 is the same as the PCA9554 allowing

up to eight of these devices in any combination to share the same

I C/SMBus.

• Latch-up testing is done to JESDEC Standard JESD78 which

exceeds 100 mA

• Five packages offered: DIP24, SO24, SSOP24, TSSOP24, and

HVQFN24

ORDERING INFORMATION

TEMPERATURE

PACKAGES

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

RANGE

24-Pin Plastic DIP

24-Pin Plastic SO

–40 °C to +85 °C

PCA9555N

PCA9555D

PCA9555

PCA9555D

PCA9555

9555

SOT101-1

SOT137-1

SOT340-1

SOT355-1

SOT616-1

24-Pin Plastic SSOP

24-Pin Plastic TSSOP

24-Pin Plastic HVQFN

PCA9555DB

PCA9555PW

PCA9555BS

Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.

I C is a trademark of Philips Semiconductors Corporation.

SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I C patent.

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

PIN CONFIGURATION — DIP, SO, SSOP, TSSOP

PIN CONFIGURATION — HVQFN

INT

SDA

I/O0.0

18 A0

SCL

I/O1.7

I/O1.6

I/O1.5

I/O1.4

I/O0.1

I/O0.2

I/O0.3

I/O0.4

I/O0.0

I/O0.1

I/O0.2

I/O0.3

I/O0.4

I/O0.5

I/O0.6

I/O0.7

I/O1.7

I/O1.6

I/O1.5

I/O1.4

I/O0.5

I/O1.3

I/O1.2

I/O1.1

I/O1.0

TOP VIEW

Figure 2. Pin configuration — HVQFN

su01683

su01438

Figure 1. Pin configuration — DIP, SO, SSOP, TSSOP

PIN DESCRIPTION

PIN NUMBER

SYMBOL

FUNCTION

DIP, SO, SSOP, TSSOP

HVQFN

INT

Interrupt output (open-drain)

Address input 1

Address input 2

I/O0.0 to I/O0.7

Supply ground

I/O1.0 to I/O1.7

Address input 0

Serial clock line

Serial data line

Supply voltage

4–11

1–8

I/O0.0–I/O0.7

13–20

10–17

I/O1.0–I/O1.7

SCL

SDA

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

BLOCK DIAGRAM

PCA9555

I/O1.0

I/O1.1

I/O1.2

I/O1.3

INPUT/

OUTPUT

PORTS

8-BIT

I/O1.4

I/O1.5

WRITE pulse

READ pulse

I/O1.6

I/O1.7

I C/SMBUS

CONTROL

I/O0.0

I/O0.1

I/O0.2

I/O0.3

SCL

INPUT

FILTER

INPUT/

OUTPUT

PORTS

8-BIT

SDA

I/O0.4

I/O0.5

WRITE pulse

READ pulse

I/O0.6

I/O0.7

INT

POWER-ON

RESET

LP FILTER

INT

NOTE: ALL I/Os ARE SET TO INPUTS AT RESET

SU01439

Figure 3. Block diagram

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

SIMPLIFIED SCHEMATIC OF I/Os

DATA FROM

SHIFT REGISTER

OUTPUT PORT

CONFIGURATION

DATA FROM

SHIFT REGISTER

100 kΩ

WRITE CONFIGURATION

PULSE

I/O PIN

WRITE PULSE

OUTPUT

PORT

INPUT PORT

READ PULSE

TO INT

DATA FROM

SHIFT REGISTER

POLARITY

WRITE

POLARITY

PULSE

POLARITY

INVERSION

SU01473

NOTE: At Power-on Reset, all registers return to default values.

Figure 4. Simplified schematic of I/Os

I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off,

creating a high impedance input with a weak pull-up to V . The

input voltage may be raised above V to a maximum of 5.5 V.

If the I/O is configured as an output, then either Q1 or Q2 is on,

depending on the state of the Output Port register. Care should be

exercised if an external voltage is applied to an I/O configured as an

output because of the low impedance path that exists between the

pin and either V or V

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

REGISTERS

Registers 4 and 5 — Polarity Inversion Registers

bit

N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0

Command Byte

default

bit

Command

N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0

Input port 0

default

Input port 1

This register allows the user to invert the polarity of the Input Port

Port data polarity is inverted. If a bit in this register is cleared (written

with a ‘0’), the Input Port data polarity is retained.

Output port 0

Output port 1

Polarity inversion port 0

Polarity inversion port 1

Configuration port 0

Configuration port 1

Registers 6 and 7 — Configuration Registers

bit

C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0

default

bit

The command byte is the first byte to follow the address byte during

a write transmission. It is used as a pointer to determine which of the

following registers will be written or read.

C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0

default

This register configures the directions of the I/O pins. If a bit in this

as an input with high impedance output driver. If a bit in this register

is cleared (written with ‘0’), the corresponding port pin is enabled as

Registers 0 and 1 — Input Port Registers

bit

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1 IO.0

default

bit

I1.1

I1.0

an output. Note that there is a high value resistor tied to V at each

pin. At reset the device’s ports are inputs with a pull-up to V

I1.7

I1.6

I1.5

I1.4

I1.3

I1.2

default

This register is an input-only port. It reflects the incoming logic levels

of the pins, regardless of whether the pin is defined as an input or an

output by Register 3. Writes to this register have no effect.

POWER-ON RESET

When power is applied to V , an internal power-on reset holds the

PCA9555 in a reset condition until V has reached V

. At that

POR

point, the reset condition is released and the PCA9555 registers and

SMBus state machine will initialize to their default states. The

power-on reset typically completes the reset and enables the part by

The default value ‘X’ is determined by the externally applied logic

level.

the time the power supply is above V

. However, when it is

POR

Registers 2 and 3 — Output Port Registers

required to reset the part by lowering the power supply, it is

necessary to lower it below 0.2 V.

bit

O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0

default

bit

O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0

default

This register is an output-only port. It reflects the outgoing logic

levels of the pins defined as outputs by Register 6 and 7. Bit values

in this register have no effect on pins defined as inputs. In turn,

reads from this register reflect the value that is in the flip-flop

controlling the output selection, NOT the actual pin value.

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

DEVICE ADDRESS

Reading the port registers

In order to read data from the PCA9555, the bus master must first

send the PCA9555 address with the least significant bit set to a

logic 0 (see Figure 5 for device address). The command byte is sent

after the address and determines which register will be accessed.

After a restart, the device address is sent again but this time, the

least significant bit is set to a logic 1. Data from the register defined

by the command byte will then be sent by the PCA9555 (see

Figures 8 and 9). Data is clocked into the register on the falling edge

of the acknowledge clock pulse. After the first byte is read, additional

bytes may be read but the data will now reflect the information in the

other register in the pair. For example, if you read Input Port 1, then

the next byte read would be Input Port 0. There is no limitation on

the number of data bytes received in one read transmission but the

final byte received, the bus master must not acknowledge the data.

slave address

A2 A1 A0 R/W

programmable

fixed

su01441

Figure 5. PCA9555 address

BUS TRANSACTIONS

Writing to the port registers

Data is transmitted to the PCA9555 by sending the device address

and setting the least significant bit to a logic 0 (see Figure 5 for device

address). The command byte is sent after the address and determines

which register will receive the data following the command byte.

Interrupt Output

The open-drain interrupt output is activated when one of the port

pins change state and the pin is configured as an input. The interrupt

is deactivated when the input returns to its previous state or the

input port register is read (see Figure 9). A pin configured as an

output cannot cause an interrupt. Since each 8-bit port is read

independently, the interrupt caused by Port 0 will not be cleared by a

read of Port 1 or the other way around.

The eight registers within the PCA9555 are configured to operate

as four register pairs. The four pairs are Input Ports, Output Ports,

Polarity Inversion Ports, and Configuration Ports. After sending data

to one register, the next data byte will be sent to the other register in

the pair (see Figures and ). For example, if the first byte is sent to

Output Port (register 3), then the next byte will be stored in Output

Port 0 (register 2). There is no limitation on the number of data bytes

sent in one write transmission. In this way, each 8-bit register may

be updated independently of the other registers.

Note that changing an I/O from an output to an input may cause a

false interrupt to occur if the state of the pin does not match the

contents of the Input Port register.

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

US1042

US1043

2004 Sep 30

data from lower

or upper byte

of register

acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

acknowledge

from master

slave address

A2 A1

A2 A1 A0

COMMAND BYTE

DATA

MSB

LSB

first byte

R/W

at this moment master-transmitter

becomes master-receiver and

slave-receiver becomes

slave-transmitter

data from upper

or lower byte of

no acknowledge

from master

MSB

LSB NA

DATA

last byte

SU01463

NOTE: Transfer can be stopped at any time by a STOP condition.

Figure 8. READ from register

SCL

SDA

I0.x

I1.x

I0.x

I1.x

A2 A1 A0

R/W ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

NON ACKNOWLEDGE

FROM MASTER

READ FROM PORT 0

DATA INTO PORT 0

READ FROM PORT 1

DATA INTO PORT 1

INT

SU01464

NOTES: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

It is assumed that the command byte has previously been set to 00 (read input port port register).

Figure 9. READ input port register — scenario 1

SCL

SDA

I0.x

I1.x

I0.x

I1.x

A2 A1 A0

DATA 00

DATA 10

DATA 03

DATA 12

R/W ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

NON ACKNOWLEDGE

FROM MASTER

READ FROM PORT 0

DATA INTO PORT 0

READ FROM PORT 1

DATA INTO PORT 1

DATA 00

DATA 01

DATA 02

DATA 03

DATA 10

DATA 11

DATA 12

INT

SU01651

NOTES: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

It is assumed that the command byte has previously been set to 00 (read input port port register).

Figure 10. READ input port register — scenario 2

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

TYPICAL APPLICATION

SUBSYSTEM 1

(e.g. temp

2 kΩ

SUBSYSTEM 2

(e.g. counter)

sensor)

10 kΩ

INT

RESET

I/O0.0

I/O0.1

I/O0.2

SCL

SDA

SCL

MASTER

CONTROLLER

SDA

INT

I/O0.3

I/O0.4

I/O0.5

ENABLE

ALARM

GND

SUBSYSTEM 3

(e.g. alarm system)

PCA9555

Controlled Switch

(e.g. CBT device)

I/O0.6

I/O0.7

I/O1.0

I/O1.1

I/O1.2

I/O1.3

I/O1.4

I/O1.5

I/O1.6

I/O1.7

10 DIGIT

NUMERIC

KEYPAD

NOTE: Device address configured as 1110100 for this example

I/O0.0, I/O0.2, I/O0.3, configured as outputs

I/O0.1, I/O0.4, I/O0.5, configured as inputs

I/O0.6, I/O0.7, and I/O1.0 to I/O1.7 configured as inputs

SW02284

Figure 11. Typical application.

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Supply voltage

–0.5

6.0

DC input current on an I/O

DC output current on an I/O

DC input current

– 0.5

I/O

—

± 50

± 20

160

200

+150

+85

°C

Supply current

—

Supply current

—

tot

Total power dissipation

Storage temperature range

Operating ambient temperature

—

stg

–65

–40

amb

°C

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take

precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”Handling MOS devices”.

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

DC CHARACTERISTICS

= 2.3 V to 5.5 V; V = 0 V; T

= –40 to +85 °C; unless otherwise specified.

amb

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Supplies

Supply voltage

Supply current

2.3

—

5.5

Operating mode; V = 5.5 V; no load;

135

200

µA

= 100 kHz

SCL

Standby mode; V = 5.5 V; no load;

Standby current

—

1.1

1.5

stbl

V = V ; f

= 0 kHz; I/O = inputs

SS SCL

Standby mode; V = 5.5 V; no load;

Standby current

—

0.25

1.5

µA

stbh

V = V ; f

= 0 kHz; I/O = inputs

DD SCL

Power-on reset voltage (Note 1)

No load; V = V or V

1.65

POR

input SCL; input/output SDA

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

Leakage current

–0.5

—

0.3 V

0.7 V

5.5

—

= 0.4V

µA

V = V = V

–1

Input capacitance

V = V

—

I/Os

LOW-level input voltage

HIGH-level input voltage

–0.5

0.7V

—

0.3V

5.5

—

= 0.5 V; V = 2.3–5.5 V; Note 2

8–20

10–24

—

LOW-level output current

= 0.7 V; V = 2.3–5.5 V; Note 2

1.8

1.7

2.6

2.5

4.1

4.0

—

= –8 mA; V = 2.3 V; Note 3

= –10 mA; V = 2.3 V; Note 3

—

= –8 mA; V = 3.0 V; Note 3

—

HIGH-level output voltage

= –10 mA; V = 3.0 V; Note 3

—

= –8 mA; V = 4.75 V; Note 3

—

= –10 mA; V = 4.75 V; Note 3

—

Input leakage current

Input capacitance

= 3.6 V; V = V

—

µA

= 5.5 V; V = V

—

–100

—

3.7

Output capacitance

—

Interrupt INT

LOW level output current

= 0.4 V

—

Select Inputs A0, A1, A2

LOW-level input voltage

HIGH-level input voltage

Input leakage current

–0.5

—

0.3V

0.7V

5.5

–1

µA

NOTES:

1. V must be lowered to 0.2 V in order to reset part.

2. Each I/O must be externally limited to a maximum of 25 mA and each octal (I/O0.0 to I/O0.7 and I/O1.0 to I/O1.7) must be limited to a

maximum current of 100 mA for a device total of 200 mA.

3. The total current sourced by all I/Os must be limited to 160 mA.

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

SW02259

1.4

= –40 °C

= +25 °C

amb

= 5.5 V

(mA)

amb

1.2

1.0

0.8

0.6

0.4

0.2

0.0

A2, A1, A0 set to ‘0’

amb

= +85 °C

All 1’s

One 0’s

Three 0’s

All 0’s

NOTE:

Each I/O adds about 0.07 mA to I when held LOW.

Figure 12. I versus number of I/Os held LOW

SW02281

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

= –8 mA

(V)

= –10 mA

2.7 V

3.6 V

5.5 V

Figure 13. V maximum

SW02282

4.5

4.0

3.5

3.0

2.5

2.0

1.5

= –8 mA

(V)

= –10 mA

2.3 V

3.0 V

4.75 V

Figure 14. V minimum

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

AC SPECIFICATIONS

STANDARD MODE

FAST MODE

I C-BUS

SYMBOL

PARAMETER

UNITS

MIN

MAX

100

—

MIN

MAX

400

—

Operating frequency

1.3

kHz

µs

SCL

Bus free time between STOP and START conditions

Hold time after (repeated) START condition

Repeated START condition setup time

Setup time for STOP condition

4.7

4.0

4.7

4.0

0.3

BUF

—

0.6

—

HD;STA

—

0.6

—

SU;STA

SU;STO

VD;ACK

—

0.6

—

Valid time of ACK condition

3.45

—

0.1

0.9

—

Data in hold time

HD;DAT

Data out valid time

300

250

4.7

4.0

—

VD;DAT

Data setup time

—

100

—

SU;DAT

Clock LOW period

—

1.3

—

LOW

Clock HIGH period

—

0.6

—

HIGH

Clock/Data fall time

300

1000

20 + 0.1C

—

300

Clock/Data rise time

—

Pulse width of spikes that must be suppressed by the input filters

—

Port Timing

Output data valid

—

150

200

—

150

200

—

µs

Input data setup time

Input data hold time

—

Interrupt Timing

Interrupt valid

Interrupt reset

—

µs

NOTES:

1. C = total capacitance of one bus line in pF.

2. t

3. t

= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

= minimum time for SDA data out to be valid following SCL LOW.

VD;ACK

VD;DAT

SDA

LOW

SU;DAT

BUF

HD;STA

SCL

SU;STD

SU;STA

HD;STA

HD;DAT HIGH

SU01469

Figure 15. Definition of timing

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

DIP24: plastic dual in-line package; 24 leads (600 mil)

SOT101-1

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

SO24: plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm

SOT340-1

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm

SOT355-1

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals;

body 4 x 4 x 0.85 mm

SOT616-1

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

REVISION HISTORY

Rev

Date

Description

20040930

Product data sheet (9397 750 14125). Supersedes data of 2004 Jul 27 (9397 750 13271).

Modifications:

• Section “Registers 0 and 1—Input Port Registers” on page 6: add register bit table and second paragraph.

• Figure 11 on page 11: resistor values modified

• “DC Characteristics” table on page 13:

– sub-section “I/Os”:

change V (max) from 0.8 V to 0.3V

change V (min) from 2.0 V to 0.7V

– sub-section “Select inputs A0, A1, A2:

change V (max) from 0.8 V to 0.3V

change V (min) from 2.0 V to 0.7V

– Add (new) Note 1

– Note 2 re-written.

20040727

20020726

Product data (9397 750 13271). Supersedes data of 2002 Jul 26 (9397 750 10164).

Product data (9397 750 10164). ECN 853-2252 28672 of 26 July 2002.

Supersedes data of 2002 May 13 (9397 750 09818).

20020513

20010507

Product data (9397 750 09818).

Product data (9397 750 08343).

2004 Sep 30

Philips Semiconductors

Product data sheet

16-bit I²C and SMBus I/O port with interrupt

PCA9555

Purchase of Philips I C components conveys a license under the Philips’ I C patent

to use the components in the I C system provided the system conforms to the

I C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Data sheet status

Product

status

Definitions

[1]

Level

Data sheet status

[2] [3]

Objective data

Development

This data sheet contains data from the objective specification for product development.

Philips Semiconductors reserves the right to change the specification in any manner without notice.

Preliminary data

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the specification without notice, in

order to improve the design and supply the best possible product.

III

Product data

This data sheet contains data from the product specification. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notification (CPCN).

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given

in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no

representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree

to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described

or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated

viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys

nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,

Koninklijke Philips Electronics N.V. 2004

Contact information

For additional information please visit

http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

Date of release: 09-04

9397 750 14125

For sales offices addresses send e-mail to:

sales.addresses@www.semiconductors.philips.com.

Document order number:

Philips

Semiconductors

2004 Sep 30

PCA9555PW [NXP]

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