PCA9557BS,118_技术文档

PCA9557

8-bit I²C-bus and SMBus I/O port with reset

Rev. 7 — 10 December 2013

Product data sheet

1. General description

The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for

SMBus and I²C-bus applications. The PCA9557 consists of an 8-bit input port register,

8-bit output port register, and an I²C-bus/SMBus interface. It has low current consumption

and a high-impedance open-drain output pin, IO0.

The system master can enable the PCA9557’s I/O as either input or output by writing to

the configuration register. The system master can also invert the PCA9557 inputs by

writing to the active HIGH polarity inversion register. Finally, the system master can reset

the PCA9557 in the event of a time-out by asserting a LOW in the reset input.

The power-on reset puts the registers in their default state and initializes the

I²C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to

occur without de-powering the part.

2. Features and benefits

 Lower voltage, higher performance migration path for the PCA9556

 8 general purpose input/output expander/collector

 Input/output configuration register

 Active HIGH polarity inversion register

 I²C-bus and SMBus interface logic

 Internal power-on reset

 Noise filter on SCL/SDA inputs

 Active LOW reset input

 3 address pins allowing up to 8 devices on the I²C-bus/SMBus

 High-impedance open-drain on IO0

 No glitch on power-up

 Power-up with all channels configured as inputs

 Low standby current

 Operating power supply voltage range of 2.3 V to 5.5 V

 5 V tolerant inputs/outputs

 0 kHz to 400 kHz clock frequency

 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

 Three packages offered: SO16, TSSOP16, HVQFN16

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

3. Ordering information

Table 1.

Ordering information

Type number Topside

marking

Package

Name

Description

Version

PCA9557BS

9557

HVQFN16

plastic thermal enhanced very thin quad flat package; no leads;

SOT629-1

16 terminals; body 4  4  0.85 mm

PCA9557D

SO16

plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

SOT403-1

PCA9557PW PCA9557

TSSOP16

plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

3.1 Ordering options

Table 2.

Ordering options

Type number

Orderable

Package

Packing method

Minimum Temperature range

part number

order

quantity

PCA9557BS

PCA9557D

PCA9557BS,118

PCA9557D,112

PCA9557D,118

PCA9557PW,112

PCA9557PW,118

HVQFN16

SO16

Reel 13” Q1/T1

*Standard mark SMD

6000

1000

2500

2400

2500

T

_amb= 40 C to +85 C

T_amb= 40 C to +85 C

_amb= 40 C to +85 C

T_amb= 40 C to +85 C

Standard marking

* IC’s tube - DSC bulk pack

SO16

Reel 13” Q1/T1

*Standard mark SMD

T

PCA9557PW

TSSOP16

Standard marking

* IC’s tube - DSC bulk pack

Reel 13” Q1/T1

T_amb= 40 C to +85 C

*Standard mark SMD

4. Block diagram

PCA9557

A0

A1

A2

IO0

IO1

IO2

8-bit

SCL

SDA

INPUT

2

IO3

IO4

IO5

IO6

IO7

INPUT/

OUTPUT

PORTS

I C-BUS/SMBus

CONTROL

FILTER

write pulse

read pulse

V

DD

POWER-ON

RESET

V

SS

RESET

002aad275

Fig 1. Block diagram of PCA9557

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

2 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

data from

shift register

configuration

register

data from

shift register

D

Q

output port

register data

FF

write configuration

pulse

D

Q

CK

Q

FF

IO0

write pulse

CK

ESD protection

diode

output port

register

V

SS

input port

register

D

Q

input port

register data

FF

CK

read pulse

polarity inversion

register

data from

shift register

polarity inversion

register data

D

Q

FF

write polarity

pulse

CK

002aad277

On power-up or reset, all registers return to default values.

Fig 2. Simplified schematic of IO0

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

3 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

data from

shift register

output port

register data

configuration

register

V

DD

data from

shift register

D

Q

ESD protection

diode

FF

write configuration

pulse

D

Q

CK

Q

FF

IO1 to IO7

write pulse

CK

ESD protection

diode

output port

register

V

SS

input port

register

D

Q

input port

register data

FF

CK

read pulse

polarity inversion

register

data from

shift register

polarity inversion

register data

D

Q

FF

write polarity

pulse

CK

002aad278

On power-up or reset, all registers return to default values.

Fig 3. Simplified schematic of IO1 to IO7

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

4 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

5. Pinning information

5.1 Pinning

1

16

15

14

13

12

11

10

9

SCL

SDA

A0

V

DD

2

3

4

5

6

7

8

RESET

IO7

1

2

3

4

5

6

7

8

16

15

14

13

SCL

SDA

A0

V

DD

RESET

IO7

A1

IO6

PCA9557D

A2

IO5

A1

IO6

PCA9557PW

12 IO5

IO0

IO1

IO4

A2

11

10

9

IO0

IO1

IO4

IO3

IO2

IO3

V

SS

IO2

V

SS

002aad272

002aad273

Fig 4. Pin configuration for SO16

Fig 5. Pin configuration for TSSOP16

terminal 1

index area

1

2

3

4

12

11

10

9

A0

A1

IO7

IO6

IO5

IO4

PCA9557BS

A2

IO0

002aad274

Transparent top view

Fig 6. Pin configuration for HVQFN16

5.2 Pin description

Table 3.

Pin description

Symbol

Description

SO16, TSSOP16

HVQFN16

SCL

SDA

A0

1

2

3

4

5

6

7

15

16

1

serial clock line

serial data line

address input 0

address input 1

address input 2

input/output 0 (open-drain)

input/output 1

A1

2

A2

3

IO0

IO1

4

5

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

5 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

Table 3.

Pin description …continued

Symbol

Description

SO16, TSSOP16

HVQFN16

V_SS

IO2

8

6^[1]

supply ground

input/output 2

input/output 3

input/output 4

input/output 5

input/output 6

input/output 7

active LOW reset input

supply voltage

9

7

IO3

10

11

12

13

14

15

16

8

IO4

9

IO5

10

11

12

13

14

IO6

IO7

RESET

V_DD

[1] HVQFN16 package die supply ground is connected to both the V_SSpin and the exposed center pad. The

V_SSpin must be connected to the supply ground for proper device operation. For enhanced thermal,

electrical, and board-level performance, the exposed pad needs to be soldered to the board using a

corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias

need to be incorporated in the PCB in the thermal pad region.

6. System diagram

INPUT

PORT

POLARITY

INVERSION

CONFIG.

Q7

OUTPUT

PORT

1.1 kΩ

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

IO0

RESET

Q6

Q5

Q4

Q3

Q2

Q1

Q0

IO1

IO2

IO3

IO4

IO5

IO6

IO7

1.6 kΩ

SCL

2

I C-BUS/SMBus

1.6 kΩ

1.1 kΩ

INTERFACE

LOGIC

SDA

A2

or

A1

A0

002aad276

Fig 7. System diagram

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

6 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

7. Functional description

Refer to Figure 1 “Block diagram of PCA9557”.

7.1 Device address

Following a START condition the bus master must output the address of the slave it is

accessing. The address of the PCA9557 is shown in Figure 8. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW.

slave address

0

1

A2 A1 A0 R/W

fixed

programmable

002aad279

Fig 8. PCA9557 device address

The last bit of the slave address defines the operation to be performed. When set to

logic 1 a read is selected, while a logic 0 selects a write operation.

7.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9557, which will be stored in the control register. This register can be

written and read via the I²C-bus.

bit:

7

0

6

0

5

0

4

0

3

0

2

0

1

0

D1 D0

002aad280

Fig 9. Control register

Table 4.

Register definition

D1

0

D0

0

Name

Access

Description

Register 0

Register 1

Register 2

Register 3

read-only

read/write

Input port register

Output port register

Polarity inversion register

Configuration register

0

1

0

1

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

7 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

7.3 Register descriptions

7.3.1 Register 0 - Input port register

This register is a read-only port. It reflects the incoming logic levels of the pins, regardless

of whether the pin is defined as an input or an output by the Configuration register. Writes

to this register have no effect.

Table 5.

Bit

Register 0 - Input port register bit allocation

7

6

5

4

3

2

1

0

Symbol

I7

I6

I5

I4

I3

I2

I1

I0

7.3.2 Register 1 - Output port register

This register reflects the outgoing logic levels of the pins defined as outputs by the

Configuration register. Bit values in this register have no effect on pins defined as inputs.

In turn, reads from this register reflect the value that is in the flip-flop controlling the output

selection, not the actual pin value.

Table 6.

Bit

Register 1 - Output port register bit allocation

7

O7

0

6

O6

0

5

O5

0

4

O4

0

3

O3

0

2

O2

0

1

O1

0

O0

0

Symbol

Default

7.3.3 Register 2 - Polarity inversion register

This register enables polarity inversion of pins defined as inputs by the Configuration

register. If a bit in this register is set (written with logic 1), the corresponding port pin’s

polarity is inverted. If a bit in this register is cleared (written with logic 0), the

corresponding port pin’s original polarity is retained.

Table 7.

Bit

Register 2 - Polarity inversion register bit allocation

7

N7

1

6

N6

1

5

N5

1

4

N4

1

3

N3

0

2

N2

0

1

N1

0

N0

0

Symbol

Default

7.3.4 Register 3 - Configuration register

This register configures the directions of the I/O pins. If a bit in this register is set, the

corresponding port pin is enabled as an input with high-impedance output driver. If a bit in

this register is cleared, the corresponding port pin is enabled as an output.

Table 8.

Bit

Register 3 - Configuration register bit allocation

7

C7

1

6

C6

1

5

C5

1

4

C4

1

3

C3

1

2

C2

1

C1

1

0

C0

1

Symbol

Default

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

8 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

7.4 Power-on reset

When power is applied to V_DD, an internal Power-On Reset (POR) holds the PCA9557 in

a reset condition until V_DDhas reached V_POR. At that point, the reset condition is released

and the PCA9557 registers and I²C-bus/SMBus state machine will initialize to their default

states. Thereafter, V_DDmust be lowered below 0.2 V to reset the device.

7.5 RESET input

A reset can be accomplished by holding the RESET pin LOW for a minimum of t_w(rst). The

PCA9557 registers and SMBus/I²C-bus state machine will be held in their default state

until the RESET input is once again HIGH. This input requires a pull-up resistor to V_DDif

no active connection is used.

8. Characteristics of the I²C-bus

The I²C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 10).

SDA

SCL

data line

stable;

data valid

change

of data

allowed

mba607

Fig 10. Bit transfer

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is defined as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P) (see Figure 11).

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

9 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

SDA

SCL

S

P

STOP condition

START condition

mba608

Fig 11. Definition of START and STOP conditions

8.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 12).

SDA

SCL

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

2

SLAVE

RECEIVER

MASTER

TRANSMITTER

I C-BUS

MULTIPLEXER

SLAVE

002aaa966

Fig 12. System configuration

8.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

10 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

data output

by transmitter

not acknowledge

acknowledge

data output

by receiver

SCL from master

1

2

8

9

S

clock pulse for

START

condition

acknowledgement

002aaa987

Fig 13. Acknowledgement on the I²C-bus

8.4 Bus transactions

Data is transmitted to the PCA9557 registers using Write Byte transfers (see Figure 14

and Figure 15). Data is read from the PCA9557 registers using Read and Receive Byte

transfers (see Figure 16 and Figure 17).

SCL

1

2

3

4

5

6

7

8

9

STOP

condition

slave address

A2 A1 A0

command byte

data to port

DATA 1

SDA

S

0

1

0

A

0

1

A

P

START condition

R/W acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

write to port

t

v(Q)

data out from port

DATA 1 VALID

002aad281

Fig 14. Write to output port register

SCL

1

2

3

4

5

6

7

8

9

STOP

condition

slave address

A2 A1 A0

command byte

data to register

DATA

SDA

S

0

1

0

A

0

1

1/0

A

P

START condition

R/W acknowledge

from slave

acknowledge

from slave

acknowledge

from slave

002aad282

Fig 15. Write to I/O configuration or polarity inversion registers

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

11 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

slave address

command byte

(cont.)

SDA

S

0

1

A2 A1 A0

0

A

START condition

R/W

acknowledge

from slave

acknowledge

from slave

slave address

data from register

DATA (first byte)

data from register

(cont.)

S

0

1

A2 A1 A0

1

A

DATA (last byte)

NA P

(repeated)

START condition

R/W

acknowledge

from master

no acknowledge STOP

from master condition

acknowledge

from slave

at this moment master-transmitter becomes master-receiver

and slave-receiver becomes slave-transmitter

002aad283

Fig 16. Read from register

no acknowledge

from master

slave address

A2 A1 A0

data from port

DATA 1

data from port

DATA 4

SDA

S

0

1

A

NA

P

START condition

R/W acknowledge

from slave

acknowledge

from master

STOP

condition

read from

port

t

su(D)

h(D)

data into

port

DATA 1

DATA 2

DATA 3

DATA 4

002aad284

Remark: This figure assumes the command byte has previously been programmed with 00h.

Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge

phase is valid (output mode). Input data is lost.

Fig 17. Read input port register

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

12 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

9. Application design-in information

V

(5 V)

DD

100 kΩ

(× 5)

620 Ω

1.8 kΩ

2 kΩ

V

DD

MASTER

CONTROLLER

PCA9557

SUBSYSTEM 1

IO0

(e.g., temp. sensor)

SCL

SDA

INT

SDA

IO1

IO2

IO3

IO4

IO5

IO6

IO7

RESET

SUBSYSTEM 2

(e.g., counter)

V

SS

A

controlled switch

(e.g., CBT device)

enable

A2

A1

A0

B

V

SS

ALARM

SUBSYSTEM 3

(e.g., alarm system)

V

DD

002aad285

Device address configured as 0011 100x for this example.

IO0, IO2, IO3 configured as outputs.

IO1, IO4, IO5 configured as inputs.

IO6, IO7 are not used.

Fig 18. Typical application

9.1 Minimizing I_DDwhen the I/Os are used to control LEDs

When the I/Os are used to control LEDs, they are normally connected to V_DDthrough a

resistor as shown in Figure 18. Since the LED acts as a diode, when the LED is off the

I/O V_Iis about 1.2 V less than V_DD. The supply current, I_DD, increases as V_Ibecomes

lower than V_DD

.

Designs needing to minimize current consumption, such as battery power applications,

should consider maintaining the I/O pins greater than or equal to V_DDwhen the LED is off.

Figure 19 shows a high value resistor in parallel with the LED. Figure 20 shows V_DDless

than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O V_I

at or above V_DDand prevents additional supply current consumption when the LED is off.

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

13 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

3.3 V

5 V

V

DD

V

100 kΩ

V

DD

LED

IOn

002aac660

002aac661

Fig 19. High value resistor in parallel with

the LED

Fig 20. Device supplied by a lower voltage

10. Limiting values

Table 9.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

Parameter

Conditions

Min

Max

+6

Unit

V

supply voltage

input voltage

input current

0.5

V_I

V_SS 0.5

5.5

V

I_I

-

20

400

mA

A

I_IHL(max)

maximum allowed input current

V_I V_DDor V_I V_SS

through protection diode (IO1 to IO7)

V_I/O

voltage on an input/output pin

input/output current

I/O as an input, except IO0

IO0 as an input

V_SS 0.5

5.5

V

V_SS 0.5

5.5

V

I_I/O

IO0 as an input

-

+400

20

50

85

A

mA

mW

C

-

I_O(IOn)

I_DD

output current on pin IOn

supply current

-

I_SS

ground supply current

total power dissipation

storage temperature

ambient temperature

-

100

200

+150

+85

P_tot

-

T_stg

T_amb

65

40

operating

C

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

14 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

11. Static characteristics

Table 10. Static characteristics

V_DD= 2.3 V to 5.5 V; V_SS= 0 V; T_amb= 40 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supplies

V_DD

supply voltage

supply current

2.3

-

5.5

25

V

I_DD

operating mode; V_DD= 5.5 V;

no load; f_SCL= 100 kHz

19

A

I_stbL

LOW-level standby current

standby mode; V_DD= 5.5 V;

no load; V_I= V_SS; f_SCL= 0 kHz;

I/O = inputs

-

0.25

0.8

1

A

mA

V

I_stbH

I_stb

V_POR

HIGH-level standby current standby mode; V_DD= 5.5 V;

no load; V_I= V_DD; f_SCL= 0 kHz;

I/O = inputs

1

additional standby current

standby mode; V_DD= 5.5 V;

every LED I/O at V_I= 4.3 V;

f_SCL= 0 kHz

1

[1]

power-on reset voltage

no load; V_I= V_DDor V_SS

1.65

2.1

Input SCL; input/output SDA

V_IL

V_IH

I_OL

I_L

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

leakage current

0.5

-

+0.3V_DD

V

0.7V_DD

-

5.5

-

V

V_OL= 0.4 V; V_DD= 2.3 V

V_I= V_DDor V_SS

V_I= V_SS

3

-

mA

A

pF

1

-

+1

10

C_i

input capacitance

6

I/Os

V_IL

V_IH

I_OL

I_OH

LOW-level input voltage

HIGH-level input voltage

LOW-level output current

HIGH-level output current

0.5

-

+0.8

V

2.0

-

5.5

V

[2]

[3]

V_OL= 5.5 V; V_DD= 2.3 V

except pin IO0; V_OH= 2.4 V

pin IO0; V_OH= 4.6 V

8

4

-

10

-

mA

A

pF

-

1

pin IO0; V_OH= 3.3 V

-

1

I_LI

C_i

input leakage current

input capacitance

output capacitance

V_DD= 5.5 V; V_I= V_SS

-

100

-

3.7

5

C_o

-

Select inputs A0, A1, A2 and RESET

V_IL

V_IH

I_LI

LOW-level input voltage

HIGH-level input voltage

input leakage current

0.5

2.0

1

-

+0.8

5.5

+1

V

A

[1] V_DDmust be lowered to 0.2 V in order to reset part.

[2] The total amount sunk by all I/Os must be limited to 100 mA and 25 mA per bit.

[3] The total current sourced by all I/Os must be limited to 85 mA and 20 mA per bit.

PCA9557

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 10 December 2013

15 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

12. Dynamic characteristics

Table 11. Dynamic characteristics

Symbol Parameter

Conditions

Standard-mode

I²C-bus

Fast-mode I²C-bus Unit

Min

0

Max

100

-

Min

0

Max

400

-

f_SCL

t_BUF

SCL clock frequency

kHz

bus free time between a STOP and

START condition

4.7

1.3

s

t_HD;STA

t_SU;STA

hold time (repeated) START condition

4.0

4.7

-

0.6

-

s

set-up time for a repeated START

condition

t_SU;STO

t_HD;DAT

t_VD;ACK

t_VD;DAT

t_SU;DAT

t_LOW

t_HIGH

t_f

set-up time for STOP condition

data hold time

4.0

-

0.6

-

s

ns

s

ns

s

ns

0

-

0

[1]

[2]

data valid acknowledge time

data valid time

-

1

-

0.9

-

1

-

data set-up time

250

4.7

4.0

-

100

1.3

LOW period of the SCL clock

HIGH period of the SCL clock

fall time of both SDA and SCL signals

rise time of both SDA and SCL signals

-

0.6

-

[3]

300

1000

50

20 + 0.1C_b

-

300

50

t_r

-

t_SP

pulse width of spikes that must be

suppressed by the input filter

-

Port timing

t_v(Q)

data output valid time

pin IO0

-

250

-

250

ns

pins IO1 to IO7

200

t_su(D)

t_h(D)

Reset timing

data input set-up time

0

-

0

-

data input hold time

200

t_w(rst)

t_rec(rst)

t_rst

reset pulse width

6

0

-

6

0

-

ns

reset recovery time

reset time

400

[1] t_VD;ACK= time for acknowledgement signal from SCL LOW to SDA (out) LOW.

[2] t_VD;DAT= minimum time for SDA data out to be valid following SCL LOW.

[3] C_b= total capacitance of one bus line in pF.

PCA9557

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 10 December 2013

16 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

0.7 × V

0.3 × V

DD

SDA

DD

t

SP

t

r

f

HD;STA

BUF

t

LOW

0.7 × V

0.3 × V

DD

SCL

DD

t

SU;STO

HD;STA

SU;STA

t

SU;DAT

HD;DAT

HIGH

P

S

Sr

P

002aaa986

Fig 21. Definition of timing on the I²C-bus

ACK or read cycle

START

SCL

SDA

30 %

t

rst

RESET

50 %

t

rec(rst)

t

w(rst)

t

rst

I/O configured

as inputs

IOn

50 %

002aad289

Fig 22. Definition of RESET timing

PCA9557

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 10 December 2013

17 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

13. Package outline

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Fig 23. Package outline SOT109-1 (SO16)

PCA9557

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 10 December 2013

18 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

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Fig 24. Package outline SOT403-1 (TSSOP16)

PCA9557

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 10 December 2013

19 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

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Fig 25. Package outline SOT629-1 (HVQFN16)

PCA9557

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 10 December 2013

20 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

14. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate precautions are taken as

described in JESD625-A or equivalent standards.

15. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

15.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

15.3 Wave soldering

Key characteristics in wave soldering are:

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

21 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

• Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath specifications, including temperature and impurities

15.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 26) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 12 and 13

Table 12. SnPb eutectic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

235

 350

220

< 2.5

 2.5

220

Table 13. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 26.

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

22 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 26. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

23 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

16. Soldering: PCB footprints

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Fig 27. PCB footprint for SOT109-1 (SO16); reflow soldering

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

24 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

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VRWꢀꢁꢂꢃꢄBIU

Fig 28. PCB footprint for SOT403-1 (TSSOP16); reflow soldering

PCA9557

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 10 December 2013

25 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

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Fig 29. PCB footprint for SOT629-1 (HVQFN16); reflow soldering

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

26 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

17. Abbreviations

Table 14. Abbreviations

Acronym

CBT

Description

Cross Bar Technology

Charged-Device Model

CDM

CMOS

ESD

Complementary Metal-Oxide Semiconductor

ElectroStatic Discharge

Human Body Model

HBM

I²C-bus

I/O

Inter-Integrated Circuit bus

Input/Output

LED

Light-Emitting Diode

MM

Machine Model

PCB

Printed-Circuit Board

Power-On Reset

POR

SMBus

System Management Bus

18. Revision history

Table 15. Revision history

Document ID

PCA9557 v.7

Modifications:

Release date

Data sheet status

Change notice

Supersedes

20131210

Product data sheet

-

PCA9557 v.6

• Section 2 “Features and benefits”, 17th bullet item: deleted phrase “150 V MM per JESD22-A115”

• Table 1 “Ordering information”: added column ‘Topside marking’ (moved from Table 2)

• Table 2 “Ordering options”:

–

deleted column ‘Topside mark’ (moved to Table 1)

–

added columns ‘Orderable part number’, ‘Package’, ‘Packing method’ and ‘Minimum order

quantity’

• Table 10 “Static characteristics”, sub-section “Input SCL; input/output SDA”:

_OL: added “V_DD= 2.3 V” to Conditions

• Table 10 “Static characteristics”, sub-section “I/Os”:

_OL: added “V_OL= 0.55 V; V_DD= 2.3 V” to Conditions

–

I

–

I

• Table 11 “Dynamic characteristics”, t_VD;DAT: Unit corrected from “ms” to “s” (this is a correction to

documentation only, no change to device)

• Added Section 16 “Soldering: PCB footprints”

PCA9557 v.6

PCA9557 v.5

20080611

20070912

20041124

Product data sheet

-

PCA9557 v.5

PCA9557 v.4

PCA9557 v.3

PCA9557 v.4

(9397 750 13336)

PCA9557 v.3

(9397 750 10872)

20021213

20020513

20011212

Product data

ECN 853-2308 29160

of 06 Nov 2002

PCA9557 v.2

PCA9557 v.1

-

PCA9557 v.2

(9397 750 09819)

ECN 853-2308 28188

of 13 May 2002

PCA9557 v.1

ECN 853-2308 27449

of 12 Dec 2001

PCA9557

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Product data sheet

Rev. 7 — 10 December 2013

27 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use — NXP Semiconductors products are not designed,

19.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

19.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

PCA9557

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 10 December 2013

28 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

19.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

I²C-bus — logo is a trademark of NXP B.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

PCA9557

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 10 December 2013

29 of 30

PCA9557

NXP Semiconductors

8-bit I²C-bus and SMBus I/O port with reset

21. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

19.3

19.4

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2

20

21

Contact information . . . . . . . . . . . . . . . . . . . . 29

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3

3.1

4

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

6

System diagram. . . . . . . . . . . . . . . . . . . . . . . . . 6

7

7.1

7.2

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.4

Functional description . . . . . . . . . . . . . . . . . . . 7

Device address. . . . . . . . . . . . . . . . . . . . . . . . . 7

Control register. . . . . . . . . . . . . . . . . . . . . . . . . 7

Register descriptions . . . . . . . . . . . . . . . . . . . . 8

Register 0 - Input port register . . . . . . . . . . . . . 8

Register 1 - Output port register. . . . . . . . . . . . 8

Register 2 - Polarity inversion register . . . . . . . 8

Register 3 - Configuration register . . . . . . . . . . 8

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9

RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.5

8

Characteristics of the I²C-bus . . . . . . . . . . . . . 9

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

START and STOP conditions . . . . . . . . . . . . . . 9

System configuration . . . . . . . . . . . . . . . . . . . 10

Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10

Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 11

8.1

8.1.1

8.2

8.3

8.4

9

9.1

Application design-in information . . . . . . . . . 13

Minimizing I_DDwhen the I/Os are used to

control LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . 13

10

11

12

13

14

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14

Static characteristics. . . . . . . . . . . . . . . . . . . . 15

Dynamic characteristics . . . . . . . . . . . . . . . . . 16

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18

Handling information. . . . . . . . . . . . . . . . . . . . 21

15

Soldering of SMD packages . . . . . . . . . . . . . . 21

Introduction to soldering . . . . . . . . . . . . . . . . . 21

Wave and reflow soldering . . . . . . . . . . . . . . . 21

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 21

Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 22

15.1

15.2

15.3

15.4

16

17

18

Soldering: PCB footprints. . . . . . . . . . . . . . . . 24

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 27

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27

19

19.1

19.2

Legal information. . . . . . . . . . . . . . . . . . . . . . . 28

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 10 December 2013

Document identifier: PCA9557


型号：	PCA9557BS,118
厂家：	NXP
描述：	PCA9557 - 8-bit I2C-bus and SMBus I/O port with reset QFN 16-Pin PC 外围集成电路
文件：	总30页 (文件大小：298K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCA9557BS,118 [NXP]

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