PCA9560_04 [NXP]
Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch; 双5位复用1位锁存I2C EEPROM的DIP开关
| 型号： | PCA9560_04 |
| 厂家： | 
NXP |
| 描述： | Dual 5-bit multiplexed 1-bit latched I2C EEPROM DIP switch |
| 文件： | 总17页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
Product data sheet
2004 May 19
Supersedes data of 2003 Jun 27
Philips
Semiconductors
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
IDentification code) configuration. It is used to bypass the
CPU-defined VID values and provide a different set of VID values to
the VRM, if an increase in the CPU voltage is desired. An increase
in CPU voltage combined with an increase in CPU frequency leads
to a performance boost of up to 7.5%. Lower CPU voltage reduces
power consumption. The main advantage of the PCA9560 over the
older PCA9559 device in this application is that it contains two
internal non-volatile EEPROM registers instead of just one, allowing
three independent settings (performance operation, deep sleep
mode and deeper sleep mode) instead of only two (performance
operation and deep sleep mode). The PCA9560 is footprint
compatible and a drop-in replacement for the PCA9559, without any
software modifications required.
FEATURES
• 5-bit 3-to-1 multiplexer, 1-bit latch DIP switch
• 5-bit external hardware pins
The PCA9560 has 2 address pins allow up to 4 devices to be placed
• Two 6-bit internal non-volatile registers, fully pin-to-pin compatible
2
on the same I C bus or SMBus.
with PCA9559
• Selection between the two non-volatile registers
PIN CONFIGURATION
• Selection between non-volatile registers and external hardware
pins
2
SCL
SDA
A1
1
2
V
• I C/SMBus interface logic
20
19
18
17
16
15
14
13
DD
WP
• Internal pull-up resistors on input pin and control signals
MUX_SELECT_1
3
• Active high write protect on input controls the ability to write to the
non-volatile registers
4
A0
NON-MUXED_OUT
MUX_OUT A
2
• 2 address pins, allowing up to 4 devices on the I C-bus
• 5 open drain multiplexed outputs
• Open drain non-multiplexed output
MUX_IN A
5
MUX_IN B
MUX_IN C
MUX_IN D
MUX_IN E
6
MUX_OUT B
MUX_OUT C
7
8
MUX_OUT D
• Internal 6-bit non-volatile registers programmable and readable via
2
I C-bus
9
12 MUX_OUT E
2
• External hardware 5-bit value readable via I C-bus
GND
10
MUX_SELECT_0
11
2
• Multiplexer selection can be overridden by I C-bus
SW00829
• Operating power supply voltage 3.0 V to 3.6 V
• 5 V and 2.5 V tolerant inputs/outputs
• 0 to 400 kHz clock frequency
Figure 1. Pin configuration
• ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V
PIN DESCRIPTION
MM per JESD22-A115, and 1000 V CDM per JESD22-C101
PIN
1
SYMBOL
FUNCTION
Serial I C-bus clock
• Latch-up testing is done to JESDEC Standard JESD78 which
2
exceeds 100 mA.
SCL
SDA
• Package offering: SO20, TSSOP20
2
2
Serial bi-directional I C-bus data
DESCRIPTION
2
3
A1
Programmable LSBs of I C
The PCA9560 is a 20-pin CMOS device consisting of two 6-bit
non-volatile EEPROM registers, 5 hardware pin inputs and a 5-bit
multiplexed output with one latched EEPROM bit. It is used for DIP
switch-free or jumper-less system configuration and supports Mobile
and Desktop VID Configuration, where 3 preset values (2 sets of
internal non-volatile registers and 1 set of external hardware pins)
set processor voltage for operation in either performance, deep
sleep or deeper sleep modes. The PCA9560 is also useful in server
and telecom/networking applications when used to replace DIP
switches or jumpers, since the settings can be easily changed via
address
4
A0
5–9
10
MUX_IN A–E
GND
External inputs to multiplexer
Ground
MUX_
SELECT_0
Selects MUX_IN inputs or register
contents for MUX_OUT outputs
11
12–16
17
MUX_OUT E–A
Open drain multiplexed outputs
NON-MUXED_
OUTPUT
Open drain output from
non-volatile memory
2
I C/SMBus without having to power down the equipment to open the
cabinet. The non-volatile memory retains the most current setting
selected before the power is turned off.
MUX_
SELECT_1
Selects between the two
non-volatile registers
18
Active high non-volatile register
write-protect input
19
20
WP
The PCA9560 typically resides between the CPU and Voltage
Regulator Module (VRM) when used for CPU VID (Voltage
V
DD
Power supply: +3.0 to +3.6 V
ORDERING INFORMATION
PACKAGES
20-Pin Plastic SO
20-Pin Plastic TSSOP
TEMPERATURE RANGE
–40 to +85 °C
ORDER CODE
PCA9560D
TOPSIDE MARK
DRAWING NUMBER
SOT163-1
PCA9560D
PCA9560
–40 to +85 °C
PCA9560PW
SOT360-1
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
2
2004 May 19
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
BLOCK DIAGRAM
PCA9560
WRITE PROTECT
NON-VOLATILE
REGISTER 0
6
6-BIT EEPROM
LATCH
NMO
NON-MUXED_OUT
NON-VOLATILE
REGISTER 1
6-BIT EEPROM
6
5
8
A0
A1
SCL
SDA
INPUT
FILTER
2
I C/SMBus
CONTROL
LOGIC
MUX_OUT_A
MUX_OUT_B
MUX_OUT_C
MUX_OUT_D
MUX_OUT_E
V
DD
POWER-ON
RESET
3
GND
MUX_IN_A
MUX_IN_B
MUX_IN_C
MUX_IN_D
5
MUX_IN_E
MUX_SELECT_1
SELECT LOGIC
MUX_SELECT_0
SW00841
Figure 2. Block diagram
3
2004 May 19
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
DEVICE ADDRESS
CONTROL REGISTER
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9560 is
shown in Figure 3. To conserve power, no internal pull-up resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9560, which will be stored
in the control register. This register can be written and read via the
2
I C-bus.
The last bit of the slave address byte defines the operation to be
performed. When set to logic 1 a read is selected while a logic 0
selects a write operation.
D7
D6
D5
D4
D3
D2
D1
D0
MSB
1
LSB
R/W
0
0
1
1
A1
A0
SW00954
Figure 4. Control Register
FIXED
PROGRAMMABLE
SW00955
Figure 3. Slave address
CONTROL REGISTER DEFINITION
Following the address and acknowledge bit with logic 0 in the read/write bit, the first byte written is the command byte. If the command byte is
reserved and therefore not valid, it will not be acknowledged. Only valid command bytes will be acknowledged.
Table 1. Register Addresses
REGISTER
NAME
REGISTER
FUNCTION
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
TYPE
Read/Write
Read/Write
Read
EEPROM byte 0
register
EEPROM 0
EEPROM byte 1
register
0
0
0
0
0
0
0
1
EEPROM 1
MUX_IN
MUX_IN values
register
1
1
1
1
1
1
1
1
Table 2. Commands
D7
1
D6
1
D5
1
D4
1
D3
1
D2
0
D1
0
D0
0
COMMAND
MUX_OUT from EEPROM byte 0
MUX_OUT from EEPROM byte 1
MUX_OUT from MUX_IN
1
1
1
1
1
1
0
0
1
1
1
1
1
X
1
0
2
1
1
1
1
1
X
X
1
MUX_OUT from MUX_SELECT
NOTE:
1. All other combinations are reserved.
2. MUX_SELECT pins select between MUX_IN and EEPROM to MUX_OUT.
4
2004 May 19
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
REGISTER DESCRIPTION
If the command byte is an EEPROM address, the next byte sent will be programmed into that EEPROM address on the following STOP
condition, if the WP is logic 0. If more than one byte is sent sequentially, the second byte will be written in the other-volatile register, on the
following STOP condition. If any more data bytes are sent after the second byte, they will not be acknowledged and no bytes will be written to
the non-volatile registers. After a byte is read from or written to the EEPROM, the part automatically points to the next non-volatile register. If the
command code was FFH, the MUX_IN values are sent with the three MSBs padded with zeroes as shown below. If the command codes was
00H, then the non-volatile register 1 is sent, and if the command code was 01H, then the non-volatile register 1 is sent.
EEPROM Byte 0 Register
D7
D6
D5
D4
D3
D2
D1
D0
Write
Read
X
X
Non-Muxed
Data
EEPROM 0
Data E
EEPROM 0
Data D
EEPROM 0
Data C
EEPROM 0
Data B
EEPROM 0
Data A
0
0
0
0
Non-Muxed
Data
EEPROM 0
Data E
EEPROM 0
Data D
EEPROM 0
Data C
EEPROM 0
Data B
EEPROM 0
Data A
Default
0
0
0
0
0
0
EEPROM Byte 1 Register
D7
D6
D5
D4
D3
D2
D1
D0
Write
Read
X
0
0
X
Non-Muxed
Data
EEPROM 1
Data E
EEPROM 1
Data D
EEPROM 1
Data C
EEPROM 1
Data B
EEPROM 1
Data A
0
0
Non-Muxed
Data
EEPROM 1
Data E
EEPROM 1
Data D
EEPROM 1
Data C
EEPROM 1
Data B
EEPROM 1
Data A
Default
0
0
0
0
0
0
MUX_IN Register
D7
D6
D5
D4
D3
D2
D1
D0
Read
0
0
0
MUX_IN
Data E
MUX_IN
Data D
MUX_IN
Data C
MUX_IN
Data B
MUX_IN
Data A
If the command byte is a MUX command byte, any additional data bytes sent after the MUX command code will not be acknowledged. If the
read/write bit in the address is a logic 1, then a read operation follows and the data sent out depends on the previously stored command code.
The MUX_SELECT_1 pin can function as the over-ride pin as on the PCA9559 if the non-volatile register 1 is left at all 0s.
The NON_MUXED_OUT pin is a latched output. It is latched when MUX_SELECT_0 = 1. It is transparent when the MUX_SELECT_0 = 0. The
data sent out on the NON_MUXED_OUT output is the 6th most significant bit of the non-volatile register. Whether this comes from the
non-volatile register 0 or non-volatile register 1 depends on the command code or the external mux-select pins.
2
2
After a valid I C write operation to the EEPROM, the part cannot be addressed via the I C for 3.6 ms. If the part is addressed prior to this time,
the part will not acknowledge its address.
NOTE:
2
1. To ensure data integrity, the non-volatile register must be internally write protected when V to the I C bus is powered down or V to the
DD
DD
component is dropped below normal operating levels.
5
2004 May 19
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
CONVERSION FROM THE PCA9559 TO THE PCA9560
The PCA9560 is a drop in replacement to the PCA9559 with no software modifications. The PCA9559 has only one MUX_SELECT pin to
choose between the MUX_IN values and the single non-volatile register. Since the PCA9560 has two internal non-volatile registers, if Register 1
is left to all 0’s (default condition) then the MUX_SELECT_1 pin can function the same as the PCA9559 OVERRIDE # pin and MUX_SELECT_0
pin can function the same as the PCA9559 MUX_IN pin.
2
The PCA9560 can read the MUX_IN_X values via I C that the PACA9559 cannot do. Another difference is that the MUX_SELECT_X control
2
pins can be overridden by I C. To replace the PCA9559 with the PCA9560, the function table for the MUX_OUT outputs and the
2
NON_MUXED_OUT output must stay the same and the MUX_SELECT pin functions should not be overridden by I C.
EXTERNAL CONTROL SIGNALS
2
The Write Protect (WP) input is used to control the ability to write the content of the non-volatile registers. If the WP signal is logic 0, the I C bus
will be able to write the contents of the non-volatile registers. If the WP signal is logic 1, data will not be allowed to be written into the
non-volatile registers. In this case, the slave address and the command code will be acknowledged but the following data bytes will not be
acknowledged and the EEPROM is not updated.
2
The factory default for the contents of the non-volatile register are all logic 0. These stored values can be read or written using the I C-bus
(described in the next section).
The WP, MUX_IN*, MUX_SELECT_0, and MUX_SELECT_1 signals have internal pull-up resistors. See the DC and AC Characteristics for
hysteresis and signal spike suppression figures.
1
Function Table
WP
MUX_SELECT_0
MUX_SELECT_1
COMMANDS
2
0
X
X
Write to the non-volatile registers through I C bus allowed
2
Write to the non-volatile registers through I C bus not
1
X
X
X
X
X
0
0
1
1
2
X
1
0
1
0
allowed
MUX_OUT and NON_MUXED_OUT (transparent) from
EEPROM byte 0
MUX_OUT and NON_MUXED_OUT (transparent) from
EEPROM byte 1
MUX_OUT from MUX_IN inputs and NON_MUXED_OUT
latched (from EEPROM 0)
MUX_OUT from MUX_IN inputs and NON_MUXED_OUT
latched (from EEPROM 1)
NOTE:
1. This table is valid when not overridden by I C control register.
POWER-ON RESET (POR)
When power is applied to V , an internal power-on reset holds the PCA9560 in a reset state until V has reached V . At that point, the
DD
DD
POR
2
reset condition is released and the PCA9560 volatile registers and I C/SMBus state machine will initialize to their default states.
The MUX_OUT and NON_MUXED_OUT pin values depend on:
– the MUX_SELECT_0 and MUX_SELECT_1 logic levels, selecting either the MUX_IN input pins or one of the two 6-bit EEPROMs
– the previously stored values in the EEPROM registers/current MUX_IN pin values as shown in the Function Table
6
2004 May 19
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
2
CHARACTERISTICS OF THE I C-BUS
2
The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line
(SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may
be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as
changes in the data line at this time will be interpreted as control signals (see Figure 5).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
SW00363
Figure 5. Bit transfer
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined
as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 6).
System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device initiates a transfer is the ‘master’ and the
devices which are controlled by the master are the ‘slaves’ (see Figure 7).
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
SW00365
Figure 6. Definition of start and stop conditions
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
2
SLAVE
RECEIVER
I C
MULTIPLEXER
MASTER
TRANSMITTER
SLAVE
SW00366
Figure 7. System configuration
7
2004 May 19
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH-level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START condition
SW00368
2
Figure 8. Acknowledgement on the I C-bus
8
2004 May 19
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
Bus Transactions
Data is transmitted to the PCA9560 registers using Write Byte transfers (see Figures 9 and 10). Data is read from the PCA9560 registers using
Read and Receive Byte transfers (see Figure 11).
control register
write on EEPROM byte 0
EEPROM byte 0 data
slave address
1
1
A1
D4 D3 D2
D5 D1 D0
1
0
0
A0
0
0
0
0
0
0
0
0
X
X
A
P
S
0
A
A
R/W
stop condition
start condition
acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
SW00956
Figure 9. WRITE on 1 EEPROM — assuming WP = 0
control register write on
EEPROM byte 0
EEPROM byte 1 data
EEPROM byte 0 data
slave address
1
1
A1
D3 D2 D1
D3 D2 D1
D5 D4 D0
1
0
0
A0
X
D5 D4
D0
A
X
A
P
0
0
0
0
0
0
0
0
S
0
A
A
X
X
R/W
start condition
acknowledge
from slave
acknowledge
from slave
stop condition
SW00957
Figure 10. WRITE on 2 EEPROMs — assuming WP = 0
control register read
MUX_IN values
slave address
slave address
data from MUX_IN
S
1
0
0
1
1
A1 A0
0
A
1
1
1
1
1
1
1
1
A
S
1
0
0
1
1
A1 A0
1
A
0
0
0
4
3
2
1
0
NA
P
R/W
R/W
restart
start condition
acknowledge
from master
acknowledge
from master
acknowledge
from master
no acknowledge
from master
stop condition
SW00958
Figure 11. READ MUX_IN register
9
2004 May 19
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
1, 2
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
DD
–0.5 to +4.0
–0.5 to +5.5
–0.5 to +5.5
–60 to +150
V
IN
DC input voltage
Note 3
Note 3
V
V
OUT
DC output voltage
V
T
stg
Storage temperature range
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The maximum input or output voltage is the lesser of 5.5 V or V + 4.0 V, except for very short (e.g., system start-up or shut-down)
DD
durations.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
3.0
–0.5
2.7
—
MAX
3.6
V
DD
DC supply voltage
—
V
V
V
V
IL
LOW-level input voltage
HIGH-level input voltage
SCL, SDA
SCL, SDA
I
OL
I
OL
I
OL
I
OL
= 3 mA
= 3 mA
= 3 mA
= 6 mA
0.9
1
V
IH
5.5
0.4
0.6
V
OL
LOW-level output voltage
LOW-level input voltage
SCL, SDA
V
V
—
MUX_IN,
MUX_SELECT_0,
MUX_SELECT_1
V
IL
—
—
–0.5
2.0
0.8
MUX_IN,
MUX_SELECT_0,
MUX_SELECT_1
1
V
IH
HIGH-level input voltage
5.5
V
MUX_OUT,
NON_MUXED_OUT
I
LOW-level output current
HIGH-level output current
—
—
—
—
8
mA
OL
MUX_OUT,
NON_MUXED_OUT
I
100
µA
OH
dt/dv
Input transition rise or fall time
Operating ambient temperature
dt/dv
—
—
0
10
85
ns/V
T
amb
T
amb
–40
°C
NOTES:
1. The maximum input voltage is the lesser of 5.5 V or V + 4.0 V, except for very short (e.g., system start-up or shut-down) durations.
DD
10
2004 May 19
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
DC CHARACTERISTICS
LIMITS
TYP.
SYMBOL
Supply
PARAMETER
TEST CONDITION
UNIT
MIN.
MAX.
V
Supply voltage
3
—
—
3.6
1
V
mA
µA
V
DD
DDL
DDH
I
I
Supply current
Operating mode ALL inputs = 0 V
—
—
—
Supply current
Operating mode ALL inputs = V
—
600
2.7
DD
V
POR
Power-on reset voltage
No load; V = V or GND
2.3
I
DD
Input SCL: Input/Output SDA
V
V
LOW-level input voltage
HIGH-level input voltage
LOW-level output current
LOW-level output current
Leakage current HIGH
Input current LOW
–0.5
2
—
—
—
—
—
—
3
0.8
V
IL
IH
1
5.5
—
—
1
V
I
I
I
I
V
V
= 0.4 V
= 0.6 V
3
mA
mA
µA
µA
pF
OL
OL
IH
OL
6
OL
V = V
–1
–1
—
I
DD
V = GND
1
IL
I
C
Input capacitance
6
I
WP, MUX_SELECT_0, MUX_SELECT_1
I
I
Leakage current HIGH
Input current LOW
Input capacitance
V = V
DD
–1
–20
—
—
—
1
–50
5
µA
µA
pF
IH
IL
I
V
DD
V
DD
V
DD
= 3.6 V; V = GND
I
C
2.5
I
MUX_IN A → E
I
IH
I
IL
Leakage current HIGH
Input current LOW
Input capacitance
V = V
I DD
–1
–20
—
—
—
1
–50
5
µA
µA
pF
= 3.6 V; V = GND
I
C
2.5
I
A0, A1 Inputs
I
IH
I
IL
Leakage current HIGH
Input current LOW
Input capacitance
V = V
I DD
–1
–20
—
—
—
2
1
–50
4
µA
µA
pF
= 3.6 V; V = GND
I
C
I
MUX_OUT
V
V
LOW-level output voltage
LOW-level output voltage
HIGH-level output current
I
= 100 µA
OL
—
—
—
—
—
—
0.4
0.7
V
V
OL
OL
I
OL
= 4 mA
I
V
OH
= V
DD
100
µA
OH
NON-MUXED_OUT
V
LOW-level output voltage
LOW-level output voltage
I
= 100 µA
—
—
—
—
0.4
0.7
V
V
OL
OL
V
OL
I
= 2 mA
OL
NOTE:
1. The maximum input voltage is the lesser of 5.5 V or V + 4.0 V, except for very short (e.g., system start-up or shut-down) durations.
DD
NON-VOLATILE STORAGE SPECIFICATIONS
PARAMETER
Memory cell data retention
Number of memory cell write cycles
2
SPECIFICATION
10 years min
100,000 cycles min
Application Note AN250 I C DIP Switch provides additional information on memory cell data retention and the minimum number of write cycles.
11
2004 May 19
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
SAC CHARACTERISTICS
LIMITS
TYP.
SYMBOL
MUX_IN
PARAMETER
UNIT
MIN.
MAX.
MUX_OUT
LOW-to-HIGH transition time
HIGH-to-LOW transition time
MUX_OUT
t
—
—
28
8
40
15
ns
ns
PLH
PHL
t
Select
t
t
LOW-to-HIGH transition time
HIGH-to-LOW transition time
Output rise time
—
—
30
10
—
—
—
43
15
3
ns
ns
PLH
PHL
t
R
1.0
1.0
—
ns/V
ns/V
pF
t
F
Output fall time
3
C
Test load capacitance on outputs
50
L
Select
NON-MUXED_OUT
t
LOW-to-HIGH transition time
HIGH-to-LOW transition time
—
—
30
9
40
15
ns
ns
PLH
PHL
t
AC SPECIFICATIONS
STANDARD MODE
FAST MODE
I C-BUS
2
2
I C-BUS
SYMBOL
PARAMETER
UNITS
MIN
0
MAX
100
—
MIN
MAX
400
—
f
Operating frequency
0
kHz
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
ns
SCL
t
Bus free time between STOP and START conditions
Hold time after (repeated) START condition
Repeated START condition setup time
Set-up time for STOP condition
4.7
4.0
4.7
4.0
0
1.3
BUF
t
—
0.6
—
HD;STA
t
—
0.6
—
SU;STA
t
—
0.6
—
SU;STO
t
Data in hold time
—
0
0.1
—
HD;DAT
VD;ACK
2
t
Valid time for ACK condition
0.3
300
250
4.7
4.0
—
3.45
—
0.9
—
3
t
t
Data out valid time
50
VD;DAT
Data set-up time
—
100
—
SU;DAT
t
Clock LOW period
Clock HIGH period
Clock/Data fall time
Clock/Data rise time
—
1.3
—
LOW
t
—
0.6
—
HIGH
1
1
t
F
300
1000
50
20 + 0.1 C
20 + 0.1 C
—
300
300
50
b
t
R
—
b
t
Pulse width of spikes that must be suppressed by the
input filters
—
SP
NOTES:
1. C = total capacitance of one bus line in pF.
b
2. t
3. t
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
= minimum time for SDA data out to be valid following SCL LOW.
VD;ACK
VD;DAT
12
2004 May 19
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
SDA
t
R
t
F
t
t
SP
HD;STA
t
t
LOW
BUF
SCL
t
t
t
SU;STO
HD;STA
SU;STA
t
t
t
SU;DAT
HD;DAT
HIGH
P
S
Sr
P
SU00645
Figure 12. Definition of timing
V
V
MUX INPUT
CC
O
V
V
M
M
t
V
V
R
t
PLZ
IN
OUT
L
PHL
V
O
PULSE
GENERATOR
D.U.T.
MUX OUTPUT
V
M
R
T
V
V
+ 0.3 V
OL
OL
C
L
Test Circuit for Open Drain Outputs
SW00500
Figure 13. Open drain output enable and disable times
DEFINITIONS
R = Load resistor; 1 kΩ
L
C = Load capacitance includes jig and probe capacitance;
L
10 pF
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SW00510
Figure 14. Test circuit
13
2004 May 19
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
14
2004 May 19
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
15
2004 May 19
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
REVISION HISTORY
Rev
Date
Description
_4
20040519
Product data sheet (9397 750 13154). Supersedes data of 2003 Jun 27 (9397 750 11676).
Modifications:
th
• Features section, 16 bullet: from “inputs” to “inputs/outputs”
• Absolute maximum ratings table: V , V , and V
limits modified. Note 3 re-written.
OUT
DD
IN
• Recommended operating conditions
– V max. (on SCL, SDA) changed from 4.0 V to 5.5 V (with Note 1 added).
IH
– V max. (on MUX_IN, MUX_SELECT_0, MUX_SELECT_1) changed from 4.0 V to 5.5 V (with Note 1
IH
added).
• DC characteristics table: Input SCL: Input/Output SDA; V parameter max. limit modified, and Note 1 added.
IH
_3
_2
20030627
20020524
Product data (9397 750 11676); ECN 853-2286 29936 dated 19 May 2003.
Supersedes data of 2002 May 24 (9397 750 09892).
Product data (9397 750 09892); ECN 853–2286 28310 of 24 May 2002.
16
2004 May 19
Philips Semiconductors
Product data sheet
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
PCA9560
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data sheet
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data sheet
Product data sheet
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys
nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2004
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 05-04
9397 750 13154
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
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