PCA9564BS [NXP]
Parallel bus to I2C-bus controller; 并行总线I2C总线控制器
| 型号： | PCA9564BS |
| 厂家： | 
NXP |
| 描述： | Parallel bus to I2C-bus controller |
| 文件： | 总31页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
PCA9564
Parallel bus to I2C-bus controller
Product data
2003 Apr 02
Supersedes data of 2003 Feb 26
Philips
Semiconductors
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
DESCRIPTION
The PCA9564 is an integrated circuit designed in CMOS technology
that serves as an interface between most standard parallel-bus
2
microcontrollers/microprocessors and the serial I C-bus and allows
the parallel bus system to communicate bi-directionally with the
2
I C-bus. The PCA9564 can operate as a master or a slave and can
2
be a transmitter or receiver. Communication with the I C-bus is
carried out on a byte-wise basis using interrupt or polled handshake.
2
The PCA9564 controls all the I C-bus specific sequences, protocol,
arbitration and timing with no external timing element required.
FEATURES
• Parallel-bus to I C-bus protocol converter and interface
The PCA9564 is similar to the PCF8584 but operates at lower
voltages and higher I@C frequencies. Other enhancements
requested by design engineers have also been incorporated.
2
• Both master and slave functions
• Multi-master capability
• Internal oscillator reduces external components
• Operating supply voltage 2.3 V to 3.6 V
• 5 V tolerant I/Os
Characteristic
PCA9564 PCF8584
Comments
Voltage range
2.3-3.6 V 4.5-5.5 V PCA9564 is 5 V
tolerant
2
Maximum
360 kHz
400 kHz
Internal
90 kHz
Faster I C interface
master mode
2
I C frequency
2
• Standard and fast mode I C capable and compatible with SMBus
2
Maximum slave
100 kHz Faster I C interface
2
mode I C
• ESD protection exceeds 2000 V HEM per JESD22-A114, 200 V
frequency
MM per JESD22-A115, and 1000 V CDM per JESD22-C101
Clock source
External Less expensive and
more flexible with
• Latch-up testing is done to JEDEC Standard JESD78 which
exceed 100 mA.
internal oscillator
• Packages offered: SO20, TSSOP20, HVQFN20
Parallel
interface
Fast
50 MHz
Slow
Compatible with
faster processors
APPLICATIONS
2
• Add I C bus port to controllers/processors that don’t have one
While the PCF8584 supported most parallel-bus microcontrollers/
microprocessors including the Intel 8049/8051, Motorola
2
• Add additional I C bus ports to controllers/processors that need
6800/68000 and the Zilog Z80, the PCA9564 has been designed to
2
multiple I C bus ports
2
be very similar to the Philips standard 80C51 microcontroller I C
hardware so the devices are not code compatible. Additionally, the
PCA9564 does not support the bus monitor “Snoop” mode nor the
long distance mode and is not foot print compatible with the
PCF8584.
• Higher frequency, lower voltage migration path for the PCF8584
• Converts 8 bits of parallel data to serial data stream to prevent
having to run a large number of traces across the entire PC board
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
-40 to +85 °C
ORDER CODE
PCA9564D
TOPSIDE MARK
PCA9564D
PCA9564
DRAWING NUMBER
SOT163-1
20-Pin Plastic SO
20-Pin Plastic TSSOP
20-Pin Plastic HVQFN
-40 to +85 °C
PCA9564PW
PCA9564BS
SOT360-1
-40 to +85 °C
9564
SOT662-1
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
2
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
PIN CONFIGURATION — SO, TSSOP
PIN CONFIGURATION — HVQFN
D2
D1 D0
V
SDA
DD
V
1
2
20
19
18
17
16
15
14
13
12
11
DD
D0
D1
15 SCL
D3
D4
D5
D6
D7
1
2
3
4
5
SDA
SCL
RESET
INT
RESET
14
13
12
11
3
D2
4
INT
A1
D3
5
D4
6
D5
A1
A0
7
D6
A0
8
D7
CE
DNU GND WR RD CE
(V
)
SS
9
DNU
RD
TOP VIEW
10
V
WR
su01665
SS
su01485
PIN CONFIGURATION
PIN NUMBER
PIN
TYPE
SO, TSSOP
HVQFN
SYMBOL
NAME AND FUNCTION
1, 2, 3, 4, 5,
6, 7, 8
1, 2, 3, 4,
5, 18, 19,
20
D0-D7
I/O
Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status
between the controller and the CPU. D0 is the least significant bit.
9
6
7
8
DNU
Do not use: must be left floating (pulled low internally)
Ground
10
11
V
SS
Pwr
I
WR
RD
CE
Write Strobe: When LOW and CE is also LOW, the contents of the data bus is loaded into
the addressed register. The transfer occurs on the rising edge of the signal.
12
13
9
I
I
Read Strobe: When LOW and CE is also LOW, causes the contents of the addressed
register to be presented on the data bus. The read cycle begins on the falling edge of RD.
10
Chip Enable: Active-LOW input signal. When LOW, data transfers between the CPU and
the controller are enabled on D0-D7 as controlled by the WR, RD and A0-A1 inputs.
When HIGH, places the D0-D7 lines in the 3-State condition.
14, 15
11, 12
A0, A1
I
Address Inputs: Selects the controller internal registers and ports for read/write
operations.
16
17
18
19
20
13
14
15
16
17
INT
O
Interrupt Request: Active-LOW, open-drain, output. This pin requires a pull-up device.
2
RESET
SCL
I
Reset: A LOW level clears internal registers resets the I C state machine.
2
I/O
I/O
Pwr
I C-bus serial clock input/output (open-drain).
2
SDA
I C-bus serial data input/output (open-drain).
V
DD
Power Supply: 2.3 to 3.6 V
3
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
PCA9564
8
D0-D7
BUS BUFFER
RD
OPERATION CONTROL
WR
ADDRESS
DECODE
CE
A0
A1
R/W CONTROL
RESET
SCL
SDA
INPUT
FILTER
POWER-ON RESET
V
MASTER/SLAVE
STATE MACHINES
DD
INT
INTERRUPT CONTROL
TIMING
CLOCK
SELECTORS
INTERNAL
OSCILLATOR
V
SS
SD00707
Figure 1. Block diagram
4
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
The Address Register, I2CADR: I2CADR is not affected by the
SIO hardware. The contents of this register are irrelevant when SIO
is in a master mode. In the slave modes, the seven most significant
bits must be loaded with the microcontroller’s own slave address.
FUNCTIONAL DESCRIPTION
General
The PCA9564 acts as an interface device between standard
2
2
high-speed parallel buses and the serial I C-bus. On the I C-bus, it
can act either as master or slave. Bidirectional data transfer between
7
6
5
4
3
2
1
0
0
I2CADR
BIT7 BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
2
the I C-bus and the parallel-bus microcontroller is carried out on a
byte-wise basis, using either an interrupt or polled handshake.
own slave address
The most significant bit corresponds to the first bit received from the
Internal Oscillator
2
I C-bus after a start condition. A logic 1 in I2CADR corresponds to a
The PCA9564 contains an internal 9 MHz oscillator which is used
2
2
HIGH level on the I C-bus, and a logic 0 corresponds to a LOW
for all I C timing. The oscillator requires up to 500 µs to start-up
level on the bus. The least significant bit is not used but should be
after ENSIO bit is set to “1”.
programmed with a ‘0’.
Registers
The Data Register, I2CDAT: I2CDAT contains a byte of serial data
to be transmitted or a byte which has just been received. In master
mode, this includes the slave address that the master wants to send
The PCA9564 contains four registers which are used to configure
the operation of the device as well as to send and receive serial data.
2
The registers are selected by setting pins A0 and A1 to the
out on the I C-bus, with the most significant bit of the slave address
appropriate logic levels before a read or write operation is executed.
in the SD7 bit position and the Read/Write bit in the SD0 bit position.
The CPU can read from and write to this 8-bit register while it is not
in the process of shifting a byte. This occurs when SIO is in a
defined state and the serial interrupt flag is set. Data in I2CDAT
remains stable as long as SI is set. Whenever the SIO generates an
interrupt, the I2CDAT registers contain the data byte that was just
2
2
CAUTION: Do not write to I C registers while the I C-bus is busy
and the SIO is in master or addressed slave mode.
REGISTER REGISTER
READ/
WRITE
A1
A0
DEFAULT
NAME
I2CSTA
I2CTO
FUNCTION
2
transferred on the I C-bus.
Status
0
0
0
1
1
0
0
1
0
1
R
F8h
FFh
00h
00h
00h
NOTE: The I2CDAT register will capture the serial address as data
when addressed via the serial bus. Also, the data register will
continue to capture data from the serial bus during 38H so the
I2CDAT register will need to be reloaded when the bus becomes
free.
Time-out
Data
W
I2CDAT
I2CADR
I2CCON
R/W
R/W
R/W
Own address
Control
7
6
5
4
3
2
1
0
The Time-out Register, I2CTO: The time-out register is used to
I2CDAT
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
determine the maximum time that SCL is allowed to be LOW before
2
the I C state machine is reset.
• SD7 - SD0:
2
When the I C interface is operating, I2CTO is loaded in the time-out
Eight bits to be transmitted or just received. A logic 1 in I2CDAT
counter at every SCL transition.
2
corresponds to a HIGH level on the I C-bus, and a logic 0
corresponds to a LOW level on the bus.
7
6
5
4
3
2
1
0
I2CTO
TE
TO6
TO5
TO4
TO3
TO2
TO1
TO0
The Control Register, I2CCON: The microcontroller can read from
and write to this 8-bit register. Two bits are affected by the SIO
hardware: the SI bit is set when a serial interrupt is requested, and
the STO bit is cleared when a STOP condition is present on the
Time-out value
The most significant bit of I2CTO (TE) is used as a time-out
2
I C-bus.
enable/disable. A “1” will enable the time-out function. The time-out
period = (I2CTO[6:0] + 1) × 113.7 µs. The time-out value may vary
some and is an approximate value.
7
6
5
4
3
2
1
0
I2CCON
ENSIO
STA
STO
SI
CR1
CR0
AA
CR2
The time-out register can be used in the following cases:
• ENSIO, THE SIO ENABLE BIT
1. When the SIO, in the master mode, wants to send a START
condition and the SCL line is held LOW by some other device.
The SIO waits a time period equivalent to the time-out value for
the SCL to be released. In case it is not released, the SIO
concludes that there is a bus error, loads 90H in the I2CSTA
register, generates an interrupt signal and releases the SCL and
SDA lines. After the microcontroller reads the status register, it
needs to send an external reset in order to reset the SIO.
ENSIO = “0”: When ENSIO is “0”, the SDA and SCL outputs are in a
high impedance state. SDA and SCL input signals are ignored, SIO
is in the “not addressed” slave state.
ENSIO = “1”: When ENSIO is “1”, SIO is enabled.
After the ENSIO bit is set, it takes 500 µs for the internal oscillator to
start up, therefore, the PCA9564 will enter either the master or the
slave mode after this time. ENSIO should not be used to temporarily
2
release the PCA9564 from the I C-bus since, when ENSIO is reset,
2. In the master mode, the time-out feature starts every time the SCL
goes LOW. If SCL stays LOW for a time period equal to or greater
than the time-out value, the SIO concludes there is a bus error
and behaves in the manner described above.
2
the I C-bus status is lost. The AA flag should be used instead (see
description of the AA flag in the following text).
In the following text, it is assumed that ENSIO = “1”.
• STA, THE START FLAG
2
3. In case of a forced access to the I C-bus. (See more details on
page 15.)
5
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
STA = “1”: When the STA bit is set to enter a master mode, the SIO
hardware checks the status of the I C-bus and generates a START
condition if the bus is free. If the bus is not free, then SIO waits for a
STOP condition (which will free the bus) and generates a START
When SIO is in the not addressed slave mode, its own slave
2
address is ignored. Consequently, no acknowledge is returned, and
a serial interrupt is not requested. Thus, SIO can be temporarily
2
released from the I C-bus while the bus status is monitored. While
condition after the minimum buffer time (t
) has elapsed.
SIO is released from the bus, START and STOP conditions are
detected, and serial data is shifted in. Address recognition can be
resumed at any time by setting the AA flag.
BUF
If STA is set while SIO is already in a master mode and one or more
bytes are transmitted or received, SIO transmits a repeated START
condition. STA may be set at any time. STA may also be set when
SIO is an addressed slave.
• THE CLOCK RATE BITS, CR2, CR1, AND CR0
Three bits determine the serial clock frequency when SIO is in
master mode. The various serial rates are shown in Table 1.
STA = “0”: When the STA bit is reset, no START condition or
repeated START condition will be generated.
The clock frequencies only take the HIGH and LOW times into
consideration. The rise and fall time will cause the actual measured
frequency to be lower than expected.
• STO, THE STOP FLAG
STO = “1”: When the STO bit is set while SIO is in a master mode, a
2
STOP condition is transmitted to the I C-bus. When the STOP
The frequencies shown in Table 1 are unimportant when SIO is in a
slave mode. In the slave modes, SIO will automatically synchronize
with any clock frequency up to 400 kHz.
condition is detected on the bus, the SIO hardware clears the STO
flag.
If the STA and STO bits are both set, then a STOP condition is
transmitted to the I C-bus if SIO is in a master mode. SIO then
Table 1. Serial Clock Rates
2
transmits a START condition.
SERIAL CLOCK FREQUENCY
CR2
CR1
CR0
(kHz)
STO = “0”: When the STO bit is reset, no STOP condition will be
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
330
288
217
146
generated.
• SI, THE SERIAL INTERRUPT FLAG
SI = “1”: When the SI flag is set, then, if the ENSIO bit is also set, a
serial interrupt is requested. SI is set by hardware when one of 24 of
the 25 possible SIO states is entered. The only state that does not
cause SI to be set is state F8H, which indicates that no relevant
state information is available.
1
88
59
44
36
While SI is set, the LOW period of the serial clock on the SCL line is
stretched, and the serial transfer is suspended. A HIGH level on the
SCL line is unaffected by the serial interrupt flag. SI must be reset
by writing “0” to the SI bit. The SI bit cannot be set by the user.
NOTE:
1. The clock frequency values are approximate and may vary
with temperature, supply voltage, process, and SCL output
2
loading. If normal mode I C parameters must be strictly followed
(SCL < 100kHz), it is recommended not to use
CR[2:0] = 100 (SCL = 88kHz) since the clock frequency might be
slightly higher than 100 kHz under certain temperature, voltage,
and process conditions and use CR[2:0] = 101 (SCL = 59 kHz)
instead.
SI = “0”: When the SI flag is reset, no serial interrupt is requested,
and there is no stretching of the serial clock on the SCL line.
• AA, THE ASSERT ACKNOWLEDGE FLAG
AA = “1”: If the AA flag is set, an acknowledge (LOW level to SDA)
will be returned during the acknowledge clock pulse on the SCL line
when:
The Status Register, I2CSTA: I2CSTA is an 8-bit read-only register.
The three least significant bits are always zero. The five most
significant bits contain the status code. There are 25 possible status
codes. When I2CSTA contains F8H, no relevant state information is
available and no serial interrupt is requested. All other I2CSTA
values correspond to defined SIO states. When each of these states
is entered, a serial interrupt is requested (SI = “1”).
- The “own slave address” has been received
- A data byte has been received while SIO is in the master receiver
mode
- A data byte has been received while SIO is in the addressed
slave receiver mode
More Information on SIO Operating Modes
The four operating modes are:
- Master Transmitter
AA = “0”: if the AA flag is reset, a not acknowledge (HIGH level to
SDA) will be returned during the acknowledge clock pulse on SCL
when:
- Master Receiver
- A data byte has been received while SIO is in the master receiver
mode
- Slave Receiver
- A data byte has been received while SIO is in the addressed
slave receiver mode
- Slave Transmitter
Data transfers in each mode of operation are shown in Figures 2-5.
These figures contain the following abbreviations:
- “Own slave address” has been received
When SIO is in the addressed slave transmitter mode, state C8H
will be entered after the last serial is transmitted (see Figure 5).
When SI is cleared, enters the not addressed slave receiver mode,
and the SDA line remains at a HIGH level. In state C8H, the AA flag
can be set again for future address recognition.
6
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
Abbreviation
S
SLA
R
W
A
A
Data
P
Explanation
Start condition
7-bit slave address
Read bit (HIGH level at SDA)
Write bit (LOW level at SDA)
Acknowledge bit (LOW level at SDA)
Not acknowledge bit (HIGH level at SDA)
8-bit data byte
Master Receiver Mode: In the master receiver mode, a number of
data bytes are received from a slave transmitter (see Figure 3). The
transfer is initialized as in the master transmitter mode. When the
start condition has been transmitted, the interrupt service routine
must load I2CDAT with the 7-bit slave address and the data
direction bit (SLA+R). The SI bit in I2CCON must then be cleared
before the serial transfer can continue.
Stop condition
When the slave address and the data direction bit have been
transmitted and an acknowledgment bit has been received, the
serial interrupt flag (SI) is set again, and a number of status codes in
I2CSTA are possible. These are 40H, 48H, or 38H for the master
mode and also 68H, or B0H if the slave mode was enabled (AA =
logic 1). The appropriate action to be taken for each of these status
codes is detailed in Table 3. ENSIO is not affected by the serial
transfer and are not referred to in Table 3. After a repeated start
condition (state 10H), SIO may switch to the master transmitter
mode by loading I2CDAT with SLA+W.
In Figures 2-5, circles are used to indicate when the serial interrupt
flag is set. A serial interrupt is not generated when I2CSTA = F8H.
This happens on a stop condition. The numbers in the circles show
the status code held in the I2CSTA register. At these points, a
service routine must be executed to continue or complete the serial
transfer. These service routines are not critical since the serial
transfer is suspended until the serial interrupt flag is cleared by
software.
When a serial interrupt routine is entered, the status code in I2CSTA
is used to branch to the appropriate service routine. For each status
code, the required software action and details of the following serial
transfer are given in Tables 2-6.
Note that a master should not transmit its own slave address.
Slave Receiver Mode: In the slave receiver mode, a number of
data bytes are received from a master transmitter (see Figure 4). To
initiate the slave receiver mode, I2CADR and I2CCON must be
loaded as follows:
Master Transmitter Mode: In the master transmitter mode, a
number of data bytes are transmitted to a slave receiver (see
Figure 2). Before the master transmitter mode can be entered,
I2CCON must be initialized as follows:
7
6
5
4
3
2
1
0
I2CADR
BIT7 BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
0
7
6
5
STA
0
4
STO
0
3
SI
0
2
1
0
own slave address
I2CCON
AA
X
ENSIO
1
CR1
CR0
CR2
bit rate
The upper 7 bits are the address to which SIO will respond when
addressed by a master.
ENSIO must be set to logic 1 to enable SIO. If the AA bit is reset,
SIO will not acknowledge its own slave address in the event of
another device becoming master of the bus. In other words, if AA is
reset, SIO cannot enter a slave mode. STA, STO, and SI must be
reset.
7
6
5
4
3
2
CR2
X
1
0
I2CCON
AA
ENSIO
STA
STO
SI
CR1
CR0
1
1
0
0
0
X
X
The master transmitter mode may now be entered by setting the
STA bit. The SIO logic will now test the I C-bus and generate a start
ENSIO must be set to logic 1 to enable SIO. The AA bit must be set
to enable SIO to acknowledge its own slave address, STA, STO,
and SI must be reset.
2
condition as soon as the bus becomes free. When a START
condition is transmitted, the serial interrupt flag (SI) is set, and the
status code in the status register (I2CSTA) will be 08H. This status
code must be used to vector to an interrupt service routine that
loads I2CDAT with the slave address and the data direction bit
(SLA+W). The SI bit in I2CCON must then be reset before the serial
transfer can continue.
When I2CADR and I2CCON have been initialized, SIO waits until it
is addressed by its own slave address followed by the data direction
bit which must be “0” (W) for SIO to operate in the slave receiver
mode. After its own slave address and the W bit have been
received, the serial interrupt flag (I) is set and a valid status code
can be read from I2CSTA. This status code is used to vector to an
interrupt service routine, and the appropriate action to be taken for
each of these status codes is detailed in Table 4. The slave receiver
mode may also be entered if arbitration is lost while SIO is in the
master mode (see status 68H).
When the slave address and the direction bit have been transmitted
and an acknowledgment bit has been received, the serial interrupt
flag (SI) is set again, and a number of status codes in I2CSTA are
possible. There are 18H, 20H, or 38H for the master mode and also
68H, or B0H if the slave mode was enabled (AA = logic 1). The
appropriate action to be taken for each of these status codes is
detailed in Table 2. After a repeated start condition (state 10H). SIO
may switch to the master receiver mode by loading I2CDAT with
SLA+R).
If the AA bit is reset during a transfer, SIO will return a not
acknowledge (logic 1) to SDA after the next received data byte.
While AA is reset, SIO does not respond to its own slave address.
2
However, the I C-bus is still monitored and address recognition may
be resumed at any time by setting AA. This means that the AA bit
may be used to temporarily isolate SIO from the I C-bus.
Note that a master should never transmit its own slave
address.
2
7
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
MT
SUCCESSFUL TRANSMISSION
TO A SLAVE RECEIVER
S
SLA
W
A
DATA
A
P
28H
08H
F8
18H
NEXT TRANSFER STARTED WITH A REPEATED START CONDITION
NOT ACKNOWLEDGE RECEIVED AFTER THE SLAVE ADDRESS
S
SLA
W
R
10H
A
P
20H
F8H
TO MST/REC MODE
ENTRY = MR
NOT ACKNOWLEDGE RECEIVED AFTER A DATA BYTE
A
P
30H
F8H
ARBITRATION LOST IN SLAVE ADDRESS OR DATA BYTE
OTHER MST
CONTINUES
OTHER MST
CONTINUES
A or A
38H
A or A
38H
ARBITRATION LOST AND ADDRESSED AS SLAVE
OTHER MST
CONTINUES
A
TO CORRESPONDING STATES IN
SLAVE RECEIVER MODE
68H
B0H
TO CORRESPONDING STATES IN
SLAVE TRANSMITTER MODE
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Data
n
A
ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS
2
THIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I C BUS. SEE TABLE 2.
NOTE: THE MASTER SHOULD NEVER TRANSMIT ITS OWN SLAVE ADDRESS
SW00816
Figure 2. Format and states in the master transmitter mode
8
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
MR
SUCCESSFUL RECEPTION
FROM A SLAVE TRANSMITTER
S
SLA
R
A
DATA
A
DATA
A
P
50H
58H
08H
F8H
40H
NEXT TRANSFER STARTED WITH A
REPEATED START CONDITION
S
SLA
R
10H
NOT ACKNOWLEDGE RECEIVED
AFTER THE SLAVE ADDRESS
A
P
W
48H
F8H
TO MST/TRX MODE
ENTRY = MT
ARBITRATION LOST IN SLAVE ADDRESS
OR ACKNOWLEDGE BIT
OTHER MST
CONTINUES
OTHER MST
CONTINUES
A
A or A
38H
38H
ARBITRATION LOST AND ADDRESSED AS SLAVE
OTHER MST
CONTINUES
A
TO CORRESPONDING STATES IN
SLAVE RECEIVER MODE
68H
B0H
TO CORRESPONDING STATES IN
SLAVE TRANSMITTER MODE
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS
DATA
n
A
2
THIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I C BUS. SEE TABLE 3.
SW00817
Figure 3. Format and states in the master receiver mode
9
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
RECEPTION OF THE OWN SLAVE ADDRESS
AND ONE OR MORE DATA BYTES
ALL ARE ACKNOWLEDGED.
S
SLA
W
A
DATA
A
DATA
A
P or S
A0H
80H
80H
60H
LAST DATA BYTE RECEIVED IS
NOT ACKNOWLEDGED
P or S
A
ARBITRATION LOST AS MST AND
ADDRESSED AS SLAVE
88H
F8H
A
ON STOP
68H
P or S
F8H
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
ON STOP
Data
A
ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS
2
n
THIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I C BUS. SEE TABLE 4.
SW00814
Figure 4. Format and states in the slave receiver mode
RECEPTION OF THE
OWN SLAVE ADDRESS
AND TRANSMISSION
OF ONE OR MORE
DATA BYTES
S
SLA
R
A
DATA
A
DATA
A
P or S
B8H
C0H
F8H
A8H
ON STOP
ARBITRATION LOST AS MST
AND ADDRESSED AS SLAVE
A
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
B0H
LAST DATA BYTE TRANSMITTED.
SWITCHED TO NOT ADDRESSED
SLAVE (AA BIT IN I2CCON = “0”)
P or S
A
All “1”s
F8H
C8H
DATA
n
A
ANY NUMBER OF DATA BYTES AND THEIR ASSOCIATED ACKNOWLEDGE BITS
ON STOP
2
THIS NUMBER (CONTAINED IN I2CSTA) CORRESPONDS TO A DEFINED STATE OF THE I C BUS. SEE TABLE 5.
SW00815
Figure 5. Format and states of the slave transmitter mode
10
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
Table 2.
Master Transmitter Mode
APPLICATION SOFTWARE RESPONSE
STATUS
CODE
(I2CSTA)
STATUS OF THE
I C BUS AND
SIO HARDWARE
2
TO I2CCON
NEXT ACTION TAKEN BY SIO HARDWARE
TO/FROM I2CDAT
STA STO
SI
AA
08H
10H
A START condition has
been transmitted
Load SLA+W
X
X
0
X
SLA+W will be transmitted;
ACK bit will be received
Load SLA+W or
Load SLA+R
X
X
X
X
0
0
X
X
As above
SLA+R will be transmitted;
SIO will be switched to MST/REC mode
A repeated START
condition has been
transmitted
Load data byte or
0
0
0
X
Data byte will be transmitted;
ACK bit will be received
Repeated START will be transmitted;
STOP condition will be transmitted;
STO flag will be reset
STOP condition followed by a
START condition will be transmitted;
STO flag will be reset
18H
20H
28H
30H
38H
SLA+W has been
transmitted; ACK has
been received
no I2CDAT action or
no I2CDAT action or
1
0
0
1
0
0
X
X
no I2CDAT action
1
1
0
X
Load data byte or
0
0
0
X
Data byte will be transmitted;
ACK bit will be received
Repeated START will be transmitted;
STOP condition will be transmitted;
STO flag will be reset
STOP condition followed by a
START condition will be transmitted;
STO flag will be reset
SLA+W has been
transmitted; NOT ACK
has been received
no I2CDAT action or
no I2CDAT action or
1
0
0
1
0
0
X
X
no I2CDAT action
1
1
0
X
Load data byte or
0
0
0
X
Data byte will be transmitted;
ACK bit will be received
Repeated START will be transmitted;
STOP condition will be transmitted;
STO flag will be reset
STOP condition followed by a
START condition will be transmitted;
STO flag will be reset
Data byte in I2CDAT
has been transmitted;
ACK has been received
no I2CDAT action or
no I2CDAT action or
1
0
0
1
0
0
X
X
no I2CDAT action
1
1
0
X
Load data byte or
0
0
0
X
Data byte will be transmitted;
ACK bit will be received
Repeated START will be transmitted;
STOP condition will be transmitted;
STO flag will be reset
STOP condition followed by a
START condition will be transmitted;
STO flag will be reset
Data byte in I2CDAT
has been transmitted;
NOT ACK has been
received
no I2CDAT action or
no I2CDAT action or
1
0
0
1
0
0
X
X
no I2CDAT action
1
1
0
X
2
No I2CDAT action or
No I2CDAT action
0
1
0
0
0
0
X
X
I C-bus will be released;
Arbitration lost in
SLA+W or
Data bytes
not addressed slave will be entered
A START condition will be transmitted when the
bus becomes free (STOP or SCL and SDA high)
11
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
Table 3.
Master Receiver Mode
APPLICATION SOFTWARE RESPONSE
TO I2CCON
STATUS
CODE
(I2CSTA)
STATUS OF THE
I C BUS AND
SIO HARDWARE
2
NEXT ACTION TAKEN BY SIO HARDWARE
TO/FROM I2CDAT
STA STO
SI
AA
08H
10H
A START condition has
been transmitted
Load SLA+R
X
X
0
X
SLA+R will be transmitted;
ACK bit will be received
Load SLA+R or
Load SLA+W
X
X
X
X
0
0
X
X
As above
SLA+W will be transmitted;
SIO will be switched to MST/TRX mode
A repeated START
condition has been
transmitted
2
No I2CDAT action or
No I2CDAT action
0
1
0
0
0
0
X
X
I C-bus will be released;
38H
40H
48H
Arbitration lost in
NOT ACK bit
SIO will enter a slave mode
A START condition will be transmitted when the
bus becomes free
No I2CDAT action or
no I2CDAT action
0
0
0
0
0
0
0
1
Data byte will be received;
NOT ACK bit will be returned
Data byte will be received;
ACK bit will be returned
SLA+R has been
transmitted; ACK has
been received
No I2CDAT action or
no I2CDAT action or
1
0
0
1
0
0
X
X
Repeated START condition will be transmitted
STOP condition will be transmitted;
STO flag will be reset
SLA+R has been
transmitted; NOT ACK
has been received
no I2CDAT action
1
1
0
X
STOP condition followed by a
START condition will be transmitted;
STO flag will be reset
Read data byte or
read data byte
0
0
0
0
0
0
0
1
Data byte will be received;
NOT ACK bit will be returned
Data byte will be received;
ACK bit will be returned
50H
58H
Data byte has been
received; ACK has been
returned
Read data byte or
read data byte or
1
0
0
1
0
0
X
X
Repeated START condition will be transmitted
STOP condition will be transmitted;
STO flag will be reset
Data byte has been
received; NOT ACK has
been returned
read data byte
1
1
0
X
STOP condition followed by a
START condition will be transmitted;
STO flag will be reset
2
No I2CDAT action or
No I2CDAT action
0
1
0
0
0
0
X
X
I C-bus will be released;
38H
Arbitration lost in
SLA+R
not addressed slave will be entered
A START condition will be transmitted when the
bus becomes free
12
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
Table 4.
Slave Receiver Mode
APPLICATION SOFTWARE RESPONSE
STATUS
CODE
(I2CSTA)
STATUS OF THE
I C BUS AND
SIO HARDWARE
2
TO I2CCON
NEXT ACTION TAKEN BY SIO HARDWARE
TO/FROM I2CDAT
STA STO
SI
AA
No I2CDAT action
or
X
X
0
0
Data byte will be received and NOT ACK will be
returned
60H
68H
Own SLA+W has
been received; ACK
has been returned
no I2CDAT action
X
X
X
X
0
0
1
0
Data byte will be received and ACK will be returned
No I2CDAT action
or
Data byte will be received and NOT ACK will be
returned
Arbitration lost in
SLA+R/W as master;
Own SLA+W has
been received, ACK
returned
no I2CDAT action
Read data byte or
X
X
X
X
0
0
1
0
Data byte will be received and ACK will be returned
Data byte will be received and NOT ACK will be
returned
80H
88H
Previously addressed
with own SLV
address; DATA has
been received; ACK
has been returned
read data byte
X
0
X
X
0
0
1
0
Data byte will be received and ACK will be returned
Read data byte or
Switched to not addressed SLV mode; no recognition
of own SLA
Previously addressed
with own SLA; DATA
byte has been
received; NOT ACK
has been returned
read data byte or
read data byte or
0
1
X
X
0
0
1
0
Switched to not addressed SLV mode; Own SLA will
be recognized
Switched to not addressed SLV mode; no recognition
of own SLA. A START condition will be transmitted
when the bus becomes free
read data byte
1
X
0
1
Switched to not addressed SLV mode; Own SLA will
be recognized. A START condition will be transmitted
when the bus becomes free.
No I2CDAT action
or
0
0
1
X
X
X
0
0
0
0
1
0
Switched to not addressed SLV mode; no recognition
of own SLA
A0H
A STOP condition or
repeated START
condition has been
received while still
addressed as
No I2CDAT action
or
Switched to not addressed SLV mode; Own SLA will
be recognized
SLV/REC
No I2CDAT action
or
Switched to not addressed SLV mode; no recognition
of own SLA. A START condition will be transmitted
when the bus becomes free
No I2CDAT action
1
X
0
1
Switched to not addressed SLV mode; Own SLA will
be recognized. A START condition will be transmitted
when the bus becomes free.
13
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
Table 5.
Slave Transmitter Mode
APPLICATION SOFTWARE RESPONSE
STATUS
CODE
(I2CSTA)
STATUS OF THE
I C BUS AND
SIO HARDWARE
2
TO I2CCON
NEXT ACTION TAKEN BY SIO HARDWARE
TO/FROM I2CDAT
STA STO
SI
AA
Load data byte or
X
X
0
0
Last data byte will be transmitted and ACK bit will be
received
Data byte will be transmitted; ACK will be received
A8H
B0H
Own SLA+R has
been received; ACK
has been returned
load data byte
X
X
X
X
0
0
1
0
Load data byte or
Last data byte will be transmitted and ACK bit will be
received
Arbitration lost in
SLA+R/W as master;
Own SLA+R has
been received, ACK
has been returned
load data byte
X
X
0
1
Data byte will be transmitted; ACK bit will be
received
Load data byte or
load data byte
X
X
X
X
0
0
0
1
Last data byte will be transmitted and ACK bit will be
received
Data byte will be transmitted; ACK bit will be
received
B8H
C0H
Data byte in I2CDAT
has been transmitted;
ACK has been
received
No I2CDAT action
or
no I2CDAT action or
0
0
1
X
X
X
0
0
0
0
1
0
Switched to not addressed SLV mode; no recognition
of own SLA
Switched to not addressed SLV mode; Own SLA will
be recognized
Switched to not addressed SLV mode; no recognition
of own SLA. A START condition will be transmitted
when the bus becomes free
Data byte in I2CDAT
has been transmitted;
NOT ACK has been
received
no I2CDAT action or
no I2CDAT action
1
X
0
1
Switched to not addressed SLV mode; Own SLA will
be recognized. A START condition will be transmitted
when the bus becomes free.
No I2CDAT action
or
no I2CDAT action or
0
0
1
X
X
X
0
0
0
0
1
0
Switched to not addressed SLV mode; no recognition
of own SLA
Switched to not addressed SLV mode; Own SLA will
be recognized
Switched to not addressed SLV mode; no recognition
of own SLA. A START condition will be transmitted
when the bus becomes free
C8H
Last data byte in
I2CDAT has been
transmitted (AA = 0);
ACK has been
received
no I2CDAT action or
no I2CDAT action
1
X
0
1
Switched to not addressed SLV mode; Own SLA will
be recognized. A START condition will be transmitted
when the bus becomes free.
Table 6.
Miscellaneous States
APPLICATION SOFTWARE RESPONSE
STATUS
CODE
(I2CSTA)
STATUS OF THE
I C BUS AND
SIO HARDWARE
2
TO I2CCON
NEXT ACTION TAKEN BY SIO HARDWARE
TO/FROM I2CDAT
STA STO
SI
0
AA
X
No I2CDAT action
No I2CDAT action
No I2CDAT action
1
0
0
X
X
X
Go into master mode; send START
No recognition of own SLA
F8H
On reset or STOP
0
0
0
1
Will recognize own SLA
70H
90H
00H
Bus error
SDA stuck LOW
Reset SIO (Requires reset to return to state F8H)
Bus error
SCL stuck LOW
Reset SIO (Requires reset to return to state F8H)
Reset SIO (Requires reset to return to state F8H)
Bus error during
master or slave
mode, due to illegal
START or STOP
condition
14
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
Slave Transmitter Mode: In the slave transmitter mode, a number
of data bytes are transmitted to a master receiver (see Figure 5).
Data transfer is initialized as in the slave receiver mode. When
I2CADR and I2CCON have been initialized, SIO waits until it is
addressed by its own slave address followed by the data direction
bit which must be “1” (R) for SIO to operate in the slave transmitter
mode. After its own slave address and the R bit have been received,
the serial interrupt flag (SI) is set and a valid status code can be
read from I2CSTA. This status code is used to vector to an interrupt
service routine, and the appropriate action to be taken for each of
these status codes is detailed in Table 5. The slave transmitter mode
may also be entered if arbitration is lost while SIO is in the master
mode (see state B0H).
I2CSTA = 90H:
This status code indicates that the SCL line is stuck LOW.
Some Special Cases: The SIO hardware has facilities to handle the
following special cases that may occur during a serial transfer:
• SIMULTANEOUS REPEATED START CONDITIONS FROM TWO MASTERS
A repeated START condition may be generated in the master
transmitter or master receiver modes. A special case occurs if
another master simultaneously generates a repeated START
condition (see Figure 6). Until this occurs, arbitration is not lost by
either master since they were both transmitting the same data.
If the SIO hardware detects a repeated START condition on the
2
I C-bus before generating a repeated START condition itself, it will
If the AA bit is reset during a transfer, SIO will transmit the last byte
of the transfer and enter state C8H. SIO is switched to the not
addressed slave mode and will ignore the master receiver if it
continues the transfer. Thus the master receiver receives all 1s as
serial data. While AA is reset, SIO does not respond to its own slave
use the repeated START as its own and continue with the sending of
the slave address.
• DATA TRANSFER AFTER LOSS OF ARBITRATION
Arbitration may be lost in the master transmitter and master receiver
modes. Loss of arbitration is indicated by the following states in
I2CSTA; 38H, 68H, and B0H (see Figures 2 and 3).
2
address. However, the I C-bus is still monitored, and address
recognition may be resumed at any time by setting AA. This means
that the AA bit may be used to temporarily isolate SIO from the
NOTE: In order to exit state 38H, a Timeout, Reset, or external
Stop are required.
2
I C-bus.
Miscellaneous States: There are four I2CSTA codes that do not
correspond to a defined SIO hardware state (see Table 6). These
are discussed below.
If the STA flag in I2CCON is set by the routines which service these
states, then, if the bus is free again, a START condition (state 08H)
is transmitted without intervention by the CPU, and a retry of the
total serial transfer can commence.
I2CSTA = F8H:
• FORCED ACCESS TO THE I2C BUS
This status code indicates that no relevant information is available
because the serial interrupt flag, SI, is not yet set. This occurs on a
STOP condition and when SIO is not involved in a serial transfer.
In some applications, it may be possible for an uncontrolled source
to cause a bus hang-up. In such situations, the problem may be
caused by interference, temporary interruption of the bus or a
temporary short-circuit between SDA and SCL.
I2CSTA = 00H:
This status code indicates that a bus error has occurred during an
SIO serial transfer. A bus error is caused when a START or STOP
condition occurs at an illegal position in the format frame. Examples
of such illegal positions are during the serial transfer of an address
byte, a data byte, or an acknowledge bit. A bus error may also be
caused when external interference disturbs the internal SIO signals.
When a bus error occurs, SI is set. To recover from a bus error, the
microcontroller must send an external reset signal to reset the SIO.
If an uncontrolled source generates a superfluous START or masks
2
a STOP condition, then the I C-bus stays busy indefinitely. If the
STA flag is set and bus access is not obtained within a reasonable
2
amount of time, then a forced access to the I C-bus is possible. If
2
the I C-bus stays idle for a time period equal to the time out period,
then the ’64 concludes that no other master is using the bus and
sends a START condition.
I2CSTA = 70H:
This status code indicates that the SDA line is stuck LOW when the
SIO, in master mode, is trying to send a START condition.
BOTH MASTERS CONTINUE
WITH SLA TRANSMISSION
S
SLA
W
A
DATA
A
S
08H
18H
28H
OTHER MASTER SENDS REPEATED
START CONDITION EARLIER
SU00975
Figure 6. Simultaneous repeated START conditions from 2 masters
15
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
TIME OUT
STA FLAG
SDA LINE
SCL LINE
START CONDITION
SU00976
2
Figure 7. Forced access to a busy I C-bus
microcontroller reads the status register, it needs to send an
external reset signal in order to reset the SIO.
• I2C BUS OBSTRUCTED BY A LOW LEVEL ON SCL OR SDA
2
An I C-bus hang-up occurs if SDA or SCL is pulled LOW by an
If a forced bus access occurs or a repeated START condition is
transmitted while SDA is obstructed (pulled LOW), the SIO
hardware performs the same action as described above. In each
case, state 08H is entered after a successful START condition is
transmitted and normal serial transfer continues. Note that the CPU
is not involved in solving these bus hang-up problems.
uncontrolled source. If the SCL line is obstructed (pulled LOW) by a
device on the bus, no further serial transfer is possible, and the SIO
hardware cannot resolve this type of problem. When this occurs, the
problem must be resolved by the device that is pulling the SCL bus
line LOW.
When the SCL line stays LOW for a period equal to the time-out
value, the ’64 concludes that this is a bus error and behaves in a
manner described on page 5 under “Time-out Register”.
• BUS ERROR
A bus error occurs when a START or STOP condition is present at
an illegal position in the format frame. Examples of illegal positions
are during the serial transfer of an address byte, a data or an
acknowledge bit.
If the SDA line is obstructed by another device on the bus (e.g., a
slave device out of bit synchronization), the problem can be solved
by transmitting additional clock pulses on the SCL line (see
Figure 8). The SIO hardware sends out nine clock pulses followed
by the STOP condition. If the SDA line is released by the slave
pulling it LOW, a normal START condition is transmitted by the SIO,
state 08H is entered and the serial transfer continues. If the SDA
line is not released by the slave pulling it LOW, then the SIO
concludes that there is a bus error, loads 70H in I2CSTA, generates
an interrupt signal, and releases the SCL and SDA lines. After the
The SIO hardware only reacts to a bus error when it is involved in a
serial transfer either as a master or an addressed slave. When a
bus error is detected, SIO releases the SDA and SCL lines, sets the
interrupt flag, and loads the status register with 00H. This status
code may be used to vector to a service routine which either
attempts the aborted serial transfer again or simply recovers from
the error condition as shown in Table 6. The microcontroller must
send an external reset signal to reset the SIO.
STA FLAG
SDA LINE
1
2
3
4
5
6
7
8
9
SCL LINE
STOP
CONDITION
START
CONDITION
su01663
Figure 8. Recovering from a bus obstruction caused by a LOW level on SDA
16
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
2
I C-BUS TIMING DIAGRAMS
The diagrams (Figures 9 to 12) illustrate typical timing diagrams for the PCA9564 in master/slave functions.
SCL
SDA
INT
first-byte
nbyte
interrupt
7-bit address
interrupt
interrupt
R/W = 0
STOP
condition
ACK
ACK
ACK
START
condition
from slave receiver
Master PCA9564 writes data to slave transmitter.
su01490
Figure 9. Bus timing diagram; master transmitter mode
SCL
SDA
INT
first-byte
nbyte
7-bit address
interrupt
interrupt
R/W = 1
STOP
condition
START
condition
ACK
ACK
no ACK
from master
receiver
from slave
Master PCA9564 reads data from slave transmitter.
su01491
Figure 10. Bus timing diagram; master receiver mode
17
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
SCL
SDA
INT
first-byte
nbyte
interrupt
7-bit address
interrupt
interrupt
R/W = 1
STOP
condition
ACK
ACK
no ACK
START
condition
from master
receiver
from slave PCA9564
External master receiver reads data from PCA9564.
su14092
Figure 11. Bus timing diagram; slave transmitter mode
SCL
SDA
INT
interrupt
(after STOP)
first-byte
nbyte
interrupt
7-bit address
R/W = 0
interrupt
interrupt
STOP
condition
ACK
ACK
ACK
START
condition
from slave PCA9564
Slave PCA9564 is written to by external master transmitter.
su01493
Figure 12. Bus timing diagram; slave receiver mode
18
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
V
DD
ADDRESS BUS
V
DD
V
DD
A0
A1
PCA9564
SLAVE
INT
DECODER
RESET
ALE
CE
SCL
80C51
8
D[0:7]
RD
SDA
WR
V
DD
INT
V
DD
RESET
V
SS
V
SS
SD00705
Figure 13. Application diagram using the 80C51
19
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
SPECIFIC APPLICATIONS
PCA8584 MIGRATION PATH
2
The PCA9564 is a parallel bus to I C bus controller that is designed
The PCA9564 does the same type of parallel to serial conversion as
the PCF8584. Although not footprint or code compatible, the
PCA9564 provides improvements such as:
2
to allow “smart” devices to interface with I C or SMBus components,
where the “smart” device does not have an integrated I C port and
2
2
the designer does not want to “bit-bang” the I C port. The PCA9564
1. Operating at 3.3 V and 2.5 V voltage nodes with 5 V tolerant I/Os
2
can also be used to add more I C ports to “smart” devices, provide a
2
2. Allows interface with I C or SMBus components at speeds up to
higher frequency, lower voltage migration path for the PCF8584 and
convert 8 bits of parallel data to a serial bus to avoid running
multiple traces across the PC board.
400 kHz.
3. Built-in oscillator provides a cost effective solution since the
external clock input is no longer required.
2
4. Parallel data can be exchanged at speeds up to 50 MHz allowing
the use of faster processors.
ADD I C BUS PORT
As shown in Figure 14, the PCA9564 converts 8-bits of parallel data
into a multiple master capable I C port for microcontrollers,
2
microprocessors, custom ASICs, DSPs, etc., that need to interface
2
with I C or SMBus components.
SDA
PCA9564
SUPPLY VOLTAGE FREQUENCY
SCL
2.3 - 3.6 V
< 400 kHz
CONTROL SIGNALS
OSCILLATOR
SDA
SCL
MICROCONTROLLER,
MICROPROCESSOR,
OR ASIC
PCA9564
4.5 - 5.5 V
< 100 kHz
8-BITS
SDA
SCL
PCF8584
SW02108
2
Figure 14. Adding I C Bus Port Application
CLOCK INPUT
SW02110
Figure 16. PCF8584 Migration Path
2
ADD ADDITIONAL I C BUS PORTS
The PCA9564 can be used to convert 8-bit parallel data into
additional multiple master capable I C port as shown in Figure 15. It
2
is used if the microcontroller, microprocessor, custom ASIC, DSP,
2
2
2
CONVERT 8 BITS OF PARALLEL DATA INTO I C
SERIAL DATA STREAM
etc., already have an I C port but need one or more additional I C
2
ports to interface with more I C or SMBus components or
components that cannot be located on the same bus (e.g., 100 kHz
and 400 kHz slaves on different buses so that each bus can operate
at its maximum potential).
Functioning as a slave transmitter, the PCA9564 can convert 8-bit
2
parallel data into a two-wire I C data stream as is shown in
Figure 17. This would prevent having to run 8 traces across the
entire width of the PC board.
SDA
SCL
CONTROL
SIGNALS
SDA
SCL
MICROCONTROLLER,
MICROPROCESSOR,
OR ASIC
PCA9564
MASTER
MICROCONTROLLER,
MICROPROCESSOR,
CONTROL SIGNALS
OR ASIC
8-BITS
SDA
PCA9564
SCL
SW02111
8-BITS
Figure 17. Converting Parallel to Serial Data Application
SW02109
2
Figure 15. Adding Additional I C Bus Ports Application
20
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN
-0.3
-0.8
-10
-10
—
MAX
4.6
UNIT
V
V
DD
Supply voltage
1
V
I
Voltage range (any input)
DC input current (any input)
DC output current (any output)
Total power dissipation
6.0
10
V
I
I
mA
mA
mW
mW
°C
I
O
10
P
tot
300
50
P
O
Power dissipation per output
Operating ambient temperature
Storage temperature
—
T
amb
-40
-65
+85
+150
T
stg
°C
NOTE:
1. 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage
tolerance on inputs and outputs when no supply voltage is present.
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take
precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”Handling MOS devices”.
DC CHARACTERISTICS
V
DD
= 2.3 V to 3.6 V; T
= -40 to +85 °C; unless otherwise specified.
amb
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
V
Supply voltage
2.3
—
—
—
—
0.1
—
3.6
3.0
6.0
2.2
V
µA
mA
V
DD
standby
I
Supply current
DD
operating - no load
V
POR
Power-on Reset voltage
1.8
Inputs WR, RD, A0, A1, CE, RESET
V
LOW level input voltage
HIGH level input voltage
Leakage current
0
2.0
-1
—
—
0.8
V
V
IL
IH
L
1
V
I
5.5
Input; V = 0 V or 5.5 V
—
1
3
µA
pF
I
C
Input capacitance
V = V or V
—
1.7
I
I
SS
DD
Inputs/outputs D0 to D7
V
LOW level input voltage
HIGH level input voltage
HIGH level output current
LOW level output current
Leakage current
0
2.0
-4.0
4.0
-1
—
—
0.8
V
V
IL
IH
1
V
5.5
I
V
V
= V - 0.4 V
-7.0
8.0
—
—
—
1
mA
mA
µA
pF
OH
OH
DD
I
OL
= 0.4 V
OL
I
L
Input; V = 0 V or 5.5 V
I
C
Input/output capacitance
V = V or V
I DD
—
2.4
4
IO
SS
SDA and SCL
V
LOW level input voltage
HIGH level input voltage
0
—
—
0.3 V
V
V
IL
DD
1
V
IH
0.7 V
-1
5.5
1
DD
Input/output; V = 0 V or 3.6 V
—
I
I
L
Leakage current
µA
Input/output; V = 5.5 V
-1
—
10
—
4
I
I
OL
LOW level output current
Input/output capacitance
V
OL
= 0.4 V
5.0
8.5
2.5
mA
pF
C
V = V or V
—
IO
I
SS
DD
Outputs INT
I
LOW level output current
Leakage current
V
V
= 0.4 V
3.0
-1
—
—
—
1
mA
µA
pF
OL
OL
I
L
= 0 or 3.6 V
O
C
Output capacitance
V = V or V
I DD
—
2.1
4
O
SS
NOTE:
1. 5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage
tolerance on inputs and outputs when no supply voltage is present.
21
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
SDA
t
t
F
LOW
t
SU;DAT
t
R
t
F
t
R
t
t
BUF
HD;STA
t
SP
SCL
t
t
SU;STO
t
SU;STA
HD;STA
t
t
S
P
S
HD;DAT HIGH
S
R
SU01755
Figure 18. Definition of timing
2
I C-BUS TIMING SPECIFICATIONS
All the timing limits are valid within the operating supply voltage and ambient temperature range; V = 2.5 V 0.2 V and 3.3 V 0.3 V,
DD
T
amb
= -40 to +85 °C; and refer to V and V with an input voltage of V to V
.
IL
IH
SS
DD
STANDARD MODE
FAST MODE
I C BUS
2
2
I C BUS
SYMBOL
PARAMETER
UNITS
MIN
0
MAX
100
—
MIN
MAX
f
t
Operating frequency
0
1.3
0.6
0.6
0.6
0
400
—
kHz
µs
µs
µs
µs
ns
µs
µs
µs
ns
µs
µs
µs
µs
ns
SCL
Bus free time between STOP and START conditions
Hold time after (repeated) START condition
Repeated START condition setup time
Setup time for STOP condition
Data in hold time
4.7
4.0
4.7
4.0
0
BUF
t
—
—
HD;STA
t
t
—
—
SU;STA
—
—
SU;STO
t
—
—
HD;DAT
VD;ACK
t
Valid time for ACK condition
Data out valid time LOW
—
0.6
0.6
0.6
—
—
0.6
0.6
0.6
—
t
t
—
—
VD;DAT(L)
Data out valid time HIGH
Data setup time
—
—
VD;DAT(H)
t
250
4.7
4.0
—
100
1.3
0.6
—
SU;DAT
t
Clock LOW period
—
—
LOW
t
Clock HIGH period
—
—
HIGH
t
F
Clock/Data fall time
0.3
1
0.3
0.3
50
t
R
Clock/Data rise time
—
—
t
Pulse width of spikes that must be suppressed by the input filters
—
50
—
SP
22
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
START
ACK OR READ CYCLE
SCL
SDA
30%
t
RES
RESET
50%
50%
50%
t
REC
t
WRES
t
RES
50%
Dn
LED OFF
SW02107
Figure 19. Reset timing
A0-A1
t
AS
t
AH
CE
t
t
CS
CH
t
t
RW
RWD
RD
t
DF
t
DD
D0-D7
(READ)
FLOAT
VALID
FLOAT
t
RWD
WR
t
DS
t
DH
D0-D7
(WRITE)
VALID
SD00711
Figure 20. Bus timing
23
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
1, 2, 3
AC CHARACTERISTICS (3.3 VOLT)
V
= 3.3 V 3.0 V, T
= -40 to +85 °C, unless otherwise specified. (See page 25 for 2.5 V.)
CC
amb
LIMITS
Min
Max
SYMBOL
Reset Timing (See Figure 19)
PARAMETER
UNIT
t
Reset pulse width
Time to reset
10
250
0
—
—
—
ns
ns
ns
WRES
4,5
t
RES
t
Reset recovery time
REC
Bus Timing (See Figure 20, 21)
t
A0-A1 setup time to RD, WR LOW
A0-A1 hold time from RD, WR LOW
CE setup time to RD, WR LOW
0
7
—
—
—
—
—
17
17
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AS
AH
CS
CH
t
t
0
t
CE Hold time from RD, WR LOW
0
t
WR, RD pulse width (Low time)
7
RW
t
Data valid after RD and CE LOW
—
—
7
DD
t
Data bus floating after RD or CE HIGH
Data bus setup time before WR or CE HIGH (write cycle)
Data hold time after WR HIGH
DF
DS
DH
t
t
0
t
High time between read and/or write cycles
12
RWD
NOTES:
1. Parameters are valid over specified temperature and voltage range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of 5 ns
maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figures 20-21.
3. Test conditions for outputs: C = 50 pF, R = 500 Ω, except open drain outputs. Test conditions for open drain outputs: C = 50 pF, R = 1 kΩ
L
L
L
L
pullup to V
.
DD
4. Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.
5. Upon reset, the full delay will be the sum of t and the RC time constant of the SDA and SCL bus.
RES
24
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
1, 2, 3
AC CHARACTERISTICS (2.5 VOLT)
V
= 2.5 V 0.2 V, T
= -40 to +85 °C, unless otherwise specified. (See page 24 for 3.3 V.)
CC
amb
LIMITS
Min
Max
SYMBOL
Reset Timing (See Figure 19)
PARAMETER
UNIT
t
Reset pulse width
Time to reset
10
250
0
—
—
—
ns
ns
ns
WRES
4,5
t
RES
t
Reset recovery time
REC
Bus Timing (See Figure 20, 21)
t
A0-A1 setup time to RD, WR LOW
A0-A hold time from RD, WR LOW
CE setup time to RD, WR LOW
0
9
—
—
—
—
—
22
17
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AS
AH
CS
CH
t
t
0
t
CE Hold time from RD, WR LOW
0
t
WR, RD pulse width (low time)
9
RW
t
Data valid after RD and CE LOW
—
—
8
DD
t
Data bus floating after RD or CE HIGH
Data bus setup time before WR or CE HIGH (write cycle)
Data hold time after WR HIGH
DF
DS
DH
t
t
0
t
High time between read and/or write cycles
12
RWD
NOTES:
1. Parameters are valid over specified temperature and voltage range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of 5 ns
maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figures 20-21.
3. Test conditions for outputs: C = 50 pF, R = 500 Ω, except open drain outputs. Test conditions for open drain outputs: C = 50 pF, R = 1 kΩ
L
L
L
L
pullup to V
.
DD
4. Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.
5. Upon reset, the full delay will be the sum of t and the RC time constant of the SDA and SCL bus.
RES
25
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
V
I
RD, CE INPUT
V
V
M
M
GND
t
DF(LZ)
t
DD(ZL)
V
CC
Dn OUTPUT
LOW-TO-FLOAT
FLOAT-TO-LOW
V
M
V
V
X
OL
t
t
DD(ZH)
DF(HZ)
V
OH
Dn OUTPUT
HIGH-TO-FLOAT
FLOAT-TO-HIGH
V
Y
V
M
GND
OUTPUTS
FLOATING
OUTPUTS ENABLED
OUTPUTS ENABLED
V
V
V
V
= 1.5 V
M
X
= V + 0.3 V
OL
=
V
- 0.3 V
OH
Y
AND V
ARE TYPICAL OUTPUT VOLTAGE DROPS THAT OCCUR WITH THE OUTPUT LOAD.
OH
OL
SW02113
Figure 21. t and t times
DD
DF
V
CC
6.0 V
Open
R
R
= 500 Ω
L
L
V
V
O
I
PULSE
GENERATOR
D.U.T.
R
T
=
C
L
500 Ω
50pF
DEFINITIONS
TEST
S1
R = Load resistor.
t
t
t
6 V
L
DD(ZH)/ DF(HZ)
t
Open
C = Load capacitance includes jig and probe capacitance
L
DD(ZL)/ DF(LZ)
R
T
=
Termination resistance should be equal to the output
impedance Z of the pulse generators.
O
SW02114
Figure 22. Test circuitry for switching times
26
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
27
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
28
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
HVQFN20: plastic, heatsink very thin quad flat package; no leads; 20 terminals;
body 5 x 5 x 0.85 mm
SOT662-1
29
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
REVISION HISTORY
Rev
Date
Description
_2
20030402
Product data (9397 750 11353): ECN 853-2419 29715 Dated 24 March 2003.
Supersedes Objective data of 2003 Feb 26 (9397 750 11153).
• Upgrade data sheet status from Objective to Product data.
_1
20030226
Objective data (9397 750 11153)
30
2003 Apr 02
Philips Semiconductors
Product data
Parallel bus to I2C-bus controller
PCA9564
2
2
Purchase of Philips I C components conveys a license under the Philips’ I C patent
2
to use the components in the I C system provided the system conforms to the
I C specifications defined by Philips. This specification can be ordered using the
2
code 9398 393 40011.
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2003
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 04-03
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 11353
Philips
Semiconductors
相关型号：
©2020 ICPDF网 联系我们和版权申明